Magnetic memory device, manufacturing method thereof, and substrate processing equipment

Abstract

A magnetic memory device, a method for manufacturing the magnetic memory device, and a substrate processing device, the device comprising: a substrate comprising a first memory region and a second memory region; a first magnetic tunnel junction pattern located on the first memory region, the first magnetic tunnel junction pattern comprising a first free pattern and a first oxide pattern located on the first free pattern; and a second magnetic tunnel junction pattern located on the second memory region, the second magnetic tunnel junction pattern comprising a second free pattern and a second oxide pattern located on the second free pattern, wherein a ratio of a thickness of the first oxide pattern to a thickness of the first free pattern is different from a ratio of a thickness of the second oxide pattern to a thickness of the second free pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0111015, titled “Magnetic Memory Device, Method for Manufacturing the Same, and Substrate Treating Apparatus,” filed on September 17, 2018 in the Korean Intellectual Property Office is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a magnetic memory device, a method of manufacturing the same, and a substrate processing apparatus. Background Art

[0004] As high-speed and / or low-power electronic devices are developed, high-speed and / or low-voltage semiconductor memory devices used therein may also be developed. Magnetic memory devices have been developed as semiconductor memory devices that can meet these characteristics. Magnetic memory devices may emerge as next-generation semiconductor memory devices because of their high speed and / or non-volatile characteristics.

[0005] The magnetic memory device may include a magnetic tunnel junction (MTJ) pattern. The magnetic tunnel junction pattern may include two magnetic layers and an insulating layer located between the two magnetic layers. The resistance value of the magnetic tunnel junction pattern may vary according to the magnetization directions of the two magnetic layers. For example, when the magnetization directions of the two magnetic layers are antiparallel to each other, the magnetic tunnel junction pattern may have a relatively high resistance value. When the magnetization directions of the two magnetic layers are parallel to each other, the magnetic tunnel junction pattern may have a relatively low resistance value. The magnetic memory device may read / write data using the difference between the resistance values ​​of the magnetic tunnel junction pattern. Summary of the invention

[0006] An embodiment may be implemented by providing a magnetic memory device, the magnetic memory device comprising: a substrate including a first memory region and a second memory region; a first magnetic tunnel junction pattern located on the first memory region, the first magnetic tunnel junction pattern including a first free pattern and a first oxide pattern located on the first free pattern; and a second magnetic tunnel junction pattern located on the second memory region, the second magnetic tunnel junction pattern including a second free pattern and a second oxide pattern located on the second free pattern, wherein a ratio of a thickness of the first oxide pattern to a thickness of the first free pattern is different from a ratio of a thickness of the second oxide pattern to a thickness of the second free pattern.

[0007] An embodiment can be implemented by providing a method for manufacturing a magnetic memory device, the method comprising: forming a magnetic layer on a substrate; forming an oxide layer on the magnetic layer; forming a cap layer on the oxide layer; forming a first hard mask layer on the cap layer; and performing an oxidation process to control interface properties between the oxide layer and the magnetic layer, wherein the cap layer comprises a first region and a second region, wherein forming the first hard mask layer comprises forming the first hard mask layer on the second region of the cap layer to expose the first region of the cap layer.

[0008] An embodiment may be implemented by providing a substrate processing device, the substrate processing device comprising:

[0009] A transfer module; a conveying module located on one side of the transfer module; a first process chamber located on one side of the conveying module; and a second process chamber located on the other side of the conveying module, wherein the first process chamber is configured to perform an oxidation process on a substrate, and the second process chamber is configured to perform a deposition process on the substrate on which the oxidation process is performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Features will be apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 A schematic block diagram of a magnetic memory device according to some embodiments is shown.

[0012] Figure 2 A circuit diagram of a memory cell array of a magnetic memory device according to some embodiments is shown.

[0013] Figure 3 A circuit diagram of a unit memory cell of a magnetic memory device according to some embodiments is shown.

[0014] Figure 4 A cross-sectional view of a magnetic memory device according to some embodiments is shown.

[0015] Figure 5A Shows Figure 4 A cross-sectional view of an example of a magnetic tunnel junction pattern.

[0016] Figure 5B Shows Figure 4 A cross-sectional view of an example of a magnetic tunnel junction pattern.

[0017] Figure 6 A flow chart of a method for fabricating a magnetic memory device according to some embodiments is shown.

[0018] Figures 7 to 9 Cross-sectional views illustrating stages in a method for fabricating a magnetic memory device according to some embodiments are shown.

[0019] Fig. 10A and Fig. 10B A graph presenting characteristics of a first magnetic tunnel junction pattern and a second magnetic tunnel junction pattern according to some embodiments is shown.

[0020] Fig.11 Shown is the method for executing Figure 6 FIG. 1 is a schematic diagram of an embodiment of a substrate processing apparatus for performing an oxidation process and a deposition process of a second hard mask layer.

[0021] Fig.12 Shows Fig.11 Schematic diagram of a first process chamber.

[0022] Fig.13 Shows Fig.11 Schematic diagram of the second process chamber.

[0023] Fig.14 A circuit diagram of a memory cell array of a magnetic memory device according to some embodiments is shown.

[0024] Fig.15 A cross-sectional view of a magnetic memory device according to some embodiments is shown.

[0025] Figures 16 to 18 Shown for manufacturing Fig.15 A cross-sectional view of various stages in a method of manufacturing a magnetic memory device. DETAILED DESCRIPTION

[0026] Figure 1 A schematic block diagram of a magnetic memory device 1 according to some embodiments is shown.

[0027] Reference Figure 1 , the magnetic memory device 1 may include a memory cell array 10 , a row decoder 20 , a column selector 30 , a read / write circuit 40 , and a control logic 50 .

[0028] The memory cell array 10 may include a plurality of word lines and a plurality of bit lines, and the memory cells may be connected to intersections of the word lines and the bit lines. Figure 2 The memory cell array 10 is described in more detail.

[0029] The row decoder 20 may be connected to the memory cell array 10 through word lines. The row decoder 20 may decode an address signal input from an external system to select one of the word lines.

[0030] The column selector 30 may be connected to the memory cell array 10 through the bit lines, and may decode an address signal input from an external system to select one of the bit lines. The bit line selected by the column selector 30 may be connected to the read / write circuit 40.

[0031] The read / write circuit 40 may provide a bit line bias for accessing a selected memory cell in response to a control signal of the control logic 50. The read / write circuit 40 may provide a bit line voltage to a selected bit line to write / read data to / from the memory cell.

[0032] The control logic 50 may output a control signal for controlling the magnetic memory device 1 in response to a command signal provided from an external system. The control signal output from the control logic 50 may control the read / write circuit 40.

[0033] Figure 2 A circuit diagram showing a memory cell array of a magnetic memory device according to some embodiments, Figure 3 A circuit diagram of a unit memory cell of a magnetic memory device according to some embodiments is shown.

[0034] Reference Figure 2 , the memory cell array 10 may include a plurality of first conductive lines, a plurality of second conductive lines, and a plurality of unit memory cells MC1 and MC2. The first conductive lines may be word lines WL0 to WL5, and the second conductive lines may be bit lines BL0 to BL3. The unit memory cells MC1 and MC2 may be arranged two-dimensionally or three-dimensionally. Each of the unit memory cells MC1 and MC2 may be connected between a corresponding one of the word lines WL0 to WL5 and a corresponding one of the bit lines BL0 to BL3. Each of the word lines WL0 to WL5 may be connected to a plurality of unit memory cells MC1 or MC2. The unit memory cells MC1 or MC2 connected to each of the word lines WL0 to WL5 may be connected to the bit lines BL0 to BL3, respectively, and the unit memory cells MC1 and MC2 connected to each of the bit lines BL0 to BL3 may be connected to the word lines WL0 to WL5, respectively. Each of the unit memory cells MC1 or MC2 connected to each of the word lines WL0 to WL5 may be connected to the bit lines BL0 to BL3 through each of the bit lines BL0 to BL3. Figure 1 The read / write circuit 40 is provided.

[0035] The memory cell array 10 may include a first memory area AR1 and a second memory area AR2. The first memory area AR1 may be a partial memory area of ​​the memory cell array 10, and the second memory area AR2 may be another partial memory area of ​​the memory cell array 10. The first memory area AR1 may include a first memory cell MC1, and the second memory area AR2 may include a second memory cell MC2. Hereinafter, the first memory area AR1 will be referred to as the first area AR1, and the second memory area AR2 will be referred to as the second area AR2. The first area AR1 and the second area AR2 may be used as different applications from each other.

[0036] Reference Figure 3 , each of the unit memory cells MC1 and MC2 may include a memory element ME and a selection element SE. The memory element ME may be connected between the bit line BL and the selection element SE, and the selection element SE may be connected between the memory element ME and the word line WL. The memory element ME may be a variable resistance element whose resistance state is switchable between two different resistance states by an electric pulse applied thereto.

[0037] In an embodiment, the memory element ME may have a thin layer structure whose resistance is variable using the spin transfer torque of electrons of a current passing therethrough. The memory element ME may have a thin layer structure exhibiting magnetoresistive characteristics and may include at least one ferromagnetic material and / or at least one antiferromagnetic material.

[0038] The selection element SE can selectively control the flow of charge through the memory element ME. For example, the selection element SE can be a diode, a PNP bipolar transistor, an NPN bipolar transistor, an NMOS field effect transistor, or a PMOS field effect transistor. When the selection element SE is a three-terminal element (e.g., a bipolar transistor or a MOS field effect transistor), additional interconnect lines can be connected to the selection element SE.

[0039] In an embodiment, the memory element ME may include a first magnetic structure MS1, a second magnetic structure MS2, and a tunneling barrier pattern TBP located between the first magnetic structure MS1 and the second magnetic structure MS2. The first magnetic structure MS1, the second magnetic structure MS2, and the tunneling barrier pattern TBP may constitute a magnetic tunneling junction pattern MTJ. Each of the first magnetic structure MS1 and the second magnetic structure MS2 may include at least one magnetic layer formed of a magnetic material. The memory element ME may also include a bottom electrode pattern BEP and a top electrode pattern TEP. The bottom electrode pattern BEP may be located between the first magnetic structure MS1 and the selection element SE, and the top electrode pattern TEP may be located between the second magnetic structure MS2 and the bit line BL.

[0040] Figure 4 2 shows a cross-sectional view of a magnetic memory device according to some embodiments. Figure 4 , the lower interlayer insulating layer 102 may be located on the substrate 100. The substrate 100 may be a semiconductor substrate including, for example, silicon, silicon on insulator (SOI), silicon germanium (SiGe), germanium (Ge), or gallium arsenic (GaAs). In an embodiment, the substrate 100 may be a system on chip. The substrate 100 may include a first region AR1 and a second region AR2.

[0041] The selection element may be located on the substrate 100, and the lower interlayer insulating layer 102 may cover the selection element. The selection element may be a field effect transistor or a diode. The lower interlayer insulating layer 102 may include at least one of an oxide layer, a nitride layer, or a nitride oxide layer.

[0042] The lower contact plugs 104 may be located in the lower interlayer insulating layer 102. Each lower contact plug 104 may penetrate the lower interlayer insulating layer 102 to be electrically connected to one terminal of a corresponding one of the selection elements. In an embodiment, the top surface of the lower contact plug 104 may be substantially coplanar with the top surface of the lower interlayer insulating layer 102.

[0043] The bottom electrode pattern BEP, the magnetic tunneling junction pattern MTJ1 or MTJ2, and the top electrode pattern TEP may be sequentially stacked on the lower interlayer insulating layer 102. The bottom electrode pattern BEP may be electrically connected to the top surface of each lower contact plug 104. The sidewalls of the bottom electrode pattern BEP, the magnetic tunneling junction pattern MTJ1 or MTJ2, and the top electrode pattern TEP may be aligned with each other. In an embodiment, the sidewalls of the bottom electrode pattern BEP, the magnetic tunneling junction pattern MTJ1 or MTJ2, and the top electrode pattern TEP may have a beveled or inclined profile. The bottom electrode pattern BEP may include a conductive material. For example, the bottom electrode pattern BEP may include a conductive metal nitride such as titanium nitride and / or tantalum nitride. In an embodiment, the top electrode pattern TEP may include a conductive material. For example, the top electrode pattern TEP may include a metal (e.g., tantalum (Ta), aluminum (Al), copper (Cu), gold (Au), silver (Ag), or titanium (Ti)) or a conductive metal nitride (e.g., tantalum nitride (TaN) or titanium nitride (TiN)).

[0044] The first magnetic tunnel junction pattern MTJ1 may be located on the first region AR1. The first magnetic tunnel junction pattern MTJ1 may include a pinning pattern RP, a first free pattern FP1, a tunnel barrier pattern TBP (located between the pinning pattern RP and the first free pattern FP1), and a first oxide pattern 112. The first free pattern FP1 may be located between the top electrode pattern TEP and the tunnel barrier pattern TBP, and the pinning pattern RP may be located between the bottom electrode pattern BEP and the tunnel barrier pattern TBP. The first oxide pattern 112 may be spaced apart from the tunnel barrier pattern TBP, and the first free pattern FP1 may be located between the first oxide pattern 112 and the tunnel barrier pattern TBP. The first oxide pattern 112 may be located between the first free pattern FP1 and the top electrode pattern TEP.

[0045] The second magnetic tunnel junction pattern MTJ2 may be located on the second region AR2. The second magnetic tunnel junction pattern MTJ2 may include a pinning pattern RP, a second free pattern FP2, a tunnel barrier pattern TBP (located between the pinning pattern RP and the second free pattern FP2), and a second oxide pattern 110. The second free pattern FP2 may be located between the top electrode pattern TEP and the tunnel barrier pattern TBP, and the pinning pattern RP may be located between the bottom electrode pattern BEP and the tunnel barrier pattern TBP. The second oxide pattern 110 may be spaced apart from the tunnel barrier pattern TBP, and a second free pattern FP2 may be located between the second oxide pattern 110 and the tunnel barrier pattern TBP. The second oxide pattern 110 may be located between the second free pattern FP2 and the top electrode pattern TEP.

[0046] The first free pattern FP1 and the second free pattern FP2 may each include a material having an interface perpendicular magnetic anisotropy. Interface perpendicular magnetic anisotropy refers to a phenomenon in which a magnetic layer having an intrinsic horizontal magnetization property is affected by an interface between the magnetic layer and another layer adjacent to the magnetic layer and has a perpendicular magnetization direction. For example, the intrinsic horizontal magnetization property may mean that the magnetic layer has a magnetization direction parallel to the widest surface of the magnetic layer when there is no external factor. For example, when a magnetic layer having an intrinsic horizontal magnetization property is formed on a substrate and there is no external factor, the magnetization direction of the magnetic layer may be substantially parallel to the top surface of the substrate. For example, when there is no external factor, the first free pattern FP1 and the second free pattern FP2 may have a magnetization direction substantially parallel to the widest surface of the first free pattern FP1 and the second free pattern FP2. The intrinsic horizontal magnetization property may be realized or presented by a single layer or multilayer structure including at least one of cobalt (Co), iron (Fe) and any alloy thereof. In an embodiment, each of the first free pattern FP1 and the second free pattern FP2 may include cobalt (Co), iron (Fe) and a first non-metallic element. The first non-metal element may be, for example, boron (B). In an implementation, each of the first free pattern FP1 and the second free pattern FP2 may have a single layer structure, for example, CoFeB.

[0047] The first oxide pattern 112 and the second oxide pattern 110 may each include a metal oxide. The first oxide pattern 112 and the second oxide pattern 110 may each include a non-magnetic metal element and an oxygen element. For example, the non-magnetic metal element may include at least one of Ta, Ti, Mg, Hf, Zr, W, and Mo.

[0048] The ratio of the thickness T1 of the first oxide pattern 112 to the thickness T2 of the first free pattern FP1 may be different from the ratio of the thickness T3 of the second oxide pattern 110 to the thickness T4 of the second free pattern FP2. In an embodiment, the ratio of the thickness T1 of the first oxide pattern 112 to the thickness T2 of the first free pattern FP1 may be greater than the ratio of the thickness T3 of the second oxide pattern 110 to the thickness T4 of the second free pattern FP2. For example, the ratio of the thickness T1 of the first oxide pattern 112 to the thickness T2 of the first free pattern FP1 may be 1.2:0.8, and the ratio of the thickness T3 of the second oxide pattern 110 to the thickness T4 of the second free pattern FP2 may be 0.8:1.2. The sum ST1 of the thickness T1 of the first oxide pattern 112 and the thickness T2 of the first free pattern FP1 may be equal to the sum ST2 of the thickness T3 of the second oxide pattern 110 and the thickness T4 of the second free pattern FP2.

[0049] The first free pattern FP1 may be in contact with (e.g., may be in direct contact with) the first oxide pattern 112. The second free pattern FP2 may be in contact with (e.g., may be in direct contact with) the second oxide pattern 110. The oxygen concentration of the first oxide pattern 112 may be higher than the oxygen concentration of the second oxide pattern 110. In an embodiment, the oxygen concentration of each of the oxide patterns 110 and 112 may be defined as a value obtained by converting a ratio of the number of oxygen atoms to the total number of atoms in each oxide pattern 110 or 112 into a percentage (e.g., atomic %).

[0050] The tunnel barrier pattern TBP may include, for example, magnesium oxide (MgO), titanium oxide (TiO), aluminum oxide (AlO), magnesium zinc oxide (MgZnO), magnesium boron oxide (MgBO), titanium nitride (TiN), or vanadium nitride (VN). For example, the tunnel barrier pattern TBP may be formed of magnesium oxide (MgO). In an embodiment, the tunnel barrier pattern TBP may include a plurality of layers, each of which may include, for example, magnesium oxide (MgO), titanium oxide (TiO), aluminum oxide (AlO), magnesium zinc oxide (MgZnO), magnesium boron oxide (MgBO), titanium nitride (TiN), or vanadium nitride (VN).

[0051] The pinning pattern RP may include a ferromagnetic material. In an implementation, the pinning pattern RP may include a plurality of layers, and at least one of the plurality of layers may include a ferromagnetic material.

[0052] Figure 5A Shows Figure 4 A cross-sectional view of an example of a magnetic tunnel junction pattern, Figure 5B Shows Figure 4 A cross-sectional view of another example of a magnetic tunnel junction pattern.

[0053] In an embodiment, if Figure 5A As shown in , the free pattern FP1 or FP2 may be a free layer having a changeable magnetization direction a1. The pinning pattern RP may include at least one pinning layer having a magnetization direction b1 fixed in one direction. The magnetization directions a1 and b1 may be substantially perpendicular to a contact surface of the free pattern FP1 or FP2 and the tunnel barrier pattern TBP.

[0054] In this case, the free pattern FP1 or FP2 may have an extrinsic perpendicular magnetization property in which the intrinsic horizontal magnetization property is changed into a perpendicular magnetization property by an external factor. For example, the free pattern FP1 or FP2 may be in contact with the tunnel barrier pattern TBP, and may have an extrinsic perpendicular magnetization property by the magnetic anisotropy caused by the contact of the free pattern FP1 or FP2 with the tunnel barrier pattern TBP. For example, when the tunnel barrier pattern TBP includes MgO and the free pattern FP1 or FP2 includes CoFeB, the magnetic anisotropy may be caused by the combination of the iron (Fe) element of the free pattern FP1 or FP2 and the oxygen of the tunnel barrier pattern TBP. In addition, the free pattern FP1 or FP2 may be in contact with the oxide pattern 112 or 110, and may have an extrinsic perpendicular magnetization property by the magnetic anisotropy caused by the contact of the free pattern FP1 or FP2 with the oxide pattern 112 or 110. For example, when the oxide pattern 112 or 110 includes TaO x And when the free pattern FP1 or FP2 includes CoFeB, magnetic anisotropy may be caused due to the combination of iron (Fe) element of the free pattern FP1 or FP2 and oxygen of the oxide pattern 112 or 110 .

[0055] The pinning pattern RP may include at least one pinning layer having a perpendicular magnetization direction b1. The pinning layer may include a perpendicular magnetic material (eg, CoFeTb, CoFeGd, or CoFeDy), a 0 At least one of a vertical magnetic material having a structure, a CoPt alloy having a hexagonal close-packed (HCP) lattice structure, and a vertical magnetic structure. 0 The vertical magnetic material of the structure may include L1 0 FePt with L1 0 FePd with L1 0 The CoPd structure and the L1 0 The vertical magnetic structure may include at least one of the CoPt of the structure. The vertical magnetic structure may include magnetic layers and non-magnetic layers that are alternately and repeatedly stacked. For example, the vertical magnetic structure may include (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n or (CoCr / Pd)n, where "n" represents the number of double layers.

[0056] In an embodiment, if Figure 5B As shown in , the free pattern FP1 or FP2 may be a free layer having a variable magnetization direction a2. The pinning pattern RP may include at least one pinning layer having a magnetization direction b2 fixed in one direction. The magnetization directions a2 and b2 may be substantially parallel to the contact surface of the free pattern FP1 or FP2 with the tunneling barrier pattern TBP. In this case, for example, the free pattern FP1 or FP2 may have a predetermined thickness capable of providing a horizontal magnetization direction a2. The pinning pattern RP may include at least one pinning layer having a horizontal magnetization direction b2. The pinning layer may include a ferromagnetic material, and may also include an antiferromagnetic material for pinning the magnetization direction of the ferromagnetic material.

[0057] In an embodiment, a ratio of a thickness T1 of the first oxide pattern 112 to a thickness T2 of the first free pattern FP1 may be greater than a ratio of a thickness T3 of the second oxide pattern 110 to a thickness T4 of the second free pattern FP2. In addition, the oxygen concentration of the first oxide pattern 112 may be higher than the oxygen concentration of the second oxide pattern 110. Therefore, the switching characteristics of the first magnetic tunnel junction pattern MTJ1 may be different from the switching characteristics of the second magnetic tunnel junction pattern MTJ2. For example, a switching current that changes the magnetization direction of the first free pattern FP1 of the first magnetic tunnel junction pattern MTJ1 may be different from a switching current that changes the magnetization direction of the second free pattern FP2 of the second magnetic tunnel junction pattern MTJ2. For example, the first magnetic tunnel junction pattern MTJ1 may have a retention characteristic that is higher than the retention characteristic of the second magnetic tunnel junction pattern MTJ2, and the second magnetic tunnel junction pattern MTJ2 may be easier to switch than the first magnetic tunnel junction pattern MTJ1.

[0058] Therefore, the first magnetic tunnel junction pattern MTJ1 located on the first area AR1 and the second magnetic tunnel junction pattern MTJ2 located on the second area AR2 may be used or perform different applications from each other. For example, the first magnetic tunnel junction pattern MTJ1 located on the first area AR1 may be used as Figure 2 The non-volatile memory (NVM) cell MC1 of FIG. 1 , the second magnetic tunnel junction pattern MTJ2 located on the second region AR2 may be used as Figure 2 As a result, without forming different kinds of memory elements on the substrate 100, memory cells performing different functions can be formed on the substrate 100 by adjusting the thicknesses of the first oxide pattern 112 and the second oxide pattern 110 of the magnetic tunnel junction patterns MTJ1 and MTJ2 and the free patterns FP1 and FP2.

[0059] Refer again Figure 4The capping pattern 120 may be located on each of the first oxide pattern 112 and the second oxide pattern 110. The capping pattern 120 may include a metal oxide. For example, the capping pattern 120 may include tantalum oxide, magnesium oxide, titanium oxide, zirconium oxide, hafnium oxide, or zinc oxide.

[0060] The mask pattern 130 may be located on the capping pattern 120. The mask pattern 130 may include a material having a higher oxygen affinity than the capping pattern 120. For example, the mask pattern 130 may include copper, tungsten, titanium, tantalum, aluminum, or a metal nitride (eg, titanium nitride or tantalum nitride).

[0061] The upper interlayer insulating layer 140 may be located on the lower interlayer insulating layer 102 to cover the bottom electrode pattern BEP, the magnetic tunneling junction patterns MTJ1 and MTJ2, and the top electrode pattern TEP. The respective upper contact plugs 150 may penetrate the upper interlayer insulating layer 140 to be connected to the respective top electrode patterns TEP, respectively. The upper interlayer insulating layer 140 may include an oxide layer, a nitride layer, and / or an oxynitride layer, and the upper contact plugs 150 may include a metal (e.g., titanium, tantalum, copper, aluminum, or tungsten) or a conductive metal nitride (e.g., titanium nitride or tantalum nitride). The interconnection line 160 may be located on the upper interlayer insulating layer 140. The interconnection line 160 may be connected to the upper contact plug 150. The interconnection line 160 may include a metal (e.g., titanium, tantalum, copper, aluminum, or tungsten) or a conductive metal nitride (e.g., titanium nitride or tantalum nitride). In an embodiment, the interconnection line 160 may be a bit line.

[0062] Figure 6 A flow chart of a method for fabricating a magnetic memory device according to some embodiments is shown. Figures 7 to 9 Cross-sectional views illustrating stages in a method for fabricating a magnetic memory device according to some embodiments are shown.

[0063] Reference Figure 6 and Figure 7, a lower interlayer insulating layer 102 may be formed on the substrate 100 (including the first region AR1 and the second region AR2). The substrate 100 may include a semiconductor substrate. For example, the substrate 100 may include a silicon substrate, a germanium substrate, or a silicon germanium substrate. In an embodiment, the substrate 100 may be part of a system on chip. In an embodiment, a selection element may be formed on the substrate 100, and a lower interlayer insulating layer 102 may be formed to cover the selection element. The selection element may be a field effect transistor. In an embodiment, the selection element may be a diode. The lower interlayer insulating layer 102 may be formed of a single layer or multiple layers including an oxide layer (e.g., a silicon oxide layer), a nitride layer (e.g., a silicon nitride layer), or a nitride oxide layer (e.g., a silicon nitride oxide layer). A lower contact plug 104 may be formed in the lower interlayer insulating layer 102. Each lower contact plug 104 may penetrate the lower interlayer insulating layer 102 to be electrically connected to one terminal of a corresponding one of the selection elements. The lower contact plug 104 may include a doped semiconductor material (eg, doped silicon), a metal (eg, tungsten, titanium, or tantalum), a conductive metal nitride (eg, titanium nitride, tantalum nitride, or tungsten nitride), or a metal semiconductor compound (eg, metal silicide).

[0064] A bottom electrode layer BEL may be formed on the lower interlayer insulating layer 102. The bottom electrode layer BEL may include a conductive metal nitride such as titanium nitride and / or tantalum nitride. In an embodiment, the bottom electrode layer BEL may include a material (e.g., ruthenium (Ru)) that can assist the crystal growth of a magnetic layer to be formed thereon. The bottom electrode layer BEL may be formed by a sputtering method, a chemical vapor deposition (CVD) method, or an atomic layer deposition (ALD) method.

[0065] A first magnetic layer RL may be formed on the bottom electrode layer BEL (S110). Subsequently, a tunnel barrier layer TBL may be formed on the first magnetic layer RL (S120). A second magnetic layer FL may be formed on the tunnel barrier layer TBL (S130).

[0066] The first magnetic layer RL may include at least one pinned layer having a magnetization direction fixed in one direction. In an embodiment, the magnetization direction of the pinned layer may be substantially perpendicular to the interface between the tunnel barrier layer TBL and the first magnetic layer RL. In this case, the pinned layer may include a perpendicular magnetic material such as CoFeTb, CoFeGd, or CoFeDy, a magnetization direction having L1 0 A vertical magnetic material with a hexagonal close-packed (HCP) lattice structure, a CoPt alloy, or a vertical magnetic structure. 0 The vertical magnetic material of the structure may include L1 0 FePt with L1 0 FePd with L10 CoPd structure and L1 0 At least one of the CoPt of the structure. The perpendicular magnetic structure may include magnetic layers and non-magnetic layers that are alternately and repeatedly stacked. For example, the perpendicular magnetic structure may include (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n or (CoCr / Pd)n, where "n" represents the number of bilayers. In an embodiment, the magnetization direction of the pinned layer may be substantially parallel to the interface between the tunnel barrier layer TBL and the first magnetic layer RL. In this case, the pinned layer may include a ferromagnetic material. The pinned layer may also include an antiferromagnetic material for pinning the magnetization direction of the ferromagnetic material included in the pinned layer.

[0067] The tunnel barrier layer TBL may include, for example, a magnesium oxide (MgO) layer, a titanium oxide (TiO) layer, an aluminum oxide (AlO) layer, a magnesium zinc oxide (MgZnO) layer, or a magnesium boron oxide (MgBO) layer.

[0068] The second magnetic layer FL may be a free layer having a magnetization direction that can be changed to be parallel or anti-parallel to the fixed magnetization direction of the pinned layer. The second magnetic layer FL may include a magnetic material having an intrinsic horizontal magnetization property. The intrinsic horizontal magnetization property may be realized or presented by a single-layer or multi-layer structure including at least one of cobalt (Co), iron (Fe) and any alloy thereof. In an embodiment, the second magnetic layer FL may include, for example, cobalt (Co), iron (Fe) and a first non-metallic element. The first non-metallic element may be, for example, boron (B). For example, the second magnetic layer FL may have a single-layer structure of CoFeB. In an embodiment, the magnetization direction of the second magnetic layer FL may be substantially perpendicular to the interface between the tunnel barrier layer TBL and the second magnetic layer FL. In this case, as described with reference to Figure 5A As described above, the second magnetic layer FL may have an extrinsic perpendicular magnetization property in which the intrinsic horizontal magnetization property is changed into a perpendicular magnetization property by an external factor. Figure 5B As described above, the magnetization direction of the second magnetic layer FL may be substantially parallel to the interface between the tunnel barrier layer TBL and the second magnetic layer FL.

[0069] Each of the first magnetic layer RL, the tunnel barrier layer TBL, and the second magnetic layer FL may be formed by an ALD method, a physical vapor deposition (PVD) method, or a CVD method.

[0070] An oxide layer 110a may be formed on the second magnetic layer FL (S140). The formation of the oxide layer 110a may include forming a metal layer on the second magnetic layer FL and performing an oxidation process on the metal layer to form the oxide layer 110a. The metal layer may be formed using, for example, a sputtering deposition process. The oxidation process may be performed using, for example, a natural oxidation method. The oxide layer 110a may be, for example, tantalum oxide (TaO x In an implementation, at least a portion of the oxide layer 110a may be amorphous.

[0071] A capping layer 120a may be formed on the oxide layer 110a (S150). The capping layer 120a may induce the second magnetic layer FL to have a magnetization direction substantially perpendicular to the top surface of the substrate 100. For example, the second magnetic layer FL may have interface perpendicular magnetic anisotropy (iPMA). The capping layer 120a may include a metal oxide.

[0072] The first hard mask layer 130a may be formed on the capping layer 120a (e.g., a portion of the capping layer 120a) (S160). The first hard mask layer 130a may not be formed on the first region AR1, but may be formed on the second region AR2. The capping layer 120a on the first region AR1 may be exposed (e.g., not covered by the first hard mask layer 130a), and the capping layer 120a on the second region AR2 may be covered by the first hard mask layer 130a. For example, the first hard mask layer 130a may be formed on a partial region or a portion of the substrate 100. The thickness H of the first hard mask layer 130a on the second region AR2 may be about 1000 mm / s. To about The first hard mask layer 130a may be formed using an ALD method, a PVD method, or a CVD method. The formation of the first hard mask layer 130a on a partial region (e.g., the second region AR2) of the substrate 100 may be performed by a selective deposition method, an etching method after deposition, and / or a stripping method. In an embodiment, a photoresist layer may be applied to the entire top surface of the substrate 100, and then a portion of the photoresist layer may be removed by an exposure and development process. Thereafter, a hard mask layer may be deposited, and then the remaining photoresist layer and a portion of the hard mask layer may be removed to form the first hard mask layer 130a.

[0073] The first hard mask layer 130a may include a material having a higher oxygen affinity than the cap layer 120a. For example, the first hard mask layer 130a may include copper, tungsten, titanium, tantalum, aluminum, nitrides thereof, oxides thereof, or borides thereof.

[0074] In an embodiment, forming a first magnetic layer RL on the substrate 100 (S110), forming a tunneling barrier layer TBL on the first magnetic layer RL (S120), forming a second magnetic layer FL on the tunneling barrier layer TBL (S130), forming an oxide layer 110a on the second magnetic layer FL (S140), forming a cap layer 120a on the oxide layer 110a (S150), and forming a first hard mask layer 130a on the cap layer 120a (S160) may be performed in the same chamber.

[0075] Reference Figure 6 and Figure 8 , an oxidation process (S200) may be performed. The oxidation process may be performed by heat treating the substrate 100. At this time, the oxidation process may be performed at a temperature of 50° C. to 600° C. The oxidation process may be performed in an ultra-high vacuum (1E -10 The oxidation process is performed at a pressure of 100 to 200 tor to atmospheric pressure. The interface properties between the oxide layer 110a and the second magnetic layer FL can be controlled by the oxidation process performed at a high temperature. The oxygen atoms Oa in the oxide layer 110a of the first region AR1 diffuse to the interface between the oxide layer 110a and the second magnetic layer FL. The diffusion of oxygen atoms in the oxide layer 110a of the second region AR2 can be suppressed or prevented by the first hard mask layer 130a.

[0076] At this time, oxygen (O 2 ) gas to control the oxygen concentration. For example, the oxygen concentration in the process chamber may be in the range of 0.001% to 100% (eg, volume %). Oxygen (O 2 ) gas to promote the movement of oxygen atoms Oa in the oxide layer 110a of the first region AR1.

[0077] Reference Figure 6 and Fig. 9 , the oxide layer 110a of the first region AR1 (see Figure 8 ) in the oxygen atom Oa (see Figure 8 ) can diffuse, and therefore, the oxide layer 112a of the first region AR1 can be expanded. For example, the size of the second magnetic layer FLa of the first region AR1 can be relatively reduced. For example, the thickness T1 of the oxide layer 112a of the first region AR1 can be increased compared to the thickness T3 of the oxide layer 110a of the second region AR2, and the thickness T2 of the second magnetic layer FLa of the first region AR1 can be reduced compared to the thickness T4 of the second magnetic layer FL of the second region AR2.

[0078] Afterwards, a second hard mask layer 135 may be formed on the first region AR1 and the second region AR2 (S300). The second hard mask layer 135 may be deposited on the cap layer 120a of the first region AR1 and the first hard mask layer 130a of the second region AR2. The second hard mask layer 135 may be formed using an ALD method, a PVD method, or a CVD method. The second hard mask layer 135 may include the same material as that of the first hard mask layer 130a. For example, the second hard mask layer 135 may include copper, tungsten, titanium, tantalum, aluminum, their nitrides, their oxides, or their borides. The second hard mask layer 135 may protect the underlying layers from subsequent processes.

[0079] The oxidation process and the formation of the second hard mask layer 135 may be performed in situ in the same device. The high temperature oxidation process and the formation of the second hard mask layer 135 may be performed under ultra-high vacuum, and thus the high temperature oxidation process and the formation of the second hard mask layer 135 may be performed in situ to constantly maintain the process environment.

[0080] Refer again Figure 4 , after which the first hard mask layer 130a and the second hard mask layer 135 may be planarized, and a conductive mask pattern may be formed on the planarized hard mask layers. For example, the conductive mask pattern may include tungsten, titanium, tantalum, aluminum, or a metal nitride (e.g., titanium nitride or tantalum nitride). The conductive mask pattern may define an area where a magnetic tunneling junction pattern will be formed.

[0081] The planarized hard mask layer, the cap layer 120a, the oxide layers 112a and 110a, the second magnetic layers FLa and FL, the tunneling barrier layer TBL, the first magnetic layer RL, and the bottom electrode layer BEL may be sequentially etched using the conductive mask pattern as an etching mask. The etching process may be performed using an ion beam etching process. The planarized hard mask layer, the cap layer 120a, the oxide layers 112a and 110a, the second magnetic layers FLa and FL, the tunneling barrier layer TBL, the first magnetic layer RL, and the bottom electrode layer BEL may be sequentially etched to form a mask pattern 130, a cap pattern 120, a first oxide pattern 112, and a second oxide pattern 110, free patterns FP1 and FP2, a tunneling barrier pattern TBP, a pinning pattern RP, and a bottom electrode pattern BEP, respectively. After the etching process, the conductive mask pattern may be defined as a top electrode pattern TEP.

[0082] The pinning pattern RP, the tunneling barrier pattern TBP, the first free pattern FP1, and the first oxide pattern 112 on the first region AR1 may constitute a first magnetic tunneling junction pattern MTJ1. The pinning pattern RP, the tunneling barrier pattern TBP, the second free pattern FP2, and the second oxide pattern 110 on the second region AR2 may constitute a second magnetic tunneling junction pattern MTJ2. The ratio of the thickness T1 of the first oxide pattern 112 to the thickness T2 of the first free pattern FP1 may be greater than the ratio of the thickness T3 of the second oxide pattern 110 to the thickness T4 of the second free pattern FP2. In addition, the oxygen concentration of the first oxide pattern 112 may be higher than the oxygen concentration of the second oxide pattern 110. Therefore, the switching characteristics of the first magnetic tunneling junction pattern MTJ1 may be different from the switching characteristics of the second magnetic tunneling junction pattern MTJ2. For example, the switching current that changes the magnetization direction of the first free pattern FP1 of the first magnetic tunneling junction pattern MTJ1 may be different from the switching current that changes the magnetization direction of the second free pattern FP2 of the second magnetic tunneling junction pattern MTJ2.

[0083] Fig. 10A and Fig. 10B A graph presenting characteristics of a first magnetic tunnel junction pattern MTJ1 and a second magnetic tunnel junction pattern MTJ2 according to some embodiments is shown. Fig. 10A 1 and 2 show a tunneling magnetoresistance ratio (TMR) of the first magnetic tunneling junction pattern MTJ1 and the second magnetic tunneling junction pattern MTJ2. Fig. 10B 2 shows the coercive force Hc of the first magnetic tunnel junction pattern MTJ1 and the second magnetic tunnel junction pattern MTJ2. Fig. 10A and Fig. 10B , the tunneling magnetoresistance ratios of the first magnetic tunneling junction pattern MTJ1 and the second magnetic tunneling junction pattern MTJ2 may be equal to each other, but the first magnetic tunneling junction pattern MTJ1 may have a higher retention characteristic than that of the second magnetic tunneling junction pattern MTJ2. For example, the second magnetic tunneling junction pattern MTJ2 may be easier to switch than the first magnetic tunneling junction pattern MTJ1.

[0084] Therefore, the first magnetic tunnel junction pattern MTJ1 on the first area AR1 and the second magnetic tunnel junction pattern MTJ2 on the second area AR2 can be used as different applications or perform functions different from each other. For example, the first magnetic tunnel junction pattern MTJ1 on the first area AR1 can be used as a non-volatile memory (NVM) cell, and the second magnetic tunnel junction pattern MTJ2 on the second area AR2 can be used as a random access memory (RAM) cell. As a result, memory cells performing different functions can be formed on the substrate 100 only by adjusting the thickness of the first oxide pattern 112 and the second oxide pattern 110 of the magnetic tunnel junction patterns MTJ1 and MTJ2 and the free patterns FP1 and FP2, without having to form different kinds of memory elements on the substrate 100.

[0085] Each bottom electrode pattern BEP may be electrically connected to a corresponding one of the lower contact plugs 104 in the lower interlayer insulating layer 102. Each of the magnetic tunnel junction patterns MTJ1 and MTJ2 may be formed between the bottom electrode pattern BEP and the top electrode pattern TEP.

[0086] The upper interlayer insulating layer 140 may be formed on the lower interlayer insulating layer 102 to cover the bottom electrode pattern BEP, the magnetic tunneling junction patterns MTJ1 and MTJ2, and the top electrode pattern TEP. The upper contact plug 150 may be formed in the upper interlayer insulating layer 140. Each upper contact plug 150 may penetrate the upper interlayer insulating layer 140 to be connected to each top electrode pattern TEP, respectively. The upper interlayer insulating layer 140 may include an oxide layer, a nitride layer, and / or an oxynitride layer, and the upper contact plug 150 may include a metal (e.g., titanium, tantalum, copper, aluminum, or tungsten) or a conductive metal nitride (e.g., titanium nitride or tantalum nitride). The interconnection line 160 may be formed on the upper interlayer insulating layer 140. The interconnection line 160 may be connected to the upper contact plug 150. The interconnection line 160 may include a metal (e.g., titanium, tantalum, copper, aluminum, or tungsten) or a conductive metal nitride (e.g., titanium nitride or tantalum nitride). In an implementation, the interconnect line 160 may be a bit line.

[0087] Fig.11 Shown is the method for executing Figure 6 Schematic diagram of an embodiment of a substrate processing apparatus for an oxidation process and a deposition process of a second hard mask layer. Fig.12 Shows Fig.11 A schematic diagram of a first process chamber, Fig.13 Shows Fig.11 Schematic diagram of the second process chamber.

[0088] Reference Fig.11 The substrate processing equipment 2 may include an indexing module 200 , a conveying module 300 , a first process chamber 400 , and a second process chamber 500 .

[0089] The transfer module 200 may include a guide rail 210 and a substrate transfer unit 220. The guide rail 210 may extend in one direction. The substrate transfer unit 220 may include a first support shaft 222, a first arm 224, and a first substrate support 226. The first support shaft 222 may be coupled to the guide rail 210. The first arm 224 may connect the first support shaft 222 and the first substrate support 226. The first substrate support 226 may support a substrate. The transfer module 200 may introduce a substrate from another device and / or another substrate transfer unit outside the substrate processing device 2 / output a substrate to another device and / or another substrate transfer unit outside the substrate processing device 2. In an embodiment, the transfer module 200 may include an equipment front end module (EFEM) and / or a loading port (roadport).

[0090] The conveying module 300 may be adjacent to the indexing module 200. The conveying module 300 may include a second substrate conveying unit 320. The second substrate conveying unit 320 may include a second supporting shaft 322, a second arm 324, and a second substrate supporting portion 326. The second arm 324 may connect the second supporting shaft 322 and the second substrate supporting portion 326. The second substrate supporting portion 326 may support the substrate. The conveying module 300 may convey the substrate among the indexing module 200, the first process chamber 400, and the second process chamber 500. In an embodiment, a load lock chamber may be provided between the conveying module 300 and the indexing module 200.

[0091] Reference Fig.11 and Fig.12 , the first process chamber 400 may be located at one side of the delivery module 300. The first process chamber 400 may include a first chamber body 410, a first support part 420, a heater 430, a gas supply part 440, and a shower head 450. The first chamber body 410 may provide an inner space 405 in which an oxidation process is performed. The substrate may be loaded on a top surface of the first support part 420. The first support part 420 may be an electrostatic chuck. The first support part 420 may be coupled to the first chamber body 410 by a support shaft 422. A heater 430 may be provided in the first support part 420.

[0092] The gas supply part 440 may be configured to supply a process gas into the inner space 405. For example, the process gas may be oxygen. The oxygen in the gas supply part 440 may be supplied to the gas supply hole 446 through the gas supply line 442. The gas supply hole 446 may be in one side of the first chamber body 410. The gas supply valve 444 may open or close the gas supply line 442.

[0093] The shower head 450 may face the top surface of the first support part 420. The shower head 450 may include a hole 452. The process gas may be uniformly supplied into the inner space 405 through the shower head 450. In an embodiment, the first process chamber 400 may include an additional process gas supply part and / or an RF power supply unit.

[0094] Reference Fig.11 and Fig.13 , the second process chamber 500 may be located at the other side of the conveying module 300. The second process chamber 500 may include a second chamber body 510, a second support portion 520, a cooler 530, and target portions 540a and 540b. The second chamber body 510 may provide an inner space 505 in which a deposition process of the second hard mask layer is performed. The substrate may be loaded on the top surface of the second support portion 520. The second support portion 520 may be an electrostatic chuck. The second support portion 520 may be coupled to the second chamber body 510 by a support shaft 522. A cooler 530 may be provided in the second support portion 520.

[0095] The second hard mask layer may be deposited by, for example, a sputtering process. The sputtering process may be a radio frequency (RF) sputtering process using at least one target portion. In an embodiment, referring to Fig.13 , the RF sputtering process may be performed using the plurality of target portions 540a and 540b. In an embodiment, different kinds of deposition processes may be performed.

[0096] The first process chamber 400 and the second process chamber 500 may share the same conveying module 300. Therefore, the oxidation process and the formation of the second hard mask layer may be performed in situ in the same device. The high-temperature oxidation process and the formation of the second hard mask layer may be performed under ultra-high vacuum, and thus the constancy of the process environment may be maintained by the in-situ device. Figures 11 to 13 , components and arrangement of the first process chamber and the second process chamber are shown as examples. In an embodiment, components and arrangement of the first process chamber and the second process chamber for performing an oxidation process and a deposition process may be variously modified.

[0097] Fig.14 A circuit diagram showing a memory cell array of a magnetic memory device according to some embodiments, Fig.15 1 shows a cross-sectional view of a magnetic memory device according to some embodiments. In the following, for the purpose of easy and convenient explanation, the above Figure 2 and Figure 4 The description of the elements that are the same or similar to the elements in the embodiments.

[0098] The substrate 100 may include a first region AR1, a second region AR2, and a third region AR3. The third magnetic tunnel junction pattern MTJ3 may be located on the third region AR3. The third magnetic tunnel junction pattern MTJ3 may include a pinning pattern RP, a third free pattern FP3, a tunnel barrier pattern TBP located between the pinning pattern RP and the third free pattern FP3, and a third oxide pattern 114. The third free pattern FP3 may be located between the tunnel barrier pattern TBP and the top electrode pattern TEP on the third region AR3, and the pinning pattern RP may be located between the tunnel barrier pattern TBP and the bottom electrode pattern BEP on the third region AR3. The third oxide pattern 114 may be spaced apart from the tunnel barrier pattern TBP, and the third free pattern FP3 may be disposed between the third oxide pattern 114 and the tunnel barrier pattern TBP. The third oxide pattern 114 may be located between the third free pattern FP3 and the top electrode pattern TEP.

[0099] The third oxide pattern 114 may include a metal oxide. The third oxide pattern 114 may include a non-magnetic metal element and an oxygen element. For example, the non-magnetic metal element may include Ta, Ti, Mg, Hf, Zr, W, or Mo.

[0100] The ratio of the thickness T5 of the third oxide pattern 114 to the thickness T6 of the third free pattern FP3 may be different from the ratio of the thickness T1 of the first oxide pattern 112 to the thickness T2 of the first free pattern FP1, and different from the ratio of the thickness T3 of the second oxide pattern 110 to the thickness T4 of the second free pattern FP2. The ratio of the thickness T5 of the third oxide pattern 114 to the thickness T6 of the third free pattern FP3 may be smaller than the ratio of the thickness T1 of the first oxide pattern 112 to the thickness T2 of the first free pattern FP1, and may be greater than the ratio of the thickness T3 of the second oxide pattern 110 to the thickness T4 of the second free pattern FP2. For example, the ratio of the thickness T1 of the first oxide pattern 112 to the thickness T2 of the first free pattern FP1 may be 1.2:0.8, the ratio of the thickness T3 of the second oxide pattern 110 to the thickness T4 of the second free pattern FP2 may be 0.8:1.2, and the ratio of the thickness T5 of the third oxide pattern 114 to the thickness T6 of the third free pattern FP3 may be 1.1:0.9. The sum ST3 of the thickness T5 of the third oxide pattern 114 and the thickness T6 of the third free pattern FP3 may be equal to the sum ST1 of the thickness T1 of the first oxide pattern 112 and the thickness T2 of the first free pattern FP1 and equal to the sum ST2 of the thickness T3 of the second oxide pattern 110 and the thickness T4 of the second free pattern FP2.

[0101] The third free pattern FP3 may contact (eg, may directly contact) the third oxide pattern 114. The oxygen concentration of the third oxide pattern 114 may be lower than that of the first oxide pattern 112, and may be higher than that of the second oxide pattern 110. Here, the oxygen concentration of each of the oxide patterns 112, 110, and 114 may be defined as a value obtained by converting a ratio of the number of oxygen atoms to the total number of atoms in each oxide pattern 112, 110, or 114 into a percentage.

[0102] Therefore, the switching characteristics of the first magnetic tunnel junction pattern MTJ1, the second magnetic tunnel junction pattern MTJ2, and the third magnetic tunnel junction pattern MTJ3 may be different from each other. For example, the switching currents of the first free pattern FP1, the second free pattern FP2, and the third free pattern FP3 that respectively change the magnetization directions of the first magnetic tunnel junction pattern MTJ1, the second magnetic tunnel junction pattern MTJ2, and the third magnetic tunnel junction pattern MTJ3 may be different from each other. For example, the first magnetic tunnel junction pattern MTJ1 may have a retention characteristic higher than that of the second magnetic tunnel junction pattern MTJ2, and the second magnetic tunnel junction pattern MTJ2 may be easier to switch than the first magnetic tunnel junction pattern MTJ1. The third magnetic tunnel junction pattern MTJ3 may have a retention characteristic higher than that of the second magnetic tunnel junction pattern MTJ2, and the second magnetic tunnel junction pattern MTJ2 may be easier to switch than the third magnetic tunnel junction pattern MTJ3. The first magnetic tunnel junction pattern MTJ1 may have a higher retention characteristic than that of the third magnetic tunnel junction pattern MTJ3 , and the third magnetic tunnel junction pattern MTJ3 may be more easily switched than the first magnetic tunnel junction pattern MTJ1 .

[0103] Therefore, the first magnetic tunnel junction pattern MTJ1 located on the first area AR1, the second magnetic tunnel junction pattern MTJ2 located on the second area AR2, and the third magnetic tunnel junction pattern MTJ3 located on the third area AR3 may be used for different applications or may perform functions different from each other. For example, the first magnetic tunnel junction pattern MTJ1 located on the first area AR1 may be used as Fig.14 The non-volatile memory (NVM) cell MC1 of FIG. 1 , the second magnetic tunnel junction pattern MTJ2 located on the second region AR2 may be used as Fig.14 The static random access memory (SRAM) cell MC2 of the embodiment of the present invention, the third magnetic tunnel junction pattern MTJ3 located on the third region AR3 can be used as Fig.14As a result, memory cells performing different functions can be formed on the substrate 100 only by adjusting the thickness of the oxide patterns 112, 110 and 114 of the magnetic tunnel junction patterns MTJ1, MTJ2 and MTJ3 and the free patterns FP1, FP2 and FP3, without having to form different kinds of memory elements on the substrate 100.

[0104] Figures 16 to 18 Shown for manufacturing Fig.15 sectional views of various stages in a method of a magnetic memory device. In the following, for the purpose of ease and convenience of explanation, the above Figures 6 to 9 For example, the manufacturing method according to the present embodiment may include forming a first magnetic layer RL on the substrate 100 (S110), forming a tunneling barrier layer TBL on the first magnetic layer RL (S120), forming a second magnetic layer FL on the tunneling barrier layer TBL (S130), forming an oxide layer 110a on the second magnetic layer FL (S140), and forming a cap layer 120a on the oxide layer 110a (S150) as described in the above embodiments.

[0105] Reference Fig.16 , the first hard mask layer 130a may be formed on the cap layer 120a (e.g., a portion of the cap layer 120a). The first hard mask layer 130a may not be formed on the first region AR1, but may be formed on the second region AR2 and the third region AR3. The cap layer 120a on the first region AR1 may be exposed, and the cap layer 120a on the second region AR2 and the third region AR3 may be covered by the first hard mask layer 130a. For example, the first hard mask layer 130a may be formed on a partial region of the substrate 100. The first hard mask layer 130a may be formed using an ALD method, a PVD method, or a CVD method.

[0106] The first hard mask layer 130a on the second region AR2 may have a first thickness H1, and the first hard mask layer 130a on the third region AR3 may have a second thickness H2. The first thickness H1 may be greater than the second thickness H2. For example, the first thickness H1 may be greater than to In the range of to The thickness of the first hard mask layer 130a may be controlled by a selective deposition method, an etching method after deposition, and / or a stripping method. In the stripping method, a photoresist layer may be coated on the entire top surface of the substrate 100, and then a portion of the photoresist layer may be removed by an exposure and development process. Afterwards, a hard mask layer may be deposited, and then the remaining photoresist layer and a portion of the hard mask layer may be removed to form the first hard mask layer 130a.

[0107] Reference Fig.17 , an oxidation process may be performed. The oxidation process may be performed by heat treating the substrate 100. At this time, the oxidation process may be performed at a temperature of 50° C. to 600° C. The oxidation process may be performed in an ultra-high vacuum (1E -10 The oxidation process is performed at a pressure of 100 to 200 tor to atmospheric pressure. The oxygen atoms Oa in the oxide layer 110a of the first region AR1 may diffuse to the interface between the oxide layer 110a and the second magnetic layer FL through the high-temperature oxidation process. In addition, the diffusion of oxygen atoms in the oxide layer 110a of the second region AR2 may be suppressed or prevented by the first hard mask layer 130a. The oxygen atoms Ob in the oxide layer 110a of the third region AR3 may diffuse to the interface between the oxide layer 110a and the second magnetic layer FL. Due to the first hard mask layer 130a of the third region AR3, the amount of diffused oxygen atoms Ob in the third region AR3 may be less than the amount of diffused oxygen atoms Oa in the first region AR1.

[0108] At this time, oxygen (O 2 ) gas to control the oxygen concentration. For example, the oxygen concentration in the process chamber may be in the range of 0.001% to 100% (eg, volume %). Oxygen (O 2 ) gas to promote the movement of oxygen atoms.

[0109] Reference Fig.18 , the oxygen atoms Oa of the first region AR1 (see Fig.17 ) can diffuse, and thus the oxide layer 112a of the first region AR1 can be expanded. Therefore, the second magnetic layer FLa of the first region AR1 can be relatively reduced. The oxygen atoms Ob (see Fig.17) may diffuse, and therefore, the oxide layer 114a of the third region AR3 may also be expanded. Therefore, the second magnetic layer FLb of the third region AR3 may be relatively reduced. For example, the thickness T1 of the oxide layer 112a of the first region AR1 may be increased compared to the thickness T3 of the oxide layer 110a of the second region AR2, and the thickness T2 of the second magnetic layer FLa of the first region AR1 may be reduced compared to the thickness T4 of the second magnetic layer FL of the second region AR2. The thickness T5 of the oxide layer 114a of the third region AR3 may be increased compared to the thickness T3 of the oxide layer 110a of the second region AR2, and the thickness T6 of the second magnetic layer FLb of the third region AR3 may be reduced compared to the thickness T4 of the second magnetic layer FL of the second region AR2. The thickness T5 of the oxide layer 114a of the third region AR3 may be smaller than the thickness T1 of the oxide layer 112a of the first region AR1, and the thickness T6 of the second magnetic layer FLb of the third region AR3 may be greater than the thickness T2 of the second magnetic layer FLa of the first region AR1.

[0110] Thereafter, a second hard mask layer 135 may be formed on the first region AR1, the second region AR2, and the third region AR3. The second hard mask layer 135 may be deposited on the cap layer 120a of the first region AR1 and the first hard mask layer 130a of the second region AR2 and the third region AR3. The second hard mask layer 135 may be formed using an ALD method, a PVD method, or a CVD method. The second hard mask layer 135 may include the same material as that of the first hard mask layer 130a. Thereafter, the planarization process and the patterning process described above may be performed to form Fig.15 Magnetic tunnel junction patterns MTJ1, MTJ2 and MTJ3.

[0111] By way of summary and review, highly integrated and / or low power consumption magnetic memory devices may be desirable in the electronics industry. Therefore, research may be conducted to meet these characteristics.

[0112] One or more embodiments may provide a magnetic memory device including a magnetic tunnel junction pattern that can be used for different applications in different regions.

[0113] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art as of the filing of this application, unless otherwise specifically noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A magnetic memory device, include: a substrate including a first memory region and a second memory region; a first magnetic tunnel junction pattern located on the first memory region, the first magnetic tunnel junction pattern comprising a first free pattern and a first oxide pattern located on the first free pattern; as well as a second magnetic tunnel junction pattern located on the second memory region, the second magnetic tunnel junction pattern comprising a second free pattern and a second oxide pattern located on the second free pattern, wherein a ratio of a thickness of the first oxide pattern to a thickness of the first free pattern is different from a ratio of a thickness of the second oxide pattern to a thickness of the second free pattern, The first oxide pattern is thicker than the second oxide pattern, and both the first free pattern and the second free pattern are free layers with a changeable magnetization direction.

2. The magnetic memory device according to claim 1, in, A sum of a thickness of the first oxide pattern and a thickness of the first free pattern is equal to a sum of a thickness of the second oxide pattern and a thickness of the second free pattern.

3. The magnetic memory device according to claim 1, in, A ratio of a thickness of the first oxide pattern to a thickness of the first free pattern is greater than a ratio of a thickness of the second oxide pattern to a thickness of the second free pattern.

4. The magnetic memory device according to claim 3, in: The first magnetic tunneling junction pattern defines a first memory cell of the first memory region, The second magnetic tunnel junction pattern defines a second memory cell of the second memory region, The first memory cell is a non-volatile memory cell, and The second memory cell is a random access memory cell.

5. The magnetic memory device according to claim 1, in: The first free pattern is in contact with the first oxide pattern, and The second free pattern contacts the second oxide pattern.

6. The magnetic memory device according to claim 1, in, The first oxide pattern has an oxygen concentration higher than that of the second oxide pattern.

7. The magnetic memory device according to claim 1, in, The substrate further includes a third memory region, and the magnetic memory device further includes: a third magnetic tunnel junction pattern located on the third memory region, the third magnetic tunnel junction pattern comprising a third free pattern and a third oxide pattern located on the third free pattern, Wherein, the ratio of the thickness of the third oxide pattern to the thickness of the third free pattern is: is different from a ratio of a thickness of the first oxide pattern to a thickness of the first free pattern, and Different from a ratio of a thickness of the second oxide pattern to a thickness of the second free pattern.

8. The magnetic memory device according to claim 7, in, Ratio of the thickness of the third oxide pattern to the thickness of the third free pattern: is smaller than a ratio of a thickness of the first oxide pattern to a thickness of the first free pattern, and is greater than a ratio of a thickness of the second oxide pattern to a thickness of the second free pattern.

9. The magnetic memory device according to claim 7, in, The sum of the thickness of the third oxide pattern and the thickness of the third free pattern: is equal to the sum of the thickness of the first oxide pattern and the thickness of the first free pattern, and is equal to the sum of the thickness of the second oxide pattern and the thickness of the second free pattern.

10. The magnetic memory device according to claim 7, in, Oxygen concentration of the third oxide pattern: is lower than the oxygen concentration of the first oxide pattern, and higher than the oxygen concentration of the second oxide pattern.

11. The magnetic memory device according to claim 7, in: The first magnetic tunneling junction pattern defines a first memory cell of the first memory region, The second magnetic tunnel junction pattern defines a second memory cell of the second memory region, The third magnetic tunnel junction pattern defines a third memory cell of the third memory region, The first memory cell is a non-volatile memory cell, The second memory cell is a static random access memory cell, and The third memory cell is a dynamic random access memory cell.

12. The magnetic memory device according to claim 1, in: The first free pattern comprises CoFeB, and The second free pattern includes CoFeB.

13. A method for manufacturing a magnetic memory device, the method include: forming a magnetic layer on a substrate, the substrate having a first memory region and a second memory region; forming an oxide layer on the magnetic layer; forming a capping layer on the oxide layer; forming a first hard mask layer on the cap layer of the second memory region; as well as performing an oxidation process to control the interface properties between the oxide layer and the magnetic layer, Wherein, performing the oxidation process comprises: forming a first magnetic tunnel junction pattern of the first memory region, the first magnetic tunnel junction pattern comprising a first free pattern and a first oxide pattern located on the first free pattern; and forming a second magnetic tunneling junction pattern of the second memory region, the second magnetic tunneling junction pattern comprising a second free pattern and a second oxide pattern located on the second free pattern, The first oxide pattern is thicker than the second oxide pattern, and both the first free pattern and the second free pattern are free layers with a changeable magnetization direction.

14. The method according to claim 13, in, Oxygen atoms in the oxide layer diffuse to the interface between the oxide layer and the magnetic layer during the oxidation process to control the interface property between the oxide layer and the magnetic layer.

15. The method according to claim 13, in, Performing the oxidation process includes supplying oxygen to control oxygen concentration in the process chamber.

16. The method according to claim 15, in, The oxygen concentration is in the range of 0.001% to 100%.

17. The method according to claim 13, further comprising: include: After performing the oxidation process, a second hard mask layer is formed on the capping layer of the first memory region and the first hard mask layer.

18. The method according to claim 17, in, The oxidation process and the formation of the second hard mask layer are performed in-situ in the same tool.

19. The method according to claim 17, in: performing the oxidation process in a first process chamber, and Forming the second hard mask layer is performed in a second process chamber that shares a transfer module with the first process chamber.

20. The method according to claim 13, in, The first hard mask layer includes copper, tantalum, titanium or tungsten.

21. The method according to claim 13, in, The oxidation process is performed at a temperature of 50°C to 600°C.

22. The method according to claim 13, in, The substrate also has a third memory area, Forming the first hard mask layer includes: forming the first hard mask layer on the cap layer of the third memory region, A first hard mask layer located on the second memory region has a first thickness, and The first hard mask layer located on the third memory region has a second thickness different from the first thickness.

23. The method according to claim 22, in, The first thickness is greater than the second thickness.

24. The method according to claim 23, in: The first thickness is to within the range of The second thickness is to within the range.

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