Semiconductor device

Abstract

A semiconductor device includes a semiconductor layer. A gate structure is located on the semiconductor layer. A spacer is located on a sidewall of the gate structure. The spacer has a height greater than a height of the gate structure. A liner layer is located on the gate structure and the spacer. The spacer and the liner layer are of different material compositions.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to methods of fabricating semiconductor devices, and more particularly to methods of fabricating semiconductor devices with metal gates. BACKGROUND

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in semiconductor integrated circuit materials, design, and manufacturing have produced increasingly sophisticated devices. However, these advances have increased the complexity of processing and manufacturing semiconductor integrated circuits. These processing and manufacturing problems, which have become more difficult with advances in device complexity, could have serious economic impacts, such as reduced yield, increased costs, and the like.

[0003] Geometric shrinking presents challenges in fabricating semiconductor devices. For example, geometric shrinking can cause loading concerns due to the different sizes of the components. For example, loading concerns can cause additional gate height loss in transistors. Once the gate height is lost, device performance is degraded and the device can even fail.

[0004] While existing semiconductor devices and methods of fabricating the same generally function for their intended purposes, there are needs for improvements in all respects. SUMMARY

[0005] One embodiment of the present application provides a semiconductor device, comprising: a semiconductor layer; a gate structure on the semiconductor layer; a spacer on a sidewall of the gate structure, wherein the spacer has a height greater than a height of the gate structure; and a liner layer on the gate structure and the spacer, wherein the spacer and the liner layer have different material compositions.

[0006] One embodiment of the present application provides a semiconductor device, comprising: a semiconductor layer; a gate structure on the semiconductor layer; a spacer on a sidewall of the gate structure; an interlayer dielectric layer adjacent to the spacer, wherein the spacer is between the interlayer dielectric layer and the gate structure; and a dielectric structure on the gate structure, wherein the dielectric structure comprises a first portion and a second portion on the first portion, a first dielectric constant of the first portion is less than a second dielectric constant of the second portion, and the second dielectric constant is greater than about 4.

[0007] An embodiment of the present invention provides a method for fabricating a semiconductor device, comprising: providing a semiconductor device including: a source and a drain; a semiconductor structure located between the source and the drain; a first metal layer located on the semiconductor structure; an interlayer dielectric layer located on the source and the drain; and a spacer located between the interlayer dielectric layer and the first metal layer; performing one or more etching processes to form an opening in the semiconductor device, wherein the upper surface of the first metal layer, the upper surface and side surface of the spacer, and the side surface of the interlayer dielectric layer define the opening; forming a pad layer to partially fill the opening, wherein the pad layer has a first material composition; forming a dielectric material on the pad layer, wherein a second material composition of the dielectric material is different from the first material composition; and performing a second etching process to remove the dielectric material, wherein the etching rate of the dielectric material is greater than the etching rate of the pad layer, such that the pad layer at least protects the spacer from etching during the second etching process. Attached Figure Description

[0008] Figure 1 This is a perspective view of a fin field-effect transistor device in one example.

[0009] Figures 2A-33A , Figures 2B-33B , Figures 2C-33C ,and Figures 2D-33D These are cross-sectional views of various stages in the fabrication of a semiconductor device according to various embodiments of the present invention.

[0010] Figure 34 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0011] Figures 35A-41A , Figures 35B-41B , Figures 35C-41C ,and Figures 35D-41D This is a cross-sectional view of various stages in the fabrication of a semiconductor device according to one embodiment of the present invention.

[0012] Figures 42A-46A This is a cross-sectional view of various stages in the fabrication of a semiconductor device according to one embodiment of the present invention.

[0013] Figure 47 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0014] Explanation of reference numerals in the attached figures:

[0015] 10. Fin Field-Effect Transistor Device Structure

[0016] 12. Epitaxial Growth Materials

[0017] 15 n-type fin field-effect transistor device structure

[0018] 25p Fin Field-Effect Transistor Device Structure

[0019] 52 substrate

[0020] 54, 110A, 110B, 110C, 110D fin structure

[0021] 55, 150A, 150B, 150C, 150D spacer

[0022] 58 isolation structure

[0023] 60 gate

[0024] 62, 64 hard mask layer

[0025] 65, 210A, 210B, 210C, 210D, 220A, 220B, 220C, 220D, 230A, 250A, 250B, 250C, 250D, 330A, 330B, 330C, 330D, 400A, 400B, 400C, 400D, 420A, 420B, 420C, 420D, 450A, 450B, 450C, 450D, 520B, 520C, 520D dielectric layer

[0026] 100A, 100B, 100C, 100D fin field effect transistor device

[0027] 120A, 120B, 120C, 120D source / drain region

[0028] 125A, 125B, 125C, 125D distance

[0029] 130A, 130B, 130C, 130D, 460A, 460B, 460C, 460D interlayer dielectric layer

[0030] 140A, 140B, 140C, 140D work function metal layer

[0031] 150A-L lower side component

[0032] 150A-U upper side component

[0033] 160A, 160B, 160C, 160D, 380A metal layer

[0034] 170A, 170B, 170C, 170D, 270A, 270B, 270C, 270D gate height

[0035] 180C, 180D, 240A, 240B, 240C, 240D opening

[0036] 235, 300, 350, 530 etching process

[0037] 245A, 245B, 245C, 245D lateral dimension

[0038] 310A, 310B, 310C, 310D, 360A recess

[0039] 320A, 320B, 320C, 320D, 340A, 340B, 340C, 340D vertical dimension

[0040] 370A, 370B, 370C, 370D, 410A, 410B, 410C, 410D, 570A, 585A, 590A, 591A, 592A height

[0041] 400A-L lower portion

[0042] 400A-U upper portion

[0043] 440A, 440B, 440C, 440D source / drain contact

[0044] 500 deposition process

[0045] 510A, 510B, 510C, 510D liner layer

[0046] 540A depth

[0047] 550A, 580A, 595A dielectric material

[0048] 560 etch-back process

[0049] 600, 800 method

[0050] 610, 620, 630, 640, 650, 660, 670, 680, 690, 810, 820, 830, 840, 850 step DETAILED DESCRIPTION

[0051] The following detailed description provides different embodiments or examples of the application. The described embodiments and examples are not meant to limit the application. For example, the description of forming a first member on a second member includes embodiments where the two are in direct contact, or embodiments where additional members are between the two. Also, the various embodiments of the application can be repeated with the same reference numerals for the sake of brevity, but the elements having the same reference numerals in the various embodiments and / or aspects need not necessarily have the same corresponding relationship. Furthermore, the various structures can be drawn to scale to simplify the drawings and make the drawings clear.

[0052] Furthermore, a relative term such as "below" or "beneath" or "lower" or "above" or "upper" or the like can be used in this specification to describe a relationship of one element to another element as illustrated in the figures. Such relative terms can be extended to encompass different orientations in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as below or beneath other elements would then be above or on top of the other elements. The exemplary term "below" can, therefore, encompass both an orientation of above and below. The elements can be oriented in any orientation using the absolute terms such as front, back, top, bottom, left, right, etc. and the relative terms can be used independently of the absolute terms.

[0053] Furthermore, when a numerical value or a range of values is described as "about," "approximately," or the like, unless otherwise specified, it includes + / - 10% of the stated value. For example, the term "about 5 nm" includes a range of values between 4.5 nm and 5.5 nm.

[0054] Embodiments of the present application relate to, but are not limited to, methods of fabricating semiconductors, such as methods of fabricating semiconductor devices with metal gates. To illustrate various embodiments of the present application, the following description will use the fabrication of fin field effect transistors as a non-limiting example. Fin field effect transistor devices are becoming increasingly popular in the semiconductor industry. Fin field effect transistor devices can be complementary metal oxide semiconductor devices, including p-type metal oxide semiconductor fin field effect transistor devices and n-type metal oxide semiconductor fin field effect transistor devices. The following description will illustrate various embodiments of the present application using one or more fin field effect transistors as an example, but it should be understood that embodiments of the present application are not limited to fin field effect transistor devices unless the claims specifically recite. In other words, various embodiments of the present application can also be applied to fabricating two-dimensional planar transistors.

[0055] Figure 1 FIG. 1 is an example of a perspective view of a fin field effect transistor device structure 10. The fin field effect transistor device structure 10 includes an n-type fin field effect transistor device structure 15 and a p-type fin field effect transistor device structure 25. The fin field effect transistor device structure 10 includes a substrate 52. The substrate 52 can be composed of silicon or other semiconductor material. In other embodiments or additional embodiments, the substrate 52 can include other semiconductor material elements such as germanium. In some embodiments, the substrate 52 is composed of a semiconductor compound such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 52 is composed of a semiconductor alloy such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide. In some embodiments, the substrate 52 includes an epitaxial layer. For example, the substrate 52 can include an epitaxial layer on a bulk semiconductor.

[0056] The finfet device structure 10 also includes one or more fin structures 54 (e.g., silicon fins) extending from the substrate 52 in the Z direction, and spacers 55 between the fin structures 54 in the Y direction. The fin structures 54 are elongated in the x direction, and can optionally contain germanium. The method of forming the fin structures 54 can employ suitable processes such as photolithography and etching processes. In some embodiments, the fin structures 54 are etched from the substrate 52 using a dry etching or plasma process. In some other embodiments, the method of forming the fin structures 54 can be a double patterning process. Double patterning divides a pattern into two interlaced patterns to create a pattern on a substrate. Double patterning can increase the density of structures (e.g., fins). The fin structures 54 also include the epitaxially grown material 12, which can be along portions of the fin structures 54 and serve as the source / drain of the finfet device structure 10.

[0057] An isolation structure 58, such as a shallow trench isolation structure, is formed to surround the fin structures 54. In some embodiments, the isolation structure 58 surrounds the lower portion of the fin structures 54, while the upper portion of the fin structures 54 is protruding from the isolation structure 58, as shown in Figure 1 In other words, a portion of the fin structures 54 is embedded in the isolation structure 58. The isolation structure 58 prevents electrical interference or crosstalk.

[0058] The finfet device structure 10 also includes a gate stack structure, which includes a gate 60 and a gate dielectric layer (not shown) under the gate 60. The gate 60 can include polysilicon or metal. The metal includes tantalum nitride, nickel silicide, cobalt silicide, molybdenum, copper, tungsten, aluminum, cobalt, zirconium, platinum, or other possible materials. The method of forming the gate 60 can be a gate-last process (or gate replacement process). Hard mask layers 62 and 64 can be used to define the gate 60. A dielectric layer 65 can also be formed on the sidewalls of the gate 60 and on the hard mask layers 62 and 64.

[0059] The gate dielectric layer (not shown) can include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, or a combination thereof. Examples of the high-k dielectric material include hafnium oxide, zirconium oxide, aluminum oxide, hafnium-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, the like, or a combination thereof.

[0060] In some embodiments, the gate stack structure includes additional layers such as an interface layer, a cap layer, a diffusion barrier layer, or other possible layers. In some embodiments, the gate stack structure is formed on a central portion of the fin structure 54. In some other embodiments, multiple gate stack structures are formed on the fin structure 54. In some embodiments, the gate stack structure includes a dummy gate stack, and is replaced with a metal gate after performing a high thermal budget process.

[0061] The formation of the gate stack structure can be performed by deposition, photolithography, and etching. The deposition can be performed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition, metal organic chemical vapor deposition, remote plasma chemical vapor deposition, plasma assisted chemical vapor deposition, electroplating, other suitable methods, and / or combinations thereof. The photolithography can include spin coating, soft baking, aligning a mask, exposing, post exposure baking, developing the photoresist, rinsing, and drying (e.g., hard baking). The etching can be performed by dry etching or wet etching. In other embodiments, other suitable methods such as maskless lithography, e-beam writing, or ion beam writing can be used to perform or replace the photolithography.

[0062] FinFET devices offer more advantages than existing MOSFET devices (also known as planar devices). These advantages can include preferred chip area efficiency, improved carrier mobility, and a fabrication process compatible with that of planar devices. It is desirable to design integrated circuit chips using FinFET devices for part or all of the integrated circuit chips.

[0063] However, fabrication of FinFET devices still presents challenges. For example, loading during etching processes can be problematic, where devices of substantially different sizes can have different etching efficiencies. In forming metal gates, existing processes form a base tungsten material (e.g., for long channel devices) having a lateral dimension that is wide as part of the metal gate. This can cause loading problems and unwanted loss of gate height, especially in the presence of other smaller devices (e.g., short channel devices). In addition, existing processes require separate etching of the work function metal and the base tungsten, which increases the complexity and cost of the fabrication process.

[0064] To reduce unwanted loss of gate height and improve loading, embodiments of the present application use a unique process flow that etches the metal gate material to have substantially the same size as each other. In addition, embodiments of the present application etch the work function metal and the metal material (e.g., tungsten) formed thereon together, which reduces the complexity and cost of the process. Embodiments of the present application also form a T-shaped cap having a high dielectric constant dielectric material on the gate spacers. In forming the source / drain contacts, the etching process of the contact holes is expected to etch the interlayer dielectric material adjacent to the gate spacers to form the contact holes. However, the material composition between the interlayer dielectric layer and the gate spacer is similar, which can undesirably etch the gate spacer, especially in short channel devices, which can exacerbate the problem of overlay misregistration. The high dielectric constant dielectric material composition of the T-shaped cap here has a higher etch resistance, and thus protects the underlying gate spacer from undesired etching when forming the contact holes.

[0065] Embodiments of the present application will be described in conjunction with Figures 2A-33A, Figures 2B-33B , Figures 2C-33C , Figures 2D-33D ,and Figure 34 Details are as follows. In this embodiment, Figures 2A-33A These are partial cross-sectional views of the fin field-effect transistor device 100A at various manufacturing stages. Figures 2B-33B These are partial cross-sectional views of the fin field-effect transistor device 100B at various manufacturing stages. Figures 2C-33C These are partial cross-sectional views of the fin field-effect transistor device 100C at various manufacturing stages, and Figures 2D-33D This is a partial cross-sectional view of the fin field-effect transistor device 100D at various manufacturing stages. It should be understood that... Figures 2A-33A , Figures 2B-33B , Figures 2C-33C ,and Figures 2D-33D The sectional view, corresponding to Figure 1 The cross-section shown is in the X direction, and can therefore be regarded as an X-section.

[0066] Fin field-effect transistor (FET) devices 100A, 100B, 100C, and 100D can be devices on the same wafer but with different dimensions (e.g., different gate lengths). In the described embodiment, fin field-effect transistor device 100A has the smallest gate length (e.g., between about 3 nm and about 5 nm), fin field-effect transistor device 100B has a larger gate length (e.g., between about 15 nm and about 25 nm) than fin field-effect transistor device 100A, fin field-effect transistor device 100C has a larger gate length (e.g., between about 31 nm and about 41 nm) than fin field-effect transistor device 100B, and fin field-effect transistor device 100D has the largest gate length (e.g., between about 72 nm and about 240 nm). Fin field-effect transistor device 100A can be considered a short-channel device. Fin field-effect transistor devices 100B and 100C can each be considered medium-channel devices. The fin field-effect transistor device 100D can be regarded as a long-channel device.

[0067] Because the fin field-effect transistor devices 100A, 100B, 100C, and 100D differ in size, they can be used in different applications or with different configurations on integrated circuits. In a non-limiting example, the short-channel fin field-effect transistor device 100A is suitable for a core device that may contain logic devices (not directly handling input / output voltage / current), such as various logic gates like NAND, NOR, converters, or the like. In some embodiments, the core device may contain transistors for a static random access memory device. In contrast, a non-limiting example of the long-channel fin field-effect transistor device 100D may contain input / output devices configured to handle input and / or output voltage / current, thus requiring it to tolerate a greater amount of voltage or current oscillation than non-input / output devices. The medium-channel fin field-effect transistor devices 100B and 100C can be used for other suitable integrated circuit applications.

[0068] like Figure 2A , Figure 2B , Figure 2C ,and Figure 2D As shown, fin field-effect transistor devices 100A, 100B, 100C, and 100D respectively include fin structures 110A, 110B, 110C, and 110D. Fin structures 110A, 110B, 110C, and 110D can each be paired with... Figure 1 The fin structure 54 described above is similar. Fin structures 110A, 110B, 110C, and 110D may contain semiconductor materials such as silicon or silicon-germanium. In some embodiments, fin structures 110A to 110D may serve as channel regions of a transistor.

[0069] The finFET devices 100A, 100B, 100C, and 100D can also include source / drain regions 120A, 120B, 120C, and 120D, respectively. The source / drain regions 120A, 120B, 120C, and 120D can each include a dopant such as boron, arsenic, phosphorous, or the like, depending on whether the respective finFET device is a p-type transistor or an n-type transistor. In some embodiments, the respective finFET devices 100A, 100B, 100C, and 100D correspond generally to the distance 125A, 125B, 125C, and 125D between two adjacent source / drain regions thereof. In this manner, the finFET device 100A has the closest source / drain regions 120A (e.g., the smallest distance 125A), the finFET device 100B has the farther apart source / drain regions 120B (e.g., distance 125B > distance 125A), the finFET device 100C has the even farther apart source / drain regions 120C (e.g., distance 125C > distance 125B > distance 125A), and the finFET device 100D has the farthest apart source / drain regions 120D (e.g., distance 125D > distance 125C > distance 125B > distance 125A).

[0070] The finFET devices 100A, 100B, 100C, and 100D include interlayer dielectric layers 130A, 130B, 130C, and 130D, respectively. The interlayer dielectric layers 130A, 130B, 130C, and 130D can each be a bottommost interlayer dielectric layer and can be considered a zeroth interlayer dielectric layer. The interlayer dielectric layers 130A, 130B, 130C, and 130D each include a dielectric material such as a low-k dielectric material (e.g., a dielectric material having a dielectric constant less than that of silicon oxide) in some embodiments or silicon oxide in some other embodiments. In some embodiments, the low-k dielectric material can include fluorine-doped silicon oxide, carbon-doped silicon oxide, porous silicon oxide, porous carbon-doped silicon oxide, a spin-on organic polymer material, a spin-on silicon-based polymer dielectric layer, or a combination thereof.

[0071] The interlayer dielectric layers 130A, 130B, 130C, and 130D are each vertically aligned with and disposed on the source / drain regions 120A, 120B, 120C, and 120D, respectively.

[0072] FinFET devices 100A, 100B, 100C, and 100D include work function metal layers 140A, 140B, 140C, and 140D, respectively. Work function metal layers 140A, 140B, 140C, and 140D are provided to adjust the work function of the corresponding FinFET device to achieve a desired threshold voltage. In various embodiments, work function metal layers 140A, 140B, 140C, and 140D can include titanium nitride, tantalum nitride, titanium aluminum, titanium aluminum nitride, tantalum carbon nitride, or combinations thereof. Work function metal layers 140A, 140B, 140C, and 140D are each aligned perpendicularly to and disposed on fin structures 110A, 110B, 110C, and 110D, respectively.

[0073] FinFET devices 100A, 100B, 100C, and 100D include spacers 150A, 150B, 150C, and 150D, respectively. Spacer 150A is disposed between ILD layer 130A and work function metal layer 140A. Spacer 150B is disposed between ILD layer 130B and work function metal layer 140B. Spacer 150C is disposed between ILD layer 130C and work function metal layer 140C. Spacer 150D is disposed between ILD layer 130D and work function metal layer 140D. Spacers 150A, 150B, 150C, and 150D include a dielectric material, such as a low-k dielectric material in some embodiments, or silicon nitride, silicon carbon nitride, silicon oxynitride, silicon carbon oxynitride, or combinations thereof in other embodiments. The method of forming spacers 150A, 150B, 150C, and 150D can each include a deposition process followed by one or more etch and polish processes. If the spacers 150A are not adequately protected, they can be damaged unintentionally during an etch process to form source / drain contact holes. In various embodiments of the present application, T-shaped caps can be formed to protect the spacers from etch damage, as described in more detail below.

[0074] Fins 110A, 110B, 110C, and 110D have gate lengths 120A, 120B, 120C, and 120D, respectively. Gate lengths 120A, 120B, 120C, and 120D can be substantially the same. In some embodiments, gate lengths 120A, 120B, 120C, and 120D are between about 90 nm and about 120 nm. In some embodiments, the thickness of metal layers 160A, 160B, 160C, and 160D is between about 10 nm and about 20 nm. In comparison with existing processes that form bulk tungsten (with much larger thickness), the thickness of metal layers 160A to 160D is substantially smaller, thus easier to etch in subsequent processes and reduce concerns of etch loading.

[0075] Fins 110A, 110B, 110C, and 110D have gate heights 130A, 130B, 130C, and 130D, respectively. Gate heights 130A, 130B, 130C, and 130D can be substantially the same. In some embodiments, gate heights 130A, 130B, 130C, and 130D are between about 90 nm and about 120 nm.

[0076] As shown in FIG. 1A, fins 110A, 110B, 110C, and 110D have different gate lengths. For example, fin 110A has the shortest gate length, fin 110B has a longer gate length than fin 110A, fin 110C has a longer gate length than fin 110B, and fin 110D has the longest gate length. Figures 2A-2D As shown in FIG. 1A, fins 110A, 110B, 110C, and 110D have different gate lengths. For example, fin 110A has the shortest gate length, fin 110B has a longer gate length than fin 110A, fin 110C has a longer gate length than fin 110B, and fin 110D has the longest gate length.

[0077] Fins 110B has a longer gate length than fin 110A, thus the portion of work function metal layer 140B on the sidewall of spacer 150B does not merge together, but defines an opening. A portion of metal layer 160B is then filled into this opening.​

[0078] For the fin field-effect transistor device 100C, its gate length is greater than that of the fin field-effect transistor device 100B. Similar to the fin field-effect transistor device 100B, the work function metal layers 140C on the sidewalls of the spacer 150C do not merge but define openings, and the metal layer 160C partially fills these openings. However, the gate length of the fin field-effect transistor device 100C is longer, so the opening defined by the work function metal layer 140C is wide enough that the metal layer 160C does not completely fill the opening. The metal layer 160C on the sidewalls of the work function metal layer 140C partially defines the opening 180C.

[0079] The fin field-effect transistor device 100D has the longest gate length. Similar to the fin field-effect transistor device 100C, the fin field-effect transistor device 100D also has an opening 180D defined by a portion of the metal layer 160D, which is located on the sidewall of the work function metal layer 140D. In other words, the work function metal layer 140D and the metal layer 160D partially (but not completely) fill the opening defined by the sidewall of the spacer 150D and the upper surface of the fin structure 110D, thus defining the opening 180D by the metal layer 160D.

[0080] like Figures 3A-3D As shown, dielectric layers 210A, 210B, 210C, and 210D are formed on metal layers 160A, 160B, 160C, and 160D, respectively. The dielectric layers 210A to 210D can be formed using a suitable deposition process such as atomic layer deposition. In some embodiments, dielectric layers 210A to 210D comprise silicon nitride. In other embodiments, dielectric layers 210A to 210D may comprise silicon oxide. Notably, for fin field-effect transistor devices 100C and 100D, dielectric layers 210C and 210D fill openings 180C and 180D, respectively. Dielectric layers 220A, 220B, 220C, and 220D are then formed on dielectric layers 210A, 210B, 210C, and 210D, respectively. The dielectric layers 220A to 220D can also be formed using one or more suitable deposition processes. For example, the dielectric layers 220A to 220D can be formed by atomic layer deposition, plasma-assisted chemical vapor deposition, or a combination of atomic layer deposition and plasma-assisted chemical vapor deposition (e.g., the lower part is formed by atomic layer deposition, while the upper part is formed by plasma-assisted chemical vapor deposition).

[0081] Dielectric layers 220A to 220D and dielectric layers 210A to 210D may contain different materials. For example, in an embodiment where dielectric layers 210A to 210D contain silicon nitride, dielectric layers 220A to 220D may contain silicon oxide, and vice versa. In other embodiments, dielectric layers 210A to 210D and dielectric layers 220A to 220D may contain the same type of material. It should be noted that in the example of the fin field-effect transistor device 100D, dielectric layers 210D and 220D together fill the opening 180D.

[0082] like Figures 4A-4D As shown, fin field-effect transistor devices 100A to 100D undergo a planarization process such as chemical mechanical polishing. The planarization process removes portions of dielectric layers 210A to 210D and 220A to 220D, as well as portions of metal layers 160A to 160D, until the work function metal layers 140A to 140D are reached. In other words, the work function metal layers 140A to 140D serve as a polishing stop layer for the planarization process.

[0083] like Figures 5A-5D As shown, a dielectric layer 230A is formed on the work function metal layer 140A for use in a fin field-effect transistor device 100A. The fin field-effect transistor devices 100B to 100D can then undergo one or more etching processes 235. The dielectric layer 230A can act as an etching mask during the one or more etching processes 235, protecting the fin field-effect transistor device 100A from etching. The one or more etching processes 235 can simultaneously etch and remove portions of the metal layers 160B to 160D and portions of the work function metal layers 140B to 140D. In some embodiments, the one or more etching processes 235 may employ one or more of the following materials as etchants: boron trichloride, chlorine, carbon tetrafluoride, nitrogen trifluoride, hydrogen bromide and nitrogen trifluoride, chlorine and oxygen and nitrogen and nitrogen trifluoride, fluoroform and hydrogen and argon, or combinations thereof.

[0084] The result of the one or more etching processes 235 is to form openings 240B, 240C, and 240D, respectively, in the fin field effect transistor devices 100B, 100C, and 100D. For the fin field effect transistor device 100B, the opening 240B exposes the remaining portion of the work function metal layer 140B and the remaining portion of the metal layer 160B. For the fin field effect transistor device 100C, the opening 240C exposes the remaining portion of the work function metal layer 140C and the remaining portion of the metal layer 160C. For the fin field effect transistor device 100D, the opening 240D exposes the remaining portion of the work function metal layer 140D and the remaining portion of the metal layer 160D. The dielectric layer 210C remains in the fin field effect transistor device 100C, and the dielectric layers 210D and 220D remain in the fin field effect transistor device 100D. The openings 240C and 240D each have a U-shaped cross-sectional profile defined by the upper surface of the work function metal layer 140C or 140D, the side surface of the dielectric layer 210 or 210D, and the side surface of the spacer 150C or 150D, respectively. The U-shaped cross-sectional profile is another unique feature of embodiments of the present application.

[0085] The lateral dimensions 245B, 245C, and 245D of the openings 240B, 240C, and 240D, respectively, are similar to each other. For example, the lateral dimension 245B is between about 30 nm and about 40 nm, the lateral dimension 245C is between about 15 nm and about 25 nm, and the lateral dimension 245D is between about 15 nm and about 25 nm. In some embodiments, the ratio between the largest and the smallest of the lateral dimensions 245B, 245C, and 245D is between about 2: 1 and about 1 : 1.

[0086] Because the lateral dimensions 245B to 245D are similar, the lateral dimensions of the metal layers 160B to 160D and the work function metal layers 140B to 140D etched by the etching process 235 are similar to each other. This can reduce the problem of etching loading. For example, if a base metal layer has been formed for the fin field effect transistor devices 100B, 100C, and 100D, the base metal layer will have substantially different lateral dimensions. For example, the fin field effect transistor device 100D has the largest base metal layer, and the fin field effect transistor device 100B has the smallest base metal layer. As such, etching different sized metal layers will have substantially different loading, which can result in lack of consistency.

[0087] Thin metal layers 160B to 160D are formed here to allow the dielectric layers 210C to 210D and 220D to be formed. The lateral dimensions 245B to 245D of the openings 240B to 240D respectively define the lateral dimensions required for etching the metal layers 160B to 160D. Since the differences between the lateral dimensions 245B to 245D are small, concerns about etching load can be significantly reduced when etching the metal layers 160B to 160D. Furthermore, in this embodiment of the invention, the work function metal layers 140B to 140D and the metal layers 160B to 160D can be etched simultaneously during etching process 235, without the need for separate etching. This reduces the complexity and cost of the fabrication process.

[0088] like Figures 6A-6D As shown, dielectric layers 250A, 250B, 250C, and 250D are formed for fin field-effect transistor devices 100A, 100B, 100C, and 100D, respectively. Dielectric layer 250A is formed on dielectric layer 230A. Dielectric layer 250B is formed on interlayer dielectric layer 130B, spacer 150B, work function metal layer 140B, and metal layer 160B, and an opening 240B is filled therein. Dielectric layer 250C is formed on interlayer dielectric layer 130C, spacer 150C, work function metal layer 140C, metal layer 160C, and dielectric layer 210C, and an opening 240C is filled therein. Dielectric layer 250D is formed on interlayer dielectric layer 130D, spacer 150D, work function metal layer 140D, metal layer 160D, and dielectric layers 210D and 220D, and an opening 240D is filled therein. Dielectric layers 250A to 250D are formed using a suitable deposition process such as atomic layer deposition. In some embodiments, dielectric layers 250A to 250D comprise silicon nitride.

[0089] like Figures 7A-7D As shown, fin field-effect transistor devices 100A to 100D undergo a planarization process, such as chemical mechanical polishing. The planarization process removes portions of dielectric layers 250A to 250D, the upper portions of spacers 150A to 150D, and portions of the work function metal layer 140A and dielectric layer 230A of the fin field-effect transistor device 100A, until the interlayer dielectric layers 130A to 130D are reached. In other words, the interlayer dielectric layers 130A to 130D serve as polishing stop layers for the planarization process. The planarization process gives the fin field-effect transistor devices 100A, 100B, 100C, and 100D reduced gate heights 270A, 270B, 270C, and 270D, respectively. The gate heights 270A, 270B, 270C, and 270D can approximately correspond to the vertical dimensions of the interlayer dielectric layers 130A, 130B, 130C, and 130D, respectively. In some embodiments, the gate heights 270A, 270B, 270C, and 270D are between about 75 nm and about 105 nm.

[0090] like Figures 8A-8D As shown, one or more etching processes 300 can be performed on fin field-effect transistor devices 100A to 100D. The one or more etching processes 300 remove interlayer dielectric layers 130A, 130B, 130C, and 130D to form recesses 310A, 310B, 310C, and 310D in the fin field-effect transistor devices 100A, 100B, 100C, and 100D. The recesses 310A, 310B, 310C, and 310D are etched to have vertical dimensions 320A, 320B, 320C, and 320D, respectively, each corresponding to the distance from the upper surface of the individual interlayer dielectric layers 130A, 130B, 130C, and 130D to the upper surface of the individual work function metal layers 140A, 140B, 140C, and 140D. In some embodiments, the vertical dimensions 320A, 320B, 320C, and 320D are between about 20 nm and about 30 nm.

[0091] like Figures 9A-9D As shown, dielectric layers 330A, 330B, 330C, and 330D are formed to fill recesses 310A, 310B, 310C, and 310D, respectively. Dielectric layers 330A, 330B, 330C, and 330D are formed on interlayer dielectric layers 130A, 130B, 130C, and 130D, respectively. The dielectric layers 330A to 330D can be formed using suitable deposition processes, such as atomic layer deposition, chemical vapor deposition, or similar methods. In some embodiments, dielectric layers 330A to 330D may comprise yttrium silicon oxide. In other embodiments, dielectric layers 330A to 330D may comprise silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonitride. After depositing dielectric layers 330A to 330D, a planarization process, such as chemical mechanical polishing, can be performed to polish the surfaces of dielectric layers 330A to 330D until the upper surface of dielectric layer 330A is coplanar with the upper surface of work function metal layer 140A, and the upper surfaces of dielectric layers 330B to 330D are coplanar with the upper surfaces of dielectric layers 250B to 250D. Dielectric layers 330A to 330D each have a vertical dimension 340A to 340D. Because the planarization process removes some portions of work function metal layer 140 and dielectric layers 250B to 250D, the vertical dimensions 340A to 340D are smaller than the vertical dimensions 320A to 320D. In some embodiments, the vertical dimensions 340A to 340D are between about 15 nm and about 21 nm.

[0092] like Figures 10A-10DAs shown, one or more etching processes 350 are performed on fin field-effect transistor devices 100A to 100D. The one or more etching processes 350 remove portions of the work function metal layer 140A and the spacer 150A to form a T-shaped recess 360A in the fin field-effect transistor device 100A. For example, in some embodiments, the one or more etching processes 350 may first perform an etch-back process to etch and remove the work function metal layer 140A and the spacer 150A at a substantially uniform rate. A subsequent etching process is then performed to selectively remove the work function metal layer 140A while substantially not etching the spacer 150A. In other embodiments, the one or more etching processes 350 have etching selectivity between the spacer 150A and the work function metal layer 140A, resulting in a faster etching removal rate for the work function metal layer 140A and a slower etching removal rate for the spacer 150A. Regardless of the final result, after one or more etching processes 350, the spacer 150A is higher than the work function metal layer 140A. Thus, the recess 360A has... Figure 10A The T-shaped cross-sectional profile is shown. One or more etching processes also etch away portions of the dielectric layers 330A to 330D. Thus, the fin field-effect transistor devices 100A to 100D each have a reduced height of 370A to 370D. In some embodiments, the heights 370A to 370D are between about 69 nm and about 79 nm.

[0093] like Figures 11A-11D As shown, metal layer 380A is formed on work function metal layer 140A for use in fin field-effect transistor device 100A. In some embodiments, metal layer 380A may contain the same material as metal layers 160B to 160D, such as tungsten. Metal layer 380A, together with work function metal layer 140A, forms the gate used in fin field-effect transistor device 100A. Metal layers 160B to 160D, together with work function metal layers 140B to 140D, form the gates of fin field-effect transistor devices 100B, 100C, and 100D.

[0094] like Figures 12A-12DAs shown, dielectric layers 400A, 400B, 400C, and 400D are formed for use in fin field-effect transistor devices 100A, 100B, 100C, and 100D, respectively. Dielectric layer 400A is formed on dielectric layer 330A, spacer 150A, and metal layer 380A, and a T-shaped recess 360A is filled therein. Dielectric layers 400B to 400D are formed on dielectric layers 330B to 330D, spacers 150B to 150D, and dielectric layers 250B to 250D. Dielectric layers 400A to 400D may contain a dielectric material with a high dielectric constant (e.g., a dielectric material with a dielectric constant greater than that of silicon oxide). In some embodiments, dielectric layers 400A to 400D may contain zirconium oxide. In other embodiments, dielectric layers 400A to 400D may comprise yttrium silicon oxide, silicon carbide, or another suitable dielectric material with a high dielectric constant.

[0095] Understandably, it is possible Figures 12A-12D Following the fabrication stage shown, other processes are performed. For example, a metal gate dicing process may be performed, the details of which are described in U.S. Patent Application 16 / 021,344 (filed: June 28, 2018). The contents of the aforementioned U.S. patent application can be found in the appendix. For simplicity, other processes are not detailed here.

[0096] like Figures 13A-13D As shown, fin field-effect transistor devices 100A to 100D undergo a planarization process, such as chemical mechanical polishing. The planarization process removes portions of dielectric layers 400A to 400D and portions of dielectric layers 330B to 330D. The planarization process can continue until interlayer dielectric layers 130A to 130D are reached. In other words, interlayer dielectric layers 130A to 130D serve as planarization stop layers for the planarization process. At the end of the planarization process, the upper surface of dielectric layer 400A and the upper surface of interlayer dielectric layer 130A are substantially coplanar. Fin field-effect transistor devices 100A to 100D may each have a reduced height 410A to 410D. In some embodiments, the reduced height 410A to 410D is between approximately 54 nm and approximately 64 nm.

[0097] like Figure 13AAs shown, each of the dielectric layers 400A has a T-shaped cross-sectional profile, as it follows the cross-sectional profile of the T-shaped recess 360A. The dielectric layers 400A also serve as a cap for the underlying spacer 150A and gate (e.g., metal layer 380A and work function metal layer 140A) during subsequent etching processes. Thus, the dielectric layers 400A can also be considered as T-shaped caps. Each of the dielectric layers 400A has an upper portion 400A-U and a lower portion 400A-L, and the lower portion 400A-L is located below and narrower than the upper portion 400A-U. The upper surface of the upper portion 400A-U is coplanar with the upper surface of the ILD layer 130A. The side surface of the upper portion 400A-U contacts the side surface of the ILD layer 130A. The lower surface of the upper portion 400A-U contacts the upper surface of the spacer 150A. The side surface of the lower portion 400A-L contacts the side surface of the spacer 150A. The lower surface of the lower portion 400A-L contacts the metal layer 380A. The dielectric layers 400A as T-shaped caps are one of the unique physical features of embodiments of the present application.

[0098] One of the advantages of the above process flow is to reduce the gate height loss. Figures 2A-2D The gate heights 170A to 170D shown are between about 90 nm to about 120 nm, and Figures 13A-13D The final gate heights 410A to 410D of the finFET devices 100A to 100D shown are between about 54 nm to about 64 nm. Compared to prior art processes, there is less loss of gate height. Another advantage of embodiments of the present application is to reduce the loading, such as loading in etching processes. For example, prior art processes form bulk tungsten, and then etch the bulk tungsten to form a portion of the gate, which causes loading issues, especially when there are large variations in device sizes (such as the short channel device, the medium channel device, and the long channel device described above). In contrast, embodiments of the present application do not form bulk tungsten, but instead form a thin layer of metal, such as the metal layer 160D (e.g., tungsten), as shown above. Furthermore, the process flow of embodiments of the present application results in the metal layers 160B to 160D having similar lateral dimensions, so the metal layers 160B to 160D can be easily etched without causing loading, as shown above. Finally, the U-shaped cross-sectional profile of the openings 204C and 240D is another unique feature of embodiments of the present application. Figures 2A-2D Figures 5A-5D The U-shaped cross-sectional profile of the openings 204C and 240D is another unique feature of embodiments of the present application.

[0099] Additional fabrication processes can be performed to complete the fabrication of the finFET devices 100A to 100D. For example, Figures 14A-14D ​For example, source / drain contacts 440A, 440B, 440C, and 440D can be formed for finFET devices 100A, 100B, 100C, and 100D, respectively. Source / drain contacts 440A to 440D are formed on source / drain regions 120A to 120D and provide electrical connections to source / drain regions 120A to 120D. Source / drain contacts 440A to 440D can comprise conductive materials such as metals or metal compounds. In the step of etching contact holes for forming source / drain contacts 440A to 440D, dielectric layer 400A of the T-cap can act as a hard mask to protect underlying spacer 150A and / or gate. Since dielectric layer 400A of the T-cap has a material composition with high dielectric constant, it has higher etch resistance and can act as an etch hard mask. This is advantageous for finFET device 100A because of its small size which is prone to cause overlay problems. If dielectric layer 400A of the T-cap is not formed, in the event of overlay shift, the contact hole etching process can expose spacer 150A and gate (e.g. work function metal layer 140A and metal layer 380A) to etching. Here, dielectric layer 400A of the T-cap can protect spacer 150A and gate from etching, which is another advantage of the embodiments of the present application.

[0100] Dielectric layers 450A, 450B, 450C, and 450D are formed on source / drain contacts 440A, 440B, 440C, and 440D, respectively. Dielectric layers 450A to 450D can have the same material composition as dielectric layers 250B to 250D, such as silicon nitride. Interlayer dielectric layers 460A, 460B, 460C, and 460D are formed on dielectric layers 450A, 450B, 450C, and 450D, respectively.

[0101] Figures 2A-2D To Figures 14A-14D The first embodiment of the present application is described above. The second embodiment of the present application will be described below. Figures 15A-15D To Figures 22A-22D The first embodiment of the present application is described above. The second embodiment of the present application will be described below.

[0102] As Figures 15A-15D shown, the fabrication stages of finFET devices 100A to 100D are similar to those of finFET devices 200A to 200D. Figures 2A-2DThe fabrication stages shown are similar. For example, work function metal layers 140A to 140D are formed on fin structures 110A to 110D. Metal layers 160A to 160D are formed on work function metal layers 140A to 140D. As described above, for the medium-channel fin field-effect transistor device 100C and the long-channel fin field-effect transistor device 100D, work function metal layers 140C and 140D and metal layers 160C and 160D do not completely fill the openings 180C and 180D. However, unlike the first embodiment, dielectric layers 330A to 330D are formed on interlayer dielectric layers 130A to 130D. As described above, the material composition of dielectric layers 330A to 330D and interlayer dielectric layers 130A to 130D may be different. In some embodiments, dielectric layers 330A to 330D may comprise yttrium silicon oxide, silicon nitride, silicon carbon oxynitride, silicon carbonitride, or silicon carbonitride.

[0103] like Figures 16A-16D As shown, a dielectric layer 210C is formed to fill the opening 180C for use in a fin field-effect transistor device 100C, and dielectric layers 210D and 220D are formed to fill the opening 180D for use in a fin field-effect transistor device 100D. Figures 3A-3D and Figures 4A-4D As shown above, the dielectric layers 210C, 210D, and 220D are formed by a planarization process following the deposition process.

[0104] like Figures 17A-17D As shown, a dielectric layer 230A is formed on the fin field-effect transistor device 100A as a masking layer. Next, an etching process 235 (with the dielectric layer 230A protecting the underlying fin field-effect transistor device 100A) is performed to partially etch away the metal layers 160B to 160D and the work function metal layers 140B to 140D of the fin field-effect transistor devices 100B, 100C, and 100D. The etching process 235 can form openings 240B, 240C, and 240D, which can have a U-shaped cross-sectional profile. The lateral dimensions 245B, 245C, and 245D of the openings 240B, 240C, and 240D are substantially similar, thus substantially reducing concerns about etch load.

[0105] like Figures 18A-18D As shown, dielectric layers 250B to 250D are formed to fill openings 240B to 240D, respectively. A planarization process is then performed to planarize the upper surfaces of dielectric layers 250B to 250D. The planarization process removes portions of dielectric layer 230A and the work function metal layer 140A located on dielectric layer 330A. After the planarization process, the upper surfaces of dielectric layers 250B to 250D are substantially coplanar with the upper surfaces of dielectric layers 330B to 330D.

[0106] likeFigures 19A-19D As shown, a T-shaped recess 360A is etched in the fin field effect transistor device 100A. The side surfaces of the interlayer dielectric layer 130A together with the side surfaces of the dielectric layer 330A define the sidewalls of the T-shaped recess 360A. A metal layer 380A is then formed in the T-shaped recess 360A on the work function metal layer 140A.

[0107] As shown, the dielectric layers 400A to 400D used in the fabrication of the fin field effect transistor devices 100A to 100D are formed. The dielectric layers 400A to 400D can comprise a high dielectric constant material such as zirconium oxide. The dielectric material 400A fills in the T-shaped recess 360A. Figures 20A-20D As shown, the dielectric layers 420A, 420B, 420C, and 420D are formed on the dielectric layers 400A, 400B, 400C, and 400D respectively. In some embodiments, the dielectric layers 420A to 420D, the dielectric layers 210C to 210D, and the dielectric layers 250B to 250D have the same material composition such as silicon nitride. The dielectric layers 420A to 420D can serve as a hard mask layer for subsequent etching processes such as the cut metal gate process described in U.S. Patent Application 16 / 021,344 (filing date: 2018 / 6 / 28). The content of the above-mentioned U.S. Patent Application can be referred to in the annexure. For simplicity of explanation, other etching processes are not elaborated here.

[0108] Figures 21A-21D As shown, a planarization process is performed to remove portions of the dielectric layers 420A to 420D and the dielectric layers 400A to 400D. After the planarization process is performed, the fin field effect transistor devices 100A to 100D have planar upper surfaces. The remaining portions of the dielectric layer 400A in the fin field effect transistor device 100A form T-shaped caps.

[0109] As shown, a planarization process is performed to remove portions of the dielectric layers 420A to 420D and the dielectric layers 400A to 400D. After the planarization process is performed, the fin field effect transistor devices 100A to 100D have planar upper surfaces. The remaining portions of the dielectric layer 400A in the fin field effect transistor device 100A form T-shaped caps. Figures 22A-22D The first embodiment described above is similar to the first embodiment described above,

[0110] The second embodiment described above is similar to the first embodiment described above, Figures 2A-2D The second embodiment described above is similar to the first embodiment described above, Figures 14A-14D The third embodiment described above is similar to the first embodiment described above, Figures 15A-15D The third embodiment described above is similar to the first embodiment described above, Figures 22A-22D The third embodiment described above is similar to the first embodiment described above,

[0111] The third embodiment described above is similar to the first embodiment described above, Figures 23A-23D The third embodiment described above is similar to the first embodiment described above, Figures 28A-28D The third embodiment described above is similar to the first embodiment described above,

[0112] The third embodiment described above is similar to the first embodiment described above, Figures 23A-23D The third embodiment described above is similar to the first embodiment described above,​Figures 2A-2D The fabrication stages shown in FIG. 2A to FIG. 2D are similar to those shown in FIG. 1A to FIG. 1D. For example, work function metal layers 140A to 140D are formed on the fin structures 110A to 110D. The upper side portions of the work function metal layers 140A to 140D are on the dielectric layers 330A to 330D, respectively. Metal layers 160A to 160D are formed on the work function metal layers 140A to 140D. As mentioned above, for the medium channel finFET device 100C and the long channel finFET device 100D, the work function metal layers 140C and 140D and the metal layers 160C and 160D do not completely fill the openings 180C and 180D. Figures 15A-15D The fabrication stages shown in FIG. 2A to FIG. 2D are similar to those shown in FIG. 1A to FIG. 1D. For example, work function metal layers 140A to 140D are formed on the fin structures 110A to 110D. The upper side portions of the work function metal layers 140A to 140D are on the dielectric layers 330A to 330D, respectively. Metal layers 160A to 160D are formed on the work function metal layers 140A to 140D. As mentioned above, for the medium channel finFET device 100C and the long channel finFET device 100D, the work function metal layers 140C and 140D and the metal layers 160C and 160D do not completely fill the openings 180C and 180D.

[0113] As shown in FIG. 2E, dielectric layers 210C and 220C are formed to fill the openings 180C for the finFET device 100C. Dielectric layers 210D and 220D are formed to fill the openings 180D for the finFET device 100D. As shown in FIG. 2F, the dielectric layers 210C and 220C are removed to expose the dielectric layers 330A and 330C. The dielectric layers 210D and 220D are removed to expose the dielectric layers 330B and 330D. Figures 24A-24D As shown in FIG. 2E, dielectric layers 210C and 220C are formed to fill the openings 180C for the finFET device 100C. Dielectric layers 210D and 220D are formed to fill the openings 180D for the finFET device 100D. As shown in FIG. 2F, the dielectric layers 210C and 220C are removed to expose the dielectric layers 330A and 330C. The dielectric layers 210D and 220D are removed to expose the dielectric layers 330B and 330D. Figures 3A-3D As shown in FIG. 2E, dielectric layers 210C and 220C are formed to fill the openings 180C for the finFET device 100C. Dielectric layers 210D and 220D are formed to fill the openings 180D for the finFET device 100D. As shown in FIG. 2F, the dielectric layers 210C and 220C are removed to expose the dielectric layers 330A and 330C. The dielectric layers 210D and 220D are removed to expose the dielectric layers 330B and 330D. Figures 4A-4D As shown in FIG. 2E, dielectric layers 210C and 220C are formed to fill the openings 180C for the finFET device 100C. Dielectric layers 210D and 220D are formed to fill the openings 180D for the finFET device 100D. As shown in FIG. 2F, the dielectric layers 210C and 220C are removed to expose the dielectric layers 330A and 330C. The dielectric layers 210D and 220D are removed to expose the dielectric layers 330B and 330D.

[0114] As shown in FIG. 2E, dielectric layers 210C and 220C are formed to fill the openings 180C for the finFET device 100C. Dielectric layers 210D and 220D are formed to fill the openings 180D for the finFET device 100D. As shown in FIG. 2F, the dielectric layers 210C and 220C are removed to expose the dielectric layers 330A and 330C. The dielectric layers 210D and 220D are removed to expose the dielectric layers 330B and 330D. Figures 25A-25D As shown in FIG. 2E, dielectric layers 210C and 220C are formed to fill the openings 180C for the finFET device 100C. Dielectric layers 210D and 220D are formed to fill the openings 180D for the finFET device 100D. As shown in FIG. 2F, the dielectric layers 210C and 220C are removed to expose the dielectric layers 330A and 330C. The dielectric layers 210D and 220D are removed to expose the dielectric layers 330B and 330D. Figures 24A-24D As shown in FIG. 2E, dielectric layers 210C and 220C are formed to fill the openings 180C for the finFET device 100C. Dielectric layers 210D and 220D are formed to fill the openings 180D for the finFET device 100D. As shown in FIG. 2F, the dielectric layers 210C and 220C are removed to expose the dielectric layers 330A and 330C. The dielectric layers 210D and 220D are removed to expose the dielectric layers 330B and 330D.

[0115] As shown in FIG. 2E, dielectric layers 210C and 220C are formed to fill the openings 180C for the finFET device 100C. Dielectric layers 210D and 220D are formed to fill the openings 180D for the finFET device 100D. As shown in FIG. 2F, the dielectric layers 210C and 220C are removed to expose the dielectric layers 330A and 330C. The dielectric layers 210D and 220D are removed to expose the dielectric layers 330B and 330D.

[0116] As shown in FIG. 2E, dielectric layers 210C and 220C are formed to fill the openings 180C for the finFET device 100C. Dielectric layers 210D and 220D are formed to fill the openings 180D for the finFET device 100D. As shown in FIG. 2F, the dielectric layers 210C and 220C are removed to expose the dielectric layers 330A and 330C. The dielectric layers 210D and 220D are removed to expose the dielectric layers 330B and 330D. Figures 26A-26DAs shown, dielectric layers 400A to 400D are used to form finned field-effect transistor devices 100A to 100D. Dielectric layers 400A to 400D may contain a material with a high dielectric constant, such as zirconium oxide. Openings 240A to 240D are filled in dielectric layers 400A to 400D respectively.

[0117] like Figures 27A-27D As shown, an etch-back process is performed to partially remove dielectric layers 400A to 400D. Dielectric layers 420A to 420D are then formed on dielectric layers 400A to 400D for use in fin field-effect transistor devices 100A to 100D. In some embodiments, dielectric layers 420A to 420D comprise silicon nitride. Dielectric layers 420A to 420D can serve as hard mask layers for subsequent etching processes, such as the metal gate dicing process described in U.S. Patent Application 16 / 021,344 (filed: 2018 / 06 / 28). The contents of the aforementioned U.S. patent application can be found in the appendix. For simplicity, other etching processes are not detailed here.

[0118] like Figures 28A-28D As shown, a planarization process is performed to remove dielectric layers 400A to 400D and dielectric layers 330A to 330D. After the planarization process, the upper surfaces of the interlayer dielectric layers 130A to 130D are substantially coplanar with the upper surfaces of dielectric layers 400A to 400D. During this fabrication stage, dielectric layers 400A and 400B each have a T-shaped cross-sectional profile. Meanwhile, dielectric layers 400C and 400D may have a similar rotated L-shape or flipped L-shape cross-sectional profile. For example, dielectric layers 400C and 400D each have a wider upper portion and a narrower lower portion. One sidewall surface of the upper portion contacts interlayer dielectric layer 130C or 130D, while the opposite sidewall surface of the upper portion contacts dielectric layer 210C or 210D. One sidewall surface of the lower portion contacts spacer 150C or 150D, while the opposite sidewall surface of the lower portion contacts dielectric layer 210C or 210D. It is emphasized again that the T-shaped contours of dielectric layers 400A and 400B and the flipped L-shaped contours of dielectric layers 400C and 400D are unique physical features of this embodiment of the invention, serving as evidence of the aforementioned manufacturing process.

[0119] As described above in the first and second embodiments, additional fabrication processes can be performed to complete the fabrication of the fin field-effect transistor devices 100A to 100D used in the third embodiment. Figures 29A-29DFor example, source / drain contacts 440A to 440D can be formed on the source / drain regions 120A to 120D of the fin field-effect transistor devices 100A to 100D, providing electrical connection to the source / drain regions 120A to 120D. Due to the high dielectric constant material composition, dielectric layers 400A to 400D can act as a hard mask, protecting the underlying spacers and gate when etching contact holes to form source / drain contacts 440A to 440D. Dielectric layers 450A to 450D are respectively located on the source / drain contacts 440A to 440D. The material composition of dielectric layers 450A to 450D can be the same as that of dielectric layers 250B to 250D, such as silicon nitride. Interlayer dielectric layers 460A to 460D are formed on dielectric layers 450A to 450D.

[0120] As shown in the figure, the fin field-effect transistor devices 100A in the device structures formed by the fabrication processes of the first, second, and third embodiments are substantially the same, that is, the dielectric layer 400A of the T-shaped cap exists in all three embodiments. The fin field-effect transistor devices 100B to 100D used in the third embodiment have dielectric layers 400B to 400D with high dielectric constants, which were not used in the first and second embodiments. Figures 23B-29B As shown, the high-dielectric-constant dielectric layer 400B used in the third embodiment also has a T-shaped profile. Meanwhile, the high-dielectric-constant dielectric layers 400C and 400D have rotated or flipped L-shaped profiles, such as... Figure 28C , Figure 28D , Figure 29C ,and Figure 29D As shown.

[0121] Figure 30A , Figure 30B , Figure 30C ,and Figure 30DIn the fourth embodiment of the present disclosure, fin field effect transistor devices 100A, 100B, 100C, and 100D are fabricated. The fabrication process of the fourth embodiment is similar to that of the third embodiment, except that a high-k dielectric material is also used to form dielectric layers 210C, 210D, and 220D, such as the same material as that of high-k dielectric layers 400A to 400D (e.g., zirconium oxide). As a result, the final device structures of all four fin field effect transistor devices 100A to 100D will have T-shaped cap dielectric layers 400A to 400D, respectively. However, for fin field effect transistor devices 100C and 100D, the shapes of T-shaped cap dielectric layers 400C and 400D are slightly different. For example, T-shaped cap dielectric layer 400C is composed of a dielectric material, with dielectric layer 210C sandwiched in between. The lower surface of dielectric layer 210C can be lower (e.g., located further down) than dielectric layer 400C. In addition, while dielectric layers 400C and 210C in some embodiments can have the same high-k material composition (e.g., zirconium oxide), dielectric layers 400C and 210C in other embodiments can have different material compositions, such as dielectric layer 400C can contain a first high-k dielectric material, and dielectric layer 210C can contain a second high-k dielectric material, and the first high-k dielectric material is different from the second high-k dielectric material. Similarly, the lower surface of dielectric layer 210D can be lower than dielectric layer 400D, and dielectric layers 210D and 400D in various embodiments can have the same or different material compositions.

[0122] Figure 31A , Figure 31B , Figure 31C , and Figure 31D In the fifth embodiment of the present disclosure, fin field effect transistor devices 100A, 100B, 100C, and 100D are fabricated. The fabrication process of the fifth embodiment is similar to that of the first embodiment, except that fin field effect transistor device 100A is fabricated using the same process as that of other fin field effect transistor devices 100B to 100D. For example, in the above-mentioned etching process 235 described in conjunction with the first embodiment, dielectric layer 230A is not formed to serve as a mask for fin field effect transistor device 100A. The fifth embodiment does not form a T-shaped cap for fin field effect transistor device 100A. In other words, the final device structures of fin field effect transistor devices 100B to 100D in the first and fifth embodiments are substantially the same, while the device structure of fin field effect transistor device 100A in the first and fifth embodiments is different, with the difference being that fin field effect transistor device 100A in the fifth embodiment does not have a T-shaped cap. Figures 5A-5D

[0123] Figure 32A , Figure 32B , Figure 32C ​, and Figure 32D In the sixth embodiment, fin field effect transistor devices 100A, 100B, 100C, and 100D are fabricated. The fin field effect transistor device 100A in the sixth embodiment still has the same structure (e.g., has a T-shaped cap) as the fin field effect transistor device 100A fabricated in the first embodiment. However, the fin field effect transistor devices 100B and 100D in the sixth embodiment have different structures, e.g., the thickness of the metal layers 160B to 160D in the sixth embodiment is significantly greater than the thickness of the metal layers 160B to 160D in the first embodiment.

[0124] Figure 33A , Figure 33B , Figure 33C , and Figure 33D In the seventh embodiment, fin field effect transistor devices 100A, 100B, 100C, and 100D are fabricated. In the seventh embodiment, the fin field effect transistor device 100A has the same structure (e.g., has a T-shaped cap) as the fin field effect transistor device 100A fabricated in the first embodiment. However, the fin field effect transistor devices 100B to 100D in the seventh embodiment have different structures. For example, the thickness of the metal layers 160B to 160D in the seventh embodiment is significantly greater than the thickness of the metal layers 160B to 160D in the first embodiment. In addition, the dielectric layers 400B to 400D used in the fin field effect transistor devices 100B to 100D in the seventh embodiment also have a T-shaped profile. In other words, the seventh embodiment can be considered as a combination of the first embodiment and the sixth embodiment.

[0125] It should be understood that for the first to seventh embodiments, a suitable gate contact can be formed for the fin field effect transistor devices 100A to 100D. For example, for circuit applications, the gate of a transistor needs to be conductive, and therefore the method of forming the gate contact can be to etch a gate contact hole through the dielectric material (e.g., the dielectric layer 400A of the T-shaped cap or the dielectric layers 210B to 210D or the dielectric layers 250B to 250D) on the work function metal layers 140A to 140D and the metal layers 160A to 160D, and then fill the gate contact hole with a metal material. For simplicity of illustration, the additional processes are not detailed herein.

[0126] Figure 34is a flowchart of a method 600 of fabricating semiconductor devices in various embodiments of the present invention. The method 600 includes a step 610 of forming a first device and a second device on a wafer, the first device including a first semiconductor structure between a first source and a first drain, and the second device including a second semiconductor structure between a second source and a second drain. A first interlayer dielectric layer and a first spacer define a first opening that exposes the first semiconductor structure. A second interlayer dielectric layer and a second spacer define a second opening that exposes the second semiconductor structure. A first distance separating the first source and the first drain is less than a second distance separating the second source and the second drain.

[0127] The method 600 includes a step 620 of forming a first conductive layer on the first device and the second device. The first conductive layer completely fills the first opening but partially fills the second opening.

[0128] The method 600 includes a step 630 of forming a second conductive layer on the first conductive layer. The second conductive layer is formed partially in the second opening but not in the first opening. The first conductive layer and the second conductive layer have different material compositions.

[0129] The method 600 includes a step 640 of forming a first dielectric material on the second conductive layer. The first dielectric material fills the second opening.

[0130] The method 600 includes a step 650 of polishing the first dielectric material until the first conductive layer is reached.

[0131] The method 600 includes a step 660 of forming a protective mask on a portion of the first conductive layer on the first device.

[0132] The method 600 includes a step 670 of etching the second device and protecting the first device with the protective mask. The etching can remove portions of the first conductive layer and the second conductive layer in the second opening.

[0133] The method 600 includes a step 680 of etching the first device to partially remove portions of the first conductive layer in the first opening and to partially remove the first spacer. In some embodiments, after etching the first device, an upper surface of the first conductive layer is lower than an upper surface of the first spacer.

[0134] The method 600 includes a step 690 of forming a second dielectric material on the first conductive layer and the remaining portions of the first spacer after etching the first device. In some embodiments, the second dielectric material has a dielectric constant that is greater than a dielectric constant of the first dielectric material.

[0135] It is to be understood that additional process steps can be performed before, during, or after the above-described steps 610-690 to complete fabrication of the semiconductor device. For example, before performing step 610, the method 600 can include forming dummy gate structures (e.g., polysilicon gates), and removing the dummy gate structures to form the first and second openings. After performing step 690, the method 600 can include forming source / drain contacts of the semiconductor device, and / or forming vias and / or metal lines. Other steps can be performed, but are not described herein to simplify the description.

[0136] An eighth embodiment of the present disclosure will be described in conjunction with Figures 35A-35D to Figures 41A-41D The eighth embodiment will be described as follows. In the eighth embodiment, a high-k spacer layer is implemented to maintain the T-profile of the cap, as described in detail below. To simplify and unify the description, similar components of the eighth embodiment and the foregoing embodiments will be labeled with the same reference numerals.

[0137] As shown in FIG. 8A, the fabrication stages of the finFET devices 100A-100D are similar to the fabrication stages shown in FIG. 2A for the second embodiment. For example, the work function metal layers 140A-140D are formed on the fin structures 110A-110D, respectively. The metal layers 160A-160D are formed on the work function metal layers 140A-140D, respectively. As described above, for the medium channel finFET device 100C and the long channel finFET device 100D, the work function metal layers 140C and 140D and the metal layers 160C and 160D do not completely fill the openings 180C and 180D. Figures 35A-35D Figures 15A-15D As shown in FIG. 8B, dielectric layers 210C and 220C are formed to fill the openings 180C for the finFET device 100C, and dielectric layers 210D and 220D are formed to fill the openings 180D for the finFET device 100D. As

[0138] As shown in FIG. 8B, dielectric layers 210C and 220C are formed to fill the openings 180C for the finFET device 100C, and dielectric layers 210D and 220D are formed to fill the openings 180D for the finFET device 100D. As Figures 36A-36D Figures 3A-3D As shown in FIG. 8B, dielectric layers 210C and 220C are formed to fill the openings 180C for the finFET device 100C, and dielectric layers 210D and 220D are formed to fill the openings 180D for the finFET device 100D. As Figures 4A-4D As shown in FIG. 8B, dielectric layers 210C and 220C are formed to fill the openings 180C for the finFET device 100C, and dielectric layers 210D and 220D are formed to fill the openings 180D for the finFET device 100D. As

[0139] Figures 37A-37D ​​​As shown, one or more etching processes 235 are performed to partially etch away the metal layers 160A-D and the work function metal layers 140A-D of the finFET devices 100A-D. Notably, unlike some of the previous embodiments, no mask is formed on the short-channel finFET device 100A. Thus, the etching process 235 etches all of the finFET devices 100A-D simultaneously. The etching process 235 forms openings 240A-D in the finFET devices 100A-D, respectively. The etched openings 240A and 240B have a T-shaped cross-sectional profile. For example, the work function metal layers 140A and 140B and the metal layers 160B are etched to a greater extent than the spacers 150A and 150B, so that the upper surfaces of the work function metal layers 140A and 140B and the metal layers 160B are recessed (e.g., lower) than the upper surfaces of the spacers 150A and 150B. In addition, the spacers 150A and 150B are etched to a greater extent than the ILD layers 130A and 130B. Thus, after the etching process 235, the upper surfaces of the spacers 150A and 150B are lower than the upper surfaces of the ILD layers 130A and 130B.

[0140] For the finFET devices 100C and 100D, the openings 240C and 240D also etch the work function metal layers 140C and 140D and the metal layers 160C and 160D to a greater extent than the spacers 150C and 150D. However, for the openings 240C or 240D, the spacer 150C or 150D is located on one side (rather than both sides) of the work function metal layer 140C or 140D and the metal layer 160C or 160D. The lateral dimensions 245A-D of the openings 240A-D are substantially similar to one another, so that etching loading concerns are substantially reduced, which can result in a more uniform etch. Figure 5C As shown, the etching process 235 also etches the work function metal layer 140B and the metal layer 160B to a greater extent than the spacer 150B. Thus, the upper surface of the work function metal layer 140B and the metal layer 160B is recessed (e.g., lower) than the upper surface of the spacer 150B. In addition, the spacer 150B is etched to a greater extent than the ILD layer 130B. Thus, after the etching process 235, the upper surface of the spacer 150B is lower than the upper surface of the ILD layer 130B. Figure 5D As shown, the etching process 235 also etches the work function metal layer 140B and the metal layer 160B to a greater extent than the spacer 150B. Thus, the upper surface of the work function metal layer 140B and the metal layer 160B is recessed (e.g., lower) than the upper surface of the spacer 150B. In addition, the spacer 150B is etched to a greater extent than the ILD layer 130B. Thus, after the etching process 235, the upper surface of the spacer 150B is lower than the upper surface of the ILD layer 130B.

[0141] As shown, the etching process 235 also etches the work function metal layer 140B and the metal layer 160B to a greater extent than the spacer 150B. Thus, the upper surface of the work function metal layer 140B and the metal layer 160B is recessed (e.g., lower) than the upper surface of the spacer 150B. In addition, the spacer 150B is etched to a greater extent than the ILD layer 130B. Thus, after the etching process 235, the upper surface of the spacer 150B is lower than the upper surface of the ILD layer 130B. Figures 38A-38DAs shown, one or more metal growth or deposition processes are performed to re-form metal layer 160A on work function metal layer 140A, and to enlarge metal layers 160B to 160D. Subsequently, deposition process 500 is performed on fin field-effect transistor devices 100A to 100D to form pad layers 510A, 510B, 510C, and 510D, respectively. Pad layer 510A is formed on interlayer dielectric layer 130A, spacer 150A, and metal layer 160A. Pad layer 510B is formed on interlayer dielectric layer 130B, spacer 150B, and metal layer 160B. Pad layer 510C is formed on interlayer dielectric layer 130C, spacer 150C, metal layer 160C, and dielectric layer 210C. The padding layer 510D is formed on the interlayer dielectric layer 130D, the spacer 150D, the metal layer 160D, and the dielectric layers 210C and 220D.

[0142] The padding layers 510A to 510D may comprise a dielectric material with a high dielectric constant, such as a metal oxide with a dielectric constant greater than about 4. In various embodiments, the metal oxide may comprise, but is not limited to, zirconium oxide, yttrium silicon oxide, silicon carbide, aluminum oxide, hafnium oxide, titanium oxide, zirconium silicon oxide, hafnium silicon oxide, silicon nitride, tantalum oxide, strontium oxide, yttrium oxide, lanthanum oxide, lanthanum diluent oxide, calcium oxide, magnesium oxide, gadolinium oxide, praseodymium oxide, cerium oxide, zirconium hafnium oxide, or combinations thereof.

[0143] In some embodiments, pad layers 510A to 510D are formed, each with a thickness between about 0.5 nm and about 5 nm. This thickness range is set such that the thickness of the pad layers 510A to 510D is sufficient to protect the underlying layers in the subsequent etching process described below, without being too thick and interfering with the intended function of the fin field-effect transistor devices 100A to 100D. For example, if the pad layers 510A to 510D are too thin, they may be etched through in subsequent etching and fail to adequately protect the underlying layers. On the other hand, if the pad layers 510A to 510D are too thick, parasitic capacitance will unnecessarily increase (because the pad layers 510A to 510D contain dielectric materials with high dielectric constants), thus degrading device performance.

[0144] like Figures 39A-39D As shown, dielectric layers 250A to 250D are formed to fill openings 240A to 240D, respectively. Since padding layers 510A to 510D have already been formed, dielectric layers 250A to 250D are formed on top of padding layers 510A to 510D. As described above, dielectric layers 250A to 250D contain a material with a non-high dielectric constant, such as silicon nitride. In other words, dielectric layers 250A to 250D have a different material composition than padding layers 510A to 510D. Other low dielectric constant dielectric materials can also be used to implement dielectric layers 250A to 250D.

[0145] like Figures 40A-40DAs shown, dielectric layers 520B, 520C, and 520D are formed on finFET devices 100B, 100C, and 100D, respectively, but not on finFET device 100A. Dielectric layers 520B-520D are different in material composition from dielectric layers 250A-250D. In some embodiments, dielectric layers 520B-520D comprise silicon oxide. Dielectric layers 520B-520D serve as a mask layer to protect the underlying finFET devices 100B-100D, but not finFET device 100A, so that additional patterning processes can be performed on finFET device 100A.

[0146] After forming dielectric layers 520B-520D, one or more etching processes 530 are performed on finFET devices 100A-100D. In some embodiments, one or more etching processes such as part of a cut metal gate process can be performed, which is described in detail in U.S. Patent Application 16 / 021,344 (filing date: 6 / 28 / 2018). The content of the above-mentioned U.S. Patent Application can be referred to in the attachment.

[0147] One or more etching processes 530 are configured to have etching selectivity (such as substantially different etching rates) between dielectric layers 520B-520D and dielectric layer 250A, so that dielectric layer 250A of finFET device 100A can be etched and removed and T-shaped opening 240A is restored, and substantially no impact on dielectric layers 520B-520D of finFET devices 100B-100D. In this way, dielectric layers 520B-520D serve as protective masks to protect the underlying components from etching.

[0148] One or more etching processes 530 are also configured to have etching selectivity between dielectric layer 250A and liner layer 510A. In this way, one or more etching processes 530 can etch and remove dielectric layer 250A without etching and opening liner layer 510A. In this way, liner layer 510A can serve as an etching stop layer to protect the underlying ILD layer 130A, spacer 150A, and metal layer 160A when etching process 530 is performed. Without liner layer 510A, etching process 530 can etch and remove some portions of ILD layer 130A, spacer 150A, and / or metal layer 160A. This phenomenon needs to be avoided because it can damage the intended T-shaped profile of opening 240A (and the subsequently formed T-shaped cap) and / or damage the metal gate. However, with the protection provided by liner layer 510A, the T-shaped profile of opening 240A (and the subsequently formed cap) can be properly maintained. An embodiment of the present disclosure employs liner layer 510A as a protective layer to maintain the T-shaped profile of opening 240A.

[0149] As shown, one or more etching processes 530 are performed on finFET devices 100A-100D. In some embodiments, one or more etching processes such as part of a cut metal gate process can be performed, which is described in detail in U.S. Patent Application 16 / 021,344 (filing date: 6 / 28 / 2018). The content of the above-mentioned U.S. Patent Application can be referred to in the attachment. Figures 41A-41DAs shown, dielectric layer 400A is formed in opening 240A. Dielectric layer 400A can be formed by one or more deposition processes, followed by one or more planarization processes such as chemical mechanical polishing to remove dielectric layers 520B to 520D. Dielectric layer 400A is formed on pad layer 510A and is located on spacer 150A and metal layer 160A. Similar to the aforementioned embodiments, dielectric layer 400A may comprise a dielectric material with a high dielectric constant such as zirconium oxide, yttrium silicon oxide, silicon carbide, aluminum oxide, hafnium oxide, titanium oxide, zirconium silicon oxide, hafnium silicon oxide, silicon nitride, tantalum oxide, strontium oxide, yttrium oxide, lanthanum oxide, lanthanum diluent oxide, calcium oxide, magnesium oxide, gadolinium oxide, praseodymium oxide, cerium oxide, zirconium hafnium oxide, aluminum oxynitride, or combinations thereof. In some embodiments, dielectric layer 400A and pad layers 510A to 510D are made of different types of high dielectric constant dielectric materials. In other embodiments, dielectric layer 400A and pad layers 510A to 510D are made of the same type of high dielectric constant dielectric material.

[0150] The dielectric layer 400A continues the T-shaped profile of the opening 240A and can be regarded as a T-shaped cover. As shown in the previous embodiment, the dielectric layer 400A can protect the underlying layers (such as spacers and metal layers) from damage during subsequent etching processes (such as the etching process used to etch the source / drain contact opening to the interlayer dielectric layer 130C).

[0151] It should be understood that, although Figures 35A-35D arrive Figures 41A-41D The T-shaped cover dielectric layer 400A (containing a high dielectric constant dielectric material) formed by the process flow is only used in fin field-effect transistor device 100A. Similar T-shaped covers can still be formed for other fin field-effect transistor devices 100B to 100D, such as... Figures 29A-29D , Figures 30A-30D ,or Figures 33A-33D The embodiments shown are similar. In fact, a dielectric layer with a high dielectric constant (similar to pad layers 510A, 510B, 510C, and 510D) can be used in any of the foregoing embodiments, and this pad layer helps to retain the T-shaped profile used for one or more caps for individual fin field-effect transistor devices.

[0152] The ninth embodiment of the present invention will be equipped with Figures 42A-45A The following explanation is provided. In the ninth embodiment, at least two different materials can be used to implement the T-shaped cover to minimize parasitic capacitance, as detailed below. For simplicity, the ninth embodiment uses a fin field-effect transistor device 100A as an illustrative example, but it should be understood that the ninth embodiment can also be used for fin field-effect transistor devices 100B to 100D. For the sake of simplicity and consistency, similar components in the ninth embodiment and the foregoing embodiments will be designated with the same reference numerals.

[0153] likeFigure 42A As shown, the fabrication stages of the fin field-effect transistor device 100A are similar to those of... Figure 40A The manufacturing process is similar. This stage involves one or more etching processes (e.g., 235). Figure 37A As shown, a T-shaped opening 240A is etched into the fin field-effect transistor device 100A, and a deposition process 500 is performed to form a pad layer 510A on the interlayer dielectric layer 130A, spacer 150A, and metal layer 160A. As described above, the material composition of the pad layer 510A may differ from that of the interlayer dielectric layer 130A and the spacer 150A. For example, the pad layer 510A may contain a high-dielectric-number dielectric material such as a metal oxide material.

[0154] like Figure 42A As shown, the opening 240A has a depth of 540A, which is the vertical distance between the upper surface of a portion of the pad layer 510A located on the interlayer dielectric layer 130A and the upper surface of a portion of the pad layer 510A located on the metal layer 160A. In some embodiments, the depth 540A may be between about 10 nm and about 60 nm. The range of the depth 540A is set to optimize the performance of the T-shaped cover subsequently formed therein. For example, if the depth 540A is too small, the T-shaped cover may not be able to properly protect the underlying layers such as the spacer 150A during the etching process. If the depth 540A is too large, the T-shaped cover may occupy too much space from the underlying metal gate and unnecessarily increase the parasitic capacitance due to the T-shaped cover.

[0155] like Figure 43A As shown, dielectric material 550A is formed to fill opening 240A. The dielectric material 550A can be formed by one or more deposition processes, such as chemical vapor deposition, atomic layer deposition, or similar methods. The material of dielectric material 550A may have a low dielectric constant (but not necessarily less than the dielectric constant of silicon oxide), for example, less than the dielectric constant of a dielectric material with a high dielectric constant of the pad layer 510A. In some embodiments, dielectric material 550A may comprise silicon nitride with a dielectric constant of about 7.5. In other embodiments, dielectric material 550A may comprise a low dielectric constant material with a dielectric constant less than about 4. For example, a low dielectric constant dielectric material may comprise fluorine-doped silicon oxide, carbon-doped silicon oxide, porous silicon oxide, porous carbon-doped silicon oxide, spin-coated organic polymer material, spin-coated silicon-based polymer dielectric layer, or a combination of the above.

[0156] like Figure 44AAs shown, a back-etch process 560 is performed on the finFET device 100A to back-etch the dielectric material 550A. The back-etch process 560 is set to have an etch selectivity to the liner layer 510A and the dielectric material 550A. For example, the rate of etching removal of the dielectric material 550A is substantially greater than the rate of etching removal of the liner layer 510A (such as ten times greater or more). In this way, the liner layer 510A protects the underlying ILD layer 130A, spacers 150A, and metal layer 160A from damage by the back-etch process 560.

[0157] After the back-etch process 560 is performed, the remaining portion of the dielectric material 550A has a height 570A, which is the distance from the upper surface to the lower surface of the remaining portion of the dielectric material 550A. In some embodiments, the height 570A is between about 5 nm and about 30 nm. The range of the height 570A is set to optimize the performance of the T-shaped cap formed therein later.

[0158] More specifically, a high-k dielectric material (such as Figure 45A As shown, a high-k dielectric material 580A (described below) is formed on the dielectric material 550A to fill the opening 240A. The high-k dielectric material 580A and the dielectric material 550A together form a T-shaped cap. If the entire T-shaped cap is composed of high-k dielectric material, the parasitic capacitance associated with the T-shaped cap is too high for some integrated circuit applications, as the parasitic capacitance of a material is directly related to the dielectric constant of the material. In this way, embodiments of the present application use the dielectric material 550A as the bottom portion of the T-shaped cap. Since the dielectric material 550A has a lower dielectric constant, the overall parasitic capacitance caused by the T-shaped cap is reduced. At the same time, the upper portion of the T-shaped cap (such as the high-k dielectric material formed on the dielectric material 550A) is still suitable for protecting the underlying layers (such as the spacers 150A and / or the metal layer 160A) from etch damage.

[0159] If the height 570A is too high, there is not enough space for the high-k dielectric material to be formed later. In other words, the high-k portion of the T-shaped cap is too thin, which defeats the intended function of protecting the underlying layers from etch damage. For example, even though the high-k portion of the T-shaped cap should have a high etch selectivity to other low-k materials, the thin high-k portion can be etched through unintentionally. On the other hand, if the height 570A is too small, even though the dielectric material 550A has a lower dielectric constant, it is not effective in reducing the overall dielectric constant of the T-shaped cap. In this way, the parasitic capacitance is still too high.

[0160] In various embodiments of the present invention, an optimized range of height 570 Å is provided such that the high dielectric constant portion of the T-shaped cover is suitable as a protective shield, while the low dielectric constant portion of the T-shaped cover is sufficient to reduce the overall dielectric constant of the T-shaped cover to reduce parasitic capacitance. It is understood that the specific value of height 570 Å depends on the specific integrated circuit application implementing the fin field-effect transistor device 100A, such as considering the requirements for parasitic capacitance. It is understood that in some embodiments, the upper surface of the dielectric material 550 Å may be configured to be higher than the upper surface of the spacer 150 Å. In other embodiments, the upper surface of the dielectric material 550 Å may be configured to be lower than the upper surface of the spacer 150 Å.

[0161] like Figure 45A As shown, a high-dielectric-constant dielectric material 580A is formed on dielectric material 550A to fill the opening 240A. In various embodiments, the high-dielectric-constant dielectric material 580A may comprise zirconium oxide, yttrium silicon oxide, silicon carbide, aluminum oxide, hafnium oxide, titanium oxide, zirconium silicon oxide, hafnium silicon oxide, silicon nitride, tantalum oxide, strontium oxide, yttrium oxide, lanthanum oxide, lanthanum diluent oxide, calcium oxide, magnesium oxide, gadolinium oxide, praseodymium oxide, cerium oxide, zirconium hafnium oxide, aluminum oxynitride, or combinations thereof. A planarization process (such as chemical mechanical polishing) is then performed to planarize the interlayer dielectric layer 130A and the upper surface of the high-dielectric-constant dielectric material 580A. The planarization process removes a portion of the pad layer 510A formed on the interlayer dielectric layer 130A. After the planarization process, the high-dielectric-constant dielectric material 580A has a height of 585 Å. In some embodiments, the height 585A is between about 5 nm and about 30 nm. In some embodiments, the ratio of height 585A to height 570A is between about 0.5 and about 2. As described above, the high dielectric constant dielectric material 580A and dielectric material 550A together form a T-shaped cap. The height 585A and the ratio between height 585A and 570A can be set to optimize the function of the T-shaped cap and reduce the overall parasitic capacitance associated with it.

[0162] As in the above embodiment, once it is confirmed that the spacer 150A is higher than the gate (composed of the work function metal layer 140A and the metal layer 160A) and the interlayer dielectric layer 130A is higher than the spacer 150A, a T-shaped profile is achieved. Figure 45A For example, the gate has a height of 590 Å, the spacer 150A has a height of 591 Å, and the interlayer dielectric layer 130A has a height of 592 Å, which are the distances from the upper surface of the fin structure 110A to the gate, the spacer 150A, and the upper surface of the interlayer dielectric layer 130A, respectively. Height 592 Å is greater than height 591 Å, and height 591 Å is greater than height 590 Å. The gate sidewall contacts the lower portion 150A-L of the spacer 150A, while a portion of the pad layer 510A contacts the upper portion 150A-U of the spacer 150A.

[0163] It should be understood that, Figure 45A The double-layer T-shaped cover shown (having two different parts, such as dielectric material 550A and high dielectric constant dielectric material 580A) can be used in fin field-effect transistor devices 100B, 100C, and 100D, and its formation method is comparable to... Figures 42A-45A The process flow shown above is similar. Furthermore, embodiments may implement a double-layer T-shaped cap without the padding layer 510A (or padding layers 510B, 510C, or 510D). Additionally, it should be understood that while two different components (one of which is a dielectric material with a lower dielectric constant and the other has a higher dielectric constant) are used to form the T-shaped cap, other embodiments may employ three or more different components to implement the T-shaped cap.

[0164] by Figure 46A For example, another dielectric material 595A can be implemented between dielectric material 550A and dielectric material 580A with a high dielectric constant. The dielectric constant of dielectric material 595A can be greater than that of dielectric material 550A, but less than that of dielectric material 580A with a high dielectric constant. In this way, dielectric material 595A can protect the spacer 150A better than dielectric material 550A, but not as well as dielectric material 580A with a high dielectric constant. Dielectric material 595A can also reduce the overall dielectric constant of the T-shaped cover, but not to the extent that dielectric material 550A reduces it. In this way, dielectric material 595A can be regarded as a compromise or transition between two different dielectric materials 550A and 580A.

[0165] It should be noted that the eighth and ninth embodiments described above may include additional processes to complete the fabrication of the fin field-effect transistor devices 100A to 100D. For example, source / drain contacts 440A to 440D may be formed (see... Figures 14A-14D Similar source / drain contacts are located on source / drain regions 120A to 120D. It should be understood that although the eighth and ninth embodiments employ fin field-effect transistor devices, these embodiments can be applied to non-fin field-effect transistor devices, such as planar devices without protruding fins.

[0166] Figure 47 This is a flowchart of a method 800 for fabricating a semiconductor device according to various embodiments of the present invention. Method 800 includes step 810 to provide a semiconductor device. The semiconductor device includes a source and a drain, a semiconductor structure located between the source and the drain, an interlayer dielectric layer located on the source and the drain, a first metal layer located on the semiconductor structure, the interlayer dielectric layer located on the source and the drain, and a spacer located between the interlayer dielectric layer and the first metal layer.

[0167] The method 800 includes a step 820 of performing one or more etching processes to form openings in the semiconductor device. The upper surface of the first metal layer, the upper surface and side surfaces of the spacers, and the side surfaces of the interlayer dielectric define the openings.

[0168] The method 800 includes a step 830 of forming a liner layer to partially fill the openings. The liner layer has a first material composition.

[0169] The method 800 includes a step 840 of forming a dielectric material on the liner layer. The second material composition of the dielectric material is different from the first material composition.

[0170] The method 800 includes a step 850 of performing a second etching process to remove the dielectric material. The dielectric material has an etch rate that is greater than an etch rate of the liner layer, such that the liner layer protects at least the spacers from etching during the second etching process.

[0171] In some embodiments, the dielectric constant of the liner layer is greater than the dielectric constant of the spacers, the interlayer dielectric layer, and the dielectric material.

[0172] In some embodiments, the method 800 further includes a step of forming a dielectric structure in the openings after the second etching process. The method of forming the dielectric structure can include forming a first portion on the liner layer, and forming a second portion on the first portion. The second portion has a dielectric constant that is greater than a dielectric constant of the first portion. In some embodiments, the method of forming the first portion includes depositing a low-k dielectric layer as the first portion, and the low-k dielectric layer has a dielectric constant of less than about 4. In some embodiments, the method of forming the second portion includes depositing a high-k dielectric layer as the second portion, and the high-k dielectric layer has a dielectric constant of greater than about 4.

[0173] It should be understood that additional process steps can be performed before, during, or after the above-described steps 810-850 to complete fabrication of the semiconductor device. For example, before performing step 810, the method 800 can include forming a dummy gate structure (e.g., a polysilicon gate), and removing the dummy gate structure to form the first and second openings. After performing step 850, the method 800 can include forming source / drain contacts of the semiconductor device and / or forming vias and / or metal lines. Other steps can be performed, but are not described here to simplify the explanation.

[0174] In summary, embodiments of the present application employ various embodiments each having a unique fabrication process flow to form a T-shaped cap with a high-k dielectric material on the gate spacer and on the gate. Embodiments of the present application also form U-shaped openings of similar dimensions (lateral dimensions) for short channel, medium channel, and long channel devices. For example, the U-shaped openings can be used to simultaneously etch the layers of the metal gate. Embodiments of the present application can also form a liner layer in the T-shaped opening, such as on the gate spacer, and the liner layer can include a high-k dielectric material. Furthermore, embodiments of the present application can employ two or more different dielectric materials to implement the T-shaped cap. For example, the bottom of the T-shaped cap can employ a lower-k dielectric material, while the top of the T-shaped cap can employ a higher-k dielectric material.

[0175] From the foregoing, it will be appreciated that embodiments of the present application offer more advantages than existing semiconductor devices and fabrication methods. However, it should be understood that other embodiments can offer additional advantages, all advantages need not be described herein, and embodiments need not have all of the described advantages to fall within the scope of the present application. One advantage of embodiments of the present application is that etch loading concerns are reduced. For example, because the U-shaped openings used for short channel devices, medium channel devices, and long channel devices are of similar lateral dimensions, the lateral dimensions of the metal layers of the metal gate used for these devices differ little from one another. This means that these metal layers can be etched simultaneously without causing loading problems. Another advantage is that the T-shaped cap protects the underlying spacer and gate from unintended etching during subsequent contact hole etch processes. This is particularly advantageous for short channel devices, which are more susceptible to layer stack misalignment problems because of their small size. Even if the layer stack is misaligned, the high-k dielectric material composition of the T-shaped cap protects the underlying spacer (which includes a low-k material) and the metal gate from etching. Other advantages result from the liner layer of high-k dielectric material, which acts as a protective layer to prevent the underlying layer (e.g., the gate spacer) from being damaged by etching. In this way, the T-shaped profile of the cap is well maintained. Another advantage is that a T-shaped cap formed of two or more different types of dielectric material can simultaneously achieve good etch resistance (because the higher-k component is on top) and reduced electrical capacitance (because the lower-k component is on the bottom) during etch processes. Other advantages include compatibility with existing fabrication process flows.

[0176] One embodiment of the present application relates to a semiconductor device. The semiconductor device includes a semiconductor layer. A gate structure is on the semiconductor layer. A spacer is on a sidewall of the gate structure. The spacer has a height greater than a height of the gate structure. A liner layer is on the gate structure and the spacer. The spacer and the liner layer are of different material compositions.

[0177] In one embodiment, the liner layer has a dielectric constant greater than a dielectric constant of the spacer.

[0178] In one embodiment, the dielectric constant of the spacer layer is greater than about 4.

[0179] In one embodiment, the gate structure is on sidewalls of a first portion of the spacer; and the spacer layer is on sidewalls of a second portion of the spacer, wherein the second portion is on the first portion.

[0180] In one embodiment, the spacer layer is also on an upper surface of the spacer.

[0181] In one embodiment, the semiconductor device further includes an interlayer dielectric layer, wherein the spacer is between the interlayer dielectric layer and the gate structure; a height of the interlayer dielectric layer is greater than a height of the spacer; and the spacer layer is also on a portion of sidewalls of the interlayer dielectric layer.

[0182] In one embodiment, the semiconductor device further includes a dielectric structure on the spacer layer, wherein the dielectric structure includes a dielectric material having a dielectric constant greater than about 4, and wherein the dielectric structure has a cross-sectional profile that resembles a letter T.

[0183] In one embodiment, the dielectric structure includes a first portion and a second portion on the first portion; and a dielectric constant of the second portion is greater than a dielectric constant of the first portion.

[0184] In one embodiment, the dielectric structure includes a third portion between the first portion and the second portion, and a dielectric constant of the third portion is less than the dielectric constant of the second portion but greater than the dielectric constant of the first portion.

[0185] One embodiment of the present invention relates to a semiconductor device. The semiconductor device includes a semiconductor layer. A gate structure is on the semiconductor layer. A spacer is on sidewalls of the gate structure. An interlayer dielectric layer is adjacent to the spacer. The spacer is between the interlayer dielectric layer and the gate structure. A dielectric structure is on the gate structure. The dielectric structure includes a first portion and a second portion on the first portion. A first dielectric constant of the first portion is less than a second dielectric constant of the second portion. The second dielectric constant is greater than about 4.

[0186] In one embodiment, a cross-sectional profile of the dielectric structure resembles a letter T.

[0187] In one embodiment, a portion of the dielectric structure is on an upper surface of the spacer.

[0188] In one embodiment, the first dielectric constant is less than about 4.

[0189] In one embodiment, the dielectric structure further includes a third portion between the first portion and the second portion, and wherein a dielectric constant of the third portion is less than the second dielectric constant but greater than the first dielectric constant.

[0190] In one embodiment, the semiconductor device further includes a liner layer having a dielectric constant less than about 4, wherein the dielectric structure is located on the liner layer and the gate structure and the spacer are located below the liner layer.

[0191] In one embodiment, a portion of the liner layer is located between a sidewall of a portion of the interlayer dielectric layer and a sidewall of a portion of the dielectric structure.

[0192] Another embodiment of the present invention relates to a method of fabricating a semiconductor device. A semiconductor device is provided that includes a source and a drain, a semiconductor structure located between the source and the drain, a first metal layer located on the semiconductor structure, an interlayer dielectric layer located on the source and the drain, and a spacer located between the interlayer dielectric layer and the first metal layer. One or more etching processes are performed to form an opening in the semiconductor device. An upper surface of the first metal layer, an upper surface and a side surface of the spacer, and a side surface of the interlayer dielectric layer define the opening. A liner layer is formed to partially fill the opening. The liner layer has a first material composition. A dielectric material is formed on the liner layer. A second material composition of the dielectric material is different from the first material composition. A second etching process is performed to remove the dielectric material. An etching rate of the dielectric material is greater than an etching rate of the liner layer, such that the liner layer protects at least the spacer from etching during the second etching process.

[0193] In one embodiment, the liner layer has a dielectric constant greater than a dielectric constant of the spacer, the interlayer dielectric layer, and the dielectric material.

[0194] In one embodiment, the method further includes, after the second etching process, forming a dielectric structure in the opening, wherein the step of forming the dielectric structure includes forming a first portion on the liner layer and forming a second portion on the first portion, wherein a dielectric constant of the second portion is greater than a dielectric constant of the first portion.

[0195] In one embodiment, the step of forming the first portion includes depositing a low dielectric constant dielectric layer as the first portion, and the low dielectric constant dielectric layer has a dielectric constant less than about 4; and the step of forming the second portion includes depositing a high dielectric constant dielectric layer as the second portion, and the high dielectric constant dielectric layer has a dielectric constant greater than about 4.

[0196] The features of the above embodiments are advantageous for those skilled in the art to understand the present invention. Those skilled in the art should understand that other processes and structures can be designed and changed based on the present invention to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not deviate from the concept and scope of the present invention, and changes, substitutions, or variations can be made without deviating from the concept and scope of the present invention.

Claims

1. A semiconductor device, comprising: A semiconductor layer; A gate structure is located on the semiconductor layer; One interlayer dielectric layer; A spacer is located between the gate structure and the interlayer dielectric layer, wherein the height of the spacer is greater than the height of the gate structure but less than the height of the interlayer dielectric layer; A pad layer is located on a portion of the sidewall of the gate structure, the spacer, and the interlayer dielectric layer, wherein the spacer and the pad layer are made of different materials; and A dielectric structure is located on the pad layer. in: The gate structure is located on the sidewall of a first portion of the spacer. The liner layer is located on the sidewall of a second portion of the spacer, wherein the second portion is located on the first portion, and The dielectric structure has a different material composition from the padding layer, wherein the dielectric structure has a T-shaped cross-sectional profile, wherein the dielectric structure includes a first portion and a second portion located on the first portion; and the dielectric constant of the second portion is greater than the dielectric constant of the first portion.

2. The semiconductor device of claim 1, wherein the dielectric constant of the pad layer is greater than the dielectric constant of the spacer.

3. The semiconductor device of claim 2, wherein the dielectric constant of the pad layer is greater than 4.

4. The semiconductor device of claim 1, wherein the pad layer is also located on the upper surface of the spacer.

5. The semiconductor device of claim 1, wherein the dielectric structure comprises a dielectric material with a dielectric constant greater than 4.

6. The semiconductor device of claim 5, wherein the dielectric structure comprises zirconium oxide or yttrium silicon oxide.

7. The semiconductor device of claim 1, wherein the dielectric structure includes a third portion located between the first portion and the second portion, and the dielectric constant of the third portion is less than the dielectric constant of the second portion but greater than the dielectric constant of the first portion.

8. A semiconductor device, comprising: A semiconductor layer; A gate structure is located on the semiconductor layer; A spacer is located on the sidewall of the gate structure; An interlayer dielectric layer is adjacent to the spacer, wherein the spacer is located between the interlayer dielectric layer and the gate structure, wherein the gate structure, the spacer, and the interlayer dielectric layer together define a T-shaped opening; as well as A dielectric structure is located on the gate structure and fills the T-shaped opening. in: The dielectric structure includes a first portion, a second portion on the first portion, and a third portion located between the first portion and the second portion; The first dielectric constant of the first part is less than the second dielectric constant of the second part; The third dielectric constant of the third part is less than the second dielectric constant but greater than the first dielectric constant; and The second dielectric constant is greater than 4.

9. The semiconductor device of claim 8, wherein the dielectric structure has a T-shaped cross-sectional profile.

10. The semiconductor device of claim 8, wherein a portion of the dielectric structure is located on the upper surface of the spacer.

11. The semiconductor device of claim 8, wherein the first dielectric constant is less than 4.

12. The semiconductor device of claim 8, further comprising a pad layer with a dielectric constant greater than 4, wherein the dielectric structure is located on the pad layer, and wherein the gate structure and the spacer are located under the pad layer.

13. The semiconductor device of claim 12, wherein a portion of the pad layer is located between a sidewall of a portion of the interlayer dielectric layer and a sidewall of a portion of the dielectric structure.

14. The semiconductor device of claim 8, wherein the dielectric structure comprises zirconium oxide or yttrium silicon oxide.

15. A semiconductor device, comprising: A semiconductor layer; A gate structure is located on the semiconductor layer; One interlayer dielectric layer; A spacer is located between the interlayer dielectric layer and the gate structure. The spacer includes a lower portion and an upper portion. The height of the spacer is greater than the height of the gate structure but less than the height of the interlayer dielectric layer. The gate structure is located on the sidewall of the lower portion of the spacer. A spacer layer is located on the upper surface and sidewall of the gate structure, a portion of the sidewall of the interlayer dielectric layer, and the upper portion of the spacer, wherein the dielectric constant of the spacer is lower than the dielectric constant of the spacer layer; and A dielectric structure is located on the pad layer, wherein the dielectric structure has a T-shaped cross-sectional profile and the dielectric material of the dielectric structure has a dielectric constant greater than 4, wherein the dielectric structure includes a first portion and a second portion located on the first portion, and wherein the dielectric constant of the second portion is greater than the dielectric constant of the first portion.

16. The semiconductor device of claim 15, wherein the dielectric constant of the pad layer is greater than 4.

17. The semiconductor device of claim 15, wherein the dielectric structure further comprises a third portion located between the first portion and the second portion, and the dielectric constant of the third portion is less than the dielectric constant of the second portion but greater than the dielectric constant of the first portion.

18. The semiconductor device of claim 15, wherein the dielectric structure comprises zirconium oxide or yttrium silicon oxide.

19. A method for forming a semiconductor device, comprising: A semiconductor device is provided, comprising: A semiconductor fin structure; Multiple source / drain regions are located on both sides of the semiconductor fin structure; A gate structure is located on the semiconductor fin structure; and Multiple gate spacers are located on the sidewalls of the gate structure; The semiconductor device is etched, wherein the etching rate of the gate structure is greater than the etching rate of the gate spacer during the etching of the semiconductor device, such that the gate structure and the gate spacer together define a T-shaped opening. After etching the semiconductor device, a pad layer is formed to fill the T-shaped opening and the gate structure and the gate spacer; After the liner layer is formed, a dielectric material is deposited on the liner layer to fill the T-shaped opening, wherein the dielectric material has a different material composition from the liner layer. Etching back a portion of the dielectric material, wherein the dielectric material is a first dielectric material; and After etching back the first dielectric material, a second dielectric material is deposited on the first dielectric material, wherein the dielectric constant of the second dielectric material is greater than the dielectric constant of the first dielectric material.

20. The method of forming a semiconductor device as claimed in claim 19, wherein: The semiconductor device also includes an interlayer dielectric structure located on the sidewall of the gate spacer; as well as The etching rate of the gate spacer during etching of the semiconductor device is greater than the etching rate of the interlayer dielectric structure.

21. The method of forming a semiconductor device as claimed in claim 20, wherein the step of forming the pad layer further comprises forming the pad layer on the interlayer dielectric structure.

22. The method of forming a semiconductor device as claimed in claim 19, wherein the step of forming the pad layer includes forming the pad layer containing a dielectric material having a dielectric constant greater than 4.

23. The method of forming a semiconductor device as claimed in claim 19, wherein the step of forming the pad layer includes forming the pad layer with a thickness between 0.5 nm and 5 nm.

24. The method of forming a semiconductor device as claimed in claim 19, further comprising: A portion of the gate structure is formed after etching the semiconductor device and before forming the pad layer.

25. The method of forming a semiconductor device as claimed in claim 24, wherein: The gate structure includes a work function metal layer; The step of etching the semiconductor device involves etching away a portion of the work function metal layer; as well as The step of forming this portion of the gate structure includes depositing a first metal layer on the work function metal layer, wherein the first metal layer and the work function metal layer have different material compositions.

26. The method of forming a semiconductor device as claimed in claim 19, wherein the step of depositing the dielectric material includes depositing the dielectric material having a dielectric constant less than that of the pad layer.

27. The method of forming a semiconductor device as claimed in claim 19, wherein the pad layer and the dielectric material have etch selectivity during the etch-back process.

28. The method of forming a semiconductor device as claimed in claim 19, wherein the step of depositing the second dielectric material includes depositing a dielectric material with a dielectric constant greater than 4 as the second dielectric material.

29. A method for forming a semiconductor device, comprising: A semiconductor device is provided, comprising: A semiconductor fin structure; Multiple source / drain regions are located on both sides of the semiconductor fin structure; A gate structure is located on the semiconductor fin structure; Multiple gate spacers are located on the sidewalls of the gate structure; and An interlayer dielectric structure is located on the sidewall of the gate spacer; A first etching process is performed on the semiconductor device, wherein the gate structure, the gate spacer, and the interlayer dielectric structure are etch-selective during the first etching process, such that the gate structure, the gate spacer, and the retained portion of the interlayer dielectric structure together define a T-shaped opening; After the first etching process, a pad layer is partially filled into the T-shaped opening, the gate structure, and the gate spacer. A first dielectric material is formed on the padding layer, and the first dielectric material is filled into the T-shaped opening, wherein the first dielectric material and the padding layer have different material compositions; A second etching process is performed to remove a portion of the first dielectric material; After removing the first dielectric material, a second dielectric material is formed to partially fill the T-shaped opening; and A third dielectric material is formed to completely fill the T-shaped opening, wherein the dielectric constant of the third dielectric material is greater than the dielectric constant of the second dielectric material, and the dielectric constant of the second dielectric material is greater than the dielectric constant of the first dielectric material.

30. The method of forming a semiconductor device as claimed in claim 29, wherein the pad layer serves as an etch stop layer during the second etch process.

31. The method of forming a semiconductor device as claimed in claim 29, wherein: The gate structure includes a work function metal layer; The first etching process partially etches away the work function metal layer; as well as The method of forming the semiconductor device further includes depositing a conductive material on the work function metal layer after the first etching process and before partially filling the T-shaped opening with the pad layer, wherein the conductive material and the work function metal layer have different material compositions.

32. A method for forming a semiconductor device, comprising: A semiconductor device is provided, comprising: One source and one drain; A semiconductor structure located between the source and the drain; A first metal layer is located on the semiconductor structure; An inter-dielectric layer is located between the source and the drain; Multiple spacers are located between the interlayer dielectric layer and the first metal layer; One or more etching processes are performed to form an opening in the semiconductor device, wherein the opening is defined by the upper surface of the first metal layer, the upper and side surfaces of the spacer, and the side surface of the interlayer dielectric layer. A liner layer is formed to partially fill the opening, wherein the liner layer has a first material composition, and the first material composition includes a material with a high dielectric constant. A dielectric material is formed on the pad layer, wherein a second material composition of the dielectric material is different from the first material composition; and A second etching process is performed to remove a portion of the dielectric material, wherein the etching rate of the dielectric material is greater than the etching rate of the pad layer, so that the pad layer at least protects the spacer from etching during the second etching process; and After the second etching process, a dielectric structure is formed in the opening, wherein the dielectric structure includes the remaining dielectric material as a first part and a second part located on the first part, wherein the dielectric constant of the second part is greater than the dielectric constant of the first part.

33. The method of forming a semiconductor device as claimed in claim 32, wherein the dielectric constant of the pad layer is greater than the dielectric constant of the spacer, the interlayer dielectric layer, and the dielectric material.

34. The method of forming a semiconductor device as claimed in claim 32, wherein the step of forming the first portion includes depositing a dielectric layer with a low dielectric constant as the first portion, and the dielectric constant of the low dielectric constant dielectric layer is less than 4; and The step of forming the second part includes depositing a dielectric layer with a high dielectric constant as the second part, wherein the dielectric constant of the high dielectric constant dielectric layer is greater than 4.

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