Memory device and memory system with multiple error correction functions and operation method thereof

Abstract

A memory device and a memory system with multiple error correction functions and an operation method thereof are provided. The memory system includes: a memory cell array including a first memory area and a second memory area; an input / output circuit including an input / output line for sending or receiving data bits and parity bits to or from the first memory area and the second memory area; and an error correction circuit including a plurality of sub-error correction circuits, the plurality of sub-error correction circuits including a first sub-error correction circuit and a second sub-error correction circuit, wherein the first sub-error correction circuit is used to perform a first error correction operation on a first data bit of the first memory area received through the input / output line, and the second sub-error correction circuit is used to perform a second error correction operation on a second data bit of the second memory area received through the input / output line. The first memory area has a higher bit error rate than the second memory area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0114183, filed on September 21, 2018 in the Korean Intellectual Property Office and entitled “MEMORY DEVICE AND MEMORY SYSTEM WITH MULTIPLE ERROR CORRECTION FUNCTIONS AND OPERATION METHOD THEREOF,” is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments relate to a memory device, and more particularly, to a memory device capable of performing a discrete error correction function or a plurality of error correction functions and an operating method thereof. Background Art

[0004] The demand for memory devices with high capacitance and low power consumption has increased rapidly. In order to meet these demands, research has been conducted on next-generation memory devices that are nonvolatile and do not require memory refresh. Such next-generation memory devices have been required to have the following characteristics: for example, the high integrity of dynamic random access memory (DRAM), the non-volatility of flash memory, the high speed of static RAM (SRAM), etc. For example, the next-generation memory devices may include magnetic RAM (MRAM), phase-change RAM (PRAM), nano-floating gate memory (NFGM), polymer RAM (PoRAM), ferroelectric RAM (FeRAM) and resistive RAM (RRAM), which meet the above requirements.

[0005] In addition, the process scale used to manufacture memory devices has been significantly reduced to increase the integrity and density of memory devices. As the process scale is reduced, the bit error rate of data in memory devices has increased rapidly, and thus error correction codes (ECC) for solving the high bit error rate have been required. Summary of the invention

[0006] An embodiment is directed to a memory system, comprising: a memory cell array, comprising a plurality of memory areas, the plurality of memory areas comprising a first memory area and a second memory area; an input / output circuit, comprising an input / output line, for sending or receiving data bits and parity bits to or from the plurality of memory areas; and an error correction circuit, comprising a plurality of sub-error correction circuits, the plurality of sub-error correction circuits comprising a first sub-error correction circuit for performing a first error correction operation on a first data bit of the first memory area received through the input / output line and a second sub-error correction circuit for performing a second error correction operation on a second data bit of the second memory area received through the input / output line, wherein the first memory area has a higher bit error rate than the second memory area.

[0007] An embodiment is directed to an operating method of a memory system including a memory device, the method comprising: performing a first error correction operation on first data to be stored in or read from a first memory area through an input / output line corresponding to the first memory area by using a first sub-error correction circuit; and performing a second error correction operation on second data to be stored in or read from a second memory area through an input / output line corresponding to the second memory area by using a second sub-error correction circuit, wherein the first memory area includes a memory area having a temperature higher than an operating temperature of a memory cell when a high temperature process is performed on the memory device.

[0008] An embodiment is directed to a memory device, comprising: a memory cell array, comprising a plurality of memory areas, the plurality of memory areas comprising a first memory area and a second memory area; an input / output circuit, comprising an input / output line, for sending or receiving data bits and parity bits to or from the plurality of memory areas; an error correction circuit, comprising a plurality of sub-error correction circuits, the plurality of sub-error correction circuits comprising a first sub-error correction circuit for performing a first error correction operation on a first data bit of the first memory area received through the input / output line, and a second sub-error correction circuit for performing a second error correction operation on a second data bit of the second memory area received through the input / output line; a switching circuit, connected to the input / output circuit and the error correction circuit; and control logic for controlling the switching circuit to electrically connect the first memory area to the first sub-error correction circuit, and controlling the switching circuit to selectively connect the second memory area to the second sub-error correction circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 A memory system according to an example embodiment is shown;

[0011] Figure 2 A memory system according to an example embodiment is shown;

[0012] Figure 3 A memory device according to an example embodiment is shown;

[0013] Figure 4 A memory device according to an example embodiment is shown;

[0014] Figure 5A A memory device according to an example embodiment is shown;

[0015] Figure 5B shows a sub-memory region according to an example embodiment;

[0016] Fig. 6A A first error correction operation of a memory device according to an example embodiment is shown;

[0017] Figure 6B A second error correction operation of a memory device according to an example embodiment is shown;

[0018] Figure 6C A multiplexer as a switching circuit of a memory device according to an example embodiment is shown;

[0019] Fig. 7A A first error correction operation of a memory device according to an example embodiment is shown;

[0020] Figure 7B A second error correction operation of a memory device according to an example embodiment is shown;

[0021] Figure 7C A multiplexer as a switching circuit of a memory device according to an example embodiment is shown;

[0022] Fig.7D shows a first sub-memory region and a second sub-memory region of a memory device according to an example embodiment;

[0023] Figure 8 A memory system according to an example embodiment is shown;

[0024] Fig. 9 Shows Figure 8 A memory system; and

[0025] Fig.10 A flowchart of a method of operating a memory system according to example embodiments is shown. DETAILED DESCRIPTION

[0026] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementations to those skilled in the art.

[0027] Figure 1 A memory system 1 according to an example embodiment is shown. Figure 1 , the memory system 1 may include a memory cell array 100, an input / output circuit 200, and an error correction circuit 400. The memory cell array 100 may include a first memory area 110 and a second memory area 120. The error correction circuit 400 may include a first sub-error correction circuit 410 and a second sub-error correction circuit 420. For example, the number of memory areas and the number of sub-error correction circuits may vary.

[0028] According to an example embodiment, the first memory area 110 may correspond to a memory area having a higher bit error rate than the second memory area 120. Due to the influence of the high temperature process, a bit error may occur in the first memory area 110. For example, the bit error in the first memory area 110 may be caused by the high temperature process. In detail, when a packaging process for attaching a memory device to a printed circuit board (PCB) or the like is performed at a high temperature, a bit error may occur in at least a portion of the memory cell array 100 (e.g., the first memory area 110). In order to avoid or correct a bit error in the first memory area 110, the memory system 1 may use a first sub-error correction circuit 410 to perform a first error correction operation on data to be written to the first memory area 110 or data to be read from the first memory area 110.

[0029] The second memory area 120 may correspond to a memory area having a lower bit error rate than the first memory area 110. The second memory area 120 may not be affected by the high temperature process, so bit errors may not occur frequently therein. For example, the second memory area 120 is less affected by the high temperature process than the first memory area 110. For example, bit errors in the second memory area 120 may occur less frequently than in the first memory area 110. In order to avoid or correct bit errors in the second memory area 120, the memory system 1 may use the second sub-error correction circuit 420 to perform a second error correction operation on data to be written to the second memory area 120 or data to be read from the second memory area 120.

[0030] The first error correction operation performed by the first sub-error correction circuit 410 may detect and correct a larger number of bit errors than the second error correction operation performed by the second sub-error correction circuit 420. For example, when the second error correction operation corrects 2 bit errors and detects 3 bit errors, the first error correction operation may correct 3 bit errors and detect 4 bit errors.

[0031] In the memory system 1, the first sub-error correction circuit 410 may perform a first error correction operation on data to be written to or read from the first memory area 110. The second sub-error correction circuit 420 may perform a second error correction operation on data to be written to or read from the second memory area 120. For example, in consideration of performance or efficiency, a bit error in the first memory area 110 affected by a high temperature process may be detected or corrected by performing the first error correction operation instead of the second error correction operation. Since the first error correction operation requiring a higher parity bit to data bit ratio is performed only on the first memory area 110 greatly affected by the high temperature process, memory overhead may be reduced, and the efficiency of the memory system 1 may be improved. For example, when the ratio of parity bits to data bits increases, the efficiency of the memory system 1 may decrease because the increased parity bits require additional memory capacity.

[0032] Figure 2 A memory system 1 according to an example embodiment is shown. Figure 2 , the memory system 1 may include a memory device 10 and a memory controller 20. The memory device 10 may include a memory cell array 100, a switching circuit 300, and an error correction circuit 400.

[0033] The memory controller 20 may control the memory device 10 to read data from the memory device 10 in response to a read request received from the host HOST, and may control the memory device 10 to write data to the memory device 10 in response to a write request received from the host HOST. For example, the memory controller 20 may control write, read, and erase operations of the memory device 10 according to a command / address signal CA and a control signal CTRL to the memory device 10. Data DTA to be written or data DTA to be read may be transmitted between the memory controller 20 and the memory device 10. The data DTA may include read data transmitted from the memory device 10 to the memory controller 20 and write data transmitted from the memory controller 20 to the memory device 10.

[0034] The memory cell array 100 may include a plurality of memory cells. The plurality of memory cells may be arranged in a matrix structure having rows and columns. The memory cell array 100 may include a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells. The plurality of word lines may extend in the row direction of the plurality of memory cells and be connected to the corresponding memory cells. The plurality of bit lines may extend in the column direction of the plurality of memory cells and be connected to the corresponding memory cells. The plurality of memory cells of the memory cell array 100 may include, for example, a dynamic random access memory (DRAM) cell, a static RAM (SRAM) cell, a flash memory cell, a phase change RAM (PRAM) cell, a resistance RAM (ReRAM) cell, a magnetic RAM (MRAM) cell, or another type of memory cell. The DRAM cell may include a synchronous DRAM (SDRAM) cell, etc.

[0035] The memory device 10 may include typical / general circuits associated with the memory cell array 100, such as a row decoder, a column decoder, a sense amplifier, etc. The row decoder may select one of a plurality of word lines connected to the memory cell array 100. The row decoder may decode a row address included in the command / address signal CA, select a word line corresponding to the row address, and activate the selected word line.

[0036] The memory device 10 according to the example embodiment may divide the memory cell array 100 into a plurality of regions, and perform different error correction functions on data bits in the plurality of regions using a plurality of error correction circuits in the error correction circuit 400. For example, based on the switching operation of the switching circuit 300, the memory controller 20 may control the memory device 10 to connect a portion of the region of the memory cell array 100 to a first sub-error correction circuit for performing a first error correction function, and to connect the other portion of the region of the memory cell array 100 to a second sub-error correction circuit for performing a second error correction function.

[0037] According to example embodiments, when the memory device 10 is produced or manufactured, bit errors may occur in multiple regions of the memory cell array 100 due to processes performed at different temperatures. For example, when the memory cell of the memory device 10 is an MRAM cell, the temperature of the memory cell should be kept below the operating temperature of the memory cell to avoid errors in the data bits in the memory cell. For example, the operating temperature of the memory cell may be about -40°C to about 150°C. However, when a high temperature process is performed on the memory cell to produce the memory device 10, the temperature of a portion of the memory cell may exceed the operating temperature. For example, when a reflow soldering process is performed on the memory cell, the temperature of the memory cell may exceed the operating temperature. In the subsequent description, the first region of the memory cell array 100 may correspond to a first memory region when the temperature of a region of the memory cell array exceeds the operating temperature due to a high temperature process. The second region of the memory cell array 100 may correspond to a second memory region when the temperature of a region of the memory cell is kept below or at the operating temperature in a high temperature process.

[0038] For example, in order to reduce data bit errors of data bits of both the first memory area and the second memory area of ​​the memory cell array 100, the parity bits of the data bits of the first memory area and the second memory area may be increased. With the increase of the parity bits, fewer data bits may be stored in the same memory capacitor. In order to increase the data bits stored in the same memory capacitor, the memory controller 20 may control the memory device 10 to perform a first error correction function on a partial area of ​​the memory cell array 100 and perform a second error correction function on another partial area of ​​the memory cell array 100 based on the command / address signal CA and the control signal CTRL. For example, the parity bit of the first error correction function may be smaller than the parity bit of the second error correction function.

[0039] According to example embodiments, the memory device 10 may include a nonvolatile memory device. The nonvolatile memory device may include, for example, a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory, a PRAM, an MRAM, an RRAM, a ferroelectric RAM (FRAM), etc.

[0040] According to example embodiments, the memory device 10 may include, for example, a volatile memory device. The volatile memory may include, for example, DRAM, synchronous DRAM (SDRAM), double data rate (double data rate, DDR) SDRAM, low power double data rate (low power double data rate, LPDDR) SDRAM, graphics double data rate (graphics double data rate, GDDR) SDRAM, rambus DRAM (rambus DRAM, RDRAM), SRAM, etc.

[0041] According to example embodiments, the memory system 1 may include, for example, at least one of a hard disk drive (HDD), a solid state drive (SSD), a compact flash (CF) card, a secure digital (SD) card, a micro secure digital (micro-SD) card, a mini secure digital (mini-SD) card, an extreme digital (xD) card, and a memory stick.

[0042] Figure 3 A memory device 10 according to an example embodiment is shown. Figure 2 and Figure 3 , the memory device 10 may include a memory cell array 100, a switching circuit 300, and an error correction circuit 400, and may further include an input / output circuit 200 and a control logic 500. The control logic 500 may include, for example, a switching control logic 510. According to another example embodiment, the switching control logic 510 may be provided outside the control logic 500.

[0043] The memory cell array 100 may include a plurality of memory cells connected to word lines and bit lines. The memory cell array 100 may be connected to a row decoder 700 via a global word line, and may be connected to an input / output circuit 200 via a global bit line. A global word line may be connected to a plurality of word lines in the memory cell array 100. A global bit line may be connected to a plurality of bit lines in the memory cell array 100. Each of the memory cells may store one or more data bits. For example, each memory cell may include, for example, a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC).

[0044] Based on the command / address signal CA and the control signal CTRL received from the memory controller 20, the control logic 500 can output various internal control signals for writing data into the memory cell array 100 or for reading data from the memory cell array 100. For example, the memory device 10 may include a voltage generator. The control logic 500 can control the voltage generator to generate a write voltage, a read voltage, and an erase voltage. Based on the command / address signal CA and the control signal CTRL, the control logic 500 can select one of the multiple word lines by controlling the row decoder 700, select one of the multiple bit lines by controlling the column decoder 800, and activate the sense amplifier corresponding to the selected bit line among the multiple sense amplifiers in the input / output circuit 200.

[0045] The input / output circuit 200 may be connected to the error correction circuit 400 through the switching circuit 300. The control logic 500 may selectively control the connection between the input / output circuit 200 and the error correction circuit 400 by controlling the switching circuit 300. According to example embodiments, the switching circuit 300 may be connected to the input / output circuit 200 through k input / output lines for transmitting data bits or parity bits to the input / output circuit 200 and for receiving data bits or parity bits from the input / output circuit 200, and the switching circuit 300 may be connected to the error correction circuit 400 through n input / output lines for transmitting data bits or parity bits to the error correction circuit 400 and for receiving data bits or parity bits from the error correction circuit 400. Herein, k may be equal to the number of sense amplifiers and the number of input / output lines included in the input / output circuit 200, and n may be equal to the number of sub-error correction circuits included in the error correction circuit 400.

[0046] According to an example embodiment, the switching control logic 510 may generate a switching signal SS based on the command / address signal CA and the control signal CTRL. The switching signal SS may control the switching circuit 300 to selectively control the connection between the input / output circuit 200 and the error correction circuit 400. According to the selected connection between the input / output circuit 200 and the error correction circuit 400, one of the plurality of sub-error correction circuits ECC1 to ECCn in the error correction circuit 400 may perform an error correction operation on data to be written to some memory cells in the memory cell array 100 or data to be read from some memory cells in the memory cell array 100.

[0047] The error correction circuit 400 may include a plurality of sub-error correction circuits ECC1 to ECCn for performing error correction operations. According to example embodiments, the sub-error correction circuits ECC1 to ECCn may correct different numbers of bit errors or detect different numbers of bit errors. In order to correct or detect different numbers of bit errors, the sub-error correction circuits ECC1 to ECCn may generate different numbers of parity bits. For example, in order to correct or detect a larger number of bit errors, the ratio of the number of parity bits generated by the sub-error correction circuits to the number of data bits corrected or detected by the sub-error correction circuits may be increased. For example, in order to correct or detect a larger number of bit errors, a larger number of parity bits may be required to resolve a larger number of bit errors.

[0048] According to example embodiments, one of the sub-error correction circuits ECC1 to ECCn (e.g., the first sub-error correction circuit ECC1 / 410) may generate parity bits PBs of write data WD received from the memory controller 20 through the buffer 600. According to the switching operation of the switching circuit 300, the error correction circuit 400 may transmit the write data WD and the generated parity bits PBs to some memory cells (e.g., the first memory region) among the plurality of memory cells in the memory cell array 100. According to example embodiments, one of the sub-error correction circuits ECC1 to ECCn (e.g., the first sub-error correction circuit ECC1 / 410) may receive data bits DBs and parity bits PBs from some memory cells (e.g., the first memory region) among the plurality of memory cells in the memory cell array 100, and perform an error correction operation with reference to the data bits DBs and the parity bits PBs. After performing the error correction operation, the error correction circuit 400 may transmit read data RD to the memory controller 20 through the buffer 600.

[0049] Figure 4 A memory device 10 according to an example embodiment is shown. Figure 4 , the memory cell array 100 may include a first memory area 110 and a second memory area 120. The input / output circuit 200 may include a first sub-input / output circuit 210 and a second sub-input / output circuit 220. The first sub-input / output circuit 210 may be connected to the switching circuit 300 through x input / output lines, and transmit x-bit data to the switching circuit 300 and receive x-bit data from the switching circuit 300. The second sub-input / output circuit 220 may be connected to the switching circuit 300 through y input / output lines, and transmit y-bit data to the switching circuit 300 and receive y-bit data from the switching circuit 300. For example, for connecting Figure 3 The k input / output lines of the input / output circuit 200 and the switching circuit 300 in Figure 4 The sum of the x input / output lines and the y input / output lines in (ie, k=x+y).

[0050] According to example embodiments, during a read operation, data of memory cells in the first memory region 110 may be amplified by x sense amplifiers in the first sub-input / output circuit 210 and input to the switching circuit 300 through x input / output lines. For example, during a read operation, data of memory cells included in the second memory region 120 may be amplified by y sense amplifiers in the second sub-input / output circuit 220 and input to the switching circuit 300 through y input / output lines. In other words, the x and y sense amplifiers may respectively amplify data output from the memory cells in the first memory region 110 and the second memory region 120, and provide the amplified data to the switching circuit 300 through x and y input / output lines, respectively.

[0051] According to example embodiments, during a write operation, data from the switching circuit 300 may be written to a memory cell in the first memory region 110 through the first sub-input / output circuit 210. For example, data from the switching circuit 300 may be written to a memory cell in the second memory region 120 through the second sub-input / output circuit 220.

[0052] The sub-error correction circuits ECC1 to ECCn may require different numbers of input / output lines to perform different error correction operations. For example, the first sub-error correction circuit ECC1 / 410 may require x input / output lines, and the second sub-error correction circuit ECC2 / 420 may require y input / output lines, because the error correction operations of the first sub-error correction circuit and the second sub-error correction circuit may be performed based on data bits DBs or parity bits PBs received from or to be transmitted to different input / output lines.

[0053] According to an example embodiment, the number of x input / output lines may be greater than the number of y input / output lines. For example, the first data written to or read from the memory cells in the first memory area 110 may include a first data bit and a first parity bit. An error of the first data bit may be detected or corrected based on the first parity bit. For example, the second data written to or read from the memory cells in the second memory area 120 may include a second data bit and a second parity bit. An error of the second data bit may be detected or corrected based on the second parity bit. For example, the first parity bit of the first data may have a different number of bits from the second parity bit of the second data. For example, the first parity bit of the first data may have a larger number of bits than the second parity bit of the second data. For example, the first parity bit of the first data may have 3 bits, and the second parity bit of the second data may have 2 bits.

[0054] For example, the first sub-error correction circuit 410 may require 50 input / output lines to perform the first error correction operation. The first sub-error correction circuit 410 may send or receive data bits DBs through 32 input / output lines among the 50 input / output lines. The 32 input / output lines can send or receive data bits DB. In addition, the first sub-error correction circuit 410 may send or receive parity bits PBs through 18 input / output lines among the 50 input / output lines. The 18 input / output lines can send or receive parity bits PBs. Since the first sub-error correction circuit 410 may include 32 input / output lines for sending or receiving data bits DBs and 18 input / output lines for sending or receiving parity bits PBs, in order to perform the first error correction operation, the ratio of the input / output lines for sending or receiving parity bits PBs to the input / output lines for sending or receiving data bits DBs in the first error correction operation may be 18 / 32.

[0055] For example, the second sub-error correction circuit 420 may require 78 input / output lines to perform the second error correction operation. The second sub-error correction circuit 420 may send or receive data bits DBs through 64 input / output lines among the 78 input / output lines, and send or receive parity bits PBs through 14 input / output lines among the 78 input / output lines. In the second error correction operation, the ratio of the input / output lines used to send or receive parity bits PBs to the input / output lines used to send or receive data bits DBs may be 14 / 64. Comparing between the first error correction operation and the second error correction operation, the first error correction operation may require a higher ratio of the input / output lines used to send or receive parity bits PBs to the input / output lines used to send or receive data bits DBs compared to the second error correction operation to detect and correct a larger number of bit errors.

[0056] Figure 5A A memory device 10 according to an example embodiment is shown. Figure 5B A sub-memory area 101 according to an example embodiment is shown.

[0057] refer to Figure 5A , the memory cell array 100 may include a first memory area 110 and a second memory area 120, and may include a plurality of sub-memory areas 101. The plurality of sub-memory areas 101 may include memory cells of the memory cell array 100. For example, the memory cells of the memory cell array 100 may be arranged in a matrix structure having rows and columns. Each sub-memory area 101 may include memory cells in at least one column or at least one row.

[0058] refer to Figure 5B, each sub-memory area 101 may include memory cells MC connected to "b" bit lines BL and "c" word lines WL, wherein the "b" bit lines BL include the first bit line BL1 to the b-th bit line BLb, and the "c" word lines include the first word line WL1 to the c-th word line WLc. In other words, the number of "b" bit lines BL may be "b", and the number of "c" bit lines WL may be "c". Herein, "b" and "c" may be natural numbers greater than zero. The memory cells MC may be arranged based on the points where the bit lines BL and the word lines WL intersect each other. In other words, the memory cells MC may be adjacent to the points where the bit lines BL and the word lines WL intersect.

[0059] refer to Figure 5B , the sub-memory area 101 may include memory cells MC connected to a plurality of bit lines BL. Each sub-memory area 101 may include a plurality of memory cells MC connected to "a" bit lines BL corresponding to a portion of "b" bit lines BL. The number of "a" bit lines BL may be "a". Herein, "a" is a natural number greater than 0. For example, the sub-memory area 101 may include memory cells MC connected to 64 bit lines BL. The number of 64 bit lines BL may be 64. The 64 bit lines BL may be adjacent to each other. For example, when a read voltage is applied to the first word line WL1, data stored in the memory cells MC connected to the 64 bit lines BL may be output to the input / output circuit 200 through the 64 bit lines BL. The output data from the memory cells MC may be amplified in the input / output circuit 200.

[0060] According to example embodiments, due to a high temperature process, a bit error may occur in the memory cells MC of some sub-memory regions 101. For example, the output data from the memory cells MC may have a bit error caused by the high temperature process. The high temperature process may be a welding process or any process performed at a high temperature. The error correction circuit 400 may perform an error correction operation to detect and correct a bit error in the output data from the memory cells MC. Since the possibility of a bit error occurring in some sub-memory regions 101 affected by the high temperature process is high, the error correction circuit 400 may perform an error correction operation for detecting and correcting a larger number of bit errors.

[0061] Reference again Figure 5A, the sub memory region 101 may be connected to the switching circuit 300 through the input / output circuit 200. The input / output circuit 200 may include a plurality of sense amplifiers SA, and each sense amplifier SA may amplify data received from each sub memory region 101 through the global bit line GBL, and transmit the amplified data to the switching circuit 300 through the corresponding input / output line IOLN. For example, each sense amplifier SA may receive data from the switching circuit 300 through the corresponding input / output line IOLN, and transmit the data to each sub memory region 101 through the global bit line GBL.

[0062] For example, when a write operation is performed on write data received from the memory controller 20, the error correction circuit 400 may generate a parity bit of the write data. The write data and the parity bit may be stored in the memory cell array 100. For example, when a read operation is performed on read data stored in the memory cell array 100, the error correction circuit 400 may perform an error correction operation for detecting and correcting errors with reference to the read data including the data bits DBs and the parity bits PBs output from the memory cell array 100. During the error correction operation, each sub memory area 101 may receive or output the data bits DB and / or the parity bits PB.

[0063] For example, the first memory area 110 may be affected by a high temperature process and therefore has a high probability of bit errors. The high temperature process may be a welding process or any process performed at a high temperature. For example, the high temperature may be higher than the operating temperature of the memory cell. For example, when the first memory area 110 is exposed to or affected by a high temperature process, the first sub-error correction circuit ECC1 / 410 may write the parity bits PBs and the data bits DBs used to correct or detect errors in the data bits DBs into the sub-memory area 101 of the first memory area 110. For example, the data bits DBs may be written to some sub-memory areas 101 of the first memory area 110, and the parity bits PBs may be written to other sub-memory areas 101 of the first memory area 110.

[0064] Fig. 6A A memory device 10 is shown performing a first error correction operation according to an example embodiment. Figure 6B A memory device 10 performing a second error correction operation according to example embodiments is shown. Figure 6C A memory device 10 including a multiplexer 310 corresponding to the switching circuit 300 according to example embodiments is shown.

[0065] The memory device 10 can be operated by using Fig. 6AThe first error correction circuit 410 in the first memory area 110 performs a first error correction operation on the first data in the first memory area 110 affected by the high temperature process, and by using Figure 6B The second sub-error correction circuit 420 in the memory performs a second error correction operation on the second data in the second memory area 120 which is not affected by the high temperature process.

[0066] refer to Fig. 6A During the first error correction operation of the memory device 10, the control logic 500 may send a switching signal SS to the switching circuit 300. The switching signal SS may control the sub-memory area 101 of the first memory area 110 to be connected to the first sub-error correction circuit 410. For example, a write operation for writing data into the first memory area 110 or a read operation for reading data from the first memory area 110 is performed as described below.

[0067] During a write operation, the control logic 500 may control the row decoder 700 and the column decoder 800 to write data bits DBs or parity bits PBs into at least some memory cells in the first memory area 110. When write data WD is received from the memory controller 20, the first sub-error correction circuit 410 may generate data bits DBs and parity bits PBs based on the write data WD, and write the data bits DBs and parity bits PBs into the sub-memory area 101 in the first memory area 110.

[0068] According to example embodiments, the first memory area 110 may include 50 sub-memory areas 101. The first sub-error correction circuit 410 may write the data bits DBs of the write data WD into the 32 sub-memory areas 101 by sending the data bits DBs (e.g., 32 data bits) to the 32 sub-memory areas 101. In addition, the first sub-error correction circuit 410 may write the parity bits (e.g., 18 parity bits) of the write data WD into the 18 sub-memory areas 101 by sending the parity bits PBs to the 18 sub-memory areas 101. For example, some of the sub-memory areas 101 of the first memory area 110 may store the data bits DBs of the write data WD, and the other sub-memory areas 101 of the first memory area 110 may store the parity bits PBs of the write data WD.

[0069] During a read operation, the memory device 10 may output read data RD, which may be generated by detecting and correcting errors of data stored in the first memory area 110. According to example embodiments, the control logic 500 may control the row decoder 700 and the column decoder 800 to read data bits DBs or parity bits PBs stored in at least some memory cells of the first memory area 110. The first sub-error correction circuit 410 may receive the data bits DBs and the parity bits PBs from the first memory area 110 through the switching circuit 300, and perform a first error correction operation for detecting or correcting errors of the data bits DBs using the parity bits PBs.

[0070] refer to Figure 6B During the second error correction operation of the memory device 10, the control logic 500 may send a switching signal SS to the switching circuit 300. The switching signal SS may control the sub memory area 101 of the first memory area 110 and the second memory area 120 to be connected to the second sub error correction circuit 420. Since both the second memory area 120 and the first memory area 110 are connected to the second sub error correction circuit 420, the number of input / output lines IOLN may be increased, and thus a high-speed error correction operation may be performed.

[0071] For example, a write operation for writing data into the first memory area 110 and the second memory area 120 or a read operation for reading data from the first memory area 110 and the second memory area 120 is similar to the above description of Fig. 6A The operation described.

[0072] refer to Fig. 6A and Figure 6B , the first error correction operation and the second error correction operation performed by the first sub-error correction circuit 410 and the second sub-error correction circuit 420 in the error correction circuit 400 may correct different numbers of bit errors or detect different numbers of bit errors. For example, the first sub-error correction circuit 410 may correct 3 bit errors and / or detect 4 bit errors in the first error correction operation, and the second sub-error correction circuit 420 may correct 2 bit errors and / or detect 3 bit errors in the second error correction operation. For example, the first sub-error correction circuit 410 may correct and detect a larger number of bit errors than the second sub-error correction circuit 420. For example, during a single read operation or write operation, the ratio of the number of parity bits PBs to the number of data bits DBs in the first error correction operation may be higher than the ratio of the number of parity bits PBs to the number of data bits DBs in the second error correction operation.

[0073] For example, the first sub-error correction circuit 410 may transmit the data bits DBs to 32 sub-memory regions 101 in the first memory region 110, and transmit the parity bits PBs to 18 sub-memory regions 101. Therefore, the ratio of the number of input / output lines IOLN for transmitting the parity bits PBs to the number of input / output lines IOLN for transmitting the data bits DBs may be 18 / 32. In addition, the second sub-error correction circuit 420 may transmit the data bits DBs to 64 sub-memory regions 101 in the first memory region 110 and the second memory region 120, and transmit the parity bits PBs to 14 sub-memory regions 101. Therefore, the ratio of the number of input / output lines IOLN for transmitting the parity bits PBs to the number of input / output lines IOLN for transmitting the data bits DBs may be 14 / 64.

[0074] refer to Figure 6C , the switching circuit 300 can be implemented as a multiplexer 310. Based on the switching signal SS received from the control logic 500, the multiplexer 310 can be similar to the above Fig. 6A and Figure 6B For example, the multiplexer 310 may be controlled by the switching signal SS to transmit data included in at least one of the first memory area 110 and the second memory area 120 to one of the first sub-error correction circuit 410 and the second sub-error correction circuit 420 .

[0075] For example, you can use Fig. 6A , Figure 6B and Figure 6C The error correction operation is performed by two memory areas including the first memory area 110 and the second memory area 120 and two sub-error correction circuits including the first sub-error correction circuit 410 and the second sub-error correction circuit 420. The number of memory areas and the number of sub-error correction circuits may vary and are not limited thereto.

[0076] Fig. 7A A memory device 10a performing a first error correction operation according to example embodiments is shown. Figure 7B A memory device 10a performing a second error correction operation according to example embodiments is shown. Figure 7C A memory device 10 a including a multiplexer 310 corresponding to the switching circuit 300 according to example embodiments is shown. Fig.7D A first sub-memory area 101 a and a second sub-memory area 101 b according to an example embodiment are shown.

[0077] refer to Fig. 7A , Figure 7B and Figure 7C, the memory cell array 100a may include a first memory region 110 and a second memory region 120. For example, the first memory region 110 may include a first region in the memory cell array 100a, which is marked with oblique lines. The first memory region 110 may include memory cells MC affected by a high temperature process. The second memory region 120 may include a second region in the memory cell array 100a, which is not marked with oblique lines. The second memory region 120 may include memory cells MC not affected by a high temperature process. In addition, the memory cell array 100a may include sub-memory regions 101. For example, each sub-memory region 101 may be connected to each sense amplifier in the input / output circuit 200. The sub-memory region 101 may include a first sub-memory region 101a and a second sub-memory region 101b.

[0078] For example, the first and second sub memory regions 101a and 101b may transmit or receive data bits DBs or parity bits PBs to or from the error correction circuit 400 through the global bit lines GBL.

[0079] refer to Fig.7D, the first sub-memory region 101a and the second sub-memory region 101b may include memory cells MC connected to different bit lines BL. For example, the first sub-memory region 101a may be connected to the bit lines BL1 and BL2, and the second sub-memory region 101b may be connected to the bit lines BLa to BLb. For example, all memory cells MC (110a) in the first sub-memory region 101a may be affected by the high temperature process and are part of the first memory region 110. In addition, only the first memory cells MC (110b) in the second sub-memory region 101b may be affected by the high temperature process to become part of the first memory region 110. The second memory cells MC (120) in the second sub-memory region 101b may not be affected by the high temperature process and are part of the second memory region 120. For example, the first memory cells MC (110b) affected by the high temperature process in the second sub-memory region 101b may be memory cells in the left region of each second sub-memory region 101b, and the second memory cells MC (120) not affected by the high temperature process in the second sub-memory region 101b may be memory cells MC in the right region of each second sub-memory region 101b. Alternatively, the first memory cells MC (110b) affected by the high temperature process in the second sub-memory region 101b may be memory cells in the right region of each second sub-memory region 101b, and the second memory cells MC not affected by the high temperature process in the second sub-memory region 101b may be memory cells MC in the left region of each second sub-memory region 101b.

[0080] The memory device 10a can be constructed by using Fig. 7A The first error correction circuit 410 in the embodiment performs a first error correction operation on data written into or read from the first memory area 110 affected by the high temperature process, and performs a first error correction operation on the ... Figure 7B The second sub-error correction circuit 420 in the embodiment performs a second error correction operation on the data written into the second memory area 120 which is not affected by the high temperature process or the data read from the second memory area 120 which is not affected by the high temperature process.

[0081] refer to Fig. 7ADuring the first error correction operation of the memory device 10a, the control logic 500 may send a switching signal SS to the switching circuit 300. The switching signal SS may control the input / output line IOLN corresponding to the first memory region 110 to be connected to the first sub-error correction circuit 410. For example, the input / output line IOLN corresponding to the first memory region 110 may be connected to the memory cells MC in the first sub-memory region 101a and the first memory cells MC in the second sub-memory region 101b that are affected by the high temperature process through the input / output circuit 200. In addition, a write operation for writing data bits DBs or parity bits PBs into the first memory regions 110a and 110b or a read operation for reading data bits DBs or parity bits PBs from the first memory region 110 is similar to the above description of Fig. 6A and Figure 6B The operation described.

[0082] refer to Figure 7B During the second error correction operation of the memory device 10a, the control logic 500 may send a switching signal SS to the switching circuit 300. The switching signal SS may control the connection of the input / output line IOLN corresponding to the second memory area 120 to the second sub-error correction circuit 420. The input / output line IOLN corresponding to the second memory area 120 may be connected to the second memory cell MC in the second sub-memory area 101b that is not affected by the high temperature process through the input / output circuit 200. In addition, a write operation for writing data into the second memory area 120 or a read operation for reading data from the second memory area 120 is similar to the above description of Fig. 6A and Figure 6B The operation described.

[0083] refer to Figure 7C , the switching circuit 300 can be implemented as a multiplexer 310. Based on the switching signal SS received from the control logic 500, the multiplexer 310 can be similar to the above Fig. 7A and Figure 7B The switching circuit 300 described in FIG.

[0084] Figure 8 A memory system 1 according to an example embodiment is shown. Figure 8 , the memory controller 20 may include an error correction circuit 400. Figure 2 Differently, the error correction circuit 400 in the memory controller 20 may be used to detect or correct bit errors of data in the memory cell array 100 .

[0085] Fig. 9 Shows Figure 8 Memory system 1. Reference Fig. 9, the memory controller 20 may include an error correction circuit 400 .

[0086] According to an example embodiment, one of the sub-error correction circuits ECC1 to ECCn (e.g., the first sub-error correction circuit 410) may generate parity bits PBs of write data WD received from the host HOST. The memory controller 20 may provide a command / address signal CA to the memory device 10 to write the write data WD and the parity bits PBs of the write data WD into the memory cells. For example, when one of the sub-error correction circuits ECC1 to ECCn (e.g., the first sub-error correction circuit 410) generates the parity bits PBs of the write data WD, the memory controller 20 may provide a command / address signal CA to the memory device 10 to write the write data WD and the parity bits PBs into some memory cells (e.g., the first memory area).

[0087] For example, when the first sub-error correction circuit 410 generates the parity bits PBs, the memory controller 20 may write the data bits DBs and the parity bits PBs into the first memory region affected by the high temperature process. In other words, the memory controller 20 may determine the memory region corresponding to the specific sub-error correction circuit that generates the parity bits PBs, and write the data bits DBs and the parity bits PBs into the determined memory region.

[0088] In addition, one of the sub-error correction circuits ECC1 to ECCn (e.g., the first sub-error correction circuit 410) may receive data bits DBs and parity bits PBs from some memory cells (e.g., the first memory region) among the plurality of memory cells in the memory cell array 100, and perform an error correction operation with reference to the data bits DBs and the parity bits PBs. After performing the error correction operation, the error correction circuit 400 may transmit the read data RD to the memory controller 20.

[0089] For example, when the memory controller 20 receives data bits DBs and parity bits PBs from a first memory region, where the first memory region is affected by a high temperature process, the first sub-error correction circuit 410 may perform an error correction operation. In other words, the memory controller 20 may determine a sub-error correction circuit corresponding to a specific memory region and perform an error correction operation.

[0090] Fig.10 is a flowchart of a method of operating the memory system 1 according to an example embodiment.

[0091] In operation S910, a first error correction operation may be performed on the first memory area 110 through the input / output line IOLN corresponding to the first memory area 110 by using the first sub-error correction circuit 410. For example, the first memory area 110 may be a memory area having a temperature exceeding the operating temperature of the memory cell when a high temperature process is performed on the memory device 10. For example, the high temperature process may be a reflow soldering process for attaching the memory device 10 to a PCB or the like at a high temperature. In addition, the high temperature process may include any process performed at a temperature higher than the operating temperature of the memory cell.

[0092] In operation S920 , a second error correction operation may be performed on the second memory area 120 through the input / output line IOLN corresponding to the second memory area 120 by using the second sub error correction circuit 420 .

[0093] According to example embodiments, one of the first error correction operation and the second error correction operation may be selected by a switching signal SS generated based on a command / address signal CA received by the memory device 10 .

[0094] According to example embodiments, the first memory region 110 may be electrically connected to the first sub error correction circuit 410 through, for example, a global bit line GBL, a sense amplifier SA, and an input / output line IOLN. The second memory region 120 may be electrically connected to the second sub error correction circuit 420 through, for example, a global bit line GBL, a sense amplifier SA, and an input / output line IOLN.

[0095] Based on the memory device and the operation method thereof, according to the example embodiment, since the first error correction code requiring a large number of parity bits is used for a partial area of ​​the memory cell array having a high bit error rate, and the second error correction code requiring a small number of parity bits is used for another partial area of ​​the memory cell array having a low bit error rate, the number of parity bits can be optimized and the overhead of the memory cell area can be reduced. The efficiency of the memory device can be improved.

[0096] In some embodiments, the blocks or steps and functions of the methods or algorithms described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in software modules executed by a processor, or in a combination of software and hardware. If implemented in software, the functions may be stored or transmitted on a tangible, non-transitory computer-readable medium as one or more instructions or codes. The software module may reside in, for example, a random access memory (RAM), a flash memory, a read-only memory (ROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD ROM, or any other suitable form of storage medium.

[0097] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art at the time of filing this application that features, characteristics, and / or elements described in conjunction with a specific embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically indicated. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A memory system, comprising: A memory cell array comprising a plurality of memory regions, the plurality of memory regions comprising a first memory region and a second memory region; an input / output circuit configured to amplify outputs from the memory cell array and comprising a plurality of input / output lines for transmitting or receiving data bits and parity bits to or from the plurality of memory regions; an error correction circuit, comprising a plurality of sub-error correction circuits, the plurality of sub-error correction circuits comprising a first sub-error correction circuit and a second sub-error correction circuit, wherein the first sub-error correction circuit is used to perform a first error correction operation on a first data bit of the first memory area received through the plurality of input / output lines, and the second sub-error correction circuit is used to perform a second error correction operation on a second data bit of the second memory area received through the plurality of input / output lines, and a switching circuit connected between the memory cell array and the first sub-error correction circuit and between the memory cell array and the second sub-error correction circuit, wherein: The plurality of input / output lines include a first input / output line connected only to the first memory area and a second input / output line connected only to the second memory area, the switching circuit is configured to electrically connect the first sub-error correction circuit to only the first of the first input / output line and the second input / output line, and to electrically disconnect the second sub-error correction circuit from both the first input / output line and the second input / output line at the same time, and the switching circuit being configured to electrically disconnect the first sub-error correction circuit from the first input / output line and to electrically connect the second sub-error correction circuit to both the first input / output line and the second input / output line at the same time, wherein the first sub-error correction circuit performs the first error correction operation on some memory cells included in the first memory area, and The second sub-error correction circuit performs the second error correction operation on other memory cells included in the first memory area and all memory cells included in the second memory area.

2. The memory system according to claim 1, further comprising: The control logic is configured to control the switching circuit.

3. The memory system of claim 2, wherein: The first memory area and the second memory area each include a sub-memory area, The first input / output line corresponds to a sub memory area included in the first memory area, and The second input / output line corresponds to a sub memory area included in the second memory area.

4. The memory system according to claim 3, wherein: During the first error correction operation, the first sub-error correction circuit writes data bits into some sub-memory areas included in the first memory area, and writes parity bits into other sub-memory areas included in the first memory area.

5. The memory system according to claim 4, wherein: A ratio of the number of sub-memory areas in which parity bits are written by the first sub-error correction circuit to the number of sub-memory areas in which data bits are written during the first error correction operation is higher than a ratio of the number of sub-memory areas in which parity bits are written by the second sub-error correction circuit to the number of sub-memory areas in which data bits are written during the second error correction operation.

6. The memory system according to claim 1, wherein: The first memory region includes a memory region having a temperature higher than an operating temperature of memory cells in the memory cell array when a high temperature process is performed on the memory system.

7. The memory system according to claim 6, wherein: The high temperature process includes a reflow soldering process.

8. The memory system according to claim 1, wherein: The first error correction operation and the second error correction operation include correcting different numbers of bit errors or detecting different numbers of bit errors.

9. The memory system of claim 1, wherein: The input / output circuit also includes a plurality of sense amplifiers, and Sub memory regions included in the plurality of memory regions are connected to the input / output lines extending from the plurality of sense amplifiers.

10. A memory device comprising: A memory cell array comprising a plurality of memory regions, the plurality of memory regions comprising a first memory region and a second memory region; an input / output circuit configured to amplify outputs from the memory cell array and comprising a plurality of input / output lines for transmitting or receiving data bits and parity bits to or from the plurality of memory regions; an error correction circuit, comprising a plurality of sub-error correction circuits, the plurality of sub-error correction circuits comprising a first sub-error correction circuit and a second sub-error correction circuit, wherein the first sub-error correction circuit is used to perform a first error correction operation on a first data bit of the first memory area received through the plurality of input / output lines, and the second sub-error correction circuit is used to perform a second error correction operation on a second data bit of the second memory area received through the plurality of input / output lines; a switching circuit connected between the memory cell array and the first sub-error correction circuit and between the memory cell array and the second sub-error correction circuit; and control logic configured to control the switching circuit to electrically connect only the first memory area to the first sub-error correction circuit, and to control the switching circuit to selectively connect both the first memory area and the second memory area to the second sub-error correction circuit, wherein the plurality of input / output lines include first input / output lines connected only to the first memory area and second input / output lines connected only to the second memory area, the number of the first input / output lines is less than the number of the second input / output lines, wherein the first sub-error correction circuit performs the first error correction operation on some memory cells included in the first memory area, and The second sub-error correction circuit performs the second error correction operation on other memory cells included in the first memory area and all memory cells included in the second memory area.

11. The memory device according to claim 10, wherein: The first memory area has a higher bit error rate than the second memory area.

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