Semiconductor device and integrated circuit manufacturing method

Abstract

The present invention provides a method for manufacturing a semiconductor device and an integrated circuit. In some examples, the method for manufacturing an integrated circuit includes receiving a workpiece, and the workpiece includes a substrate and a plurality of fins extending from the substrate, forming a first layer on a side surface of each of the fins, so that a groove defined by the first layer extends between the fins, forming a cutting structure in the groove, forming a first gate structure on the first fin of the fins, and forming a second gate structure on the second fin of the fins, so that the cutting structure is located between the first gate structure and the second gate structure.

Description

Technical Field

[0001] The embodiment of the present invention relates to a method for manufacturing an integrated circuit, and more particularly to a gate cutting structure. Background Art

[0002] The integrated circuit industry has experienced rapid growth. In the evolution of integrated circuits, functional density (the number of interconnected devices per unit chip area) has generally increased as geometry (the smallest component or circuit that can be produced using a manufacturing process) has decreased. This reduction in size generally has the benefit of increasing production capacity and reducing associated costs. However, this reduction in size also increases the complexity of designing and forming the devices that contain these integrated circuits. Parallel advances in formation methods have enabled the accurate and reliable production of increasingly complex designs.

[0003] For example, advances in manufacturing methods can implement three-dimensional designs such as fin field effect transistors. Fin field effect transistors can be viewed as structures that are generally planar devices that are extruded from a substrate to a gate. An exemplary fin field effect transistor has a thin fin (or fin-shaped structure) that extends upward from a substrate. The channel region of the field effect transistor is formed in a vertical fin, and the gate is located on the channel region of the fin (such as the channel region that covers the fin). The gate covering the fin can increase the contact area between the channel region and the gate, allowing the gate to control the channel from multiple sides. In some applications, the above structure can be implemented in a variety of ways. Fin field effect transistors can reduce short channel effects, reduce leakage current, and increase current. In other words, fin field effect transistors are faster, smaller, and more efficient than planar devices.

[0004] The fins of the fin field effect transistor extend parallel to the entire substrate, and the gate is perpendicular to the fins, so that the gate can extend over multiple fins and around multiple fins. However, circuits generally require nearby fin field effect transistors to have electrically isolated gates. The method of forming this structure can be to first form a single gate, cut a groove to separate the single gate into two gates, and fill the groove with dielectric material to isolate the two gates after cutting. In additional or other ways, the placeholder material can reserve space for the gate. The placeholder material is cut to separate it and the dielectric material is inserted. After removing the placeholder material, a gate component is formed at the place where the placeholder material is removed, and the dielectric material can separate and isolate the gate component. As the size of the device decreases, the space between the fins can be reduced, which can affect the ability to perform these cutting processes and other processes. Advances in reducing the size of the cutting area, improving cutting alignment and / or improving cutting consistency have the potential to increase yield, reduce variability, reduce circuit area, and provide other advantages. Summary of the invention

[0005] A method for manufacturing an integrated circuit provided by one embodiment of the present invention includes: receiving a workpiece, and the workpiece includes a substrate and a plurality of fins extending from the substrate; forming a first layer on the side surface of each of the fins, so that the groove defined by the first layer extends between the fins; forming a cutting structure in the groove; and forming a first gate structure on the first fin of the fins, and forming a second gate structure on the second fin of the fins, so that the cutting structure is located between the first gate structure and the second gate structure.

[0006] A method for manufacturing an integrated circuit provided by one embodiment of the present invention includes: receiving a substrate having a plurality of fins extending from the substrate; forming a dielectric layer on the side surface of a first fin of the fins; forming a cutting structure along a side of the dielectric layer opposite to the first fin; recessing the dielectric layer so that the first fin and the cutting structure extend higher than the dielectric layer; forming a gate structure on the first fin and the cutting structure; and recessing the gate structure to form a second gate and a first gate on the first fin, wherein the cutting structure electrically isolates the second gate from the first gate.

[0007] An integrated circuit device provided by one embodiment of the present invention includes a substrate; a first fin and a second fin extending from the substrate; a dielectric layer extending between the first fin and the second fin; a first cutting structure located on the dielectric layer; a first gate structure located on the first fin; and a second gate structure located on the second fin, so that the first gate structure and the second gate structure are separated by the first cutting structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A and Figure 1B The present invention is a flowchart of a method for manufacturing a gate cut structure in various embodiments.

[0009] Figures 2 to 6 and Figures 8 to 9 1 is a perspective view of a workpiece manufactured by a method according to various embodiments of the present invention.

[0010] Figure 7 It is a cross-sectional view of a workpiece manufactured by the method along the length direction of the fin in various embodiments of the present invention.

[0011] Figures 10 to 13 It is a cross-sectional view along the gate region of a workpiece manufactured by the method in various embodiments of the present invention.

[0012] Fig.14 and Fig.15 A cross-sectional view of a workpiece along a gate region having a thinned cutting structure in various embodiments of the present invention.

[0013] Fig.16The flowchart is a method for manufacturing a workpiece using a self-aligned contact process in various embodiments of the present invention.

[0014] Figures 17 to 19 It is a cross-sectional view along the gate region of a workpiece manufactured by a self-aligned contact process in various embodiments of the present invention.

[0015] Fig. 20 It is a cross-sectional view along the gate region of a workpiece manufactured by a self-aligned contact process in various embodiments of the present invention.

[0016] Fig.21 and Fig. 22 A cross-sectional view of a workpiece along a gate region having a thinned cutting structure in various embodiments of the present invention.

[0017] Fig.23 The flowchart is a method for manufacturing a workpiece having a multi-layer gate cutting structure according to various embodiments of the present invention.

[0018] Fig.24 and Fig.25 A perspective view of a workpiece formed by a method of manufacturing a multi-layer gate cutting structure in various embodiments of the present invention.

[0019] Fig.26 and Fig. 27 1 is a cross-sectional view of a workpiece along a gate region in various embodiments of the present invention.

[0020] Fig.28 1 is a cross-sectional view of a workpiece along a gate region in various embodiments of the present invention.

[0021] Fig.29A and Fig.29B The flowchart is a method for manufacturing a workpiece having a multi-layer gate cutting structure according to various embodiments of the present invention.

[0022] Figure 30 to Figure 36 1 is a perspective view of a workpiece manufactured by a method according to various embodiments of the present invention.

[0023] Figures 37 to 40 1 is a cross-sectional view of a workpiece along a gate region in various embodiments of the present invention.

[0024] The reference numerals are as follows:

[0025] 100, 1600, 2300, 2900 methods

[0026] Step 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 1602, 1604, 1606, 1608, 2302, 2304, 2306, 2308, 2310, 2312, 2314, 2316, 2902, 2904, 2906, 2908, 2910, 2912, 2914, 2916, 2918, 2920, 2922, 2924, 2926, 2928, 2930, 2932

[0027] 200, 1400, 1500, 1700, 2000, 2100, 2200, 2400, 2800, 3000 workpieces

[0028] 202 substrate

[0029] 204 Fins

[0030] 206, 208 Fin top hard mask

[0031] 302 first dielectric layer

[0032] 304 Groove

[0033] Thickness: 306, 1302, 1804, 2508, 2706, 2810, 3004, 3202, 4006

[0034] 402, 402A, 402B, 402C, 402D, 2502, 2802, 3402 cutting structure

[0035] 402' Concave cutting structure

[0036] 404, 1402, 1404, 2102, 2104 Width

[0037] 602 second dielectric layer

[0038] 604 Placeholder Gate

[0039] 606, 1102, 1104, 1406, 1702, 1704, 2002, 2106, 2702, 2704, 4002, 4004 Distance

[0040] 608 Placeholder Gate Hard Mask Layer

[0041] 702 Sidewall Spacer

[0042] 704 Source / Drain Structure

[0043] 706 Contact Etch Stop Layer

[0044] 708 interlayer dielectric layer

[0045] 902, 904 Cutting patterned hard mask

[0046] 1202 Functional Gate

[0047] 1204 Interface layer

[0048] 1206 gate dielectric layer

[0049] 1208 Work Function Layer

[0050] 1210 Gate filling layer

[0051] 1304 Second interlayer dielectric layer

[0052] 1306, 1902 contacts

[0053] 1802 Self-aligned contact dielectric layer

[0054] 2504, 2804 First floor

[0055] 2506, 2806 Second floor

[0056] 2808 Third Floor

[0057] 3002 First cutting structure dielectric layer

[0058] 3102 Second cutting structure dielectric layer

[0059] 3302 The third cutting structure dielectric layer

[0060] 3304 Fourth cutting structure dielectric layer

[0061] 3602 Fifth cutting structure dielectric layer DETAILED DESCRIPTION

[0062] The different embodiments or examples provided below can implement different structures of the present invention. The following specific components and arrangement embodiments are used to simplify the present invention and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes an embodiment in which the two are in direct contact, or an embodiment in which the two are separated by other additional components but not in direct contact. In addition, the structure of the embodiment of the present invention is connected to another structure and / or coupled to another structure, which means that the structure can directly contact another structure, or an additional structure can be formed between the structure and the other structure (i.e., the structure does not directly contact the other structure).

[0063] In addition, spatially relative terms such as "below", "below", "below", "above", "above", or similar terms may be used to simplify the description of the relative relationship between one element and another element in the diagram. Spatially relative terms may be extended to elements used in other orientations, rather than being limited to the orientation of the diagram. In addition, multiple examples of the present invention may repeatedly use the same reference numerals for simplicity, but elements with the same reference numerals in multiple embodiments and / or arrangements do not necessarily have the same corresponding relationship.

[0064] Integrated circuits include an increasing number of active and passive circuit devices formed on a substrate or chip, one example being the FinFET. For space and other considerations, the FinFET can be configured with parallel fins and parallel gates, with the gates perpendicular to the fins. Because the gate can be shared, a single gate structure can extend over multiple fins corresponding to multiple devices and / or over multiple fins forming a single larger device.

[0065] In contrast, in cases where the circuit requires an electrically isolated gate, the technology of an embodiment of the present invention provides an insulating cutting structure between the device fins, which can separate the gates. A self-aligned process can be used to form the cutting structure, and a spacer material can be formed on the side of the fin to control the distance between the cutting structure and the adjacent fin. This can eliminate alignment problems that may exist with other technologies, thereby improving yield. Improving the alignment and accuracy of the cutting structure can reduce the space between the fin and the cutting structure. Similarly, the thickness of the cutting structure can be reduced. In some examples, the minimum cutting structure width is less than or equal to the minimum fin width of the fin field effect transistor. In some examples, portions of the cutting structure can be thinned to provide additional space for coupling to contacts of adjacent gates. These advantages are merely examples, and any particular embodiment does not necessarily have a particular advantage.

[0066] Embodiments of the present invention provide examples of integrated circuits containing multiple field effect transistors, and forming electrically isolated gates on the channel regions of selected field effect transistor devices. In this regard, Figure 1A and Figure 1B Flowchart of method 100 for manufacturing workpiece 200 with gate cut structure in various embodiments of the present invention. Additional steps may be provided before, during, and after method 100, and other embodiments of method 100 may replace or omit some of the steps. Figures 2 to 6 and Figures 8 to 9 FIG. 1 is a perspective view of a workpiece 200 manufactured by performing the method 100 according to various embodiments of the present invention. Figure 7 It is a cross-sectional view of a workpiece 200 along the length direction of a fin during the method 100 in various embodiments of the present invention. Figures 10 to 13 FIG. 1 is a cross-sectional view of a workpiece 200 along a gate region during the method 100 in various embodiments of the present invention.

[0067] like Figure 1A Step 102 with Figure 2 As shown, a workpiece 200 is received. The workpiece 200 includes a substrate 202 on which a device is to be formed. In various examples, the substrate 202 includes a semiconductor element (single element) such as silicon or germanium in a crystalline structure, a semiconductor compound (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), a semiconductor alloy (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide), a non-semiconductor material (such as soda lime glass, fused silica, fused quartz and / or calcium fluoride) and / or a combination of the above. The substrate 202 may have a uniform composition or may include multiple layers, and some of the substrates 202 may be selectively etched to form fins. The layers may have similar or different compositions. In various embodiments, the layers of some substrates have inconsistent compositions, which may induce device stress to adjust device performance. Examples of layered substrates include substrates 202 of silicon on insulator. In these examples, the layers of substrate 202 may include insulating layers such as semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, and / or other suitable insulating materials.

[0068] Doped regions such as well regions may be formed on the substrate 202. In this regard, some portions of the substrate 202 may be doped with p-type dopants such as boron, boron difluoride, or indium, while other portions of the substrate 202 may be doped with n-type dopants such as phosphorus or arsenic, and / or other suitable dopants including combinations thereof.

[0069] In some examples, devices formed on substrate 202 extend beyond substrate 202. For example, fin field effect transistors and / or non-planar devices may be formed on fins 204 on substrate 202. Fins 204 may be any raised structure and may include fins 204 for fin field effect transistors, as well as fins 204 for forming other raised active and passive devices on substrate 202. Fins 204 and substrate 202 may have similar or different compositions. For example, in some embodiments, substrate 202 comprises primarily silicon, and one or more layers of fins 204 comprise primarily germanium or silicon germanium semiconductors. In some embodiments, substrate 202 comprises silicon germanium semiconductor, and fins 204 include one or more layers of silicon germanium oxide having a different silicon germanium ratio than substrate 202.

[0070] The method of forming the fin 204 may be to etch a portion of the substrate 202, and the etching method may be to deposit a plurality of layers on the substrate 202 and etch the layers, and / or other suitable techniques. For example, the fin 204 may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, the double patterning or multiple patterning process combines photolithography with a self-alignment process, and the pattern spacing produced may be smaller than the pattern spacing obtained using a single direct photolithography process. For example, one embodiment forms a sacrificial layer on the fin 204 and one or more fin top hard masks (such as fin top hard masks 206 and 208). The sacrificial layer is patterned using a photolithography process. Using a self-alignment process, spacers are formed along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the retained spacers can be used to pattern the fin 204. The method of patterning the fin 204 may be to remove the fin top hard masks 206 and 208 and the material of the fin 204 not covered by the spacers.

[0071] Fin top hard masks 206 and 208 may be used to control the etching process used to define fin 204 and may protect fin 204 during subsequent processes. As described above, fin top hard masks 206 and 208 may have different etch selectivities with respect to each other and with respect to the material of fin 204. Fin top hard masks 206 and 208 may include dielectric materials such as semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbonitrides, semiconductor carbon oxynitrides, and / or metal oxides.

[0072] The patterning and etching process can leave gaps of any width between the fins 204. This technique can be used to selectively form cutting structures in these gaps, and the gaps are greater than the minimum space, as described in detail below.

[0073] like Figure 1A Step 104 and Figure 3 As shown, a first dielectric layer 302 is formed on the substrate 202, the fins 204, and the fin top hard masks 206 and 208. The first dielectric layer 302 can fill the recesses between the fins 204 separated by the minimum space and define the grooves 304. The grooves 304 are used to form a cutting structure between some of the fins 204, and the space between these fins 204 is greater than the minimum space. This can be done by using a substantially conformal technique to form the first dielectric layer 302, whose thickness 306 is at least half of the minimum space between the fins 204, so that a first portion of the sidewall of the fin 204 merges with a second portion of the sidewall of another adjacent fin 204 (if the fins 204 are separated by the minimum space). In various examples, this means that the thickness 306 is between about 10nm and about 50nm.

[0074] In summary, the first dielectric layer 302 may be formed by any suitable process. In some examples, the first dielectric layer 302 may be deposited by atomic layer deposition, plasma-assisted atomic layer deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, and / or other suitable deposition processes. The first dielectric layer 302 may include a dielectric material such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, a semiconductor carbon nitride, a semiconductor carbon nitride oxide, a metal oxide, or the like. In some examples, the first dielectric layer 302 includes a plurality of sublayers of different dielectric materials.

[0075] like Figure 1A Step 106 and Figure 4 As shown, a cutting structure 402 is formed between the fins 204 in the grooves 304 in the first dielectric layer 302. The cutting structure 402 is self-aligned to the first dielectric layer 302, extends in a direction parallel to the fins 204, and is spaced a fixed distance from the nearest fin 204. Using the first dielectric layer 302 to align the cutting structure 402, rather than using photolithography to form the cutting structure, can avoid position errors caused by the alignment of the photolithography system. In this way, the space between the cutting structure 402 and the adjacent fins 204 can be safely reduced. The width 404 of the cutting structure 402 can be similarly and safely reduced, even if the cutting structures 402 throughout the workpiece 200 can have different widths. In some examples, the smallest width 404 of the smallest cutting structure 402 can be substantially the same as the smallest fin width, such as between about 3nm and about 10nm.

[0076] The cut structure 402 may include any suitable material such as one or more dielectric materials, including semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbonitrides, semiconductor carbon oxynitrides, and / or metal oxides. The material of the cut structure 402 may be selected to have a different etch selectivity than the material of the first dielectric layer 302, the fin top hard masks 206 and 208, and / or the fin 204. In various examples, the cut structure 402 includes hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, boron nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride, and / or other suitable materials.

[0077] The formation method of the cutting structure 402 can be any suitable process. In some examples, the deposition method of the cutting structure 402 adopts chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma-assisted atomic layer deposition and / or other suitable deposition systems. In these examples, the formation method of the cutting structure 402 adopts a flowable chemical vapor deposition process to fill the groove 304 in the first dielectric layer 302. After deposition, a chemical mechanical polishing process can be performed to remove the material of the cutting structure 402 from the top of the first dielectric layer 302. In summary, the chemical mechanical polishing process can use the first dielectric layer 302 as a chemical mechanical polishing stop layer. In subsequent examples, the formation technology used for the cutting structure with multiple different material layers is described.

[0078] like Figure 1A Step 108 and Figure 5 As shown, an etching process is performed to etch back the first dielectric layer 302 from between the fin 204 and the cutting structure 402. The etching process can be configured to retain some portions of the first dielectric layer 302 between the fin 204 and the cutting structure 402 for electrical isolation and to expose portions of the fin 204 and the cutting structure 402. In various examples, the distance that the fin 204 extends above the topmost surface of the remaining first dielectric layer 302 can be between about 100 nm and about 500 nm.

[0079] The etching process of step 108 may include any suitable etching technique, such as wet etching, dry etching, reactive ion etching, ashing, and / or other etching methods. In some embodiments, the etching process includes anisotropic dry etching using a fluorine-based etchant, an oxygen-based etchant, a chlorine-based etchant, a bromine-based etchant, an iodine-based etchant, other suitable etchant gases or plasmas, and / or combinations thereof. Specifically, the etching step and etching chemistry may be configured to etch the first dielectric layer 302 without significantly etching the fin 204, the fin top hard masks 206 and 208, or the cut structure 402.

[0080] like Figure 1A Step 110 and Figure 6 As shown, a second dielectric layer 602 may be formed on the fin 204 and the cut structure 402. The second dielectric layer 602 may include any suitable material such as one or more dielectric materials including semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbonitrides, and / or semiconductor carbon oxynitrides. In one example, the second dielectric layer 602 includes silicon oxide.

[0081] The second dielectric layer 602 may be formed by any suitable process. In some examples, the second dielectric layer 602 may be formed by thermal oxidation, atomic layer deposition, plasma-assisted atomic layer deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, and / or other suitable techniques. The second dielectric layer 602 may have any suitable thickness. In various examples, the second dielectric layer 602 may have a thickness between about 1 nm and about 5 nm.

[0082] like Figure 1A Step 112 and Figure 6 As shown, a placeholder gate 604 is formed on and around the channel region of the fin 204, and is formed on and around the cut structure 402. When the material of the functional gate structure is susceptible to the manufacturing process or difficult to pattern, some manufacturing processes may use a placeholder gate 604 of polysilicon, dielectric layer and / or other elastic material. In the gate-last process, the placeholder gate is then removed and replaced with a functional gate unit such as a gate, a gate dielectric layer, an interface layer, and the like. In this way, the placeholder gate 604 can reserve space for the functional gate formed subsequently.

[0083] The placeholder gate 604 is perpendicular to the fin 204 and the cutting structure 402 and extends a distance 606 above the top of the fin 204 (including any fin top hardmasks 206 and 208) and the cutting structure 402. In one example, the fin 204 and the fin top hardmasks 206 and 208 extend above the first dielectric layer 302 by a distance between about 100 nm and about 500 nm, and the placeholder gate 604 further extends from the uppermost surface of the fin top hardmasks 206 and 208 by a distance greater than or equal to 50 nm.

[0084] The placeholder gate 604 may include any suitable material, such as polysilicon, one or more dielectric materials (such as semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbonitrides, semiconductor carbon oxynitrides, or the like), and / or other suitable materials. The material of the placeholder gate 604 may be formed by any suitable process, including chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma-assisted atomic layer deposition, and / or other suitable deposition processes. In some examples, the material of the placeholder gate is blanket deposited and etched to selectively remove portions of the material of the placeholder gate 604, so that the placeholder gate 604 remains on the channel region of the fin 204. To assist in patterning, one or more placeholder gate hard mask layers 608 (such as dielectric materials or other suitable materials) may be formed on top of the placeholder gate material prior to etching.

[0085] like Figure 1AStep 114 and Figure 7 As shown, sidewall spacers 702 are formed on the side surfaces of the placeholder gate 604. In various examples, the sidewall spacers 702 include one or more layers of suitable materials such as dielectric materials, which may be semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbon oxynitrides, or the like. In one embodiment, the sidewall spacers 702 each include a first layer of semiconductor oxide, a second layer of semiconductor nitride located on the first layer, and a third layer of semiconductor oxide located on the second layer. In an embodiment, each layer of the sidewall spacers 702 has a thickness between about 1 nm and about 50 nm.

[0086] like Figure 1A Step 116 and Figure 7 As shown, the source / drain structure 704 is formed on the fin 204 and on both sides of the placeholder gate 604. The method of forming the source / drain structure 704 may be to recess the fin 204 and deposit a material in the recess, and the deposition method may adopt a deposition technique of chemical vapor deposition (such as vapor phase epitaxy and / or ultra-vacuum chemical vapor deposition), molecular beam epitaxy and / or other suitable processes. The epitaxial process may use a vapor phase and / or liquid phase precursor, which reacts with the composition of the retained portion of the fin 204 (such as silicon or silicon germanium) to form the source / drain structure 704. The semiconductor composition of the source / drain structure 704 may be similar to or different from the retained portion of the fin 204. For example, a source / drain structure 704 containing silicon may be formed on a fin 204 containing silicon germanium, and vice versa. When the source / drain structures 704 and the fins 204 include multiple semiconductors, the proportions of the semiconductors may be substantially similar or different.

[0087] The source / drain structure 704 may be in-situ doped to include p-type dopants such as boron, boron difluoride, or indium; n-type dopants such as phosphorus or arsenic; and / or other suitable dopants including combinations of the foregoing. In additional or other embodiments, the source / drain structure 704 may be doped using an implantation process (such as a junction implantation process) after the source / drain structure 704 is formed. With respect to the particular doping type, the source / drain structure 704 has an opposite doping type to the rest of the fin 204. For a p-type channel device, the fin 204 may be doped with an n-type dopants, while the source / drain structure 704 may be doped with a p-type dopants. For an n-type channel device, the fin 204 may be doped with a p-type dopants, while the source / drain structure 704 may be doped with an n-type dopants. Once the dopants are introduced into the source / drain structure 704, a doping annealing process such as a rapid thermal annealing process and / or a laser annealing process may be performed to activate the dopants.

[0088] The contact etch stop layer 706 may be formed on the source / drain structure 704 and may be along the top and sides of the placeholder gate 604. The contact etch stop layer 706 may include a dielectric layer (such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, or the like) and / or other suitable materials. In various embodiments, the contact etch stop layer 706 may include silicon nitride, silicon oxide, silicon oxynitride and / or silicon carbide. The deposition method of the contact etch stop layer 706 may be any suitable technology, including atomic layer deposition, plasma-assisted atomic layer deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition and / or high-density plasma chemical vapor deposition. The contact etch stop layer 706 may be deposited to any suitable thickness by a suitable technique. In some examples, the thickness of the contact etch stop layer 706 is between about 1 nm and about 50 nm.

[0089] like Figure 1A Step 118 and Figure 7 and Figure 8 As shown, an interlayer dielectric layer 708 is formed on the workpiece 200. The interlayer dielectric layer 708 can serve as an insulating layer that supports and isolates the conductive lines of the electrically multi-layer interconnect structure. In other words, the multi-layer interconnect structure can electrically interconnect the units of the workpiece 200 such as the source / drain structure 704 and the functional gate. The interlayer dielectric layer 708 can include a dielectric material (such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, or the like), a spin-on glass, a fluorine-doped silicate glass, a phosphosilicate glass, a borophosphosilicate glass, a Black (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, polyparaxylene, benzocyclobutene, (Dow Chemical, Midland, Michigan) and / or combinations thereof. The interlayer dielectric layer 708 may be formed by any suitable process, including chemical vapor deposition, physical vapor deposition, spin-on deposition, and / or other suitable processes.

[0090] like Figure 7 and Figure 8 As shown, a chemical mechanical polishing process may be performed after depositing the interlayer dielectric layer 708 to planarize the interlayer dielectric layer 708, the contact etch stop layer 706, the sidewall spacer 702 and / or the placeholder gate 604. Specifically, the chemical mechanical polishing process may remove the placeholder gate hard mask layer 608 from the top of the placeholder gate 604.

[0091] like Figure 1B Step 120 and Fig. 9As shown, one or more patterned hard masks (such as cut patterned hard masks 902 and 904) are formed on the interlayer dielectric layer 708 and the placeholder gate 604. The cut patterned hard masks 902 and 904 can be patterned to expose a portion (unnecessary portion) of the cut structure 402. In subsequent processes, the portion of the cut structure 402 not protected by the cut patterned hard masks 902 and 904 will be recessed, so that the gate formed subsequently can extend on the recessed cut structure 402 and connect. On the contrary, the portion of the cut structure 402 covered by the patterned cut patterned hard masks 902 and 904 will be retained to separate the gates.

[0092] The cut patterned hard masks 902 and 904 may include any suitable mask material such as one or more dielectric materials, including semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbonitrides, semiconductor carbon oxynitrides, or metal oxides. In one example, the cut patterned hard mask 902 may include amorphous silicon, and the second cut patterned hard mask may include a dielectric material.

[0093] like Figure 1B As shown in step 122, the cut structures 402 not covered by the cut patterned hard masks 902 and 904 are etched back, while other cut structures 402 covered by the cut patterned hard masks 902 and 904 remain intact. This practice includes one or more etching processes, each of which is configured to selectively etch a specific material or a group of materials. The etching process of step 122 may include any suitable etching technology, such as wet etching, dry etching, reactive ion etching, ashing and / or other etching methods.

[0094] like Fig.10 In some examples shown, step 122 includes a first etching process to etch back the portion of the placeholder gate 604 exposed by cutting the patterned hard masks 902 and 904 to expose at least the fin 204 and the top of the cutting structure 402 below. Fig.11 In the example shown, the first etching process is followed by a second etching process configured to remove the second dielectric layer 602 and recess the exposed cut structure 402 to form a recessed cut structure 402'. Any suitable amount of the cut structure 402 may be removed. In one example, after the exposed cut structure 402 is recessed, it is a distance 1102 below the topmost surface of the fin 204 (including any fin top hard mask 206 and / or 208 remaining on the fin 204) ranging from about 20 nm to about 100 nm. The space left by this manner of recessing the cut structure 402 can then be used to form a gate, and the gate extends between the fins 204 on both sides of the cut structure 402.

[0095] The second etching process may also recess the fin top hardmasks 206 and 208. In some examples, the second etching process completely removes the fin top hardmasks 206 and 208 to expose the fin 204. In some examples, the second etching process leaves the fin top hardmasks 206 and 208 with a combined thickness of no greater than about 10 nm. In both examples, the top of the fin 204 and any fin top hardmasks 206 and 208 is below the topmost surface of the unetched cut structure 402, which may reserve space for a functional gate extending over the fin 204. In some examples, step 122 causes the topmost surface of the unetched cut structure 402 to be above the fin 204 and the fin top hardmasks 206 and 208 by a distance 1104 between about 5 nm and about 50 nm.

[0096] like Figure 1B As shown in step 124 of the embodiment, an etching process may be performed to remove the remaining cut patterned hard masks 902 and 904 and the placeholder gate 604. This step may include removing the remaining second dielectric layer 602 from the fin 204 and the cut structure 402. The etching process may include one or more repetitions of a plurality of etching techniques, such as wet etching, dry etching, reactive ion etching, ashing, or the like, each configured to selectively etch a particular material or group of materials.

[0097] The recess left by the placeholder gate 604 is removed to form a functional gate. Figure 1B Step 126 and Fig.12 As shown, the method of forming the functional gate 1202 in the recess begins by forming an interface layer 1204 on the side surface of the fin 204 and on the top of the fin 204. In these embodiments, the fin top hard masks 206 and 208 have been removed. The interface layer 1204 may include an interface material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, other semiconductor dielectric materials, other suitable interface materials and / or combinations thereof. Any suitable process may be used to form the interface layer 1204 of a suitable thickness, and the process may include thermal growth, atomic layer deposition, chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, spin coating deposition and / or other suitable deposition processes. In some examples, the method of forming the interface layer 1204 is a thermal oxidation process, which may include a thermal oxide of a semiconductor present in the fin 204, such as silicon oxide of a silicon-containing fin 204, silicon germanium oxide of a silicon-germanium-containing fin 204, or the like.

[0098] like Figure 1BAs shown in step 128, a gate dielectric layer 1206 is formed on the interface layer 1204 on the side surface and the bottom of the fin 204. The gate dielectric layer 1206 may include one or more dielectric materials, which are generally characterized by a dielectric constant relative to silicon oxide. In some embodiments, the gate dielectric layer 1206 includes a high dielectric constant dielectric material, such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, aluminum oxide, hafnium oxide-aluminum oxide alloy, other suitable high dielectric constant dielectric materials and / or combinations thereof. In additional embodiments or other embodiments, the gate dielectric layer 1206 may include other dielectric layers such as semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, amorphous carbon, oxides of tetraethoxysilane, other suitable dielectric materials and / or combinations thereof. The gate dielectric layer 1206 may be formed by any suitable process, including atomic layer deposition, plasma-assisted atomic layer deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, spin-on deposition, and / or other suitable deposition processes. The gate dielectric layer 1206 may have any suitable thickness. In some examples, the gate dielectric layer 1206 has a thickness between about 0.1 nm and about 3 nm.

[0099] like Figure 1B As shown in step 130, one or more work function layers 1208 of the functional gate 1202 are formed on the gate dielectric layer 1206. Specifically, the work function layer 1208 can be formed on the top and side of the fin 204, and on the top and side of the cut structure 402 and the recessed cut structure 402'. Suitable materials for the work function layer include n-type and / or p-type work function materials depending on the device type. Exemplary p-type work function metals include titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, tungsten nitride, other suitable p-type work function materials and / or combinations thereof. Exemplary n-type work function metals include titanium, silver, tantalum aluminum, tantalum aluminum carbide, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, other suitable n-type work function materials and / or combinations thereof. The work function layer 1208 may be deposited by any suitable technique, including atomic layer deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, plasma-assisted atomic layer deposition, physical vapor deposition, and / or combinations thereof.

[0100] like Figure 1BAs shown in step 132, an electrode filling layer 1210 of the functional gate 1202 is deposited on the work function layer 1208. The electrode filling layer 1210 may include any suitable material, including metal (such as tungsten, aluminum, tantalum, titanium, nickel, copper, cobalt, or the like), metal oxide, metal nitride and / or a combination thereof. In one example, the electrode filling layer 1210 may include tungsten. The deposition method of the electrode filling layer 1210 may be any suitable technique, including atomic layer deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, plasma-assisted atomic layer deposition, physical vapor deposition and / or a combination thereof.

[0101] like Figure 1B Step 134 and Fig.13 As shown, a chemical mechanical polishing process may be performed to remove excess gate material (such as gate dielectric layer 1206, work function layer 1208, electrode filling layer 1210, and the like) outside of the functional gate 1202. Specifically, the chemical mechanical polishing process removes the conductive material of the functional gate 1202 including the work function layer 1208 and the electrode filling layer 1210 from the top of the cut structure 402 that is not recessed in step 122. In this manner, these cut structures 402 provide insulating structures that can electrically isolate the functional gates 1202. Therefore, the functional gates 1202 produced by the above-mentioned techniques extend and are aligned in the same plane, but are electrically isolated by the cut structures 402. As shown in FIG. Fig.13 As shown, the recessed cutting structure 402 ′ does not serve as an insulating structure, and the functional gate 1202 extends on the recessed cutting structure 402 ′.

[0102] In contrast, the CMP process may leave a portion of the conductive material of the functional gate 1202 on the fin 204 and any fin top hard masks 206 and 208. In these examples, the thickness 1302 of the functional gate 1202 on the fin 204 is between about 5 nm and about 50 nm.

[0103] like Figure 1B As shown in step 136, the workpiece 200 may then be subjected to subsequent fabrication processes. In various examples, these fabrication processes include forming additional interlayer dielectric layers (e.g., second interlayer dielectric layer 1304), forming contacts 1306 coupled to the source / drain structure 704 and the functional gate 1202, forming the rest of the electrical interconnect structure, dicing, packaging, and other fabrication processes.

[0104] These remaining processes may include forming contacts electrically coupled to the functional gate 1202. In some examples, changing the pattern of the cut patterned hard masks 902 and 904 in step 120 may thin the wider cut structure 402 horizontally to provide additional coupling area for the contacts. Examples of the thinned cut structure formed by method 100 may be used in conjunction with Fig.14and Fig.15 illustrate. Fig.14 and Fig.15 A cross-sectional view of a workpiece having a thinned cutting structure along a gate region in various embodiments of the present invention.

[0105] like Fig.14 As shown, workpiece 1400 is substantially similar to workpiece 200, with the following differences. Cut patterned hard masks 902 and 904 protect only a portion of cut structure 402A, and the width 1402 of the top of cut structure 402A is narrower than the width 1404 of the bottom. In some examples, the width 1404 of the bottom is about 500nm, and the width 1402 of the top is between about 3nm and about 490nm. The distance 1406 that the top extends above the bottom can be any height. In various examples, the distance 1406 that the top extends above the bottom is between about 20nm and about 150nm.

[0106] As shown, when the second interlayer dielectric layer 1304 is formed on the functional gate 1202 , the narrower cut structure 402A allows a larger area for the contact 1306 to be coupled to the functional gate 1202 .

[0107] Fig.15 The workpiece 1500 is similar to the workpiece 200 and the workpiece 1400, except for the differences described below. Specifically, the workpiece 1500 is substantially similar to the workpiece 1400, except that the narrower top of the cut structure 402B is disposed in the middle of the wider bottom of the cut structure 402B. This arrangement allows more area to be used for the contact 1306 coupled to the functional gate 1202 when forming the second interlayer dielectric layer 1304 on the functional gate 1202.

[0108] The above method 100 can be used for self-aligned contact process. Examples of the present invention can provide integrated circuits containing multiple field effect transistors, and cutting techniques used to form electrically isolated gates on the channel regions of selected field effect transistor devices. In this regard, Fig.16 Flowchart of method 1600 for fabricating workpiece 1700 using self-aligned contact process in various embodiments of the present invention. Additional steps may be provided before, during, and after method 1600, and other embodiments of method 1600 may replace or omit some of the steps. Figures 17 to 19 It is a cross-sectional view along the gate region of a workpiece 1700 manufactured by the method 1600 using a self-aligned contact process in various embodiments of the present invention.

[0109] like Fig.16 As shown in step 1602, the workpiece 1700 is performed Figure 1A and Figure 1B The process of steps 102 to 134 makes the workpiece 1700 substantially similar to the workpiece 200, with the differences as follows. Fig.17 As shown in step 1604 of the present invention, an etching process is performed to recess the material of the functional gate 1202 (such as the gate dielectric layer 1206, the work function layer 1208, the gate fill layer 1210, and the like) to expose the top of the cut structure 402 that was not recessed in step 122. Various examples control the etching so that the top of the functional gate 1202 is higher than the top of the fin 204 and any remaining fin top hard mask 206 and / or 208 by a distance 1702 between about 5 nm and about 50 nm. In these examples, the cut structure 402 extends above the top of the etched functional gate 1202 by a distance 1704 between about 1 nm and about 30 nm. The etching process may include any suitable etching technique, such as wet etching, dry etching, reactive ion etching, ashing and / or other etching methods, and the etching steps and etching chemicals may be configured to etch the materials of the gate fill layer 1210, the work function layer 1208 and / or the gate dielectric layer 1206 without significantly etching the cutting structure 402.

[0110] like Fig.16 Step 1606 and Fig.18 As shown, a self-aligned contact dielectric layer 1802 is formed on the etched functional gate 1202. The self-aligned contact dielectric layer 1802 may include any suitable material such as one or more dielectric materials, including semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbonitrides, semiconductor carbon oxynitrides, and / or metal oxides. In various examples, the self-aligned contact dielectric layer 1802 includes hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, boron nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and / or silicon carbon oxynitride.

[0111] The self-aligned contact dielectric layer 1802 may be formed by any suitable process. In some examples, the self-aligned contact dielectric layer 1802 is deposited by chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma-assisted atomic layer deposition, and / or other deposition processes. After deposition, a chemical mechanical polishing process may be performed to remove material outside the gate region. After the chemical mechanical polishing process, the planarized self-aligned contact dielectric layer 1802 in the gate region may have any suitable thickness 1804. In various examples, the thickness 1804 of the self-aligned contact dielectric layer 1802 is between about 30 nm and about 500 nm.

[0112] like Fig.16 Step 1608 and Fig.19As shown, the workpiece 1700 is then subjected to subsequent processing. In various examples, the additional processing includes forming contacts 1902 coupled to the source / drain structure 704 and the functional gate 1202, forming the rest of the electrical interconnect structure, dicing, packaging, and other processing.

[0113] In some examples, the etching of step 1604 may intentionally or unintentionally recess portions of the cutting structure 402 . Fig. 20 The workpiece 2000 is substantially similar to the workpiece 1700, with the following differences. As shown, the top of the cut structure 402 is recessed below the top of the functional gate 1202. The recessed portion of the cut structure 402 can be filled with a self-aligned contact dielectric layer 1802. In various examples, the self-aligned contact dielectric layer 1802 extends below the functional gate 1202 by a distance 2002 between about 1 nm and about 50 nm.

[0114] In some examples, changing the pattern of cutting the patterned hard masks 902 and 904 in step 120 can thin the wider cut structure 402 horizontally to provide additional coupling area for the contacts. Fig.21 and Fig. 22 illustrate. Fig.21 and Fig. 22 A cross-sectional view of a workpiece along a gate region having a thinned cutting structure in various embodiments of the present invention.

[0115] Fig.21 The workpiece 2100 is shown to be similar to the workpiece 1700, with the following differences. The cut patterned hard masks 902 and 904 protect only a portion of the cut structure 402C, so that the cut structure 402C is formed to have a width 2102 at the top that is narrower than the width 2104 at the bottom. In some examples where the width 2104 at the bottom is about 500 nm, the width 2102 at the top can be between about 3 nm and about 490 nm. The distance 2106 that the top extends above the bottom can be any value. In various examples, the distance 2106 that the top extends above the bottom is between about 20 nm and about 150 nm. As shown, the narrower cut structure 402C allows for more space for the contact 1902 coupled to the functional gate 1202.

[0116] Fig. 22 The workpiece 2200 is shown to be substantially similar to the workpiece 1700 and the workpiece 2100, with the following differences. Specifically, the workpiece 2200 is substantially similar to the workpiece 2100, with the difference that the narrower top of the cutting structure 402D is disposed in the middle of the wider bottom of the cutting structure 402D. This arrangement allows a larger space for the contact 1902 to couple to the functional gate 1202.

[0117] As mentioned above, the cutting structure may include a variety of similar or different materials. The material differences of the cutting structure can be used to selectively etch specific layers of the cutting structure. In this regard, Fig.23 Flowchart of method 2300 for fabricating workpiece 2400 with multi-layer gate cutting structure in various embodiments of the present invention. Additional steps may be performed before, during, and after method 2300, and other embodiments of method 2300 may replace or omit some of the steps. Fig.24 and Fig.25 FIG. 2 is a perspective view of a workpiece 2400 formed by performing a method 2300 for fabricating a multi-layer gate cutting structure according to various embodiments of the present invention. Fig.26 and Fig. 27 FIG. 2 is a cross-sectional view of a workpiece 2400 formed by performing the method 2300 along a gate region in various embodiments of the present invention.

[0118] like Fig.23 Step 2302 and Fig.24 As shown, the workpiece 2400 is Figure 1A The process of steps 102 to 104 makes the workpiece 2400 substantially similar to the workpiece 200, with the differences as described below.

[0119] like Fig.23 Step 2304 and Fig.25 As shown, a cutting structure 2502 is formed between the fins 204 in the trench in the first dielectric layer 302. The cutting structure 2502 includes a first layer 2504 of a first material and a second layer 2506 of a second material, and the etching selectivity of the first material and the second material is different. The first layer 2504 and the second layer 2506 can each include a dielectric material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, a semiconductor carbonitride, a semiconductor carbon oxynitride and / or a metal oxide. In various examples, the first layer 2504 and the second layer 2506 of the cutting structure 2502 include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, boron nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride and / or other suitable materials.

[0120] The first layer 2504 and the second layer 2506 can have any suitable heights. In one example, the upper surface of the first layer 2504 is substantially coplanar with the top of the fin 204 including any fin top hardmask 206 and / or 208. In this example, the thickness 2508 of the second layer 2506 is between about 10 nm and about 30 nm.

[0121] The first layer 2504 and the second layer 2506 of the cutting structure 2502 may be formed by any suitable process. In some examples, the deposition method of the cutting structure 2502 uses chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma-assisted atomic layer deposition, and / or other suitable deposition processes. In these examples, the first layer 2504 is formed by a flowable chemical vapor deposition process that is configured to fill the trench 304 in the first dielectric layer 302. The first layer 2504 is then etched back to create a recess in which the second layer 2506 can be deposited. In some examples, the step of forming the first layer 2504 does not fill the trench 304 to leave a recess in the trench 304, and the recess is then used to deposit the second layer 2506. The deposition process may be followed by a chemical mechanical polishing process to remove the material of the first layer 2504 and the second layer 2506 from the top of the first dielectric layer 302.

[0122] like Fig.23 As shown in step 2306, the workpiece 2400 is performed Figure 1A and Figure 1B The process of steps 108 to 120 may include forming a cutting patterned hard mask 902 on a portion of the multi-layer cutting structure 2502. Fig.23 Step 2308 and Fig.26 As shown, the cutting structure 2502 not covered by the patterned hard masks 902 and 904 is etched back, while the cutting structure 2502 covered by the patterned hard masks 902 and 904 remains intact. The etching technology used in this step is configured to etch the second layer 2506 of the cutting structure 2502 without significantly etching the first layer 2504. The surface (defined by the first layer 2504) provided by the selective etching of the second layer 2506 is substantially flat and free of dishing or rounded corners, and a consistent and controlled etching depth can be provided without the need for precise etching time. The etching of step 2308 may include any suitable etching technology, such as wet etching, dry etching, reactive ion etching, ashing and / or other etching methods. In some embodiments, the fin top hard mask 206 and / or 208 not covered by the patterned hard masks 902 and 904 is etched back. In some examples, the fin top hard mask 206 and / or 208 not covered by the cut patterned hard masks 902 and 904 are partially removed. For example, the fin top hard mask 208 is removed and the fin top hard mask 206 is partially removed. In some other examples, the fin top hard mask 206 and / or 208 not covered by the cut patterned hard masks 902 and 904 are completely removed to expose the fin 204.

[0123] like Fig.23 As shown in step 2310, the workpiece 2400 is performed Figure 1B In this manner, the functional gate 1202 formed on the fin 204 and the cut structure 2502 is substantially as described above. Fig.23 Step 2312 and Fig. 27 As shown, an etching process is performed to recess the material of the functional gate 1202 (e.g., the gate dielectric layer 1206, the work function layer 1208, the gate fill layer 1210, and the like) to expose the top of the unrecessed cut structure 2502. Various examples control the etching so that the top of the functional gate 1202 is between about 5 nm and about 50 nm above the fin 204 and any remaining fin top hard mask 206 and / or 208. In these examples, the cut structure 2502 extends above the top of the etched functional gate 1202 by a distance 2704 between about 1 nm and about 30 nm.

[0124] like Fig.23 As shown in step 2314, a self-aligned contact dielectric layer 1802 is formed on the etched functional gate 1202. The self-aligned contact dielectric layer 1802 is substantially as described above, and may include any suitable material such as one or more dielectric materials, including semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbonitrides, semiconductor carbon oxynitrides, and / or metal oxides.

[0125] The self-aligned contact dielectric layer 1802 may be formed by any suitable process, including chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma-assisted atomic layer deposition, and / or other deposition processes, and the self-aligned contact dielectric layer 1802 may have any suitable thickness 2706. In various examples, the thickness 2706 of the self-aligned contact dielectric layer 1802 is between about 30 nm and about 500 nm.

[0126] like Fig.23 As shown in step 2316, the workpiece 1700 may be subjected to subsequent fabrication processes. In various examples, these fabrication processes include forming contacts 1902 coupled to the source / drain structures 704 and the functional gate 1202, forming the rest of the electrical interconnect structure, dicing, packaging, and other fabrication processes.

[0127] In other examples, the cutting structure has additional layers. Fig.28The workpiece 2800 shown is substantially similar to the workpiece 2400. The cut structure 2802 of the workpiece 2800 includes a first layer 2804, a second layer 2806 located on the top and sides of the first layer 2804, and a third layer 2808 located on the second layer 2806. In this example, the thickness 2810 of the second layer 2806 is between about 3 nm and about 50 nm. The first layer 2804, the second layer 2806, and the third layer 2808 can each include any suitable material such as one or more dielectric materials, including semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbonitrides, semiconductor carbon oxynitrides, and / or metal oxides, and the materials of the first layer 2804, the second layer 2806, and the third layer 2808 can be different from each other.

[0128] Other examples of techniques for forming multi-layer gate cut structures can be combined with FIG. 29A to FIG. 40 Explanation. Considering this, Fig.29A and Fig.29B Flowchart of method 2900 for fabricating workpiece 3000 with multi-layer gate cutting structure in various embodiments of the present invention. Additional steps may be provided before, during, and after method 2900, and other embodiments of method 2900 may replace or omit some of the steps. Figure 30 to Figure 36 FIG. 2 is a perspective view of a workpiece 3000 manufactured by performing method 2900 in various embodiments of the present invention. Figures 37 to 40 This is a cross-sectional view of a workpiece 3000 along a gate region in various embodiments of the present invention.

[0129] like Fig.29A Step 2902 and Fig.30 As shown, the workpiece 3000 is Figure 1A As such, the workpiece 3000 may include the fin 204 and the first dielectric layer 302 on the fin 204, substantially as described above.

[0130] like Fig.29A Step 2904 and Fig.30 As shown, the first cut structure dielectric layer 3002 is formed on the upper surface and the side surface of the first dielectric layer 302. The first dielectric layer 302 is self-aligned to extend parallel to the fin 204, and the first cut structure dielectric layer 3002 is spaced a fixed distance from the closest fin 204.

[0131] The first cut structure dielectric layer 3002 may include any suitable material such as one or more dielectric materials, including semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbonitrides, semiconductor carbon oxynitrides, and / or metal oxides. In various examples, the first cut structure dielectric layer 3002 includes hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, boron nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbon nitride oxynitride, and / or other suitable materials.

[0132] The first cut structure dielectric layer 3002 may be formed by any suitable process. In some examples, the first cut structure dielectric layer 3002 is deposited by atomic layer deposition, plasma-assisted atomic layer deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, and / or other suitable deposition processes. The process may form the first cut structure dielectric layer 3002 of any suitable thickness. In some examples, the thickness 3004 of the first cut structure dielectric layer 3002 is substantially the same as the minimum fin width, such as between about 3 nm and about 10 nm.

[0133] like Fig.29A Step 2906 and Fig.31 As shown, the second cut structure dielectric layer 3102 is formed between the fins 204 in the trenches in the first cut structure dielectric layer 3002. The second cut structure dielectric layer 3102 may include any suitable material such as one or more dielectric materials, including semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbon nitrides, semiconductor carbon oxynitrides, and / or metal oxides. The material of the second cut structure dielectric layer 3102 may be selected to have an etching selectivity different from the etching selectivity of the first cut structure dielectric layer 3002. In one example, the first cut structure dielectric layer 3002 includes semiconductor nitrides, and the second cut structure dielectric layer 3102 includes flowable silicon oxide.

[0134] The second cutting structure dielectric layer 3102 may be formed by any suitable process. In some examples, the second cutting structure dielectric layer 3102 is deposited by chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma-assisted atomic layer deposition, and / or other suitable deposition processes. In these examples, the second cutting structure dielectric layer 3102 is formed by a flowable chemical vapor deposition process configured to fill the grooves in the first cutting structure dielectric layer 3002.

[0135] like Fig.29A Step 2908 and Fig.32As shown, the second cut structure dielectric layer 3102 is etched back. The remaining portion of the second cut structure dielectric layer 3102 left by the etch back process can have any suitable thickness 3202. In these examples, the thickness 3202 of the second cut structure dielectric layer 3102 remaining after the etch back process is between about 30 nm and about 100 nm.

[0136] The etching process of step 2908 may include any suitable etching technique, such as wet etching, dry etching, reactive ion etching, ashing and / or other etching methods. The etching step and etching chemistry are configured to etch the second cut structure dielectric layer 3102 without significantly etching the first cut structure dielectric layer 3002.

[0137] like Fig.29A Step 2910 and Fig.33 As shown, a third cutting structure dielectric layer 3302 is formed on the top of the second cutting structure dielectric layer 3102 and on the side of the first cutting structure dielectric layer 3002. The third cutting structure dielectric layer 3302 may include any suitable material such as one or more dielectric materials, including semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbon nitrides, semiconductor carbon nitrides and / or metal oxides. In some examples, the composition of the third cutting structure dielectric layer 3302 is substantially the same as that of the first cutting structure dielectric layer 3002.

[0138] The third cutting structure dielectric layer 3302 may be formed by any suitable process. In some examples, the third cutting structure dielectric layer 3302 may be deposited by atomic layer deposition, plasma-assisted atomic layer deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, and / or other suitable deposition processes.

[0139] like Fig.29A As shown in step 2912, a fourth cut structure dielectric layer 3304 is formed in the trench of the third cut structure dielectric layer 3302. The fourth cut structure dielectric layer 3304 may include any suitable material such as one or more dielectric materials, including semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbon nitrides, semiconductor carbon nitrides and / or metal oxides. In various examples, the fourth cut structure dielectric layer 3304 includes a high dielectric constant dielectric layer or other suitable dielectric materials.

[0140] The fourth cutting structure dielectric layer 3304 may be formed by any suitable process. In some examples, the fourth cutting structure dielectric layer 3304 is deposited by chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma-assisted atomic layer deposition, and / or other suitable deposition processes. In these examples, the fourth cutting structure dielectric layer 3304 may be formed by a chemical vapor deposition process configured to fill the grooves in the third cutting structure dielectric layer 3302.

[0141] like Fig.29A Step 2914 and Fig.34 As shown, a chemical mechanical polishing process is performed on the workpiece 3000 to remove excess material of the first cut structure dielectric layer 3002, the second cut structure dielectric layer 3102, the third cut structure dielectric layer 3302, the fourth cut structure dielectric layer 3304 and / or the first dielectric layer 302. The chemical mechanical polishing process can use one of the materials of the fin top hard mask 206 and 208 as a chemical mechanical polishing stop layer to planarize the above layers so that the above layers are substantially level with the fin 204. The chemical mechanical polishing process of this method can define a gate cut structure 3402, which includes the first cut structure dielectric layer 3002, the second cut structure dielectric layer 3102, the third cut structure dielectric layer 3302 and / or the fourth cut structure dielectric layer 3304.

[0142] like Fig.29A Step 2916 and Fig.35 As shown, the exposed portions of the first cut structure dielectric layer 3002 and the third cut structure dielectric layer 3302 are etched back. For a wider cut structure 3402, this step can cause the exposed portions of the first cut structure dielectric layer 3002 and the third cut structure dielectric layer 3302 at the edge of the cut structure 3402 to be recessed, while the portion protected by the fourth cut structure dielectric layer 3304 in the middle of the cut structure 3402 remains intact. The first cut structure dielectric layer 3002 and the third cut structure dielectric layer 3302 left by the etch back process can have any suitable height. In some examples, the top of the remaining portions of the exposed first cut structure dielectric layer 3002 and the third cut structure dielectric layer 3302 after etching is substantially the same height as the portion of the third cut structure dielectric layer 3302 below the fourth cut structure dielectric layer 3304. In some examples, the exposed and etched portions of the retained first and third cut dielectric layers 3002 and 3302 extend above the portion of the third cut dielectric layer 3302 below the fourth cut dielectric layer 3304 by a distance between about 10 nm and about 50 nm.

[0143] The etching process of step 2916 may include any suitable etching technique, such as wet etching, dry etching, reactive ion etching, ashing and / or other etching methods. The etching step and etching chemistry may be configured to etch the first cut structure dielectric layer 3002 and the third cut structure dielectric layer 3302 without significantly etching the fourth cut structure dielectric layer 3304 or the first dielectric layer 302.

[0144] like Fig.29B Step 2918 and Fig.36 As shown, a fifth cutting structure dielectric layer 3602 is formed on the recessed first cutting structure dielectric layer 3002 and the third cutting structure dielectric layer 3302. The fifth cutting structure dielectric layer 3602 may include any suitable material such as one or more dielectric materials, including semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbon nitrides, semiconductor carbon nitrides and / or metal oxides. In some examples, the fifth cutting structure dielectric layer 3602 has substantially the same composition as the fourth cutting structure dielectric layer 3304, and includes a high dielectric constant dielectric layer or other suitable dielectric materials.

[0145] The fifth cutting structure dielectric layer 3602 may be formed by any suitable process. In some examples, the fifth cutting structure dielectric layer 3602 is deposited by chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma-assisted atomic layer deposition, and / or other suitable deposition processes. After the fifth cutting structure dielectric layer 3602 is formed, a chemical mechanical polishing process may be performed.

[0146] like Fig.29A As shown in step 2920, the workpiece 3000 is Figure 1A and Figure 1B The process of steps 108 to 120 may include recessing the first dielectric layer 302, forming a second dielectric layer on the fin 204 and the cut structure 3402, forming a placeholder gate 604, and forming one or more cut patterned hard masks 902 and 904 on the workpiece 3000 to expose a set of cut structures 3402 to be recessed, so that the functional gate extends on the recessed cut structure 3402.

[0147] like Fig.29AAs shown in step 2922, the cut structures 3402 not covered by the cut patterned hard masks 902 and 904 are etched back, while other cut structures 3402 covered by the cut patterned hard masks 902 and 904 remain intact. This practice includes one or more etching processes, each of which is configured to selectively etch a specific material or a group of materials. The etching process of step 2922 may include any suitable etching technology, such as wet etching, dry etching, reactive ion etching, ashing and / or other etching methods.

[0148] like Fig.37 In some examples shown, step 2922 includes a first etching process that etches back the portion of the placeholder gate 604 exposed by cutting the patterned hard masks 902 and 904 to expose at least the fin 204 and the top of the cutting structure 3402 below. Fig.38 In the example shown, the first etching process is followed by a second etching process configured to remove the second dielectric layer 602 and recess the exposed portion of the cut structure 3402. In some examples, the second etching process is configured to selectively remove certain materials of the cut structure 3402, such as the fourth cut structure dielectric layer 3304 and the fifth cut structure dielectric layer 3602, without significantly etching other materials, such as the first cut structure dielectric layer 3002 and the third cut structure dielectric layer 3302. Thus, the upper surface of the remaining material of the cut structure 3402 can be a substantially flat surface without dishing, rounded corners, and other defects.

[0149] The second etching process may also recess the fin top hard masks 206 and 208. In some examples, the second etching process completely removes the fin top hard masks 206 and 208 to expose the fin 204. In some examples, the second etching process leaves the fin top hard masks 206 and 208 with a combined thickness of no greater than about 10 nm. In both examples, the top of the fin 204 and any fin top hard masks 206 and 208 is below the topmost surface of the unetched dicing structure 3402 to leave room for a functional gate extending over the fin 204.

[0150] like Fig.29B As shown in step 2924, an etching process is performed to remove the remaining cut patterned hard masks 902 and 904 and the placeholder gate 604. This step may include removing the remaining second dielectric layer 602 from the fin 204 and the cut structure 3402. The etching process may include one or more repeated passes of a plurality of etching techniques, such as wet etching, dry etching, reactive ion etching, ashing, or the like, each of which is configured to selectively etch a particular material or group of materials.

[0151] The recess left after removing the placeholder gate 604 can be used to form a functional gate. Fig.29B Step 2926 and Fig.39 As shown, Figure 1B Steps 126 to 134 are performed to form the functional gate 1202 in the recess. In the embodiment where the fin top hard masks 206 and 208 are removed, these steps may include forming an interface layer 1204 on the side surfaces and top of the fin 204, forming a gate dielectric layer 1206 on the interface layer 1204, forming one or more work function layers 1208 on the gate dielectric layer 1206, and / or forming a gate fill layer 1210 on the work function layer 1208, and each of the above steps is substantially as described above. A chemical mechanical polishing process may be performed to remove excess gate material (such as materials of the gate dielectric layer 1206, the work function layer 1208, the gate fill layer 1210, and the like) outside the functional gate 1202.

[0152] like Fig.29B Step 2928 and Fig.40 As shown, an etching process is performed to recess the material of the functional gate 1202 (e.g., the gate dielectric layer 1206, the work function layer 1208, the gate fill layer 1210, and the like) to expose the upper surface of the cut structure 3402 that was not recessed in step 2922. Various examples control the etching so that the top of the functional gate 1202 is above any remaining fin top hard mask 206 and / or 208 and the top of the fin 204 by a distance 4002 between about 5 nm and about 50 nm. In these examples, the cut structure 3402 extends above the etched functional gate 1202 by a distance 4004 between about 1 nm and about 30 nm. The etching process can include any suitable etching technique, such as wet etching, dry etching, reactive ion etching, ashing and / or other etching methods, and the etching steps and etching chemistry can be configured to etch the material of the gate fill layer 1210, the work function layer 1208 and / or the gate dielectric layer 1206 without significantly etching the cut structure 3402.

[0153] like Fig.29B Step 2930 and Fig.40 As shown, a self-aligned contact dielectric layer 1802 is formed on the etched functional gate 1202. The self-aligned contact dielectric layer 1802 may include any suitable material such as one or more dielectric materials, including semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbonitrides, semiconductor carbon oxynitrides, and / or metal oxides. In various examples, the self-aligned contact dielectric layer 1802 includes hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, boron nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and / or silicon carbon oxynitride.

[0154] The self-aligned contact dielectric layer 1802 may be formed by any suitable process. In some examples, the self-aligned contact dielectric layer 1802 is deposited by chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma-assisted atomic layer deposition, and / or other deposition processes. After deposition, a chemical mechanical polishing process may be performed to remove materials outside the gate region so that the self-aligned contact dielectric layer 1802 planarized in the gate region has any suitable thickness 4006. In various examples, the thickness 4006 of the self-aligned contact dielectric layer 1802 is between about 30 nm and about 500 nm.

[0155] like Fig.29B As shown in step 2932, the workpiece 3000 may then be subjected to subsequent fabrication processes. In various examples, these fabrication processes include forming contacts to couple to the source / drain structure 704 and the functional gate 1202, forming the rest of the electrical interconnect structure, dicing, packaging, and other fabrication processes.

[0156] Therefore, embodiments of the present invention provide examples of integrated circuits with gate cutting structures, and methods for forming integrated circuits. In some examples, the method includes receiving a workpiece, and the workpiece includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on the side surface of each of the fins, so that the groove defined by the first layer extends between the fins. A cutting structure is formed in the groove. A first gate structure is formed on the first fin of the fin, and a second gate structure is formed on the second fin of the fin, so that the cutting structure is located between the first gate structure and the second gate structure. In some examples, the first layer is recessed before forming the first gate structure and the second gate structure. The first layer is located between the first gate structure and the substrate, and between the second gate structure and the substrate. In some examples, the first layer is recessed before forming the first gate structure and the second gate structure, wherein after the first layer is recessed, the fin extends above the topmost surface of the first layer. In some examples, the cutting structure is a first cutting structure and the groove is a first groove. A second cutting structure is formed in a second trench defined by the first layer; and the second cutting structure is recessed so that the first gate structure extends over the second cutting structure. In some examples, the width of the first cutting structure is different from the width of the second cutting structure. In some examples, the step of recessing the second cutting structure includes forming a patterned hard mask on the first cutting structure and exposing the second cutting structure, and the step of recessing the second cutting structure uses a patterned hard mask to avoid significantly etching the first cutting structure. In some examples, the step of recessing the second cutting structure includes forming a patterned hard mask on a first portion of the first cutting structure and exposing a second portion of the first cutting structure and the second cutting structure. The step of recessing the second cutting structure further recesses the second portion of the first cutting structure so that the bottom width of the first cutting structure is greater than the top width of the first cutting structure. In some examples, each of the first cutting structure and the second cutting structure includes a first cutting structure layer of a first material and a second cutting structure layer of a second material located on the first cutting structure layer, wherein the step of recessing the second cutting structure removes the second cutting structure layer of the second cutting structure. In some examples, the first gate structure and the second gate structure are recessed. A dielectric layer is formed on the first gate structure and the second gate structure, wherein the cut structure extends into the dielectric layer. In some examples, the step of recessing the first gate structure and the second gate structure further recesses the cut structure, and the dielectric layer extends below the upper surface of the first gate structure and extends to the upper surface of the cut structure.

[0157] In other examples, the method includes receiving a substrate having a plurality of fins extending from the substrate. Forming a dielectric layer on a side surface of a first fin of the fins; and forming a cut structure along a side of the dielectric layer opposite the first fin. Recessing the dielectric layer so that the first fin and the cut structure extend above the dielectric layer. Forming a gate structure on the first fin and the cut structure; and recessing the gate structure to form a second gate and the first gate on the first fin, and the cut structure electrically isolates the second gate from the first gate. In some examples, the dielectric layer is located between the gate structure and the substrate, and between the cut structure and the substrate. In some examples, the step of forming the dielectric layer further forms the dielectric layer on a side surface of a second fin of the fin. The cut structure is a first cut structure. Forming a second cut structure along a side of the dielectric layer opposite the second fin. In some examples, the width of the first cut structure is different from the width of the second cut structure. In some examples, the second cut structure is recessed without recessing the first cut structure. In some examples, the first gate extends over the second cut structure. In some examples, the cutting structure is partially recessed so that the bottom of the cutting structure is wider than the top of the cutting structure.

[0158] In another example, the device includes a substrate; a first fin and a second fin extending from the substrate; a dielectric layer extending between the first fin and the second fin; a first cut structure located on the dielectric layer; a first gate structure located on the first fin; and a second gate structure located on the second fin, such that the first gate structure and the second gate structure are separated by the first cut structure. In some examples, the dielectric layer is a first dielectric layer, and the device also includes a second dielectric layer located on the first gate structure and the second gate structure, such that the first cut structure extends into the second dielectric layer. In some examples, the device also includes a second cut structure located on the dielectric layer and adjacent to the first fin, wherein a portion of the first gate structure extends over the second cut structure. In some examples, the first cut structure includes a first layer containing a first material and a second layer containing a second material, and the first material is different from the second material.

[0159] The features of the above embodiments are helpful for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing an integrated circuit, comprising: Receiving a workpiece, wherein the workpiece includes a substrate and a plurality of fins extending from the substrate; forming a first layer on the side surface of each of the plurality of fins, so that a groove defined by the first layer extends between the plurality of fins; forming a cutting structure in the groove; forming a first gate structure on a first fin of the plurality of fins, and forming a second gate structure on a second fin of the plurality of fins, such that the cutting structure is located between the first gate structure and the second gate structure; recessing the first gate structure and the second gate structure; and A dielectric layer is formed on the first gate structure and the second gate structure, wherein the cutting structure extends into the dielectric layer.

2. The method for manufacturing an integrated circuit as claimed in claim 1, further comprising recessing the first layer before forming the first gate structure and the second gate structure, wherein the first layer is located between the first gate structure and the substrate, and between the second gate structure and the substrate.

3. The method for manufacturing an integrated circuit as described in claim 1 further includes recessing the first layer before forming the first gate structure and the second gate structure, wherein after the first layer is recessed, the plurality of fins extend above the topmost surface of the first layer.

4. The method for manufacturing an integrated circuit as claimed in claim 1, wherein the cutting structure is a first cutting structure and the trench is a first trench, and the method further comprises: forming a second cutting structure in a second trench defined by the first layer; as well as The second cutting structure is recessed to allow the first gate structure to extend on the second cutting structure. 5 . The method for manufacturing an integrated circuit as claimed in claim 4 , wherein a width of the first cutting structure is different from a width of the second cutting structure.

6. The method for manufacturing an integrated circuit as described in claim 4, wherein the step of recessing the second cutting structure includes forming a patterned hard mask on the first cutting structure and exposing the second cutting structure, and wherein the step of recessing the second cutting structure adopts the patterned hard mask to avoid significantly etching the first cutting structure.

7. A method for manufacturing an integrated circuit as described in claim 4, wherein the step of recessing the second cutting structure includes forming a patterned hard mask on the first portion of the first cutting structure to expose the second portion of the first cutting structure and the second cutting structure, and wherein the step of recessing the second cutting structure also recesses the second portion of the first cutting structure so that the bottom width of the first cutting structure is greater than the top width of the first cutting structure.

8. The method for manufacturing an integrated circuit as described in claim 4, wherein each of the first cutting structure and the second cutting structure comprises a first cutting structure layer of a first material and a second cutting structure layer of a second material located on the first cutting structure layer, and wherein the step of recessing the second cutting structure removes the second cutting structure layer of the second cutting structure.

9. A method for manufacturing an integrated circuit, comprising: receiving a substrate having a plurality of fins extending from the substrate; forming a dielectric layer on a side surface of a first fin of the plurality of fins; forming a cutting structure along a side of the dielectric layer opposite to the first fin, wherein the dielectric layer covers a bottom surface and sidewalls of the cutting structure, and the bottom surface of the cutting structure is lower than a top surface of the dielectric layer; After forming the cutting structure, selectively recessing the dielectric layer until the first fin and the cutting structure extend above the recessed dielectric layer; forming a gate structure on the first fin and the cutting structure; as well as After forming the gate structure, the gate structure is recessed to form a second gate structure and a first gate structure on the first fin, and the cutting structure electrically isolates the second gate structure from the first gate structure. 10 . The method for manufacturing an integrated circuit as claimed in claim 9 , wherein the recessed dielectric layer is located between the first gate structure and a substrate, and between the cutting structure and the substrate.

11. The method for manufacturing an integrated circuit according to claim 9, wherein: The step of forming the dielectric layer also forms the dielectric layer on the side surface of a second fin of the plurality of fins, and the cutting structure is a first cutting structure, wherein the method further includes forming a second cutting structure along a side of the dielectric layer opposite to the second fin. 12 . The method for manufacturing an integrated circuit as claimed in claim 11 , wherein a width of the first cutting structure is different from a width of the second cutting structure. 13 . The method for manufacturing an integrated circuit as claimed in claim 11 , further comprising recessing the second cutting structure but not recessing the first cutting structure. 14 . The method for manufacturing an integrated circuit as claimed in claim 13 , wherein the first gate structure extends on the recessed second cutting structure. 15 . The method for manufacturing an integrated circuit as claimed in claim 9 , further comprising partially recessing the cutting structure so that a bottom of the cutting structure is wider than a top of the cutting structure.

16. The method for manufacturing an integrated circuit according to claim 9, further comprising: After the gate structure is recessed, the cutting structure is recessed so that the upper surface of the recessed cutting structure is lower than the upper surface of the first gate structure and the upper surface of the second gate structure; as well as An insulating layer is formed on the first gate structure and the second gate structure, wherein the insulating layer extends downward from the upper surface of the first gate structure to the upper surface of the recessed cutting structure.

17. A method for manufacturing an integrated circuit, comprising: receiving a workpiece comprising a substrate and a plurality of fins extending from the substrate; forming a first layer on the side surface of each of the plurality of fins, so that a first trench and a second trench extend between the plurality of fins, and the first layer defines each of the first trench and the second trench; forming a first cutting structure in the first trench, and forming a second cutting structure in the second trench; After forming the first cutting structure and the second cutting structure, selectively recessing the first layer until the plurality of fins, the first cutting structure, and the second cutting structure extend above the recessed first layer; as well as A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins, so that the first fin is located between the first cutting structure and the second cutting structure, and the second cutting structure is located between the first gate structure and the second gate structure.

18. The method for manufacturing an integrated circuit as claimed in claim 17, wherein the step of forming the first cutting structure and the second cutting structure comprises: Depositing a first dielectric layer in the first trench and the second trench; as well as depositing a second dielectric layer on the first dielectric layer in the first trench and the second trench, The composition of the first dielectric layer is different from that of the second dielectric layer.

19. The method for manufacturing an integrated circuit according to claim 18, further comprising: Before forming the first gate structure and the second gate structure, forming a placeholder gate structure on the first fin and the second fin; forming a patterned hard mask on the second cutting structure and exposing the first fin, the second fin and the first cutting structure; Using the patterned hard mask as an etch mask, and etching the workpiece to remove the second dielectric layer from the first cut structure; as well as The placeholder gate structure is selectively removed.

20. The method for manufacturing an integrated circuit as claimed in claim 17, wherein the step of forming the first gate structure and the second gate structure further comprises: A placeholder gate structure is formed to surround the first cutting structure and the second cutting structure.

21. A semiconductor device comprising: a substrate; a first fin and a second fin extending from the substrate; a dielectric layer extending between the first fin and the second fin; a first cutting structure located on the dielectric layer, wherein the dielectric layer covers the bottom surface and sidewalls of the first cutting structure, and the bottom surface of the first cutting structure is lower than the top surface of the dielectric layer; a first gate structure located on the first fin; and A second gate structure is located on the second fin, so that the first gate structure and the second gate structure are separated by the first cutting structure. 22 . The semiconductor device of claim 21 , further comprising a second cutting structure on the dielectric layer and adjacent to the first fin, wherein a portion of the first gate structure extends over the second cutting structure. 23 . The semiconductor device of claim 22 , wherein an upper surface of the first cutting structure is coplanar with an upper surface of the first gate structure. 24 . The semiconductor device of claim 22 , wherein a thickness of the first cutting structure is different from a thickness of the second cutting structure. 25 . The semiconductor device of claim 22 , wherein a composition of the first cutting structure is the same as a composition of the second cutting structure. 26 . The semiconductor device of claim 21 , wherein the first cutting structure comprises a first layer comprising a first material and a second layer comprising a second material, and the first material and the second material are different, wherein the second layer is located on the first layer.

27. The semiconductor device according to claim 21, further comprising: a third cutting structure located on the dielectric layer and adjacent to the second fin, The width of the third cutting structure is different from the width of the first cutting structure. 28 . The semiconductor device of claim 27 , wherein a portion of the first cutting structure is located in the dielectric layer, such that the portion of the first cutting structure is separated from the first fin and the second fin by the dielectric layer.

29. A semiconductor device comprising: a first fin-shaped structure located on a substrate; a first cutting structure, adjacent to the first fin structure and having a first upper surface; a first gate structure, located on the first fin structure and the first cutting structure; a second fin-shaped structure located on the substrate; a dielectric layer extending between the first fin structure and the second fin structure, wherein the dielectric layer covers the bottom surface and sidewalls of the first cut structure, and the bottom surface of the first cut structure is lower than the top surface of the dielectric layer; a second cutting structure, located between the first fin structure and the second fin structure and having a second upper surface, wherein the second upper surface is higher than the first upper surface; and A second gate structure is located on the second fin structure, wherein the second cutting structure electrically isolates the second gate structure from the first gate structure.

30. The semiconductor device according to claim 29, further comprising: A hard mask layer is located on the first fin structure, wherein the first gate structure is located on the hard mask layer.

31. The semiconductor device according to claim 30, further comprising: an interface layer located between the first gate structure and the sidewall of the first fin structure, The first gate structure directly contacts the hard mask layer.

32. The semiconductor device of claim 29, wherein the second cutting structure is raised higher than an upper surface of the second gate structure.

33. The semiconductor device according to claim 29, Each of the first cutting structure and the second cutting structure includes a first layer and a second layer, The second layer is located on the upper surface and side wall of the first layer.

34. The semiconductor device of claim 33, wherein a composition of the first layer is different from a composition of the second layer. 35 . The semiconductor device of claim 34 , wherein the second cutting structure further comprises another dielectric layer on an upper surface of the second layer, and the another dielectric layer is raised higher than an upper surface of the second gate structure.

36. A semiconductor structure comprising: a substrate; a first fin and a second fin extending from the substrate; a dielectric layer located on the substrate and extending between the first fin and the second fin; a first cutting structure located between the first fin and the second fin, wherein a portion of the first cutting structure is located in the dielectric layer and is separated from the first fin and the second fin by the dielectric layer, wherein an upper surface of the first cutting structure is higher than an upper surface of the first fin, wherein the dielectric layer covers a bottom surface and sidewalls of the first cutting structure, and a bottom surface of the first cutting structure is lower than a top surface of the dielectric layer; a first gate structure located on the first fin; and A second gate structure is located on the second fin, and the first cutting structure electrically isolates the second gate structure from the first gate structure.

37. The semiconductor structure of claim 36, further comprising: a second cutting structure, adjacent to the first fin, The first gate structure is also located on the second cutting structure, The composition of the second cutting structure is different from that of the first cutting structure.

38. The semiconductor structure of claim 36, further comprising: another dielectric layer, located on the first gate structure, the second gate structure and the first cutting structure, A portion of the lower surface of the other dielectric layer is lower than the upper surface of the first gate structure and directly contacts the upper surface of the first cutting structure.

39. The semiconductor structure of claim 36, wherein the first cut structure is an integral structure and comprises a top portion and a bottom portion, wherein a width of the top portion is smaller than a width of the bottom portion, and a portion of the bottom portion is located in the dielectric layer.

40. The semiconductor structure of claim 36, The first cutting structure includes a first layer formed of a first material and a second layer formed of a second material, and the second layer is located on the first layer. The second material is different from the first material, and the width of the second layer is smaller than the width of the first layer.

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