Method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device is provided, wherein a first recess in a semiconductor layer is provided between a first dummy gate and a second dummy gate. A first spacer is formed on a side wall of the first dummy gate, and a second spacer is formed on a side wall of the second dummy gate. The first and second spacers form a triangular spacer extension contacting a bottom surface of the first recess. After forming the first and second spacers, a second recess is formed in the semiconductor layer between the first dummy gate and the second dummy gate. A source / drain region is epitaxially grown in the second recess.

Description

Technical Field

[0001] Some embodiments of the present invention relate to methods for manufacturing semiconductor devices, and more particularly, to semiconductor devices having triangular spacer extensions and methods for forming the same. Background Art

[0002] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry continues to reduce the minimum feature size to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), so that more components can be integrated into a given area. However, reducing the minimum feature size also creates additional problems that need to be dealt with.

[0004] FinFETs are increasingly being used in integrated circuit manufacturing due to their small size and high performance. Fully strained channels further improve the performance of FinFETs, but there are still defects that need to be addressed due to the fully strained channel architecture. Summary of the invention

[0005] In one embodiment, a method for manufacturing a semiconductor device includes forming a first dummy gate and a second dummy gate on a semiconductor layer. Etching the semiconductor layer using the first dummy gate and the second dummy gate as a first mask. Etching the semiconductor layer forms a first recess disposed between the first dummy gate and the second dummy gate in the semiconductor layer. A first spacer is formed on a sidewall of the first dummy gate, and a second spacer is formed on a sidewall of the second dummy gate. The first spacer and the second spacer form a triangular spacer extension contacting a bottom surface of the first recess. After forming the first spacer and the second spacer, a second recess disposed between the first dummy gate and the second dummy gate is formed in the semiconductor layer. A source / drain region is epitaxially grown in the second recess.

[0006] According to another embodiment, a method for manufacturing a semiconductor device includes epitaxially growing a semiconductor layer on a substrate. Forming a first gate on the semiconductor layer. Etching the semiconductor layer using the first gate as a mask. Etching the semiconductor layer to form first and second recesses adjacent to the first gate in the semiconductor layer. Forming a spacer on a sidewall of the first gate. The spacer forms a triangular spacer extension that contacts a bottom surface of the first recess. Forming a second recess in the semiconductor layer using the spacer as a mask. Forming a source / drain region in the second recess. Forming a contact on the source / drain region.

[0007] According to yet another embodiment, a device includes a substrate having a fin. A first gate extends from the fin. A source / drain region is disposed in the fin adjacent to the first gate. A contact is disposed on the source / drain region. A spacer is disposed along a sidewall of the first gate. The spacer forms a triangular spacer extension extending to a topmost surface of the fin below the first gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Through the following detailed description in conjunction with the accompanying drawings, we can better understand the content of the embodiments of the present invention. It should be noted that, according to standard practices in the industry, many components (features) are not drawn to scale. In fact, in order to clearly discuss, the sizes of these components may be arbitrarily increased or decreased.

[0009] Figure 1 is a three-dimensional diagram illustrating an example of a FinFET according to some embodiments.

[0010] Figures 2 to 19B is a cross-sectional schematic diagram showing various intermediate steps of forming a FinFET according to some embodiments.

[0011] Description of reference numerals:

[0012] 50~base;

[0013] 56~Isolation area;

[0014] 58~Fin;

[0015] 82~source / drain region;

[0016] 92~gate dielectric layer;

[0017] 94~gate electrode;

[0018] 100~base;

[0019] 111~lightly doped source / drain region;

[0020] 114~Epitaxial layer;

[0021] 115~first depression;

[0022] 116~Semiconductor fin;

[0023] 117~Triangular interstitial extension;

[0024] 118~lining;

[0025] 120~Dielectric materials;

[0026] 122~Insulating materials;

[0027] 124~Shallow trench isolation area;

[0028] 130~dummy gate layer;

[0029] 131~dummy gate;

[0030] 132~mask layer;

[0031] 133~Mask;

[0032] 134~first gate sub-spacer;

[0033] 135~second gate sub-spacer;

[0034] 136~third grid sub-spacer;

[0035] 137~gate gap;

[0036] 138 ~ second depression;

[0037] 139~ epitaxial source / drain region;

[0038] 140~first interlayer dielectric;

[0039] 142~depression;

[0040] 144~gate dielectric layer;

[0041] 146~gate electrode;

[0042] 147~Metal work function layer;

[0043] 148~filling material;

[0044] 150~Second interlayer dielectric;

[0045] 152~gate contact;

[0046] 154~Source / drain contact;

[0047] 156~Silicide contact;

[0048] D1, D2 ~ first depth;

[0049] H1~height;

[0050] S1~bottom surface;

[0051] S2~top surface;

[0052] W1, W2 ~ width;

[0053] α~angle. DETAILED DESCRIPTION

[0054] The following disclosure provides many different embodiments or examples for implementing different components of the present invention. Specific examples of components and configurations are described below to simplify the description of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the following description mentions that a first component is formed on or above a second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples, and such repetition is for the purpose of simplicity and clarity, and is not intended to specify the relationship between the various embodiments and / or configurations discussed herein.

[0055] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to facilitate describing the relationship of one element or component to another (or additional) elements or components in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0056] Although not limiting the present disclosure, the manufacture of FinFETs may cover many embodiments. In such embodiments, the processes described below may be implemented on the corresponding fins. Through the contents of the present disclosure, a person skilled in the art to which the present invention belongs will be able to understand the various alternatives and extensions of the teachings provided herein, and these are all within the scope of the present disclosure. For example, although the embodiment shown is a FinFET, a person skilled in the art to which the present invention belongs will be able to recognize the applicability of the above teachings to planar transistors, microelectromechanical systems (MEMS) devices, three-dimensional integrated circuit (3DIC) devices, etc.

[0057] Some embodiments of the present invention may also include other components and processes. For example, a test structure may be included to assist in verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit device. For example, the test structure may include a test pad formed in a redistribution layer or formed on a substrate to enable testing of the three-dimensional package or the three-dimensional integrated circuit, use of a probe and / or a probe card, and the like. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods to improve yield and reduce costs.

[0058] Advantageous features of one or more embodiments disclosed herein include low source / drain capacitance due to the triangular profile of the spacer extension as a metal barrier for outward diffusion, resulting in faster device performance, preferred yield and product reliability. To improve reliability, mobile phone chips have a need for low power consumption, which depends on reducing the parasitic capacitance of the source / drain region. Unlike the low thermal stability of the interface between the contact metal and the source / drain epitaxy in the conventional structure, which may lead to low yield and poor reliability, the embodiments disclosed herein provide improved yield and reliability. Further advantageous features of at least some embodiments described and / or shown herein include lower capacitance, improved yield and stability due to the channel profile under the spacer. The process is compatible with standard integrated manufacturing processes without changing other cycle processes. At least some of the embodiments described herein can be extended to other embodiments using epitaxial technology that requires shape change, such as micro-electromechanical system devices, three-dimensional integrated circuit (3DIC) devices, etc.

[0059] Figure 1 A three-dimensional schematic diagram showing an example of a fin field effect transistor is provided for reference in accordance with some embodiments. The fin field effect transistor includes a fin 58 on a substrate 50 (e.g., a semiconductor substrate). An isolation region 56 is disposed in the substrate 50, and the fin 58 protrudes from and protrudes over the adjacent isolation region 56. Although the description and the drawings show that the isolation region 56 is separated from the substrate 50, the term "substrate" as used herein may be used to refer to the semiconductor substrate alone, or the semiconductor substrate including the isolation region 56. A gate dielectric layer 92 is disposed on the top surface of the fin 58 and along the sidewalls of the fin 58, and a gate electrode 94 is disposed on the gate dielectric layer 92. Source / drain regions 82 are disposed in opposite sides of the fin 58 relative to the gate dielectric layer 92 and the gate electrode 94. Figure 1 Reference cross-sectional schematic diagrams for the subsequent figures are further shown. Section AA is along the longitudinal axis of the gate electrode 94, and is taken as an example in a direction perpendicular to the current direction between the source / drain regions 82 of the fin field effect transistor. Section BB is perpendicular to section AA and along the longitudinal axis of the fin 58, such as the current direction between the source / drain regions 82 of the fin field effect transistor. Section CC is parallel to section AA and extends through one of the source / drain regions 82 of the fin field effect transistor. Subsequent figures refer to these reference cross-sections for clear description.

[0060] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments encompass solutions for planar devices, such as planar FETs.

[0061] Figures 2 to 19Bis a cross-sectional schematic diagram of an intermediate step in manufacturing a FinFET according to some embodiments. In addition to showing multiple fins / FinFETs, Figures 2 to 7 show Figure 1 Reference section AA is shown in . FIG. 8A to FIG. 9B and FIG. 14A to FIG. 19B Figure numbers ending with "A" indicate the Figure 1 Reference cross-section AA is shown (except that multiple fins / FinFETs are shown), while figures ending with "B" are shown along Figure 1 Similar section BB is shown. Figures 10 to 13 Is displayed along Figure 1 Section BB is shown.

[0062] exist Figure 2 In the invention, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc. The substrate may be doped (e.g., doped with a P-type dopant or an N-type dopant) or undoped. The substrate 100 may be a wafer, such as a silicon wafer. Generally speaking, a semiconductor-on-insulator (SOI) substrate is a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulating layer is provided on a substrate (typically a silicon or glass substrate). Other substrates, such as a multilayer or gradient substrate, may also be used.

[0063] The substrate 100 may have an N-type well region or a P-type well region (not explicitly shown) formed therein. The N-type well region or the P-type well region may be formed in the substrate 100 by performing an ion implantation process on the substrate 100. N-type dopants (e.g., arsenic ions) may be implanted into the substrate 100 to form the N-type well region. P-type dopants (e.g., boron ions) may be implanted into the substrate 100 to form the P-type well region.

[0064] exist Figure 3In the process, an epitaxial layer 114 is formed on the substrate 100. The epitaxial layer 114 can be formed, for example, by epitaxial growth or other similar processes. The epitaxial layer 114 may include a material such as silicon germanium (SiGe) or a similar material, and may be doped (for example, doped with P-type dopants or N-type dopants) or undoped. In one embodiment, the epitaxial layer 114 includes SiGe, and the germanium percentage is between about 10% and about 50%. SiGe includes a lower bandgap than Si, allowing for a larger hole mobility for a subsequently formed P-type metal oxide semiconductor (PMOS) device. A planarization process may be performed on the epitaxial layer 114. The epitaxial layer 114 may be planarized by any suitable planarization process, such as chemical mechanical polish (CMP), an etch-back process, a combination of the foregoing, and the like. In some embodiments, after the planarization process, the epitaxial layer may have a thickness of about About The thickness between.

[0065] exist Figure 4 In some embodiments, the epitaxial layer 114 and the substrate 100 are etched to form semiconductor fins 116 (also referred to as first semiconductor fins). In some embodiments, the first semiconductor fins 116 can be formed by etching grooves in the epitaxial layer 114 and the substrate 100. The aforementioned etching can be one or more of any acceptable etching processes, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination of the aforementioned. The aforementioned etching can be anisotropic. Although the semiconductor fins 116 shown have rounded corners and linear edges, the semiconductor fins 116 can have any other suitable shape, such as having tapered sidewalls. In some embodiments, the semiconductor fins 116 can have a thickness of about 1000 nm. About The height between.

[0066] The semiconductor fins 116 may be patterned by any suitable method. For example, the semiconductor fins 116 may be patterned using one or more photolithography processes, the photolithography process including a double patterning or multiple patterning process. In general, the double patterning or multiple patterning process combines photolithography and a self-aligned process, allowing the formation of patterns with a spacing smaller than that obtained using a single, direct photolithography process. Although the double patterning or multiple patterning process is not separately shown, in one embodiment, the double patterning or multiple patterning process may include forming a sacrificial layer on the substrate. The sacrificial layer is patterned using a photolithography process. Spacers are formed along the sides of the sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the first semiconductor fin 116 is patterned with the remaining spacers.

[0067] Including an epitaxial layer 114 formed of, for example, silicon germanium within the semiconductor fin 116 can increase the hole mobility of a subsequently formed PMOS transistor. Additionally, since germanium has a smaller energy gap than silicon, including the epitaxial layer 114 within the semiconductor fin 116 can result in a higher current within a subsequently formed PMOS transistor. In embodiments where an N-type metal-oxide semiconductor (NMOS) transistor is to be formed, the epitaxial layer 114 can be formed of a material that can increase carrier mobility, such as silicon carbide. The silicon carbide can be doped with an N-type dopant, such as phosphorus.

[0068] exist Figure 5 In some embodiments, an insulating material 122 is formed on the substrate 100 and the semiconductor fins 116 to fill the openings between the semiconductor fins. Figure 5 As shown, the insulating material 122 includes a liner 118 and a dielectric material 120 on the liner 118. The liner 118 may be formed as a conformal layer, with horizontal and vertical portions of the conformal layer having thicknesses similar to each other.

[0069] In some embodiments, the liner 118 is formed by oxidizing the exposed surfaces of the substrate 100 and the semiconductor fins 116 in an oxygen-containing environment. For example, by local oxidation of silicon (LOCOS), wherein oxygen (O2) may be included in the respective process gases. In other embodiments, for example, a combination of hydrogen (H2) and oxygen (O2) or in-situ steam generation (ISSG) of water vapor may be used to oxidize the exposed surfaces of the substrate 100 and the semiconductor fins 116. In other embodiments, a deposition technique is used to form the liner 118, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), sub-atmospheric chemical vapor deposition (SACVD), or a combination of the foregoing. In some embodiments, the liner 118 has a thickness of about 100 to about 1000. About The thickness between.

[0070] The dielectric material 120 is formed to fill the remaining portion of the opening between the semiconductor fins 116. The dielectric material 120 may overfill the opening between the semiconductor fins 116, so that a portion of the dielectric material 120 extends to the top surface of the semiconductor fins 116. In some embodiments, the dielectric material 120 may include silicon oxide, silicon carbide, silicon nitride, etc., or a combination thereof, and may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), low pressure chemical vapor deposition (LPCVD), etc., or a combination thereof. After the dielectric material 120 is deposited, an annealing / curing step may be performed to convert the flowable dielectric material 120 into a solid dielectric material. In some embodiments, the interface between the liner 118 and the dielectric material 120 is distinguishable due to different material properties (such as different types of materials and / or different densities).

[0071] exist Figure 6In some embodiments, the planarization process includes chemical mechanical polishing (CMP), an etch-back process, or a combination thereof. Figure 6 As shown, the planarization process may expose the top surface of the semiconductor fin 116. The planarization process may also planarize a portion of the semiconductor fin 116. After the planarization process is completed, the top surfaces of the semiconductor fin 116 and the insulating material 122 are flush (within process variation).

[0072] exist Figure 7 In the embodiment of the present invention, the insulating material 122 is recessed to form a shallow trench isolation (STI) region 124. The insulating material 122 is recessed so that the semiconductor fin 116 protrudes from the adjacent shallow trench isolation region 124. The shallow trench isolation region 124 is recessed using an acceptable etching process, such as one that is selective to the material of the shallow trench isolation region 124. For example, a plasma-less gas etching process (such as an etching process using hydrofluoric acid (HF) gas, ammonia (NH3) gas, etc.), a remote plasma assisted dry etching process (such as a process using hydrogen (H2), nitrogen trifluoride (NF3) and ammonia byproducts, etc.), or a chemical oxide removal method using diluted hydrofluoric acid (dHF).

[0073] exist Fig. 8A and Figure 8B In the embodiment, a dummy gate layer 130 is formed on the semiconductor fin 116 and the shallow trench isolation region 124, and a mask layer 132 is formed on the dummy gate layer 130. Before forming the dummy gate layer 130, a dummy dielectric layer (not explicitly shown) may be formed on the semiconductor fin 116 and the shallow trench isolation region 124. The dummy dielectric layer may be, for example, silicon oxide, silicon nitride, a combination of the foregoing, etc., and may be deposited or thermally grown according to an acceptable technique. The dummy gate layer 130 may be deposited on the semiconductor fin 116, and then the dummy gate layer 130 may be planarized, for example, by chemical mechanical polishing (CMP). A mask layer 132 may be deposited on the dummy gate layer 130. The dummy gate layer 130 may be, for example, amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 130 may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering deposition, or other known techniques for depositing conductive materials in the art to which the present invention pertains. The dummy gate layer 130 may be made of a material having a high etching selectivity relative to etching of the isolation region. The mask layer 132 may include, for example, SiN, SiON, etc.

[0074] exist Fig. 9A and Fig. 9B In the embodiment, the mask layer 132 (see Fig. 8A and Figure 8B ) is patterned to form a mask 133. The pattern of the mask 133 is transferred to the dummy gate layer 130 by an acceptable etching technique to form a dummy gate 131. The dummy gate 131 covers the channel region of each semiconductor fin 116. The pattern of the mask 133 can be used to physically separate each dummy gate 131 from an adjacent dummy gate 131. The dummy gate 131 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the semiconductor fin 116.

[0075] exist Fig.10 In the embodiment, the epitaxial layer 114 is etched using the dummy gate 131 as a mask to form a first recess 115 on either side of the dummy gate 131. In the embodiment where the epitaxial layer 114 includes silicon germanium, the aforementioned etching may include a dry etching process using Cl2, HBr, HF, SF6, CHF3, CH2F2, CF4, S O2, NH3, NF3, He, Si Cl4, O2, Ar, H2 and / or other gas etchants. The etching may be performed at a temperature between about room temperature and about 500° C. for about 10 -3 The etching is performed at a pressure between about 100 mTorr and about 760 mTorr, and for a time period between about 0.1 seconds and about 500 seconds. Fig.10 As shown, since etching is performed along the crystal plane of silicon germanium of the epitaxial layer 114, the surface of the epitaxial layer 114 in the generated first recess 115 will have a shallow concave surface. In one embodiment, the first recess 115 may have a first depth D1, and the first depth D1 measured from the lowest point of the first recess 115 to the top surface of the epitaxial layer 114 is between about 1 nm and 10 nm. Fig.10 As shown, the first recess 115 may have a width measured between adjacent sidewalls of the dummy gate 131 between about 20 nm and about 200 nm, and an angle α between a surface flush with the top surface of the epitaxial layer 114 and the sidewalls of the first recess 115 between about 5 degrees and about 60 degrees.

[0076] exist Fig.11 In the embodiment, a gate spacer 137 is formed along the sidewalls of the dummy gate 131 and the mask 133. Fig.11As shown, the gate spacer 137 can be formed by conformally depositing a material on the top surface and sidewalls of the dummy gate 131 and the mask 133, and then anisotropically etching the aforementioned material to remove a portion located on the top surface of the mask 133 and a portion located farther than the width W1 from the sidewall of the dummy gate 131. The material of the gate spacer 137 can be silicon nitride, SiCN, SiOC, SiOCN, a combination of the aforementioned, etc.

[0077] In various embodiments, the gate spacer 137 may include a plurality of gate subspacers. In one embodiment shown in FIG. 11-19B , the gate spacer 137 includes three gate subspacers: a first gate subspacer 134, a second gate subspacer 135, and a third gate subspacer 136. The first gate subspacer 134 is an etch stop layer for removing the dummy gate 131 during subsequent processing. The first gate subspacer 134 may have a thickness between about 0.5 nm and about 5 nm. In one embodiment, the second gate subspacer 135 reduces the capacitance of the device structure. The second gate subspacer 135 may have a thickness between about 0.5 nm and about 5 nm. In one embodiment, the third gate subspacer 136 may be a dummy or sacrificial spacer layer that serves as a sacrificial etch stop layer in subsequent production processes. The third gate subspacer 136 may have a thickness between about 1 nm and about 10 nm. The first gate subspacer 134 and the second gate spacer 135 may include the same material or may include different materials. In one embodiment, the third gate sub-spacer 136 includes at least a material different from that of the second gate sub-spacer 135 to serve as a sacrificial etch stop layer.

[0078] After forming the first gate sub-spacer 134, implantation of a lightly doped source / drain (LDD) region 111 may be performed. In some embodiments such as PMOS devices, a suitable type of impurity (e.g., P-type) may be implanted into the exposed semiconductor fin 116. The P-type impurity may be boron, BF2, etc. In other embodiments such as NMOS devices, a suitable type of impurity (e.g., N-type) may be implanted into the exposed semiconductor fin 116. The N-type impurity may be phosphorus, arsenic, etc. The lightly doped source / drain region 111 may have a thickness of about 10 15 cm -3 to about 10 16 cm -3 Annealing can be used to activate the implanted impurities. Fig.11The lightly doped source / drain region 111 is shown as a non-limiting example. The lightly doped source / drain region 111 may also have other configurations, shapes, and formation methods, and are fully encompassed by the scope of the present disclosure. In addition, the gate spacer may have different configurations, such as including various numbers of sub-spacers, various shapes (such as L-shaped spacers), and / or other similar configurations. In the subsequent figures, the lightly doped source / drain region 111 is not shown for illustration purposes only.

[0079] In one embodiment, the gate spacer 137 extends to the bottom surface of the first recess 115 to form a Fig.11 The triangular spacer extension 117 is shown. The triangular spacer extension 117 blocks the diffusion of metal from the metal contact to the source / drain region, thereby reducing the parasitic capacitance of the device. In one embodiment, the triangular spacer extension 117 may include a triangular profile extending into the first recess 115. In one embodiment, as shown in FIG. Fig.11 As shown, the triangular spacer extension 117 includes a height H1 between about 1 nm and about 10 nm, and a width W1 between about 1 nm and about 10 nm. In various embodiments, the ratio of the height H1 to the width W1 may be between about 0.1 and 10. These dimensions and ratios have a strong correlation with the performance and parasitic capacitance of the device. When the ratio of the height H1 to the width W1 is large, the performance of the device may be degraded, while when the ratio of the height H1 to the width W1 is small, excessive source / drain region parasitic capacitance may result.

[0080] exist Fig.12 In the embodiment of the present invention, a second recess 138 is formed in the epitaxial layer 114 using the gate spacer 137 as a mask. The second recess 138 is formed to have a greater depth D2 than the depth D1 of the first recess 115. The depth D2 of the second recess 138 may be between about 35 nm and 70 nm. In some embodiments, the second recess 138 may extend through the epitaxial layer 114 into the substrate 100. The second recess 138 may be formed by anisotropic etching using Cl2, HBr, HF, SF6, CHF3, CH2F2, CF4, SO2, NH3, NF3, He, SiCl4, O2, Ar, H2 and / or other gaseous etchants. The etching may be performed at a temperature between about room temperature and about 500°C for about 10 - 3 The etching is performed at a pressure between about 100 mTorr and about 760 mTorr, and the etching is performed for a period of time between about 0.1 seconds and about 500 seconds. Fig.12 As shown, etching of the second recess 138 may produce an undercut of the triangular spacer extension with a width W2 between 0 nm and 5 nm.

[0081] exist Fig.13 In the embodiment of the present invention, epitaxial source / drain regions 139 may be formed by epitaxial growth in the second recess 138. In some embodiments, the epitaxial source / drain regions 139 may extend through the epitaxial layer 114 into the substrate 100. In some embodiments, the second gate sub-spacer 135 is used to separate the epitaxial source / drain regions 139 from the dummy gate 131 by an appropriate lateral distance, so that the epitaxial source / drain regions 139 do not short-circuit the gates of the subsequently formed FinFETs.

[0082] In some embodiments, the epitaxial source / drain regions 139 may include any acceptable material suitable for a P-type fin field effect transistor. For example, the epitaxial source / drain regions 139 may include SiGe, SiGeB, Ge, GeSn, etc. The epitaxial source / drain regions 139 may be formed of a material having a larger lattice constant than the lattice constant of the epitaxial layer 114, generating a compressive stress in the channel region to increase the hole mobility of the PMOS device. In an exemplary embodiment, the epitaxial source / drain regions 139 include SiGeB, and the germanium percentage is about 20% higher than the germanium percentage of the SiGe included in the epitaxial layer 114. The epitaxial source / drain regions 139 may have a surface that is elevated from the surface of each of the semiconductor fins 116, and may have a facet.

[0083] In other embodiments, the epitaxial source / drain regions 139 may include any acceptable material suitable for an N-type FinFET. For example, the epitaxial source / drain regions 139 may include Si, SiC, SiCP, SiP, etc. The epitaxial source / drain regions 139 may be formed of a material having a smaller lattice constant than the lattice constant of the epitaxial layer 114 to generate tensile stress in the channel region to increase the electron mobility of the NMOS device. The epitaxial source / drain regions 139 may also have surfaces that are elevated from the respective surfaces of the semiconductor fins 116 and may have crystal planes.

[0084] Similar to the process of forming lightly doped source / drain regions and then annealing discussed above, dopants may be implanted into the epitaxial source / drain regions 139 and / or the semiconductor fins 116 to form source / drain regions. The source / drain regions may have a thickness of about 10 19 cm -3 To about 10 21 cm -3 The P-type impurities in the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 139 may be doped in-situ during growth.

[0085] According to some embodiments, Fig.14A and Fig. 14BIn the embodiment of the present invention, a first interlayer dielectric (ILD) 140 is deposited. The first interlayer dielectric 140 may be formed of a dielectric material and may be deposited by any suitable method, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or flow chemical vapor deposition (FCVD). The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulators formed by any acceptable process may also be used. In some embodiments, a contact etch stop layer (CESL) (not explicitly shown) is provided between the first interlayer dielectric 140 and the epitaxial source / drain regions 139, the mask 133, and the gate spacer 137.

[0086] exist Fig.15A and Fig. 15B In the process, a planarization process (e.g., chemical mechanical polishing (CMP)) may be performed to make the top surface of the first interlayer dielectric 140 flush with the top surface of the dummy gate 131. The planarization process may also remove the mask 133 on the dummy gate 131 and the portion of the gate spacer 137 along the sidewall of the mask 133. After the planarization process, the top surfaces of the dummy gate 131, the gate spacer 137, and the first interlayer dielectric 140 are flush. Therefore, the top surface of the dummy gate 131 is exposed by the first interlayer dielectric 140.

[0087] exist Fig.16A and Fig. 16B In some embodiments, the dummy gate 131 is removed in an etching step(s) to form a recess 142. In some embodiments, the dummy gate 131 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using an etching gas(es) that selectively etches the dummy gate 131 without etching the first interlayer dielectric 140 or the gate spacer 136. Each recess 142 exposes a channel region of a respective semiconductor fin 116. Each channel region is disposed between adjacent paired epitaxial source / drain regions 139.

[0088] exist Fig.17A and Fig. 17BIn the embodiment of the present invention, a gate dielectric layer 144 and a gate electrode 146 of a replacement gate are formed. The gate dielectric layer 144 is conformally deposited in the recess 142, for example, on the top surface and sidewalls of the semiconductor fin 116, and on the sidewalls of the gate spacer 137. The gate dielectric layer 144 may also be formed on the top surface of the first interlayer dielectric 140. According to some embodiments, the gate dielectric layer 144 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 144 is a high-k dielectric material, and in these embodiments, the gate dielectric layer 144 may have a k value greater than 7.0, and may include metal oxides or silicides of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The gate dielectric layer 144 may be formed by molecular beam deposition (MBD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), etc.

[0089] A gate electrode 146 is formed on the gate dielectric layer 144, and the gate electrode 146 fills the remaining portion of the recess 142. The gate electrode 146 may be a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, a combination of the foregoing, or a multi-layer thereof. The gate electrode 146 may include one or more layers of conductive materials, such as a metal work function layer 147 and a filling material 148. After filling the gate electrode 146, a planarization process (such as chemical mechanical polishing (CMP)) may be performed to remove the gate dielectric layer 144 and the excess portion of the gate electrode 146, the excess portion refers to the portion on the top surface of the first interlayer dielectric 140. The remaining portion of the gate dielectric layer 144 and the gate electrode 146 thus forms a replacement gate of the fin field effect transistor. The gate electrode 146 and the gate dielectric layer 144 may be collectively referred to as a "gate structure" or a "gate stack". The gate structure or gate stack may extend along the sidewalls of the channel region of the semiconductor fin 116.

[0090] exist Fig.18A and Fig.18B In the figure, a second interlayer dielectric 150 is deposited on the first interlayer dielectric 140. In one embodiment, the second interlayer dielectric 150 is a flowable film formed by a flow-type chemical vapor deposition method. In some embodiments, the second interlayer dielectric 150 is formed of a dielectric material, such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., and can be deposited using any suitable method, such as chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition (PECVD).

[0091] exist Fig.19A and Fig.19B In the embodiment, a gate contact 152 and a source / drain contact 154 are formed through the second interlayer dielectric 150 and the first interlayer dielectric 140. An opening for the source / drain contact 154 is formed through the second interlayer dielectric 150 and the first interlayer dielectric 140, and an opening for the gate contact 152 is formed through the second interlayer dielectric 150. Acceptable photolithography and etching techniques may be used to form the aforementioned openings. In one embodiment, as shown in FIG. Fig.19B As shown, the aforementioned opening extends into the epitaxial source / drain region 139 to a depth such that the bottom surface of the opening is above or flush with the bottom surface S1 of the triangular spacer extension 117, and below or flush with the top surface S2 of the triangular spacer extension 117. A liner (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material may be formed in the aforementioned opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0092] Prior to forming the gate contact 152 and / or the source / drain contacts 154, a silicide contact 156 may be selectively formed. The silicide contact 156 may include titanium, nickel, cobalt, or erbium, and may be used to reduce the Schottky barrier height of the gate contact 152 and / or the source / drain contacts 154. However, other materials, such as platinum, palladium, etc., may also be used. Silicidation may be performed by blanket depositing a suitable metal layer, followed by an annealing step to react the metal with the exposed silicon underneath. The unreacted metal is then removed, for example, using a selective etching process. In an exemplary embodiment, the silicide contact 156 is formed within the epitaxial source / drain region 139 such that the silicide contact 156 is disposed between the triangular spacer extensions 117. In some embodiments, such as Fig.19B As shown, the silicide contact 156 may be disposed in a U-shape along the bottom surface and the lower portion of the sidewall of the source / drain contact. In one embodiment, the silicide contact 156 may have a thickness of about 3 to about 15 nm between its top and bottom surfaces, and may have a width between about 1 nm and about 10 nm between opposite sidewalls.

[0093] The gate contact 152 and the source / drain contact 154 may be formed of a conductive material, such as Al, Cu, W, Co, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi, combinations thereof, or other similar materials, although any suitable material may be used. The materials for the gate contact 152 and the source / drain contact 154 may be deposited within the openings of the first interlayer dielectric 140 and the second interlayer dielectric 150 using a deposition process to fill and / or overflow the openings, such as sputtering, chemical vapor deposition, electroplating, electroless plating, or the like. After filling or overflowing the openings, a planarization process (e.g., chemical mechanical polishing) may be used to remove the deposited material outside the openings. During the formation of the source / drain contact 154, the triangular spacer extension 117 will block the outward diffusion of unstable metal from the source / drain contact 154. Reducing the outward diffusion of unstable metal in this way will reduce the parasitic capacitance of the source / drain region and improve the reliability of the product.

[0094] The gate contact 152 is physically and electrically connected to the fill material 148 , and the source / drain contacts 154 are physically and electrically connected to the epitaxial source / drain regions 139 . Fig.19A and Fig.19B The gate contact 152 and the source / drain contact 154 are shown in the same cross-section, however, in other embodiments, the gate contact 152 and the source / drain contact 154 can be arranged in different cross-sections. Fig.19A and Fig.19B The locations of the gate contacts 152 are for illustration only and are not intended to be limiting in any way. For example, the gate contact 152 may be vertically aligned with one of the semiconductor fins 116 shown, or may be disposed at a different location on the fill material 148. Additionally, the source / drain contacts 154 may be formed before, simultaneously with, or after the gate contact 152.

[0095] As discussed above, in order to improve reliability, mobile phone chips have a low power consumption requirement. Reducing power consumption depends on reducing the parasitic capacitance of the source / drain region. Unlike traditional structures where the low thermal stability of the interface between the contact metal and the source / drain epitaxy may lead to low yield and poor reliability, the embodiments disclosed herein have a triangular profile spacer extension as a metal barrier layer for outward diffusion, which can reduce parasitic capacitance and power consumption, thereby accelerating device performance, improving yield and reliability. The aforementioned process is compatible with standard integrated manufacturing processes without changing other cyclic processes. At least some of the embodiments described herein can be extended to any process using epitaxial technology that requires a shape change, such as microelectromechanical systems (MEMS) devices, three-dimensional integrated circuit devices, etc.

[0096] In one embodiment, a method for manufacturing a semiconductor device includes forming a first dummy gate and a second dummy gate on a semiconductor layer. Etching the semiconductor layer using the first dummy gate and the second dummy gate as a first mask. Etching the semiconductor layer forms a first recess disposed between the first dummy gate and the second dummy gate in the semiconductor layer. A first spacer is formed on the sidewall of the first dummy gate, and a second spacer is formed on the sidewall of the second dummy gate. The first spacer and the second spacer form a triangular spacer extension contacting the bottom surface of the first recess. After forming the first spacer and the second spacer, a second recess disposed between the first dummy gate and the second dummy gate is formed in the semiconductor layer. Extending a source / drain region in the second recess. In one embodiment, the second recess is formed to undercut the triangular spacer extension. In one embodiment, a contact is formed on the source / drain region. The aforementioned contact extends a depth on the bottom surface of the triangular spacer extension or flush with the bottom surface of the triangular spacer extension, and below the top surface of the triangular spacer extension or flush with the top surface of the triangular spacer extension. In one embodiment, the second recess is formed by anisotropic etching using the first spacer and the second spacer as a second mask. In one embodiment, the triangular spacer extension is formed to have a corner profile height between about 1 nm and about 10 nm, and a corner profile width between about 1 nm and about 10 nm. In one embodiment, the triangular spacer extension is formed to have a ratio of the corner profile height to the corner profile width between about 0.1 and 1.0.

[0097] According to another embodiment, a method for manufacturing a semiconductor device includes epitaxially growing a semiconductor layer on a substrate. Forming a first gate on the semiconductor layer. Etching the semiconductor layer using the first gate as a mask. Etching the semiconductor layer to form first and second recesses adjacent to the first gate in the semiconductor layer. Forming a spacer on the sidewall of the first gate. The spacer forms a triangular spacer extension that contacts the bottom surface of the first recess. Forming a second recess in the semiconductor layer using the spacer as a mask. Forming a source / drain region in the second recess. Forming a contact on the source / drain region. In one embodiment, the semiconductor layer includes SiGe, and the germanium percentage of the SiGe is between about 10% and 50%. In one embodiment, etching the semiconductor layer including SiGe is along the crystal plane of the SiGe. In one embodiment, etching the semiconductor layer is a dry etching process. In one embodiment, the dry etching process is performed with Cl2, HBr or HF. In one embodiment, forming the spacer comprises forming a plurality of sub-spacers. In one embodiment, to form a contact, the source / drain region is etched to form a third recess to a depth flush with the bottom surface of the triangular spacer extension. In one embodiment, a metal is deposited in the third recess and the metal is annealed to form a silicide. In one embodiment, the contact is formed such that a bottom surface of the contact is below a top surface of the triangular spacer extension and above a bottom surface of the triangular spacer extension.

[0098] According to yet another embodiment, a device includes a substrate having a fin. A first gate extends from the fin. A source / drain region is disposed within the fin adjacent to the first gate. A contact is disposed on the source / drain region. A spacer is disposed along a sidewall of the first gate. The spacer forms a triangular spacer extension extending to a topmost surface of the fin below the first gate. In one embodiment, the triangular spacer extension has a height between about 1 nm and about 10 nm, and has a width between about 1 nm and about 10 nm. In one embodiment, the spacer is composed of a plurality of sub-spacers. In one embodiment, a silicide region is flush with the triangular spacer extension, and the contact is directly located on the silicide region. In one embodiment, the fin includes SiGe and has a germanium percentage of about 10% to about 50%.

[0099] The features of several embodiments or examples are summarized above so that those skilled in the art can better understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments or examples introduced herein. Those skilled in the art should also understand that such equivalent structures do not deviate from the concept and scope of the embodiments of the present invention, and they can make various changes, substitutions and replacements without violating the concept and scope of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first dummy gate and a second dummy gate on a semiconductor layer; Etching the semiconductor layer using the first dummy gate and the second dummy gate as a first mask, wherein etching the semiconductor layer forms a first recess disposed between the first dummy gate and the second dummy gate in the semiconductor layer; Forming a first spacer on the sidewall of the first dummy gate and forming a second spacer on the sidewall of the second dummy gate, wherein the first spacer and the second spacer form a triangular spacer extension contacting a bottom surface of the first recess; After forming the first spacer and the second spacer, forming a second recess disposed between the first dummy gate and the second dummy gate in the semiconductor layer; and A source / drain region is formed in the second recess. 2 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the second recess is formed to undercut the triangular spacer extension portion.

3. The method for manufacturing a semiconductor device as claimed in claim 1 , further comprising forming a contact on the source / drain region, the contact extending a depth above or flush with a bottom surface of the triangular spacer extension portion, and below or flush with a top surface of the triangular spacer extension portion. 4 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein forming the second recess comprises performing anisotropic etching using the first spacer and the second spacer as a second mask. 5 . The method for fabricating a semiconductor device as claimed in claim 1 , wherein the triangular spacer extension is formed to have a corner profile height between 1 nm and 10 nm, and a corner profile width between 1 nm and 10 nm. 6 . The method for fabricating a semiconductor device as claimed in claim 5 , wherein the triangular spacer extension is formed to have a ratio of the corner profile height to the corner profile width between 0.1 and 1.

0.

7. A method for manufacturing a semiconductor device, comprising: epitaxially growing a semiconductor layer on a substrate; forming a first gate on the semiconductor layer; Using the first gate as a mask to etch the semiconductor layer, wherein etching the semiconductor layer forms a first recess and a second recess adjacent to the first gate in the semiconductor layer; forming a spacer on a sidewall of the first gate, wherein the spacer forms a triangular spacer extension contacting a bottom surface of the first recess; Using the spacer as a mask to form a second recess in the semiconductor layer; forming a source / drain region in the second recess; as well as A contact is formed on the source / drain region. 8 . The method for manufacturing a semiconductor device as claimed in claim 7 , wherein the semiconductor layer comprises SiGe, and a germanium percentage of SiGe is between 10% and 50%. 9 . The method for manufacturing a semiconductor device as claimed in claim 8 , wherein etching the semiconductor layer comprising SiGe is etching along a crystal plane of SiGe.

10. The method for manufacturing a semiconductor device as claimed in claim 7, wherein etching the semiconductor layer comprises a dry etching process.

11. The method for manufacturing a semiconductor device as claimed in claim 10, wherein the dry etching process is performed using Cl2, HBr or HF. 12 . The method for manufacturing a semiconductor device as claimed in claim 7 , wherein forming the spacer comprises forming a plurality of sub-spacers. 13 . The method for manufacturing a semiconductor device as claimed in claim 7 , wherein forming the contact on the source / drain region comprises etching the source / drain region to form a third recess to a depth flush with a bottom surface of the triangular spacer extension.

14. The method for manufacturing a semiconductor device according to claim 13, wherein forming the contact comprises: depositing a metal in the third recess; as well as The metal is annealed to form a silicide. 15 . The method for fabricating a semiconductor device as claimed in claim 7 , wherein the contact has a bottom surface, the bottom surface being below a top surface of the triangular spacer extension and on a bottom surface of the triangular spacer extension.

16. A semiconductor device comprising: a base having a fin; a gate on the fin; a source / drain region within the fin and adjacent to the gate; a contact on the source / drain region; as well as A spacer is provided along the sidewall of the gate, the spacer comprising a triangular spacer extension portion extending to a topmost surface of the fin below the gate. 17 . The semiconductor device of claim 16 , wherein the triangular spacer extension has a height between 1 nm and 10 nm, and has a width between 1 nm and 10 nm.

18. The semiconductor device of claim 16, wherein the spacer comprises a plurality of sub-spacers.

19. The semiconductor device of claim 16, wherein the contact is directly located on a silicide region, wherein the silicide region is flush with the triangular spacer extension.

20. The semiconductor device of claim 16, wherein the fin comprises SiGe having a germanium percentage of 10% to 50%.

21. The semiconductor device of claim 16, wherein the triangular spacer extension extends over a portion of the source / drain region.

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