Method of forming a semiconductor device

Abstract

A method of forming a semiconductor device includes etching a semiconductor fin to form a groove; and forming source / drain regions in the groove, the forming of the source / drain regions including: epitaxially growing a first semiconductor material in the groove at a temperature of 600 °C to 800 °C, the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material on the first semiconductor material at a temperature of 300 °C to 600 °C, the second semiconductor material including doped silicon germanium and having a different composition from the first semiconductor material.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for forming a semiconductor device, and more particularly to a method for forming a semiconductor device including fin field-effect transistors (FinFETs). Background Art

[0002] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layer materials on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and parts thereon.

[0003] The semiconductor industry has improved the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum component size, which allows more components to be integrated in a given area. However, when the minimum component size is reduced, other problems to be solved have emerged. Summary of the Invention

[0004] Embodiments of the present invention include a method for forming a semiconductor device, including etching a semiconductor fin to form a groove; and forming source / drain regions in the groove, the forming of the source / drain regions including: epitaxially growing a first semiconductor material in the groove at a temperature of 600°C to 800°C, the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material on the first semiconductor material at a temperature of 300°C to 600°C, the second semiconductor material including doped silicon germanium and having a different composition from the first semiconductor material. Brief Description of the Drawings

[0005] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the various feature components are not drawn to scale and are only for illustrative purposes. In fact, the dimensions of the components may be enlarged or reduced to clearly show the technical features of the embodiments of the present invention.

[0006] Figure 1 is a three-dimensional view showing an example of a fin field-effect transistor according to some embodiments.

[0007] Figure 2 is a cross-sectional view showing a semiconductor substrate according to some embodiments.

[0008] Figure 3 is a cross-sectional view showing the formation of fins according to some embodiments.

[0009] Figure 4 is a cross-sectional view showing the formation of an insulating material according to some embodiments.

[0010] Figure 5 is a cross-sectional view showing planarization of an insulating material according to some embodiments.

[0011] Figure 6 is a cross-sectional view showing formation of an isolation region according to some embodiments.

[0012] Figure 7 is a cross-sectional view showing formation of a dummy dielectric layer, a dummy gate layer, and a mask layer according to some embodiments.

[0013] Figure 8A and Figure 8B is a cross-sectional view showing formation of a dummy gate layer, a mask layer, and a gate seal spacer according to some embodiments.

[0014] Figure 9A and Figure 9B is a cross-sectional view showing formation of a gate spacer according to some embodiments.

[0015] Figures 10A - 10C is a cross-sectional view showing formation of a groove according to some embodiments.

[0016] Figure 11A and Figure 11B is a cross-sectional view showing formation of a first source / drain layer according to some embodiments.

[0017] Figure 12A and Figure 12B is a cross-sectional view showing formation of a second source / drain layer according to some embodiments.

[0018] Figure 13A and Figure 13B is a cross-sectional view showing formation of a third source / drain layer according to some embodiments.

[0019] Figure 14A and Figure 14B is a cross-sectional view showing formation of a fourth source / drain layer according to some embodiments.

[0020] Figure 15A and Figure 15B is a cross-sectional view showing formation of a first source / drain layer and a second source / drain layer according to some embodiments.

[0021] Figure 16A and Figure 16B is a cross-sectional view showing formation of a first interlayer dielectric layer according to some embodiments.

[0022] Figure 17A and Figure 17B is a cross-sectional view showing planarization of a first interlayer dielectric layer, a mask layer, a gate seal spacer, and a gate spacer according to some embodiments.

[0023] Figure 18A and Figure 18B is a cross-sectional view showing the formation of a groove according to some embodiments.

[0024] Figures 19A - 19C is a cross-sectional view showing the formation of a gate stack according to some embodiments.

[0025] Figure 20A and Figure 20B is a cross-sectional view showing the formation of a second interlayer dielectric layer according to some embodiments.

[0026] Figures 21A - 21C is a cross-sectional view showing the formation of gate contacts and source / drain contacts according to some embodiments.

[0027] Description of reference numerals:

[0028] 50 - Substrate

[0029] 50N, 50P - Regions

[0030] 51 - Spacer

[0031] 52 - Fin

[0032] 54 - Insulating material

[0033] 56 - Shallow trench isolation region

[0034] 58 - Channel region

[0035] 60 - dummy dielectric layer

[0036] 62 - dummy gate layer

[0037] 64 - Mask layer

[0038] 72 - dummy gate

[0039] 74 - Mask layer

[0040] 80 - Gate seal spacer

[0041] 86 - Gate spacer

[0042] 88 - Groove

[0043] 90 - First source / drain layer

[0044] 92 - Second source / drain layer

[0045] 94 - Third source / drain layer

[0046] 95 - First source / drain layer

[0047] 96 - Fourth source / drain layer

[0048] 97 to the second source / drain layer

[0049] 98, 98A, 98B - source / drain regions

[0050] 100 - the first interlayer dielectric layer

[0051] 101 - contact etch stop layer

[0052] 102 - groove

[0053] 104 - gate dielectric layer

[0054] 106 - gate electrode

[0055] 106A - liner

[0056] 106B - work function adjustment layer

[0057] 106C - filling material

[0058] 107 - region

[0059] 110 - gate mask

[0060] 112 - the second interlayer dielectric layer

[0061] 114 - gate contact

[0062] 116 - source / drain contact

[0063] 118 - silicide

[0064] A - A, B - B, C - C - cross sections

[0065] H1, H2, H3, H4, H5, H6 - heights

[0066] D1 - distance

[0067] θ1, θ2, θ3 - angles Detailed implementation manners

[0068] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the present invention describes a first feature component formed on or above a second feature component, it means that it may include an embodiment in which the above - mentioned first feature component and the above - mentioned second feature component are in direct contact, and may also include an embodiment in which an additional feature component is formed between the above - mentioned first feature component and the above - mentioned second feature component, so that the above - mentioned first feature component and the second feature component may not be in direct contact.

[0069] In addition, spatially relative terms may be used, such as "below", "beneath", "lower", "above", "higher", and like terms, which are used to facilitate description of the relationship between one or more elements or features in the drawings and another element or feature. These spatially relative terms include different orientations of the device in use or operation and the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used therein will be interpreted according to the turned orientation.

[0070] Various embodiments provide a process for forming source / drain regions having increased germanium and dopant concentrations, reduced volume, and increased undulations (e.g., an increased height difference between the top surface of the source / drain region and the valleys between the merged source / drain regions). A first source / drain layer may be epitaxially grown in a recess formed in a semiconductor fin, a second source / drain layer may be epitaxially grown on the first source / drain layer, a third source / drain layer may be conformally deposited on the second source / drain layer, and a fourth source / drain layer may be conformally deposited on the third source / drain layer to form the source / drain regions. The first source / drain layer and the second source / drain layer are grown at a temperature of about 600°C to about 800°C, and the third source / drain layer and the fourth source / drain layer are deposited at a temperature of about 300°C to about 600°C. A semiconductor device fabricated according to an embodiment of the present invention and including source / drain regions may experience a reduced channel resistance R ch , a reduced source / drain resistance R sd , improved device performance such as an increased on-current (I on ), a reduced gate-to-drain capacitance, a reduced resistance-capacitance delay (RC delay), and an increased device speed.

[0071] According to some embodiments, Figure 1 a three-dimensional view of a fin field-effect transistor example is shown. The fin field-effect transistor includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Shallow trench isolation (STI) regions 56 are located in the substrate 50, and the fin 52 protrudes above adjacent shallow trench isolation regions 56 and between adjacent shallow trench isolation regions 56. Although the shallow trench isolation regions 56 are separately described / shown from the substrate 50, the term "substrate" as used herein may be used to refer only to the substrate 50 or the substrate 50 including the shallow trench isolation regions 56. In addition, although the fin 52 and the substrate 50 are shown as a single continuous material, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this document, the fin 52 refers to the portion extending between adjacent shallow trench isolation regions 56.

[0072] The gate dielectric layer 104 is along the sidewalls of the fin 52 and above its top surface, and the gate electrode 106 is above the gate dielectric layer 104. The source / drain regions 98 are located on opposite sides of the fin 52 with respect to the gate dielectric layer 104 and the gate electrode 106. Figure 1 Further shown are reference cross-sections used in subsequent figures. Cross-section A-A is along the longitudinal axis of the gate electrode 106 and in a direction, for example, perpendicular to the direction of current between the source / drain regions 98 of the fin field-effect transistor. Cross-section B-B is perpendicular to cross-section A-A and along the longitudinal axis of the fin 52 and in a direction, for example, perpendicular to the direction of current between the source / drain regions 98 of the fin field-effect transistor. Cross-section C-C is parallel to cross-section A-A and extends through the source / drain regions of the fin field-effect transistor. For clarity, subsequent figures refer to these reference cross-sections.

[0073] Some of the embodiments discussed herein are discussed in the context of fin field-effect transistors formed using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, some embodiments contemplate aspects for use in planar devices such as planar field-effect transistors. For example, the field-effect transistors discussed herein may be used in ring-oscillator devices.

[0074] According to some embodiments, Figures 2 to 21C A cross-sectional view showing an intermediate stage of manufacturing a fin field-effect transistor is shown. Figures 2 to 7 Shown is Figure 1 The reference cross-section A-A shown in, except for a multi-fin / fin field-effect transistor. Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A 、 Figure 20A 、and Figure 21A Shown along Figure 1 The reference cross-section A-A shown in, and Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16B 、 Figure 17B 、 Figure 18B 、 Figure 19B 、 Figure 19C 、 Figure 20B 、and Figure 21B Shown along Figure 1 A similar cross-section B-B shown in, except for a multi-fin / fin field-effect transistor.Figure 10C , Figure 11B , Figure 12B , Figure 13B , Figure 14B , and Figure 21C shows in the p-type metal oxide semiconductor region along the reference section C-C shown in Figure 1 , and Figure 15B shows in the n-type metal oxide semiconductor region along the reference section C-C shown in Figure 1 , except for the multi-fin / fi nFETs.

[0075] In Figure 2 , a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Generally, a semiconductor-on-insulator substrate is a semiconductor material layer formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. An insulating layer is provided on the substrate, which is usually a silicon or glass substrate. Other substrates, such as multi-layer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 can include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or a combination of the above.

[0076] The substrate 50 has a region 50N and a region 50P. The region 50N can form n-type components, such as n-type metal oxide semiconductor transistors, such as n-type finFETs. The region 50P can form p-type components, such as p-type metal oxide semiconductor transistors, such as p-type finFETs. The region 50N can be physically separated from the region 50P (e.g., by the shown separator 51), and any number of component parts (e.g., other active components, doped regions, isolation regions, etc.) can be located between the region 50N and the region 50P.

[0077] In Figure 3In [description], fins 52 are formed in a substrate 50. The fins 52 are strip-shaped semiconductors. In some embodiments, trenches are etched in the substrate 50 to form the fins 52 in the substrate 50. The etching can be an acceptable etching process such as reactive ion etch (RIE), neutral beam etch (NBE), similar processes, or a combination of the above. The etching can be anisotropic. Although the fins 52 are shown in [reference] as having linear edges, the fins 52 can have rounded edges or any other suitable shape. Figure 3 The fins 52 can be patterned in any suitable method. For example, one or more photolithography processes can be used to pattern the fins 52, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with pitches, for example, smaller than those obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed and patterned on the substrate 50 using a photolithography process. Spacers are formed beside the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and the remaining spacers or mandrels can then be used to pattern the fins 52.

[0078] In [description], an insulating material 54 is formed on the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide such as silicon oxide, a nitride, a similar material, or a combination of the above, and can be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (for example, depositing a chemical vapor deposition-based material in a remote plasma system and post-curing it to convert it to another material, such as an oxide), similar methods, or a combination of the above. Any acceptable process can be used to form other insulating materials. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by a flowable CVD process. Once the insulating material 54 is formed, an annealing process can be performed. In one embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments can utilize multiple layers. For example, in some embodiments, a liner layer (not shown separately) can be first formed along the surfaces of the substrate 50 and the fins 52. Then, a filling material such as the above can be formed on the liner layer.

[0079] In [description] Figure 4 In [description], an insulating material 54 is formed on the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide such as silicon oxide, a nitride, a similar material, or a combination of the above, and can be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (for example, depositing a chemical vapor deposition-based material in a remote plasma system and post-curing it to convert it to another material, such as an oxide), similar methods, or a combination of the above. Any acceptable process can be used to form other insulating materials. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by a flowable CVD process. Once the insulating material 54 is formed, an annealing process can be performed. In one embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments can utilize multiple layers. For example, in some embodiments, a liner layer (not shown separately) can be first formed along the surfaces of the substrate 50 and the fins 52. Then, a filling material such as the above can be formed on the liner layer.

[0080] In [description] Figure 5In [the process], a removal process is applied to the insulating material 54 to remove the excess insulating material 54 on the fin 52. In some embodiments, a planarization process such as chemical mechanical polish (CMP), an etch-back process, a combination of the above, or a similar process may be utilized. The planarization process exposes the fin 52 such that after the completion of the planarization process, the top surfaces of the fin 52 and the insulating material 54 are flush.

[0081] In Figure 6 [the process], the insulating material 54 is etched to form a shallow trench isolation (STI) region 56. The etching of the insulating material 54 causes the upper portions of the fins 52 in the regions 50N and 50P to protrude between adjacent shallow trench isolation regions 56. Additionally, the top surface of the shallow trench isolation region 56 may have a flat surface, a convex surface, a concave surface (such as a dish shape), or a combination of the above as shown. Using a suitable etch, the top surface of the shallow trench isolation region 56 can be formed to be flat, protruding, and / or recessed. The isolation region 56 can be etched using an acceptable etching process, such as an etching process selective to the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate compared to the material of the fin 52). For example, a chemical oxide can be removed using a suitable etching process such as dilute hydrofluoric (dHF).

[0082] Regarding Figures 2 to 6 The processes described [above] are merely an example of how the fins 52 can be formed. In some embodiments, the fins 52 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed on the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be etched such that the homoepitaxial structure protrudes from the dielectric layer to form the fins 52. Additionally, in some embodiments, the fins 52 can use a heteroepitaxial structure. For example, the fins 52 in Figure 5 [the process] can be etched, and a material different from the fins 52 can be epitaxially grown on the etched fins 52. In such an embodiment, the fins 52 include, in addition to the etched material, an epitaxially grown material on top of the etched material. In another embodiment, a dielectric layer is formed on top of the substrate 50, and trenches are etched through the dielectric layer. A heteroepitaxial structure can be epitaxially grown in the trenches using a material different from the substrate 50, and the dielectric layer can be etched such that the heteroepitaxial structure protrudes from the dielectric layer to form the fins 52. In some embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, the epitaxially grown material can be doped in-situ during growth, although in-situ and implantation doping can be used together, which can eliminate prior or subsequent implantations.

[0083] Furthermore, it may be beneficial to epitaxially grow different materials in region 50N (e.g., an n-type metal oxide semiconductor region) than in region 50P (e.g., a p-type metal oxide semiconductor region). In various embodiments, the upper portion of fin 52 may be formed of silicon germanium (Si x Ge 1-x , where x may range from 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, or the like. For example, suitable materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0084] In addition, in Figure 6 , suitable well regions (not shown separately) may be formed in fin 52 and / or substrate 50. In some embodiments, a p-type well region may be formed in region 50N, and an n-type well region may be formed in region 50P. In some embodiments, a p-type well region or an n-type well region is formed in both region 50N and region 50P.

[0085] In embodiments having different well region types, different implantation steps for regions 50N and 50P may be achieved using photoresist or other masks (not shown). For example, photoresist may be formed over fin 52 and shallow trench isolation region 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, e.g., a p-type metal oxide semiconductor region. The photoresist may be formed using a spin technique and patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may act as a mask to substantially prevent the n-type impurity from being implanted into region 50N, e.g., an n-type metal oxide semiconductor region. The n-type impurity may be phosphorus, arsenic, antimony, or the like, implanted into the region to a concentration equal to or less than 10 18 atoms / cm 3 , e.g., from about 10 17 atoms / cm 3 to about 10 18 atoms / cm 3 . After implantation, the photoresist is removed using an acceptable ashing process, for example.

[0086] After implanting in region 50P, a photoresist is formed over fins 52 and shallow trench isolation regions 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as an n-type metal oxide semiconductor region. The photoresist can be formed using a spin technique and patterned using an acceptable photolithography technique. Once the photoresist is patterned, p-type impurity implantation can be performed in region 50N, and the photoresist can act as a mask to largely avoid p-type impurity implantation into region 50P, such as a p-type metal oxide semiconductor region. The p-type impurity can be boron, BF2, indium, or the like, implanted into the region to a concentration equal to or less than 10 18 atoms / cm 3 , for example, from about 10 17 atoms / cm 3 to about 10 18 atoms / cm 3 . After implantation, the photoresist is removed using, for example, an acceptable ashing process.

[0087] After implanting in regions 50N and 50P, annealing can be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in-situ during growth, although in-situ and implantation doping can be used together, which can obviate implantation.

[0088] In Figure 7Therein, a dummy dielectric layer 60 is formed over the fin 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination of the above, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed over the dummy dielectric layer 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 can be deposited over the dummy dielectric layer 60 and then planarized by a process such as chemical mechanical polishing. The mask layer 64 can be deposited over the dummy gate layer 62. The dummy gate layer 62 can be a conductive material and can be selected from the group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, metal, and the like. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), chemical vapor deposition, sputter deposition, or other techniques known in the art and used for depositing conductive materials. The dummy gate layer 62 can be made of other materials having a high etch selectivity for etching isolation regions (such as the shallow trench isolation region 56). The mask layer 64 can include, for example, SiN, SiON, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across the region 50N and the region 50P. It should be noted that, for illustrative purposes only, the dummy dielectric layer 60 is shown as only covering the fin 52. In some embodiments, the dummy dielectric layer 60 can be deposited such that the dummy dielectric layer 60 covers the shallow trench isolation region 56 and extends between the dummy gate layer 62 and the shallow trench isolation region 56.

[0089] Figures 8A to 21C Additional steps for manufacturing the exemplary components are shown. Figures 8A to 21C Components within either the region 50N or the region 50P are shown. For example, Figures 8A to 16B the structures shown therein can be applicable to both the region 50N and the region 50P. Differences (if any) in the structures of the region 50N and the region 50P are described in the text accompanying each figure.

[0090] In Figure 8A and Figure 8B the mask layer 64 can be patterned using acceptable lithography and etching techniques (see Figure 7)To form a mask layer 74. The pattern of the mask layer 74 can then be transferred to the dummy gate layer 62 using an acceptable etching technique to form dummy gates 72. In some embodiments (not shown separately), the pattern of the mask layer 74 can also be transferred to the dummy dielectric layer 60 using an acceptable etching technique. The dummy gates 72 cover the respective channel regions 58 of the fins 52. The pattern of the mask layer 74 can be used to physically separate each dummy gate 72 from adjacent dummy gates 72. The length direction of the dummy gates 72 is generally perpendicular to the length direction of the respective fins 52.

[0091] Further, in Figure 8A and Figure 8B , gate seal spacers 80 can be formed on the exposed surfaces of the dummy gates 72, the mask layer 74, and / or the fins 52. Thermal oxidation or deposition followed by anisotropic etching can be used to form the gate seal spacers 80.

[0092] After forming the gate seal spacers 80, lightly doped source / drain (LDD) region implantation can be performed. In embodiments of different device types, similar to the implantation discussed above Figure 6 , a mask such as photoresist can be formed over the region 50N while exposing the region 50P, and impurities of a suitable type (e.g., p-type) can be implanted into the fins 52 exposed in the region 50P. The mask can then be removed. Subsequently, a mask such as photoresist can be formed over the region 50P while exposing the region 50N, and impurities of a suitable type (e.g., n-type) can be implanted into the fins 52 exposed in the region 50N. The mask can then be removed. The n-type impurities can be any of the n-type impurities discussed previously, and the p-type impurities can be any of the p-type impurities discussed previously. The lightly doped source / drain regions can have an impurity concentration of about 10 15 atoms / cm 3 to about 10 16 atoms / cm 3 . Annealing can be used to activate the implanted impurities.

[0093] In Figure 9A and Figure 9B , gate spacers 86 are formed over the gate seal spacers 80 along the sidewalls of the dummy gates 72 and the mask layer 74. The gate spacers 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacers 86 can be silicon nitride, SiCN, a combination of the above, or the like.

[0094] Figures 10A - 14B Illustrates the various steps of forming source / drain regions 98A in the fins 52 in the region 50P. As Figures 10A - 14BAs shown, the source / drain regions 98A in the region 50P can be formed using a multi-step epitaxial deposition process. As Figures 10A - 10C shown, the source / drain regions 98A in the region 50P, such as a p-type metal oxide semiconductor region, can be formed by masking the region 50N, such as an n-type metal oxide semiconductor region, and etching the source / drain regions of the fins 52 in the region 50P to form the grooves 88 in the fins 52.

[0095] In Figure 11A and Figure 11B , a first source / drain layer 90 is epitaxially grown in the groove 88. The first source / drain layer 90 can include any acceptable material, such as those suitable for p-type fin field effect transistors. For example, in an embodiment where the fin 52 includes silicon, the first source / drain layer 90 in the region 50P can include a material that applies compressive strain in the channel region 58, such as SiGe, SiGeB, Ge, GeSn, or the like. In some embodiments, the first source / drain layer 90 can include silicon germanium, which has a germanium atomic percentage of about 20% to about 40%.

[0096] In-situ doping during growth can be used to implant dopants into the first source / drain layer 90, or a process similar to the aforementioned process for forming lightly doped source / drain regions can be used, followed by annealing. The first source / drain layer 90 can have an impurity concentration of less than about 5x10 20 atoms / cm 3 . The dopants can include p-type dopants such as boron, BF2, indium, or the like.

[0097] The first source / drain layer 90 is grown at a temperature of about 600 °C to about 800 °C, such as below about 700 °C, and a pressure of about 5 Torr to about 50 Torr, such as below about 25 Torr. The first source / drain layer 90 is grown for a time of about 10 seconds to about 200 seconds, such as about 100 seconds. The first source / drain layer 90 can be epitaxially grown from precursor gases such as silane, disilane, dichlorosilane, germane, germanium tetrachloride, combinations of the above, or the like. The first source / drain layer 90 has a thickness of between about 1 nm and about 10 nm, such as about 5 nm. As Figure 11A and Figure 11B shown, the first source / drain layer 90 can have facets.

[0098] In Figure 12A and Figure 12BIn this case, the epitaxial growth second source / drain layer 92 is on top of the first source / drain layer 90 in the groove 88. The second source / drain layer 92 can include any acceptable material, such as those suitable for p-type fin field-effect transistors. For example, the second source / drain layer 92 can include a material that applies compressive strain in the channel region 58, such as SiGe, SiGeB, Ge, GeSn, or the like. In some embodiments, the second source / drain layer 92 can include silicon germanium, which has a germanium atom percentage of about 40% to about 50%.

[0099] In-situ doping during growth can be used to implant dopants into the second source / drain layer 92, or a process similar to the process for forming lightly doped source / drain regions described above can be used, followed by annealing. The second source / drain layer 92 can have an impurity concentration greater than about 6x10 20 atoms / cm 3 . The dopants can include p-type dopants such as boron, BF2, indium, or the like.

[0100] The second source / drain layer 92 is grown at a temperature of about 600 °C to about 800 °C, such as below about 700 °C, and a pressure of about 5 Torr to about 50 Torr, such as below about 25 Torr. The second source / drain layer 92 is grown for a time of about 100 seconds to about 600 seconds, such as about 500 seconds. The second source / drain layer 92 can be epitaxially grown from precursor gases such as silane, disilane, dichlorosilane, germane, germanium tetrachloride, combinations of the above, or the like. The second source / drain layer 92 has a thickness of less than 25 nm or less than 40 nm, such as about 20 nm. As Figure 12A and Figure 12B shown, the second source / drain layer 92 can have facets. Although the second source / drain layers 92 shown in Figure 12A and Figure 12B do not fuse, in some embodiments, the facets can cause adjacent second source / drain layers 92 to fuse.

[0101] In Figure 13A and Figure 13BTherein, the third source / drain layer 94 is conformally deposited on top of the second source / drain layer 92 within the recess 88. The third source / drain layer 94 can be deposited using a conformal process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or a similar process. The third source / drain layer 94 can include any acceptable material, such as those suitable for p-type fin field-effect transistors. For example, the third source / drain layer 94 can include a material that applies compressive strain in the channel region 58, such as SiGe, SiGeB, Ge, GeSn, or the like. In some embodiments, the third source / drain layer 94 can include silicon germanium having a germanium atomic percentage of about 60% to about 80%.

[0102] In some embodiments, the third source / drain layer 94 can be formed using a selective deposition process. For example, the third source / drain layer 94 can be deposited using a selective chemical vapor deposition process or a similar process. In a representative embodiment, an etch gas (such as SiH2Cl2, HCl, or a similar gas) can be used to control the selective growth between the silicon germanium region of the second source / drain layer 92 and the dielectric surfaces of the dummy dielectric layer 60, the gate spacer 86, the gate seal spacer 80, and the mask layer 74. In other embodiments, the deposition and etching processes can be performed separately or otherwise controlled separately. For example, an epitaxial deposition process can be performed to non-selectively grow the third source / drain layer 94, followed by an etching step to remove the deposited material from the dielectric surfaces of the dummy dielectric layer 60, the gate spacer 86, the gate seal spacer 80, and the mask layer 74 to maintain selectivity.

[0103] In-situ doping during deposition can be used to implant dopants into the third source / drain layer 94, or a process similar to the process for forming the lightly doped source / drain regions described above can be used, followed by annealing. The third source / drain layer 94 can have an impurity concentration greater than about 8x10 20 atoms / cm 3 . The dopants can include p-type dopants such as boron, BF2, indium, or the like.

[0104] The third source / drain layer 94 is deposited at a temperature of about 300°C to about 600°C, such as below about 450°C, and a pressure greater than about 20 Torr, such as below about 50 Torr. The low-temperature and high-pressure process used to form the third source / drain layer 94 causes the third source / drain layer 94 to conformally form on top of the second source / drain layer 92. As Figure 13BAs shown, it can prevent the third source / drain layer 94 from growing in the (100) plane between adjacent fins 52, such that a recessed valley is formed in the fused portion of the third source / drain layer 94 between adjacent fins 52. The third source / drain layer 94 is deposited for about 100 seconds to about 300 seconds, such as about 200 seconds. The third source / drain layer 94 can be epitaxially grown from a precursor gas such as silane, disilane, dichlorosilane, germane, germanium tetrachloride, a combination of the foregoing, or the like. The third source / drain layer 94 has a thickness greater than 20 nm, such as about 30 nm. As Figure 13A and Figure 13B shown, the third source / drain layer 94 can have a surface that protrudes from the respective surfaces of the fins 52 and can have facets. Additionally, as Figure 13B shown, the conformal process used to form the third source / drain layer 94 can cause adjacent third source / drain layers 94 to fuse.

[0105] In Figure 14A and Figure 14B , a fourth source / drain layer 96 is conformally deposited over the third source / drain layer 94 to form a source / drain region 98A including a first source / drain layer 90, a second source / drain layer 92, a third source / drain layer 94, and a fourth source / drain layer 96. The fourth source / drain layer 96 can be deposited using a conformal process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or a similar process. The fourth source / drain layer 96 can include any acceptable material, such as one suitable for a p-type fin field-effect transistor. For example, the fourth source / drain layer 96 can include a material that applies compressive strain in the channel region 58, such as SiGe, SiGeB, Ge, GeSn, or the like. In some embodiments, the fourth source / drain layer 96 can include silicon germanium, which has a germanium atom percentage of less than about 40%.

[0106] In some embodiments, the fourth source / drain layer 96 may be formed by a selective deposition process. For example, the fourth source / drain layer 96 may be deposited by a selective chemical vapor deposition process, a selective atomic layer deposition process, or a similar process. In a representative embodiment, an etch gas (such as SiH2Cl2, HCl, or a similar gas) may be used to control the selective growth between the silicon germanium region of the third source / drain layer 94 and the dielectric surfaces of the dummy dielectric layer 60, the gate spacer 86, the gate seal spacer 80, and the mask layer 74. In other embodiments, the deposition and etch processes may be performed separately, or otherwise controlled separately. For example, an epitaxial deposition process may be performed to non-selectively grow the fourth source / drain layer 96, followed by an etch step to remove the deposited material from the dielectric surfaces of the dummy dielectric layer 60, the gate spacer 86, the gate seal spacer 80, and the mask layer 74 to maintain selectivity.

[0107] In-situ doping during deposition may be used to implant dopants into the fourth source / drain layer 96, or a process similar to the process for forming the lightly doped source / drain regions described above may be used, followed by annealing. The fourth source / drain layer 96 may have an impurity concentration greater than about 1x10 20 atoms / cm 3 . The dopants may include p-type dopants such as boron, BF2, indium, or the like.

[0108] The fourth source / drain layer 96 is deposited at a temperature of about 300 °C to about 600 °C, for example, below about 450 °C. The deposition of the fourth source / drain layer 96 takes about 10 seconds to about 200 seconds, for example, about 100 seconds. The fourth source / drain layer 96 has a thickness of less than 10 nm, for example, about 5 nm. The fourth source / drain layer 96 may be epitaxially grown from a precursor gas such as silane, disilane, dichlorosilane, germane, germanium tetrachloride, a combination of the above, or the like. As Figure 14A and Figure 14B shown, the fourth source / drain layer 96 may have a surface that protrudes from the corresponding surfaces of the fin 52 and may have facets.

[0109] The fourth source / drain layer 96 may be a sacrificial layer or an etch stop layer. For example, as will be discussed in more detail below with respect to Figure 19B , the fourth source / drain layer 96 may protect the third source / drain layer 94 during the etch process for forming the opening for forming the source / drain contact 116.

[0110] As Figure 14A shown, the height H1 between the top surface of the fin 52 and the bottom of the fin 52 is greater than about 40 nm. The height H2 between the top surface of the fin 52 and the bottom surface of the source / drain region 98A is greater than about 40 nm. The height H3 between the top surface of the source / drain region 98A and the top surface of the fin 52 is greater than about 3 nm. As Figure 14BAs shown, adjacent source / drain regions 98A may be fused. The height H4 between the top surface of the source / drain region 98A and the trough between the source / drain regions 98A is greater than about 5 nm. The height H5 between the bottom surface of the facet within the source / drain region 98A and the bottom of the fin 52 is greater than about 25 nm. The height H6 between the bottom surface of the outer facet of the source / drain region 98A and the bottom of the fin 52 is greater than about 20 nm. To limit the lateral growth of the first source / drain layer 90 and the second source / drain layer 92 and to control the critical dimensions of the source / drain regions 98A, the heights H5 and H6 of the source / drain regions 98A may be greater. The distance D1 between the inner surfaces of adjacent fins 52 is greater than 5 nm. The angle θ1 between the intersecting facets of the troughs between the source / drain regions 98A is less than about 90 degrees. The angle θ2 between the intersecting facets of the top surface of the source / drain region 98A is less than about 90 degrees. The angle θ3 between the intersecting facets of the outermost surface is greater than about 90 degrees.

[0111] The source / drain regions 98A formed according to the above embodiments may have a wavy profile in the reference cross-section C-C (e.g., the height H4 may be increased and the angles θ1 and θ2 may be decreased), which may increase the contact area between the source / drain regions 98A and the subsequently formed source / drain contacts 116 (refer to Figure 19B discussed below), and reduce the source / drain resistance R sd . The source / drain regions 98A may also have a reduced volume, which reduces the gate-to-drain capacitance C gd . In addition, the source / drain regions 98A may have a greater germanium and dopant ion (e.g., boron) concentration, which increases the stress applied to each channel region 58, reduces the channel resistance R ch , reduces the source / drain resistance R sd , improves the device performance I on , reduces the resistive-capacitive delay, and increases the device speed.

[0112] In Figure 15A and Figure 15BIn the figure, a source / drain region 98B is formed in a fin 52 in a region 50N. The source / drain region 98B can be formed by existing methods. The region 50P, such as a p-type metal oxide semiconductor region, can be masked to form the source / drain region 98B in the region 50N, such as an n-type metal oxide semiconductor region, and the source / drain region of the fin 52 in the region 50P is etched to form a groove (not shown separately) in the fin 52. Then, a first source / drain layer 95 in the region 50N is epitaxially grown in the groove. A second source / drain layer 97 is conformally formed on the first source / drain layer 95 using a process such as chemical vapor deposition, atomic layer deposition, or a similar process, and serves as a sacrificial layer or an etch stop layer, similar to the aforementioned fourth source / drain layer 96. The source / drain region 98B includes the combination of the first source / drain layer 95 and the second source / drain layer 97. The source / drain region 98B can include any acceptable material, such as those suitable for an n-type fin field effect transistor. For example, if the fin 52 is silicon, the source / drain region 98B in the region 50N can include a material that applies tensile strain in the channel region 58, such as SiC, SiCP, SiP, or the like. The source / drain region 98B in the region 50N can have a surface that protrudes from the corresponding surface of the fin 52 and can have facets.

[0113] The source / drain region 98B and / or the fin 52 can be implanted with dopants to form the source / drain region, using a process similar to the aforementioned process for forming a lightly doped source / drain region, and then annealed. The source / drain region can have an impurity concentration of about 10 19 cm -3 to about 10 21 cm -3 . The n-type dopant of the source / drain region 98B can be any dopant discussed above. In some embodiments, the source / drain region 98B can be in-situ doped during growth.

[0114] Due to the epitaxial process used to form the source / drain region 98B in the region 50N, the upper surface of the source / drain region 98B has facets that laterally extend beyond the sidewalls of the fin 52. In some embodiments, as Figure 15B shown, these facets cause adjacent source / drain regions 98B of the same fin field effect transistor to merge. In other embodiments (not shown separately), the adjacent source / drain regions 98B remain separated after the epitaxial process is completed.

[0115] As Figure 14A and Figure 15A shown, the major surfaces of the source / drain region 98A and the source / drain region 98B can have a (100) plane crystal plane in the cross-section A-A. As Figure 14B and Figure 15BAs shown, the major surfaces of source / drain region 98A and source / drain region 98B may have a (111) plane crystal face in cross-section B-B.

[0116] In FIGS. 16A and 16B, a first interlayer dielectric layer 100 is deposited over Figures 14A - 15B the structure shown. The first interlayer dielectric layer 100 may be formed of a dielectric material and may be formed by any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials may be formed using any acceptable process. In some embodiments, a contact etch stop layer (CESL) 101 is located between the first interlayer dielectric layer 100 and the source / drain regions 98A and 98B, the mask layer 74, and the gate spacers 86. The contact etch stop layer 101 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having an etch rate different from that of the material of the first interlayer dielectric layer 100 thereabove.

[0117] In Figure 17A and Figure 17B , a planarization process such as chemical mechanical polishing may be performed to make the top surface of the first interlayer dielectric layer 100 flush with the top surface of the dummy gate 72 or the mask layer 74. The planarization process may also remove the mask layer 74 on the dummy gate 72 and portions of the gate seal spacers 80 and the gate spacers 86 along the sidewalls of the mask layer 74. After the planarization process, the top surfaces of the dummy gate 72, the gate seal spacers 80, the gate spacers 86, and the first interlayer dielectric layer 100 are flush. Accordingly, the top surface of the dummy gate 72 is exposed through the first interlayer dielectric layer 100. In some embodiments, the mask layer 74 may be retained, in which case the planarization process makes the top surface of the first interlayer dielectric layer 100 flush with the top surface of the mask layer 74.

[0118] In Figure 18A and Figure 18BIn [the above], during the etching step, the dummy gate 72 and, if present, the mask layer 74 are removed, thereby forming the recess 102. The portion of the dummy dielectric layer 60 within the recess 102 may also be removed. In some embodiments, only the dummy gate 72 is removed, and the dummy dielectric layer 60 is retained and exposed from the recess 102. In some embodiments, the dummy dielectric layer 60 is removed from the recess 102 in a first region of the die (e.g., the core logic region), and the dummy dielectric layer 60 is retained in a second region of the die (e.g., the input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process that uses a reactive gas to selectively etch the dummy gate 72 without etching the first interlayer dielectric layer 100 or the gate spacer 86. Each recess 102 exposes the channel region 58 of each fin 52. Each channel region 58 is located between adjacent source / drain region pairs 98A and 98B. When removing, the dummy dielectric layer 60 may be used as an etch stop layer when etching the dummy gate 72. After removing the dummy gate 72, the dummy dielectric layer 60 may then optionally be removed.

[0119] In Figure 19A and Figure 19B therein, a gate dielectric layer 104 and a gate electrode 106 are formed to form a replacement gate. Figure 19C shows Figure 19B a detailed view of the region 107. The gate dielectric layer 104 is conformally deposited within the recess 102, e.g., over the top surface and sidewalls of the fin 52, and over the sidewalls of the gate seal spacer 80 / gate spacer 86. The gate dielectric layer 104 may also be formed over the top surface of the first interlayer dielectric layer 100. According to some embodiments, the gate dielectric layer 104 includes silicon oxide, silicon nitride, or a multi-layer thereof. In some embodiments, the gate dielectric layer 104 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 104 has a dielectric constant greater than about 7.0 and may include a metal oxide or silicide of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination of the above. The method of forming the gate dielectric layer 104 may include molecular beam deposition (MBD), atomic layer deposition, plasma enhanced chemical vapor deposition, and similar methods. In embodiments where a portion of the dummy dielectric layer 60 is retained within the recess 102, the gate dielectric layer 104 includes the material of the dummy dielectric layer 60 (e.g., SiO2).

[0120] The gate electrodes 106 are respectively located over the gate dielectric layer 104 and fill the remaining portion of the recess 102. The gate electrodes 106 may include a metal-containing material such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, a combination of the above, or a multi-layer of the above. For example, although in Figure 19BShown as a single-layer gate electrode 106, as Figure 19C As shown, the gate electrode 106 may include any number of liner layers 106A, any number of work function adjustment layers 106B, and a fill material 106C. After filling the gate electrode 106, a planarization process such as chemical mechanical polishing may be performed to remove the gate dielectric layer 104 and the excess portions of the gate electrode 106 material that are above the top surface of the first interlayer dielectric layer 100. The remaining portions of the gate electrode 106 and the gate dielectric layer 104 then form the replacement gate of the resulting fin field effect transistor. The gate electrode 106 and the gate dielectric layer 104 are collectively referred to as the "gate stack". The gate and the gate stack may extend along the sidewalls of the channel region 58 of the fin 52.

[0121] The formation of the gate dielectric layer 104 may occur simultaneously in the regions 50N and 50P such that the gate dielectric layer 104 is formed of the same material in each region, and the formation of the gate electrode 106 may occur simultaneously such that the gate electrode 106 is formed of the same material in each region. In some embodiments, the gate dielectric layer 104 may be formed by different processes in each region such that the gate dielectric layer 104 may be of different materials, and / or the gate electrode 106 may be formed by different processes in each region such that the gate electrode 106 may be of different materials. When different processes are used, different masking steps may be used to mask and expose the appropriate regions.

[0122] In Figure 20A and Figure 20B A second interlayer dielectric layer 112 is deposited over the first interlayer dielectric layer 100. In some embodiments, the second interlayer dielectric layer 112 is a flowable film layer formed by a flowable chemical vapor deposition method. In some embodiments, it is formed of a dielectric material such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like, and may be deposited by any suitable method such as chemical vapor deposition and plasma enhanced chemical vapor deposition. According to some embodiments, as Figure 20A and Figure 20B shown, before forming the second interlayer dielectric layer 112, the gate stack (including the gate dielectric layer 104 and the corresponding gate electrode 106 thereon) is etched to form a groove between directly above the gate stack and the opposing portions of the gate spacers 86. The gate mask 110 includes one or more layers of dielectric material such as silicon nitride, silicon oxynitride, or the like, which is filled into the groove, followed by a planarization process to remove the excess dielectric material extending above the first interlayer dielectric layer 100. The subsequently formed gate contact 114 ( Figures 21A - 21C ) penetrates the gate mask 110 to contact the top surface of the etched gate electrode 106.

[0123] According to some embodiments, inFigures 21A - 21C In this case, gate contacts 114 and source / drain contacts 116 are formed through the second interlayer dielectric layer 112 and the first interlayer dielectric layer 100. Source / drain contact 116 openings are formed through the first interlayer dielectric layer 100, the second interlayer dielectric layer 112, and the fourth source / drain layer 96 or the second source / drain layer 97 (not shown separately), and gate contact 114 openings are formed through the second interlayer dielectric layer 112 and the gate mask 110. The openings can be formed using acceptable lithography and etching techniques. A liner such as a diffusion barrier layer, an adhesion layer, or a similar layer, and a conductive material are formed in the openings. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as chemical mechanical polishing can be performed to remove excess material from the surface of the second interlayer dielectric layer 112. The remaining liner and conductive material form source / drain contacts 116 and gate contacts 114 in the openings. As Figure 21B and Figure 21C shown, an annealing process can be performed to form silicide 118 at the interfaces between the source / drain regions 98A and the source / drain contacts 116 and between the source / drain regions 98B and the source / drain contacts 116. The source / drain contacts 116 are physically and electrically coupled to the source / drain regions 98A and the source / drain regions 98B, and the gate contacts 114 are physically and electrically coupled to the gate electrode 106. The source / drain contacts 116 and the gate contacts 114 can be formed in different processes or in the same process. Although shown as being formed in the same cross-section, it should be understood that each source / drain contact 116 and gate contact 114 can be formed in a different cross-section, which can avoid contact short circuits.

[0124] As described above, the source / drain region 98A can have increased undulations (e.g., an increased height difference between the top surface of the source / drain region 98A and the valleys between the fused source / drain regions 98A), a reduced volume, and increased concentrations of germanium and dopant ions. The semiconductor device including the source / drain region 98A has a reduced channel resistance R ch , a reduced source / drain resistance R sd , improved device performance I on , a reduced gate-to-drain capacitance, a reduced resistance-capacitance delay, and an increased device speed.

[0125] According to one embodiment, a method includes etching one or more semiconductor fins to form one or more grooves; and forming source / drain regions in the one or more grooves, wherein forming the source / drain regions includes: epitaxially growing a first semiconductor material in the one or more grooves at a temperature of 600°C to 800°C, the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material on the first semiconductor material at a temperature of 300°C to 600°C, the second semiconductor material including doped silicon germanium and having a different composition from the first semiconductor material. In one embodiment, the one or more grooves include a first groove and a second groove, and when epitaxially growing the first semiconductor material, the first semiconductor material in the first groove merges with the first semiconductor material in the second groove. In one embodiment, the first semiconductor material includes silicon germanium having a germanium atomic percentage of 40% to 50% and a boron concentration greater than 6x10 20 atoms / cm 3 . In one embodiment, the one or more grooves include a first groove and a second groove, and when conformally depositing the second semiconductor material, the second semiconductor material on the first groove merges with the second semiconductor material on the second groove. In one embodiment, the second semiconductor material includes silicon germanium having a germanium atomic percentage of 60% to 80% and a boron concentration greater than 8x10 20 atoms / cm 3 . In one embodiment, the first semiconductor material is epitaxially grown at a pressure of 5 Torr to 50 Torr, and the second semiconductor material is conformally deposited at a pressure greater than 20 Torr. In one embodiment, epitaxially growing the first semiconductor material includes epitaxially growing a first semiconductor layer in the one or more grooves, the first semiconductor layer having a thickness of 1 nm to 10 nm, the first semiconductor layer including a germanium concentration of 20 to 40 atomic percentage, the first semiconductor layer including a boron dopant concentration of less than 5x10 20 atoms / cm 3 ; and epitaxially growing a second semiconductor layer on and in contact with the first semiconductor layer, the second semiconductor layer having a thickness of less than 25 nm, the second semiconductor layer including a germanium concentration of 40 to 50 atomic percentage, the second semiconductor layer including a boron dopant concentration of greater than 6x10 20 atoms / cm 3 . In one embodiment, depositing the second semiconductor material includes conformally depositing a third semiconductor layer on and in contact with the second semiconductor layer, the third semiconductor layer having a thickness greater than 20 nm, the third semiconductor layer including a germanium concentration of 60 to 80 atomic percentage, the third semiconductor layer including a boron concentration greater than 8x10 20 atoms / cm 3the boron doping concentration; and conformally depositing a fourth semiconductor layer over and in contact with the third semiconductor layer, the fourth semiconductor layer having a thickness less than 10 nm, the fourth semiconductor layer including a germanium concentration of less than 40 atomic percent, the fourth semiconductor layer including a boron doping concentration greater than 1 x 10 20 atoms / cm 3 of the boron doping concentration.

[0126] According to another embodiment, a device includes fins extending from a substrate; a gate stack located over the fins, at least one source / drain region located in the fins adjacent to the gate stack, the at least one source / drain region including a first source / drain material having a germanium concentration of 30 to 50 atomic percent and having a thickness less than 30 nm; and a second source / drain material located over the first source / drain material, the second source / drain material having a germanium concentration of 50 to 80 atomic percent and having a thickness greater than 10 nm; and a source / drain contact contacting the at least one source / drain region. In one embodiment, the first source / drain material includes a first source / drain layer and a second source / drain layer located over the first source / drain layer, the first source / drain layer having a germanium concentration of 30 to 40 atomic percent and having a thickness of 1 to 10 nm, the second source / drain layer having a germanium concentration of 40 to 50 atomic percent and having a thickness less than 25 nm. In one embodiment, the first source / drain layer has a dopant ion concentration less than 5 x 10 20 atoms / cm 3 and the second source / drain layer has a dopant ion concentration greater than 6 x 10 20 atoms / cm 3 and the second source / drain material has a dopant ion concentration greater than 8 x 10 20 atoms / cm 3The dopant ion concentration. In one embodiment, the device further includes a third source / drain material on top of the second source / drain material, the third source / drain material having a germanium concentration of less than 40 atomic percent and a thickness of less than 10 nm. In one embodiment, the device further includes source / drain contacts extending through the third source / drain material to physically contact the second source / drain material. In one embodiment, at least one source / drain region includes a first source / drain region and a second source / drain region, and the first source / drain material of the first source / drain region is fused with the first source / drain material of the second source / drain region. In one embodiment, at least one source / drain region includes a first source / drain region and a second source / drain region, and the second source / drain material of the first source / drain region is fused with the second source / drain material of the second source / drain region. In one embodiment, the second source / drain material includes a valley between the first source / drain region and the second source / drain region, and a first height measured between the highest surface of the first source / drain region and the valley is greater than 5 nm.

[0127] According to yet another embodiment, a method includes etching fins to form a first opening, the fins extending from a substrate; forming source / drain regions in the first opening, forming the source / drain regions including epitaxially growing a first semiconductor material in the first opening at a pressure of 5 Torr to 50 Torr, the first semiconductor material having a dopant ion concentration of less than 5 x 10 20 atoms / cm 3 ; epitaxially growing a second semiconductor material on top of the first semiconductor material at a pressure of 5 Torr to 50 Torr, the second semiconductor material having a dopant ion concentration of greater than 6 x 10 20 atoms / cm 3 ; and conformally depositing a third semiconductor material on top of the second semiconductor material at a pressure of less than 20 Torr, the third semiconductor material having a dopant ion concentration of greater than 8 x 10 20 atoms / cm 3 ; forming an interlayer dielectric on top of the source / drain regions; etching the interlayer dielectric to form a second opening exposing the third semiconductor material; and forming source / drain contacts extending through the second opening to contact the third semiconductor material. In one embodiment, the method further includes conformally depositing a fourth semiconductor material on top of the third semiconductor material at a pressure of less than 20 Torr, the fourth semiconductor material having a dopant ion concentration of greater than 1 x 10 20 atoms / cm 3The dopant ion concentration. In one embodiment, the source / drain regions include a first source / drain region and a second source / drain region, and the first source / drain region and the second source / drain region are fused after the epitaxial growth of the second semiconductor material. In one embodiment, the first source / drain region and the second source / drain region include facets, and the angle between a first facet of the first source / drain region and a second facet of the second source / drain region that intersects the first facet is less than 90 degrees.

[0128] The foregoing text outlines the characteristic components of many embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the present invention shall be determined by what is defined in the claims. Additionally, although the present invention has been disclosed above in several preferred embodiments, it is not intended to limit the present invention, and not all advantages have been detailed herein.

Claims

1. A method of forming a semiconductor device, comprising: etching one or more semiconductor fins to form one or more grooves; and forming source / drain regions in the one or more grooves, wherein forming the source / drain regions comprises: epitaxially growing a first semiconductor material in the one or more grooves at a temperature between 600 °C and 800 °C, the first semiconductor material comprising doped silicon germanium; and epitaxially growing a second semiconductor material on the first semiconductor material, the second semiconductor material comprising doped silicon germanium and having a different composition from the first semiconductor material; conformally depositing a third semiconductor material on the second semiconductor material at a temperature between 300 °C and 600 °C, the third semiconductor material comprising doped silicon germanium and having a different composition from the second semiconductor material, wherein the step of depositing the third semiconductor material comprises: conformally depositing a first semiconductor layer on the second semiconductor material and in contact with the second semiconductor material; and during the deposition of the first semiconductor layer, delivering an etching gas, conformally depositing a fourth semiconductor material on the third semiconductor material, the fourth semiconductor material comprising doped silicon germanium and having a different composition from the third semiconductor material, wherein the topmost point of the first semiconductor material is lower than the bottommost points of the third semiconductor material and the fourth semiconductor material, and wherein the first semiconductor material, the second semiconductor material, the third semiconductor material, and the fourth semiconductor material comprise crystal planes.

2. The method of forming a semiconductor device according to claim 1, wherein the one or more grooves comprise a first groove and a second groove, and wherein during the epitaxial growth of the second semiconductor material, the second semiconductor material on the first groove merges with the second semiconductor material on the second groove.

3. The method of forming a semiconductor device as claimed in claim 2, wherein the second semiconductor material comprises silicon germanium having a germanium atom percentage of 40% to 50% and a boron concentration greater than 6x10 20 atoms / cm 3 ³.

4. The method of forming a semiconductor device according to claim 1, wherein the one or more grooves comprise a first groove and a second groove, and wherein during the epitaxial growth of the third semiconductor material, the third semiconductor material on the first groove merges with the third semiconductor material on the second groove.

5. The method of forming a semiconductor device as claimed in claim 4, wherein the third semiconductor material comprises silicon germanium having a germanium atom percentage of 60% to 80% and a boron concentration greater than 8 x 10 20 atoms / cm 3 .

6. The method of forming a semiconductor device according to claim 1, wherein the first semiconductor material is epitaxially grown at a pressure of 5 Torr to 50 Torr, and the third semiconductor material is conformally deposited at a pressure greater than 20 Torr.

7. The method of forming a semiconductor device according to claim 1, wherein epitaxially growing the first semiconductor material comprises: A second semiconductor layer is epitaxially grown in the one or more grooves, the second semiconductor layer having a thickness of 1 nm to 10 nm, the second semiconductor layer including a germanium concentration of 20 to 40 atomic percent, the second semiconductor layer including a boron dopant concentration of less than 5 x 10 20 atoms / cm 3 .

8. The method of forming a semiconductor device as claimed in claim 7, wherein the first semiconductor layer has a thickness greater than 20 nm, the first semiconductor layer comprises a germanium concentration of 60 to 80 atomic percent, and the first semiconductor layer comprises a boron dopant concentration greater than 8x10 20 atoms / cm 3 .

9. A semiconductor device, comprising: a fin extending from a substrate; a gate stack located on the fin; at least one source / drain region located in the fin adjacent to the gate stack, the at least one source / drain region comprising: a first source / drain material having a germanium concentration of 30 to 50 atomic percent and having a thickness of less than 30 nm; and A second source / drain material, located above the first source / drain material, the second source / drain material having a germanium concentration of 50 to 80 atomic percent and having a thickness greater than 10 nm, wherein a first angle between intersecting crystal planes of the top surface of the second source / drain material is less than 90 degrees but greater than a second angle between intersecting crystal planes of the upper surface of the first source / drain material, wherein the first angle is higher than and overlaps with the second angle; and A source / drain contact, contacting the at least one source / drain region.

10. The semiconductor device according to claim 9, wherein the first source / drain material includes a first source / drain layer and a second source / drain layer located above the first source / drain layer, the first source / drain layer having a germanium concentration of 30 to 40 atomic percent and having a thickness of 1 to 10 nm, the second source / drain layer having a germanium concentration of 40 to 50 atomic percent and having a thickness less than 25 nm.

11. The semiconductor device according to claim 10, wherein the first source / drain layer has a dopant ion concentration of less than 5 x 10 20 atoms / cm 3 , the second source / drain layer has a dopant ion concentration of greater than 6 x 10 20 atoms / cm 3 , and the second source / drain material has a dopant ion concentration of greater than 8 x 10 20 atoms / cm 3 .

12. The semiconductor device according to claim 9, further comprising a third source / drain material above the second source / drain material, the third source / drain material having a germanium concentration less than 40 atomic percent and having a thickness less than 10 nm.

13. The semiconductor device according to claim 12, further comprising a source / drain contact extending through the third source / drain material to physically contact the second source / drain material.

14. The semiconductor device according to claim 9, wherein the at least one source / drain region includes a first source / drain region and a second source / drain region, and wherein the first source / drain material of the first source / drain region is fused with the first source / drain material of the second source / drain region.

15. The semiconductor device according to claim 9, wherein the at least one source / drain region includes a first source / drain region and a second source / drain region, and wherein the second source / drain material of the first source / drain region is fused with the second source / drain material of the second source / drain region.

16. The semiconductor device according to claim 15, wherein the second source / drain material includes a trough between the first source / drain region and the second source / drain region, and wherein a first height measured between the highest surface of the first source / drain region and the trough is greater than 5 nm.

17. A method of forming a semiconductor device, comprising: Etching a fin to form a plurality of first openings, the fin extending from a substrate; Forming a plurality of source / drain regions in the first openings, forming the source / drain regions including: Epitaxially grow a first semiconductor material in the first openings under a pressure of 5 Torr to 50 Torr, the first semiconductor material having a dopant ion concentration of less than 5 x 10 20 atoms / cm 3 ; Epitaxially grow a second semiconductor material on the first semiconductor material under a pressure of 5 Torr to 50 Torr, the second semiconductor material having a dopant ion concentration greater than 6x10 20 atoms / cm 3 ; and Depositing a third semiconductor material conformally on the second semiconductor material under a pressure less than 20 Torr, the third semiconductor material having a dopant ion concentration greater than 8 x 10 20 atoms / cm 3 ; and Compliance-depositing an etch stop layer on the third semiconductor material, wherein a first angle between intersecting crystal planes of the upper surface of the etch stop layer is less than 90 degrees but greater than a second angle between intersecting crystal planes of the upper surface of the second semiconductor material, wherein the first angle is higher than and overlaps with the second angle; Forming an interlayer dielectric on the source / drain regions; Etch the interlayer dielectric and the etch stop layer to form a second opening exposing the third semiconductor material; and Form a source / drain contact extending through the second opening to contact the third semiconductor material.

18. The method of forming a semiconductor device as described in claim 17, wherein the step of conformally depositing the etch stop layer comprises depositing a fourth semiconductor material on top of the third semiconductor material at a pressure less than 20 Torr, the fourth semiconductor material having a dopant ion concentration greater than 1 x 10 20 atoms / cm 3 .

19. The method of forming a semiconductor device according to claim 17, wherein the lowest points of the first semiconductor material and the second semiconductor material are lower than the lowest points of the third semiconductor material and the etch stop layer.

20. The method of forming a semiconductor device according to claim 17, wherein the source / drain region includes a first source / drain region and a second source / drain region, the first source / drain region and the second source / drain region include a plurality of crystal planes, and the angle between a first crystal plane of the first source / drain region and a second crystal plane of the second source / drain region is less than 90 degrees.

21. A method of forming a semiconductor device, comprising:[[]] Form a fin extending from a substrate; Form a gate stack over the fin; Etch the fin to form a groove in the fin adjacent to the gate stack; Form a source / drain region in the groove, wherein the step of forming the source / drain region includes: Deposit a first source / drain layer in the groove, the first source / drain layer having a germanium concentration of 30 to 40 atomic percent; Deposit a second source / drain layer in the groove on the first source / drain layer, the second source / drain layer having a germanium concentration of 40 to 50 atomic percent; Deposit a third source / drain layer in the groove on the second source / drain layer, the third source / drain layer having a germanium concentration of 60 to 80 atomic percent; and Deposit a fourth source / drain layer in the groove on the third source / drain layer, the fourth source / drain layer having a germanium concentration of less than 40 atomic percent, wherein each of the first source / drain layer, the second source / drain layer, the third source / drain layer, and the fourth source / drain layer includes a plurality of crystal planes, and the lowest points of the third source / drain layer and the fourth source / drain layer are higher than the highest point of the first source / drain layer; and Form a source-drain contact to contact the source / drain region.

22. The method of forming a semiconductor device according to claim 21, wherein the first source / drain layer has a thickness of 1 nm to 10 nm; and the second source / drain layer has a thickness of less than 25 nm.

23. The method of forming a semiconductor device according to claim 22, wherein the first source / drain layer has a dopant ion concentration of less than 5x10 20 atoms / cm 3 , the second source / drain layer has a dopant ion concentration of greater than 6x10 20 atoms / cm 3 , and the third source / drain layer has a dopant ion concentration of greater than 8x10 20 atoms / cm 3 .

24. The method of forming a semiconductor device according to claim 21, wherein the third source / drain layer has a thickness of less than 10 nm.

25. The method of forming a semiconductor device according to claim 21, wherein the step of forming the source / drain contact includes etching a groove to extend through the fourth source / drain layer and expose the third source / drain layer.

26. The method of forming a semiconductor device according to claim 21, wherein the first source / drain layer is deposited by an epitaxial process at a temperature of 600 °C to 800 °C, and the first source / drain layer includes doped silicon germanium.

27. The method of forming a semiconductor device according to claim 21, wherein the second source / drain layer is deposited by a conformal process at a temperature of 300°C to 600°C.

28. The method of forming a semiconductor device according to claim 21, further comprising forming a second source / drain region in a second recess of a second fin adjacent to the fin, wherein the source / drain region merges with the second source / drain region, wherein an upper surface of the source / drain region and the second source / drain region includes a valley between the fin and the second fin, and wherein a vertical first height measured between a highest surface of the source / drain region and a bottommost surface of the valley is greater than 5 nm.

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