Reticle for EUV Lithography

Abstract

A photomask for extreme ultraviolet lithography includes a substrate having a front surface and a rear surface opposite to the front surface; a multi-layer Mo / Si stack disposed on the front surface of the substrate; a capping layer disposed on the multi-layer Mo / Si stack; an absorption layer disposed on the capping layer; and a backside conductive layer disposed on the rear surface of the substrate. The backside conductive layer is made of tantalum boride.

Description

Technical Field

[0001] The present disclosure relates to a mask for extreme ultraviolet lithography. Background Art

[0002] Photolithography is one of the key operations in semiconductor manufacturing. Photolithography techniques include ultraviolet lithography, deep ultraviolet lithography, and extreme ultraviolet lithography (EUVL). The mask is an important component in photolithography. It is critical to manufacture defect-free EUV masks. Summary of the invention

[0003] According to one aspect of the present application, a mask for extreme ultraviolet (EUV) lithography includes a substrate having a front surface and a rear surface opposite to the front surface; a multi-layer Mo / Si stack disposed on the front surface of the substrate; a capping layer disposed on the multi-layer Mo / Si stack; an absorption layer disposed on the capping layer; and a backside conductive layer disposed on the rear surface of the substrate. The backside conductive layer is made of tantalum boride. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0005] Figure 1A and Figure 1B FIG. 1 shows an EUV mask blank according to one embodiment of the present disclosure;

[0006] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2G Schematically illustrating a method for manufacturing an EUV mask according to an embodiment of the present disclosure;

[0007] Figure 3 A schematic diagram illustrating an etching operation of an EUV mask according to one embodiment of the present disclosure;

[0008] Figure 4 A schematic diagram illustrating an etching operation of an EUV mask according to another embodiment of the present disclosure;

[0009] Figure 5 A schematic diagram illustrating an etching operation of an EUV mask according to another embodiment of the present disclosure;

[0010] Figure 6 A schematic diagram illustrating an etching operation of an EUV mask according to another embodiment of the present disclosure;

[0011] Figure 7 Schematic diagram of a linear protrusion or a linear O-ring according to an embodiment of the present disclosure;

[0012] Figure 8 FIG. 1 shows an operation of loading an EUV mask to be etched into an etching chamber via a load lock chamber.

[0013]

Explanation of symbols

[0014] 5 EUV mask blanks

[0015] 10 substrate

[0016] 15 Multilayer Mo / Si stack

[0017] 20 Capping layer

[0018] 25 Absorption layer

[0019] 30 Hard Mask Layers

[0020] 35 First photoresist layer

[0021] 40 Patterns

[0022] 41 Pattern

[0023] 42 Pattern

[0024] 45 Back side conductive layer

[0025] 50 Patterns

[0026] 51 Pattern

[0027] 55 Second photoresist layer

[0028] 200 units

[0029] 210 Base

[0030] 220 Capture Ring

[0031] 222 Part 1 / Flat Part

[0032] 225 Protrusion

[0033] 227 O-ring

[0034] 230 Cathode

[0035] 235 Knot DETAILED DESCRIPTION

[0036] It should be understood that the following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the size of the element is not limited to the disclosed range or value, but may depend on the process conditions and / or the desired properties of the device. In addition, in the following description, the first feature is formed above or on the second feature, which may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed to insert the first feature and the second feature so that the first feature and the second feature may not be in direct contact. For simplicity and clarity, various features can be arbitrarily drawn in different proportions.

[0037] In addition, for simplicity of description, spatially relative terms such as "below", "below", "lower", "above", "upper", and the like may be used herein to describe the relationship of one element or feature to another (other) element or feature as illustrated in the figures. In addition to the orientation depicted in the figures, these spatially relative terms are intended to also cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, the term "made of" may mean "including" or "consisting of". In the present disclosure, the term "one of A, B, and C" means "A, B, and / or C (A, B, C, A and B, A and C, B and C, or A, B and C)", and does not mean one element from A, one element from B, and one element from C, unless otherwise described.

[0038] Embodiments of the present disclosure provide a method of manufacturing an EUV mask. More specifically, the present disclosure provides techniques for preventing or inhibiting damage to a backside conductive layer of an EUV mask.

[0039] EUV lithography (EUVL) employs a scanner that uses light in the extreme ultraviolet (EUV) region, which has a wavelength of about 1 nm to about 100 nm (e.g., 13.5 nm). The mask is a key component of the EUVL system. Because optical materials are opaque to EUV radiation, the EUV mask is a reflective mask. The EUV mask requires extremely low surface roughness and must be free of discernible defects.

[0040] EUV masks with circuit patterns for EUV lithography require various etching operations, such as plasma dry etching. The EUV mask to be etched is placed on a mask stage in a plasma etching chamber. In some embodiments, the mask stage includes an electric chuck mechanism to hold the EUV mask during plasma etching. The EUV mask includes a backside conductive layer relative to the electric chuck mechanism. However, when there is a large gap between the EUV mask and the stage, the active species of the plasma may diffuse to the bottom portion of the EUV mask, resulting in damage to the backside conductive layer of the EUV mask. Damage to the backside conductive layer may cause various problems, such as the generation of particles and / or tree-like erosion at the edge of the conductive film. Such particles and / or defects in the backside conductive layer may result in insufficient clamping and / or defects in the circuit pattern on the front side of the EUV mask.

[0041] The present disclosure provides techniques for preventing or inhibiting damage to a backside conductive layer of an EUV reticle caused by reactive species of the plasma during plasma etching.

[0042] Figure 1A and Figure 1B An EUV mask blank according to an embodiment of the present disclosure is shown. Figure 1A is a cross-sectional view and Figure 1B This is a plan view viewed from the back side of the EUV mask.

[0043] In some embodiments, an EUV mask having a circuit pattern is formed from an EUV mask blank 5. The EUV mask blank 5 includes a substrate 10, a multilayer Mo / Si stack 15 of a plurality of alternating layers of silicon and molybdenum, a capping layer 20, an absorber layer 25, and a hard mask layer 30. Figure 1A As shown in , the backside conductive layer 45 is formed on the backside of the substrate 10 .

[0044] In some embodiments, the substrate 10 is formed of a low thermal expansion material. In some embodiments, the substrate is a low thermal expansion glass or quartz, such as fused silica or fused quartz. In some embodiments, the low thermal expansion glass substrate transmits light of visible wavelengths, portions of infrared wavelengths near the visible spectrum (near infrared), and portions of ultraviolet wavelengths. In some embodiments, the low thermal expansion glass substrate absorbs extreme ultraviolet wavelengths and deep ultraviolet wavelengths near the extreme ultraviolet. In some embodiments, the size of the substrate 10 is 152 mm×152 mm, with a thickness of about 20 mm.

[0045] In some embodiments, the Mo / Si multilayer stack 15 includes about 30 alternating layers of each of silicon and molybdenum to about 60 alternating layers of each of silicon and molybdenum. In certain embodiments, about 40 to about 50 alternating layers of each of silicon and molybdenum are formed. In some embodiments, for the wavelength of interest (e.g., 13.5nm), the reflectivity is higher than about 70%. In some embodiments, the silicon and molybdenum layers are formed by chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD) (sputtering) or any other suitable formation method. Each layer of silicon and molybdenum is about 2nm to about 10nm thick. In some embodiments, the layers of silicon and molybdenum are about the same thickness. In other embodiments, the layers of silicon and molybdenum are different thicknesses. In some embodiments, the thickness of each layer of silicon and molybdenum is about 3nm to about 4nm.

[0046] In other embodiments, the multilayer stack 15 includes alternating layers of molybdenum and beryllium. In some embodiments, the number of layers in the multilayer stack 15 ranges from about 20 to about 100, but any number of layers is allowed as long as sufficient reflectivity is maintained to image the target substrate. In some embodiments, the reflectivity is greater than about 70% for wavelengths of interest (e.g., 13.5 nm). In some embodiments, the multilayer stack 15 includes about 30 to about 60 alternating layers of Mo and Be. In other embodiments of the present disclosure, the multilayer stack 15 includes about 40 to about 50 alternating layers of Mo and Be.

[0047] In some embodiments, a capping layer 20 is disposed on top of the Mo / Si multilayer 15 to prevent oxidation of the multilayer stack 15. In some embodiments, the capping layer 20 is made of ruthenium and has a thickness from about 2 nm to about 10 nm. In certain embodiments, the thickness of the capping layer 20 is from about 2 nm to about 4 nm. In some embodiments, the capping layer 20 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation method. In other embodiments, a Si layer is used as the capping layer 20.

[0048] The absorber layer 25 is disposed on the capping layer 20. In some embodiments, the absorber layer 25 is a Ta-based material. In some embodiments, the absorber layer 25 is made of TaN, TaO, or TaBN, and has a thickness from about 25 nm to about 100 nm. In certain embodiments, the thickness of the absorber layer 25 ranges from about 50 nm to about 75 nm. In some embodiments, the absorber layer 25 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation method.

[0049] In some embodiments, an anti-reflection layer (not shown) is optionally disposed on the absorption layer 25. In some embodiments, the anti-reflection layer is made of silicon oxide and has a thickness from about 2 nm to about 10 nm. In other embodiments, a TaBO layer having a thickness in the range of from about 12 nm to about 18 nm is used as the anti-reflection layer. In some embodiments, the thickness of the anti-reflection layer 20 is from about 3 nm to about 6 nm. In some embodiments, the anti-reflection layer is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation method.

[0050] In some embodiments, the hard mask layer 30 is disposed on the absorption layer 25. In some embodiments, the hard mask layer 30 is formed on the anti-reflection layer. In some embodiments, the hard mask layer 30 is made of silicon, silicon-based compounds, chromium, or chromium-based compounds, and has a thickness of about 4 nm to about 20 nm. In some embodiments, the chromium-based compounds include CrON, chromium oxide, and / or chromium nitride. In some embodiments, the hard mask layer 30 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation method. In other embodiments, TaO, TaN, Ru, RuB, RuB, TaB, TaBN, or TaBO is used as the hard mask layer 30.

[0051] In some embodiments, the backside conductive layer 45 is disposed on a second main surface of the substrate 10 opposite to the first main surface of the substrate 10 on which the Mo / Si multilayer 15 is formed. In some embodiments, the backside conductive layer 45 is made of TaB (tantalum boride) or other Ta-based conductive materials.

[0052] Currently, Cr-based conductive materials (CRN or CrON) have been used for the back-side conductive layer. Compared with Cr-based conductive materials, TaB has a lower sheet resistance (higher conductivity) and a flatter surface, while TaB has sufficient rigidity similar to CrN. In some embodiments, the sheet resistance of the back-side conductive layer 45 is equal to or less than 20Ω / □. In some embodiments, the sheet resistance of the back-side conductive layer 45 is equal to or greater than 0.1Ω / □. In some embodiments, the surface roughness Ra of the back-side conductive layer 45 is equal to or less than 0.25nm. In some embodiments, the surface roughness Ra of the back-side conductive layer 45 is equal to or greater than 0.05nm. In addition, in some embodiments, the flatness of the back-side conductive layer 45 is equal to or less than 50nm (inside the EUV mask). In some embodiments, the flatness of the back-side conductive layer 45 is greater than 1nm.

[0053] In some embodiments, the tantalum boride is crystalline. Crystalline tantalum boride includes TaB, Ta5B6, Ta3B4, and TaB2. In some embodiments, the backside conductive layer 45 is TaB crystal. In other embodiments, the tantalum body is polycrystalline or amorphous.

[0054] In some embodiments, the thickness of the backside conductive layer is in the range of from about 50 nm to about 400 nm. In other embodiments, the backside conductive layer 45 has a thickness of from about 50 nm to about 100 nm. In certain embodiments, the thickness is in the range of from about 65 nm to about 75 nm.

[0055] In some embodiments, the backside conductive layer 45 is formed by atmospheric pressure chemical vapor deposition (CVD), low pressure CVD, plasma enhanced CVD, laser enhanced CVD, atomic layer deposition (ALD), molecular beam epitaxy (MBE), physical vapor deposition (including thermal deposition, pulsed laser deposition, electron beam evaporation, ion beam assisted evaporation and sputtering), or any other suitable film formation method. In the case of CVD, in some embodiments, the source gas includes TaCl5 and BCl3.

[0056] In some embodiments, the area of ​​the back conductive layer 45 is smaller than the area of ​​the substrate, and the peripheral portion of the second main surface of the substrate 10 is exposed (not covered by the back conductive layer 45), such as Figure 1BAs shown. When the substrate 10 is a 6-inch substrate (i.e., 152 mm × 152 mm), in some embodiments, the size of the backside conductive layer 45 is greater than 142 mm × 142 mm and less than 150 mm × 150 mm. In other embodiments, the size of the backside conductive layer 45 is greater than 142 mm × 142 mm and less than 148 mm × 148 mm. In some embodiments, the shape of the backside conductive layer 45 is square or rectangular. In some embodiments, when the shape of the backside conductive layer 45 has a first side LX and a second side LY in the cross direction (e.g., perpendicular), 0.98 ≤ LX / LY ≤ 1.02. In some embodiments, 142 mm < LX < 150 mm and 142 mm < LY < 150 mm, and in other embodiments, 144 mm < LX < 148 mm and 144 mm < LY < 148 mm. In some embodiments, the ratio of the side LX or LY of the backside conductive layer 45 to a side of the substrate 10 is from about 0.93 to about 0.99.

[0057] In some embodiments, the distance D1 from the edge of the substrate 10 to the edge of the backside conductive layer 45 (at the center of such edges) ranges from about 1 mm to about 5 mm, and in other embodiments is in the range from about 2 mm to about 4 mm. In some embodiments, the corners of the backside conductive layer 45 are cut to form an octagonal shape. As explained below, the backside conductive layer 45 will contact the protrusion of the electric clamping mechanism. In other embodiments, only the EUV mask is placed on the cathode of the mask stage. In some embodiments, the maximum area of the protrusion arrangement is about 142 mm × 142 mm, and thus the area of the backside conductive layer 45 is greater than 142 mm × 142 mm.

[0058] In other embodiments, substrates of different sizes are used. When the substrate 10 is a 5-inch substrate (i.e., 126.6 mm × 126.6 mm), in some embodiments, the size of the backside conductive layer 45 is greater than 120 mm × 120 mm and less than 125 mm × 125 mm, and in other embodiments is greater than 122 mm × 122 mm and less than 123.5 mm × 123.5 mm. When the substrate 10 is a 7-inch substrate (i.e., 177.4 mm × 177.4 mm), in some embodiments, the size of the backside conductive layer 45 is greater than 170 mm × 170 mm and less than 175 mm × 175 mm, and in other embodiments is greater than 172 mm × 172 mm and less than 173.5 mm × 173.5 mm.

[0059] In some embodiments, a TaB backside conductive layer 45 is formed on the entire rear surface of the substrate 10, and an edge portion of the backside conductive layer 45 is removed to partially expose the rear surface of the substrate 10. The backside conductive layer 45 is removed by using one or more lithography and etching operations. In other embodiments, an edge portion of the rear surface of the substrate 10 is covered by, for example, a hard cap having an opening, and a sputtered material for TaB is deposited on the rear surface of the substrate 10 through the opening of the hard cap.

[0060] Figures 2A to 2G A method of manufacturing an EUV mask 5 for use in extreme ultraviolet lithography (EUVL) is schematically illustrated. It should be understood that Figures 2A to 2G Additional operations are provided before, during, and after the processes shown in the drawings, and some of the operations described below may be replaced or eliminated to obtain additional embodiments of the method. The order of the operations / processes may be interchanged.

[0061] In the manufacture of the EUV mask 5, a first photoresist layer 35 is formed on the hard mask layer 30 of the EUV mask blank, and the photoresist layer 35 is selectively exposed to actinic radiation. Before forming the first photoresist layer 35, the EV mask blank is inspected. The selectively exposed first photoresist layer 35 is developed to form a pattern 40 in the first photoresist layer 35. In some embodiments, the actinic radiation is an electron beam or an ion beam. In some embodiments, the pattern 40 corresponds to a pattern of semiconductor device features, which will be formed using the EUV mask 5 in subsequent operations.

[0062] Next, if Figure 2B As shown in FIG. 1 , the pattern 40 in the first photoresist layer 35 is extended into the hard mask layer 30, thereby forming a pattern 41 in the hard mask layer 30, the pattern 41 exposing a portion of the absorption layer 25. In some embodiments, the pattern 41 extending into the hard mask layer 30 is formed by etching using a suitable wet etchant or dry etchant that is selective to the hard mask layer 30. After the pattern 41 is formed through the hard mask layer 30, the first photoresist layer 35 is removed by a photoresist stripper to expose the upper surface of the hard mask layer 30, as shown in FIG. Figure 2C as shown in .

[0063] Next, the pattern 41 in the hard mask layer 30 is extended into the absorption layer 25, thereby forming a pattern 42 in the absorption layer 25, wherein the pattern 42 exposes a portion of the capping layer 20, as shown in FIG. Figure 2D In some embodiments, the pattern 42 extending into the absorption layer 25 is formed by etching using a suitable wet etchant or dry etchant that is selective to the absorption layer 25. In some embodiments, plasma dry etching is used.

[0064] like Figure 2EAs shown in , a second photoresist layer 55 is formed over the absorber layer 25 to fill the pattern 42 in the absorber layer 25. The second photoresist layer 55 is selectively exposed to actinic radiation, such as an electron beam or UV radiation. The selectively exposed second photoresist layer 55 is developed to form a pattern 50 in the second photoresist layer 55. The pattern 50 corresponds to a black border surrounding the circuit pattern. The black border is a frame-shaped area created by removing all the multiple layers on the EUV mask in the area around the circuit pattern area. It is created to prevent exposure of adjacent fields when the EUV mask is printed on the wafer. In some embodiments, the width of the black border is in a range from about 1 mm to about 5 mm.

[0065] Next, the pattern 50 in the second photoresist layer 55 is extended to the absorption layer 25, the capping layer 20 and the Mo / Si multilayer 15, so as to form a pattern 51 in the absorption layer 25, the capping layer 20 and the Mo / Si multilayer 15, wherein the pattern 51 exposes a portion of the substrate 10, as shown in FIG. Figure 2F In some embodiments, the pattern 51 is formed by etching using one or more suitable wet or dry etchants that are selective to each of the etched layers. In some embodiments, plasma dry etching is used.

[0066] Next, the second photoresist layer 55 is removed by a suitable photoresist stripper to expose the upper surface of the absorption layer 25. In some embodiments of the present disclosure, the absorption layer 25, the capping layer 20, and the pattern 51 in the Mo / Si multilayer 15 define a black border of the mask 5, such as Figure 2G After the second photoresist layer is removed, the photomask 5 undergoes a cleaning operation, inspection, and, if necessary, repair of the photomask 5 to provide a completed photomask 5 .

[0067] As explained, there are various etching (plasma etching) operations in manufacturing EUV masks.

[0068] Figure 3 A schematic diagram illustrating an etching operation of an EUV mask according to one embodiment of the present disclosure is shown.

[0069] In some embodiments, the stage 200 of the etching apparatus includes a capture ring 220 supported by a pedestal 210. In addition, in some embodiments, the etching apparatus includes an electric chuck mechanism including a cathode 230 having a protrusion 235 to hold an EUV mask. The stage 200, the pedestal 210, and the cathode 230 are placed inside a plasma etching chamber.

[0070] When the EUV mask 5 is transferred to the etching chamber, the EUV mask 5 is placed on the burls 235 of the cathode 230 , and the burls 235 are arranged in a matrix in a plan view. Figure 3 The diagram shows a state when the EUV mask 5 is placed on the burl 235. In some embodiments, the distance H1 between the level of the bottom of the back conductive layer 45 and the upper surface of the flat portion 222 of the capture ring 220 is in a range from about 0.5 mm to 1.5 mm. Since the distance D1 from the edge of the substrate 10 to the edge of the back conductive layer 45 is set long (for example, in a range from about 1 mm to about 5 mm or in a range from about 2 mm to about 4 mm), the active species of the plasma PL does not reach the back conductive layer 45. In some embodiments, when the distance D1 is equal to or greater than 3 mm, the back conductive layer 45 is substantially free from damage caused by the active species of the plasma.

[0071] Figure 4 A schematic diagram illustrating an etching operation of an EUV mask according to one embodiment of the present disclosure is shown.

[0072] In this embodiment, the stage 200 and / or the cathode 230 of the electric chuck mechanism are configured so that when the EUV mask 5 is placed on the protrusion 235 of the cathode 230 of the electric chuck mechanism, the level of the bottom of the backside conductive layer 45 is positioned lower than the upper surface of the flat portion 222 of the stage 200. In some embodiments, the height difference H1 between the flat portion 222 and the bottom of the substrate 10 is in the range from about 0 nm (contact) to about 100 nm. According to this configuration, active substances of the plasma PL can be prevented from entering the back of the EUV mask 5 during plasma etching. Therefore, damage to the backside conductive layer 45 can be prevented. In some embodiments, the level of the bottom of the backside conductive layer 45 is lower by a height H3 than the upper surface flat portion 222 of the stage 200, as shown in FIG. Figure 4 . In some embodiments, the height H3 is in a range from about 0 nm (coplanar) to about 100 nm, and in other embodiments, H3 is in a range from about 10 nm to about 50 nm. In some embodiments, the flat portion 222 of the capture ring 220 extends below the substrate 10 so that the flat portion 222 overlaps the EUV mask 5 by a width W1. In some embodiments, the width W1 is in a range from about 0 nm (non-overlapping) to about 50 nm, and in other embodiments, W1 is in a range from about 10 nm to about 30 nm.

[0073] Figure 5 A schematic diagram illustrating an etching operation of an EUV mask according to one embodiment of the present disclosure is used to prevent active species of plasma from entering a bottom portion of the EUV mask during plasma etching.

[0074] In some embodiments, the flat portion 222 of the capture ring 220 of the stage 200 has a protrusion 225, so that when the EUV mask 5 is placed on the protrusion 235 of the cathode 230 of the electric chuck mechanism, the bottom surface of the substrate 10 contacts the protrusion 225 of the capture ring 220, as shown in FIG. Figure 5 In some embodiments, there is a small gap between the bottom surface of the substrate 10 and the protrusion 225. In certain embodiments, the gap is in a range from about 0 mm to about 0.1 mm.

[0075] In some embodiments, the protrusion 225 is a linear pattern and is formed along the entire periphery of the flat portion 222. In other embodiments, a plurality of protrusions 225 are discretely provided along the periphery of the flat portion 222. In some embodiments, the protrusion amount of the protrusion 225 is in a range from about 0.1 mm to about 1.0 mm. When the protrusion 225 is used, the contact area of ​​the flat portion 222 of the capture ring 220 with the bottom surface of the substrate 10 of the EUV mask 5 can be minimized when the substrate 10 of the EUV mask 5 contacts the flat portion 222. In other embodiments, there is a gap between the protrusion 225 and the bottom surface of the substrate 10 of the EUV mask 5. In some embodiments, the gap is in a range from about 0 mm to about 0.1 mm. By using the protrusion 225 on the flat portion 222 of the stage 200, the active species of the plasma PL can be prevented from entering the back of the EUV mask 5 during plasma etching. Therefore, damage to the backside conductive layer 45 can be prevented.

[0076] Figure 6 A schematic diagram illustrating an etching operation of an EUV mask according to an embodiment of the present disclosure is used to prevent active species of plasma from entering a bottom portion of the EUV mask during plasma etching.

[0077] In this embodiment, instead of Figure 5 The protrusion 225 shown in FIG. 2 is contacted with the bottom surface of the substrate 10 of the EUV mask 5 using an O-ring 227 embedded in a groove formed on the flat portion 222 of the catch ring 220 of the stage 200. The O-ring 227 is made of a flexible material, such as but not limited to rubber (e.g., butadiene rubber, butyl rubber, ethylene propylene diene monomer rubber or nitrile rubber), polytetrafluoroethylene (PTFE), perfluoroelastomer or silicone. Similar to the linear protrusion 225, the contact area of ​​the flat portion 222 of the stage 200 with the bottom surface of the substrate 10 of the EUV mask 5 can be minimized by using the O-ring 227. In some embodiments, the size of the O-ring is in the range from about 1 mm to about 5 mm. By using the O-ring 227 on the flat portion 222 of the stage 200, active substances of the plasma PL can be prevented from entering the back of the EUV mask 5 during plasma etching. Therefore, damage to the backside conductive layer 45 can be prevented.

[0078] Figure 7 FIG. 2 is a plan view showing a linear protrusion 225 or a linear O-ring 227 according to an embodiment of the present disclosure.

[0079] Figure 8 The diagram shows an operation of loading an EUV mask 5 to be etched into an etching chamber via a load lock chamber. In some embodiments, the EUV mask 5 to be subjected to plasma etching is stored in a SMIF (standard mechanical interface) cabin and carried to an etching apparatus from the SMIF cabin. The EUV mask 5 is transferred from the SMIF cabin to a load lock chamber of the etching apparatus. Next, the EUV mask 5 is transferred from the load lock chamber to the etching chamber, as shown in FIG. Figure 8 In the etching chamber, the EUV mask 5 is placed on the protrusion 235 of the cathode 230 of the electric chuck. After the etching operation is completed, the EUV mask 5 is transferred from the etching chamber to the load lock chamber, and then unloaded from the load lock chamber to the SMIF cabin for the next operation, such as cleaning.

[0080] It should be understood that not all advantages have been discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0081] For example, by using a TaB backside conductive layer, higher electrical and mechanical properties suitable for an electric clamping mechanism can be obtained. In addition, by adjusting the size (area) of the backside conductive layer, damage to the backside conductive layer caused by active substances of the plasma during plasma etching can be prevented or suppressed. In addition, by contacting the bottom surface of the substrate with the flat portion of the catch ring of the stage or positioning it tightly, active substances of the plasma can be prevented from entering the back of the EUV mask during plasma etching. Therefore, damage to the backside conductive layer can be prevented and the generation of particles or unsafe clamping of the electric substrate clamping mechanism can be prevented.

[0082] According to one aspect of the present application, a mask for extreme ultraviolet (EUV) lithography includes a substrate having a front surface and a back surface opposite the front surface; a multilayer Mo / Si stack disposed on the front surface of the substrate; a capping layer disposed on the multilayer Mo / Si stack; an absorption layer disposed on the capping layer; and a backside conductive layer disposed on the back surface of the substrate. The backside conductive layer is made of tantalum boride. In one or more of the foregoing and following embodiments, the thickness of the backside conductive layer ranges from 50 nm to 400 nm. In one or more of the foregoing and following embodiments, the thickness of the backside conductive layer ranges from 50 nm to 100 nm. In one or more of the foregoing and following embodiments, the sheet resistance of the backside conductive layer is equal to or less than 20 Ω / sq. In one or more of the foregoing and following embodiments, the surface roughness Ra of the backside conductive layer is equal to or less than 0.25 nm. In one or more of the foregoing and following embodiments, the flatness of the backside conductive layer is equal to or less than 50 nm. In one or more of the foregoing and following embodiments, the backside conductive layer has a rectangular shape having a first side and a second side intersecting the first side, and the length LX of the first side and the length LY of the second side satisfy 142 mm < LX < 150 mm and 142 mm < LY < 150 mm. In one or more of the foregoing and following embodiments, 144 mm < LX < 148 mm and 144 mm < LY < 148 mm. In one or more of the foregoing and following embodiments, 0.98 ≤ LX / LY ≤ 1.02. In one or more of the foregoing and following embodiments, the mask further includes a hard mask layer disposed on the absorption layer.

[0083] According to another aspect of the present disclosure, a mask for extreme ultraviolet (EUV) lithography includes a substrate having a front surface and a back surface opposite the front surface; a multilayer Mo / Si stack disposed on the front surface of the substrate; a capping layer disposed on the multilayer Mo / Si stack; an absorption layer disposed on the capping layer; and a backside conductive layer disposed on the back surface of the substrate. The backside conductive layer has a rectangular shape having a first side and a second side intersecting the first side, and the length LX of the first side and the length LY of the second side satisfy 142 mm < LX < 150 mm and 142 mm < LY < 150 mm. In one or more of the foregoing and following embodiments, 144 mm < LX < 148 mm and 144 mm < LY < 148 mm. In one or more of the foregoing and following embodiments, 0.98 ≤ LX / LY ≤ 1.02. In one or more of the foregoing and following embodiments, the mask further includes a hard mask layer disposed on the absorption layer.

[0084] According to another aspect of the present disclosure, in a method of manufacturing a mask for extreme ultraviolet (EUV) lithography, a multilayer Mo / Si stack is formed on a front surface of a substrate. A capping layer is formed on the multilayer Mo / Si stack. An absorption layer is formed on the capping layer. A backside conductive layer is formed on a back surface of the substrate opposite to the front surface. The backside conductive layer is made of tantalum boride. In one or more of the foregoing and following embodiments, the thickness of the backside conductive layer is in a range from 50nm to 400nm. In one or more of the foregoing and following embodiments, the thickness of the backside conductive layer is in a range from 50nm to 100nm. In one or more of the foregoing and following embodiments, the sheet resistance of the backside conductive layer is equal to or less than 20Ω / □. In one or more of the foregoing and following embodiments, the surface roughness Ra of the backside conductive layer is equal to or less than 0.25nm. In one or more of the foregoing and following embodiments, the flatness of the backside conductive layer is equal to or less than 50nm.

[0085] The foregoing summarizes the features of several embodiments or examples so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments or examples described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and replacements herein without departing from the spirit and scope of the present disclosure.

Claims

1. A mask for extreme ultraviolet lithography, characterized in that: Comprising: A substrate having a front surface and a rear surface opposite to the front surface; A multi-layer Mo / Si stack disposed on the front surface of the substrate; A capping layer disposed on the multi-layer Mo / Si stack; An absorption layer disposed on the capping layer; And A backside conductive layer disposed on the rear surface of the substrate, wherein the backside conductive layer is made of tantalum boride, the tantalum boride is crystalline, the area of the backside conductive layer is smaller than the area of the substrate, and the distance from the edge of the substrate to the edge of the backside conductive layer is equal to or greater than 3 mm.

2. The photomask according to claim 1, wherein: Wherein a thickness of the backside conductive layer is in a range from 50 nm to 400 nm.

3. The photomask according to claim 1, wherein: Wherein a thickness of the backside conductive layer is in a range from 50 nm to 100 nm.

4. The photomask according to claim 1, wherein: Wherein the sheet resistance of the backside conductive layer is equal to or less than 20 Ω / □.

5. The photomask according to claim 1, wherein: Wherein the surface roughness Ra of the backside conductive layer is equal to or less than 0.25 nm.

6. The photomask according to claim 1, wherein: Wherein the flatness of the backside conductive layer is equal to or less than 50 nm.

7. The photomask according to claim 1, wherein: Wherein: The backside conductive layer has a rectangular shape having a first side and a second side intersecting the first side, and A length LX of the first side and a length LY of the second side satisfy 142 mm < LX < 150 mm and 142 mm < LY < 150 mm.

8. The photomask according to claim 7, wherein: Where 144 mm < LX < 148 mm and 144 mm < LY < 148 mm.

9. The photomask according to claim 7, wherein: Where 0.98 ≤ LX / LY ≤ 1.

02.

10. The photomask according to claim 1, wherein: Further comprising a hard mask layer disposed on the absorption layer.

11. A mask for extreme ultraviolet lithography, characterized in that: Comprising: A substrate having a front surface and a rear surface opposite to the front surface; A multi-layer Mo / Si stack disposed on the front surface of the substrate; A capping layer disposed on the multi-layer Mo / Si stack; An absorption layer disposed on the capping layer; And A backside conductive layer disposed on the rear surface of the substrate, wherein The backside conductive layer has a rectangular shape having a first side and a second side intersecting the first side, and a length LX of the first side and a length LY of the second side satisfy 142 mm < LX < 150 mm and 142 mm < LY < 150 mm, the backside conductive layer is made of tantalum boride, the tantalum boride is crystalline, the area of the backside conductive layer is smaller than the area of the substrate, and the distance from the edge of the substrate to the edge of the backside conductive layer is equal to or greater than 3 mm.

12. The photomask according to claim 11, wherein: Where 144 mm < LX < 148 mm and 144 mm < LY < 148 mm.

13. The photomask according to claim 11, wherein: Where 0.98 ≤ LX / LY ≤ 1.

02.

14. The photomask according to claim 11, wherein: Where further comprising a hard mask layer disposed on the absorption layer.

15. A method for manufacturing a mask for extreme ultraviolet lithography, characterized in that: Comprising: Forming a multi-layer Mo / Si stack on a front surface of a substrate; Forming a capping layer on the multi-layer Mo / Si stack; Forming an absorption layer on the capping layer; and A back conductive layer is formed on a back surface of the substrate opposite to the front surface, wherein the back conductive layer is made of tantalum boride, which is crystalline, the area of ​​the back conductive layer is smaller than the area of ​​the substrate, and the distance from the edge of the substrate to the edge of the back conductive layer is equal to or greater than 3 mm.

16. The method according to claim 15, characterized in that The thickness of the back conductive layer is in a range from 50 nm to 400 nm.

17. The method according to claim 15, characterized in that The thickness of the back conductive layer is in a range from 50 nm to 100 nm.

18. The method according to claim 15, characterized in that The sheet resistance of the back conductive layer is equal to or less than 20Ω / □.

19. The method according to claim 15, characterized in that The surface roughness Ra of the back conductive layer is equal to or less than 0.25 nm.

20. The method according to claim 15, characterized in that The flatness of the back conductive layer is equal to or less than 50 nm.

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