Memory device, error correction code system, and method of correcting errors

Abstract

Memory devices, such as MRAM devices, include a plurality of memory macros, where each memory macro includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit is remote from the plurality of memory macros and communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors. Embodiments of the invention also relate to error correction code systems and methods of correcting errors.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to memory devices, error correction code systems, and methods of correcting errors. BACKGROUND

[0002] Memory is widely used to store information (data and programs) in digital systems. During system operation, information (bits) stored in memory can be corrupted due to various reasons. One possible reason for corruption is due to environmental events both inside the memory and outside the memory. One such external event is particle strikes. In addition to environmental events, there are other reasons that cause corruption (failure) of bits. When a certain bit is corrupted, the stored information is lost, resulting in system malfunction or data loss. Therefore, it is important to protect the integrity of the memory contents. Various ways have been used to protect the memory contents from corruption. Error correction codes (ECC) have the advantage of being able to detect errors in codewords (data field and check bits) and correct the errors. SUMMARY

[0003] Embodiments of the present invention provide a memory device comprising: a plurality of memory macros, each memory macro comprising an array of memory cells and a first error correction code (ECC) circuit configured to detect data errors in the respective memory macro; a second error correction code circuit remote from the plurality of memory macros and communicatively coupled to each of the plurality of memory macros and configured to receive detected data errors from the first error correction code circuits of the plurality of memory macros and write corrected data to a memory array.

[0004] Another embodiment of the present invention provides an error correction code system comprising: a plurality of first error correction code circuits, each of the plurality of first error correction code circuits configured to be communicatively coupled to a respective memory array and configured to detect data errors in the respective memory array; and a second error correction code circuit communicatively coupled to each of the plurality of first error correction code circuits and configured to receive detected data errors from the plurality of first error correction code circuits and correct the data errors.

[0005] Another embodiment of the present invention provides a method for correcting errors, comprising: providing a plurality of memory macros, each memory macro including an array of memory cells and a first error correction code circuit; providing a second error correction code circuit that is remote from the plurality of memory macros and communicatively coupled to each of the plurality of memory macros; refreshing the memory array, including using the first error correction code circuit to check for data errors in the memory array; if the first error correction code circuit identifies a data error, sending the detected data error to the second error correction code circuit; correcting the data error by the second error correction code circuit; and writing the corrected data into the memory array. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion. Furthermore, the accompanying drawings are shown as examples of embodiments of the invention and are not intended to be limiting.

[0007] Figure 1 The diagram illustrates an example MRAM device with multiple MRAM arrays, each with a dedicated and simplified ECC circuitry, according to an embodiment.

[0008] Figure 2 This is a block diagram illustrating an example MRAM cell within an MRAM array, according to an embodiment.

[0009] Figure 3 This is a block diagram illustrating an example ECC logic process for MRAM error correction, based on an embodiment.

[0010] Figure 4 This is a flowchart of a method for correcting MRAM errors using ECC logic processing according to an embodiment.

[0011] Figure 5 This is a block diagram illustrating an example ECC logic process for MRAM error correction, based on an embodiment.

[0012] Figure 6 This is a flowchart of a method for correcting MRAM errors using ECC logic processing according to an embodiment.

[0013] Figure 7 This is a block diagram illustrating an example ECC logic process for MRAM error correction, based on an embodiment.

[0014] Figure 8 This is a flowchart of a method for correcting MRAM errors using ECC logic processing according to an embodiment.

[0015] Figure 9 This is a block diagram illustrating an example ECC logic process for MRAM error correction, based on an embodiment.

[0016] Figure 10 This is a flowchart of a method for correcting MRAM errors using ECC logic processing according to an embodiment.

[0017] Figure 11 This is a block diagram illustrating an example ECC logic process for MRAM error correction, based on an embodiment.

[0018] Figure 12 This is a flowchart of a method for correcting MRAM errors using ECC logic processing according to an embodiment.

[0019] Figure 13 This is a block diagram illustrating an example ECC logic process for MRAM error correction, based on an embodiment.

[0020] Figure 14 This is a flowchart of a method for correcting MRAM errors using ECC logic processing according to an embodiment.

[0021] Figure 15 This is a block diagram illustrating an example ECC logic process for MRAM error correction, based on an embodiment.

[0022] Figure 16 This is a flowchart of a method for correcting MRAM errors using ECC logic processing according to an embodiment.

[0023] Figure 17 This is a block diagram illustrating an example ECC logic process for MRAM error correction, based on an embodiment.

[0024] Figure 18 This is a flowchart of a method for correcting MRAM errors using ECC logic processing according to an embodiment.

[0025] Figure 19 This is a flowchart of a method for correcting MRAM errors using hierarchical ECC logic processing according to an embodiment. Detailed Implementation

[0026] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. These are merely examples and not intended to be limiting. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. As used herein, forming a first component on a second component means forming a first component in direct contact with the second component. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0027] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0028] Memory devices are used to store information in semiconductor devices and systems. Popular dynamic random access memory (DRAM) cells include switches and capacitors. DRAM does not retain data when power is turned off. Non-volatile memory devices, however, retain data even after power is cut off. Examples of non-volatile memory devices include flash memory, magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), and phase-change random access memory (PRAM). MRAM uses changes in magnetization direction at the tunnel junction to store data. FRAM uses the polarization properties of ferroelectricity to store data. PRAM uses changes in resistance caused by a phase transition in a specific material to store data.

[0029] Memory arrays are typically arranged in a two-dimensional array. A memory array can be itself or embedded in another device, and can also include many memory bit cells. Each memory bit cell can typically store one bit of information. A memory macro may include one or more arrays of bit cells and other logic circuitry, such as drivers, buffers, clock fan-out circuitry, ECC circuitry, and other peripheral circuitry.

[0030] Certain types of memory devices (such as MRAM) have two or more resistance states depending on the magnetization alignment between two or more layers of magnetic material (such as ferromagnetic material). More specifically, MRAM stores data in memory cells having two stacked layers of magnetic material separated by a thin insulating film. The layered structure forms the magnetic tunnel junction (“MTJ” or “MTJ element”) of the MRAM cell. These two layers comprise a magnetic layer permanently magnetized in a fixed magnetic field alignment direction (this layer is called the “fixed layer”) and a magnetic layer with variable magnetization (this layer is called the “free layer”). The free layer can be magnetized in one of two orientations relative to the permanently magnetized layer. These two orientations are characterized by significantly different series resistances through the stacked layers of the MTJ. The magnetic field orientation of the variable layer can be the same as (parallel) or opposite to (antiparallel) the magnetic field orientation of the permanent magnetic layer. The parallel alignment state has relatively low resistance, while the antiparallel alignment state has high resistance.

[0031] Two states of an MRAM cell can be sensed from their relatively high or low resistances (RH and RL), representing different binary logic values ​​of bits stored in the memory. For example, RL (or high cell current) can be designated as logic "1" ("data-1"); RH (or low cell current) can be designated as logic "0" ("data-0"). In some embodiments, a reference voltage can be applied to the MRAM cell, and the resulting cell current can be used to determine whether the cell is in a low-resistance state or a high-resistance state. In some embodiments, a sense amplifier can be used to compare the cell current with a reference current.

[0032] Data errors (such as soft errors that are not permanent or represent physical damage to the device) may be caused by interference, radiation effects, or thermal effects. These errors may be deterministic or stochastic processes. Data error rates that include soft errors may require the use of an error correction code scheme (ECC) built into the MRAM device chip. ECC can be used to detect and correct bit errors stored in memory. ECC encodes data by generating ECC check bits (e.g., redundancy bits or parity bits), which are stored in the memory device along with the data. The data and parity bits together form a codeword. For example, an ECC that generates 8 parity bits for 64-bit data can typically detect two errors and correct one error in the 64-bit data; this is known as SECDED code, Single Error Correction (SEC), and Double Error Detection (DED).

[0033] Additional storage space may be required to store the parity bits used in conjunction with ECC. Therefore, one or more additional memory devices (e.g., one or more additional chips) may be needed to store the parity bits used to provide ECC capability. In some memory arrays, additional columns can be added to the array to store parity bits (also called check bits). Data included in a row of a memory array can be called a word. A codeword refers to a string of data including the word plus the parity bits added in the additional columns. If a codeword includes a word portion with K bits and M parity bits, then the codeword length N will be N = K + M. For example, an ECC memory that can provide 8 bits of parity for each 32-bit data word may include a 40-bit wide interface to access a 40-bit codeword with 32 bits of data. Similarly, an ECC memory that can provide 8 bits of parity for each 64-bit data word may include a 72-bit wide interface to access a 72-bit codeword with 64 bits of data.

[0034] Providing ECC circuitry for each memory array or macro increases the device area requirements. An alternative to minimizing the area requirements of the ECC circuitry is to provide global ECC circuitry shared between memory arrays or macros. However, using shared ECC circuitry for memory arrays or macros increases the energy consumption for moving data into or to the memory arrays and ECC circuitry compared to providing ECC circuitry for each memory array or macro.

[0035] Detecting bit errors in a codeword requires fewer operations than bit error correction, and therefore requires less circuitry to support fewer operations. According to the disclosed embodiments, a first portion of the ECC circuitry is provided locally for each memory macro, while a second portion is implemented as a shared global ECC accessible by all memory macros of the memory device. For example, the error detection aspect of the ECC circuitry can be implemented as a first local ECC or a small set of macros for each MRAM macro. The error correction aspect of the ECC is implemented as a second or global ECC supporting many MRAM macros. In this way, only memory errors detected by the local ECC must be sent to the global ECC for error correction.

[0036] Compared to providing local complete ECC for each memory array or macro, hierarchical ECC structures such as those with local and global ECC implementations can effectively balance device area requirements and power consumption associated with error correction by reducing the area of ​​overhead ECC circuitry, and reduce global data communication energy compared to providing shared global complete ECC. Global data communication energy is reduced by only moving or propagating detected memory errors to the global ECC circuitry for correction, and device area requirements are minimized by providing detection ECC circuitry only for each memory array or macro, while providing error correction circuitry through shared global ECC circuitry.

[0037] Figure 1 This is a block diagram illustrating an example memory device with multiple memory arrays, each memory array having dedicated and simplified ECC circuitry, according to some embodiments of the present invention. Figure 1 In the example shown, the memory device may be an MRAM device 100, but other memory types are also within the scope of this invention. The MRAM device 100 includes multiple memory arrays 102a-n, local ECC circuitry 140a-n coupled to each of the respective memory arrays 102a-n, local I / O circuitry 106a-n coupled to both the respective memory arrays 102a-n and the ECC circuitry 140a-n, a controller 108 coupled to each of the local I / O circuitry 106a-n, a global ECC circuitry 160, and a global I / O circuitry 110. In the illustrated embodiment, memory macros 130a-n may include local memory arrays 102a-n, local ECC circuitry 140a-n, and local I / O circuitry 106a-n.

[0038] According to some embodiments, if the refresh interval is properly designed, most read operations during memory refresh should be relatively error-free. In this case, an ECC scheme can be implemented where simple error detection functions can be performed locally, resulting in shorter local refresh data paths 120 and reduced latency during refresh. ECC circuitry including error correction can then be shared among multiple macros 130a-n, and the longer global refresh data path 122 will be used for such relatively rare events. In such a scheme, the areas required for local ECC circuitry 140a-n with only error detection will each require significantly less area.

[0039] Many schemes have been developed to implement ECC, including Hamming codes and triple modulo redundancy. For example, Hamming codes are a class of binary linear block codes. Depending on the number of parity bits used, other codes can detect at most two bit errors per codeword, or correct one bit error without detecting uncorrected errors. Several schemes have been developed, but generally, if the parity bits are arranged within the codeword such that different incorrect bits produce different error results, the erroneous bits can be identified. For erroneous codewords, the error pattern is called an error corrector, and the erroneous bits are identified. This corrector decoding is an efficient method for decoding linear block codes with errors.

[0040] As described herein, local ECC 140a-n and global ECC 160 can utilize ECC encoders and decoders to leverage ECC encoding and decoding. ECC encoders can include any technique or algorithm that adds redundancy to information to detect or correct errors. For example, error-correcting codes can include non-binary block codes (such as Reed-Solomon [255, 239] or [255, 221] codes), linear block codes (such as Hamming codes and Bose-Chaudhuri Hocquenghem (BCH) codes), cyclic Hamming codes, Hadamard codes (such as Hadamard [16, 5] codes), Golay codes (such as Golay [23, 12] codes, extended Golay [24, 12] codes, or cyclic Golay [24, 12] codes), maximum-length shift register codes, Reed-Muller codes, spare codes, Gappa codes, binary and non-binary convolutional codes, double-K codes, turbo codes, turbo product codes, LDPC codes, concatenated codes formed by enclosing one code within another, etc. By adding more parity bits, the strength of the error correction code can be adjusted as needed. For example, the code strength can be measured by the minimum Hamming distance. The ECC decoder can be coupled to the ECC encoder and used to calculate the corrector of the codeword.

[0041] In some embodiments, and particularly, the ECC decoder may include local ECC 140a-n and perform matrix multiplication on a predefined parity matrix and codeword. The predefined parity matrix can be determined based on the type of ECC employed. For example, the predefined parity matrix may be a 7×3 parity matrix H of (7,4) Hamming code. Therefore, the ECC decoder outputs a 3-bit vector. The ECC decoder is used to check whether the encoded codeword is valid based on the principle of (7,4) Hamming code. When the 3-bit vector (i.e., the corrector) generated by the ECC decoder is equal to (0,0,0), the encoded codeword is determined to be valid. In this case, only the operation to determine codeword validity is required, and local refresh data path 120 is utilized. When the 3-bit vector generated by the ECC decoder is not equal to (0,0,0) in the operation, the encoded codeword is determined to have at least one error. In this case, a more complete ECC including error correction is required, and global refresh data path 122 is utilized.

[0042] Figure 2This is a block diagram illustrating other aspects of an example of an MRAM device 100. In the illustrated embodiment, the local memory array 102a includes a plurality of MRAM bit cells, such as MRAM bit cells 200, arranged in rows and columns. MRAM bit cell 200 includes an access transistor 212 and an MTJ element 214. The MTJ element 214 has a variable resistance depending on the orientation of its free layer and is operatively coupled between the access transistor 212 and a bit line 204. The access transistor 212 is operatively coupled between the bit line 206 and the MTJ element 214 and has a gate coupled to a word line 202. During a read or write operation, a voltage greater than a threshold voltage of the access transistor 212 is applied to the word line 202, thereby “turning on” the access transistor 212 and allowing current to flow from the bit line 206 through the MTJ element 214 to the bit line 204. The current is detected by a sense amplifier (not shown) capable of sensing and comparing the current in the bit lines and outputs a logic high "1" or low "0" corresponding to the state of the free layer in the MTJ element 214, and finally outputs the data ("1" or "0") stored in the MRAM bit cell 200. Access to any bit cell in the plurality of bit cells in the local memory array 102a is performed by applying voltage to the word lines at the correct timing and sensing the current on the corresponding bit lines. Data in the bit cells of the local memory array 102a can be sent, for example, to the local ECC circuitry via bit lines 204 and 206. Data in the bit cells of the local memory array 102a can be sent to and from the local I / O circuitry 106a, for example, via bit lines 204 and 206. Figure 1 The external circuitry of macro 130a shown receives signals.

[0043] Figure 3 This is a block diagram illustrating an example ECC logic process 300 for MRAM error correction according to an embodiment. In the illustrated embodiment, the ECC logic process 300 includes local ECC logic 340 and global ECC logic 360. In some embodiments, the local ECC logic 340 is provided with a memory array or macro, and the global ECC logic 360 is shared among multiple memory arrays or macros. For example, refer to... Figure 1 Local ECC logic 340 may correspond to local ECC circuit 140a that provides local memory array 102a in local memory macro 130a, and global ECC logic may correspond to global ECC circuit 160, which is shared among multiple memory macros 130a-n.

[0044] Local ECC logic 340 includes a corrector s1 generator 342, a corrector s3 generator 344, and an error checking circuit 346. MRAM bit cells 200 in memory arrays 102a-n store data and parity bits for error detection and correction. In the illustrated example, ECC logic processing 300 operates on codewords read from local memory array 102a, for example, reading N-bit data from MRAM macro 130a. In some embodiments, only correctors s1 and s3 are needed to determine whether the read data has errors, thus requiring only partial decoding of the read data. Correctors s1 and s3 can be single digital elements, or they can each be a vector of multiple digital elements, or they can be a matrix of multiple digital elements. The corrector s1 generator 342 performs matrix multiplication on the read data using a predefined parity matrix to obtain the corrector s1, and similarly, the corrector s3 generator 344 performs matrix multiplication on the predefined parity matrix to obtain the corrector s3. The error checking circuit 346 is configured to evaluate the correctors s1 and s3 and determine whether the read data (e.g., codewords) contains at least one error.

[0045] If the error checking circuit 346 determines that the read data contains at least one error, the global ECC logic 360 needs to fully decode the read data. The global ECC logic 360 includes an x^3 (x cubed) calculation circuit 351, an encoder (EN) calculation circuit 352, a parity bit generator 353, an XOR calculation circuit 354, an inverse calculation circuit 355, a finite field multi-computation circuit 356 such as a Galois field (GF), and an error correction circuit 362. In some embodiments, the EN calculation circuit 352 operates on the read data and outputs a single bit that encodes whether the codeword needs to be written back to the local memory array 102a after correction. For example, the EN calculation circuit 352 could be an encoder level of a BCH cyclic error correction code. In some embodiments, the EN calculation circuit 352 adds a parity bit, allowing the global ECC logic 360 to have additional error detection beyond correction, such as single error correction double error detection (SECDED), double error correction triple error detection (DECTED), etc. Figure 3In the illustrated embodiment, correctors s1 and s3 are computed in local ECC logic 340 and sent and used by global ECC logic 360. Specifically, x^3 calculation circuit 351 operates on corrector s1 to obtain s1^3, XOR calculation circuit 354 operates on corrector s3 and obtains s1^3 from cubic calculation circuit 351 to compare s3 and s1^3 and output a vector according to the XOR truth table. Inverse calculation circuit 355 operates on corrector s1 and outputs the inverse of corrector s1, and GF multi-computation circuit 356 operates on the outputs of inverse calculation circuit 355 and XOR calculation circuit 354. In some embodiments, GF multi-computation circuit 356 may be a decoder level of a BCH cyclic error-corrected code, including error detection and error correction. In some embodiments, GF multi-computation circuit 356 operates on the codeword through multiplication and accumulation in the Galois field of each data bit, where the data bits are treated as coefficients of a polynomial. The output of the GF multi-computation circuit 356, along with the read data and the corrector s1, is input to the error correction circuit 362. The output of the error correction circuit 362 is the error-corrected codeword. Then, the parity bit generator 353 operates on the corrected word (e.g., data without parity bits) to encode the parity bits according to a predetermined parity matrix of the selected ECC type or scheme, forming the corrected codeword to be written to the local memory array 102a.

[0046] Figure 4 Is using Figure 3 The flowchart illustrates a method 400 for correcting MRAM errors using ECC logic processing 300. Method 400 begins at step 402, where correctors s1 and s3 are calculated from read data as part of a memory refresh operation of the memory array. For example, a codeword is read from one of a plurality of macros 130a-n comprising local memory arrays 102a-n, and correctors s1 and s3 are calculated by performing matrix multiplication on the read data using a predefined parity check matrix within local ECC circuits 140a-n associated with local memory arrays 102a-n from which read data is generated during a refresh cycle. In some embodiments, methods such as... Figure 3The s1 corrector generator 342 and s3 corrector generator 344 within the local ECC logic 340 shown perform the calculation of correctors s1 and s3. In step 404, correctors s1 and s3 are evaluated to determine if the codeword has at least one error, for example, using error checking 346 within the local ECC logic 340. If no error is found, method 400 ends for that codeword, and step 402 begins for the next codeword in the refresh cycle of the local memory arrays 102a-n. If at least one error is found, method 400 proceeds to step 406, where the read data and correctors s1 and s3 are input to a global ECC circuit 160 (such as global ECC logic 360) associated with multiple local macros, including local macros that have been determined to have at least one error in the currently generated read data. For example, by using EN calculation circuit 352, it is determined from the read data whether the codeword needs to be written back to the local memory arrays 102a-n after correction. For example, EN calculation circuit 352 could be an encoder level for BCH cyclic error correction codes. In some embodiments, the EN calculation circuit 352 adds a parity check bit, enabling the global ECC logic 360 to have additional error detection capabilities beyond correction, such as single error correction double error detection (SECDED), double error correction triple error detection (DECTED), etc. In step 408, s1^3 is calculated by the x^3 calculation circuit 351 within the global ECC logic 360. In step 410, the XOR of the inputs s1^3 and s3 is calculated, for example, by the XOR calculation circuit 354 within the global ECC logic 360, and the inverse of s1 is calculated, for example, by the inverse calculation circuit 355 within the global ECC logic 360. In step 412, the GF multi is calculated, for example, by the GF multi calculation circuit 356, using the output from the inverse s1 and the XOR calculation. In some embodiments, the GF multi calculation circuit 356 can be a decoder level for a BCH cyclic error-corrected code, including error detection and error correction. In some embodiments, the GF multi calculation circuit 356 operates on the codeword through multiplication and accumulation in the Galois field of each data bit, where the data bits are treated as coefficients of a polynomial. In step 414, the output of the readout data and the calculation of GF multi and the corrector s1 is used to calculate the corrected codeword, such as by the error correction circuit 362 within the global ECC logic 360. In step 416, for example, the corrected word (corrected data) is extracted from the corrected codeword, and a parity bit generator (e.g., parity bit generator 353 within the global ECC logic 360) encodes the corrected data with parity bits using a predefined parity matrix according to the selected ECC type or scheme. The corrected and encoded codeword is then written back to the local macros 130a-n.

[0047] Figure 5This is a block diagram illustrating an example ECC logic process 500 for MRAM error correction, according to an embodiment. In the ECC logic process 500, with... Figure 3 Compared to the ECC logic processing 300, the parity bit generator 353 is no longer included in the global ECC logic 360, but is included in the local ECC logic 340. This difference from the ECC logic processing 300 offloads the operation of encoding the parity bit to the corrected data and writes the resulting corrected codeword to the local memory array 102a to the local ECC logic 340 associated with the local memory array 102a, so that the global ECC logic 360 is no longer responsible for encoding the parity bit and writing the corrected codeword back to the local memory arrays 102a-n that share the multiple macros of the global ECC logic 360.

[0048] Figure 6 This is a flowchart of method 600 for correcting MRAM errors using ECC logic processing 500. Method 600 is similar to method 400 above, except that in step 616, the same operations included in step 416 are performed within a local ECC instead of a global ECC, offloading the work to the local ECC logic circuitry, as described above. Figure 5 Specifically, step 616 includes extracting the corrected word, such as the corrected data, from the corrected codeword, encoding the corrected data with parity bits using a predefined parity check matrix according to the selected ECC type or scheme, and writing the corrected and encoded codeword back to the local macro associated with the local ECC logic circuitry.

[0049] Figure 7This is a block diagram illustrating an example ECC logic process 700 for MRAM error correction according to an embodiment. ECC logic process 700 is similar to ECC logic process 500 above, with two differences. The first difference is that the corrector s1 generator 342 and the corrector s3 generator 344 are replicated within the global ECC logic 360. Replicating the corrector s1 generator 342 and the corrector s3 generator 344 within the global ECC logic 360 reduces the number of connections required throughout the hierarchical ECC scheme and also simplifies the layout structure. For example, ECC logic processes 300 and 500 require each local ECC circuit 140a-n and local I / O circuit 106a-n to support readout data and the transmission of correctors s1 and s3, and require the global ECC circuit 160 to support receiving correctors s1 and s3 as well as readout data. Conversely, the ECC logic processing 700 requires only local ECC circuits 140a-n and local I / O circuits to support the transmission of read data, and only global ECC circuit 160 to support the reception of read data. Thus, in some embodiments, the ECC logic processing 700 can be used to eliminate the connection required to transmit checksums s1 and s3 between local I / O circuits 106a-n and global ECC circuit 160, which simplifies the layout of the MRAM device 100.

[0050] The second difference is that the error detection circuit 357 is included within the global ECC logic 360. Similar to the error checking circuit 346, the error detection circuit 357 is configured to determine whether the read data (e.g., codeword) contains at least one error, but does so within the global ECC logic 360. The error detection circuit 357 receives the output of the EN calculation circuit 351, s1, s3, and s1^3 as inputs, and outputs whether the read data contains at least one error. The error detection circuit 357 can output whether at least one error exists in the read data, or whether at least two errors exist in the read data, or whether at least three or more errors exist in the read data.

[0051] Figure 8 This is a flowchart of method 800 for correcting MRAM errors using ECC logic processing 700. Method 800 is similar to method 600 above, with two differences. First, step 406 is replaced by step 806, where s1 and s3 are calculated within global ECC circuit 160 (e.g., global ECC logic 360), instead of from the same operational inputs included in step 406 of methods 400 and 600. Second, in step 809 between steps 408 and 410, the presence and number of errors in the read data are calculated within global ECC circuit 160 (e.g., error detection circuit 357).

[0052] Figure 9This is a block diagram illustrating an example ECC logic process 900 for MRAM error correction according to an embodiment. The ECC logic process 900 is similar to the ECC logic process 700 above, with four differences. First, the corrector s1 generator 342 and the corrector s3 generator are no longer replicated within the global ECC logic 360. Second, the cubic calculation circuit 351, the EN calculation circuit 352, and the error detection circuit 357 are included in the local ECC logic 340, and are no longer included in the global ECC logic 360. Including the cubic calculation circuit 351, the EN calculation circuit 352, and the error detection circuit 357 in the local ECC logic 340 increases the computational utility and power consumption of the local ECC logic 340. For an MRAM device 100 experiencing a relatively high data error rate, the energy consumption burden of moving data and the data latency due to offloading error detection and correction operations from the shared global ECC circuit 160 can outweigh the area savings from removing the circuitry performing those operations in the local memory macros 130a-n. In this context, the efficiency of the MRAM device 100 can be improved by increasing the operations performed locally and by adjusting the balance between the region associated with error checking, energy consumption, and data latency. For example, the local ECC logic 340 of the ECC logic processing 900 can also include error detection, for example, through error detection circuit 357, by including EN calculation and corrector s1 cubic calculation, and thus the number of errors can be detected more accurately, including detecting whether errors exist in the codeword and the number of errors within the codeword and word.

[0053] The third difference is that the error checking circuit 351 is omitted. The fourth difference is that the parity bit generator 353 is again included in the global ECC logic 360 instead of the local ECC logic 340, similar to the ECC logic processing 300.

[0054] Figure 10This is a flowchart of method 1000 for correcting MRAM errors using ECC logic processing 900. Method 1000 is similar to method 800 above, with four differences. First, step 1003 is included after step 402, where s1^3 and EN are calculated by x^3 calculation circuit 351 and EN calculation circuit 352 within local ECC logic 340, respectively. Second, step 404 is replaced by step 1004, where the presence of errors in the read data and the number of errors in the read data are calculated by error detection circuit 357 within local ECC logic 340, based on s1, s3, s1^3, and EN. If there are no errors, method 1000 ends for that codeword and begins at step 402 of method 1000 for the next codeword in the refresh cycle of local memory array 102a. Third, if at least one error exists, method 1000 proceeds to step 1006, where the read data, correctors s1 and s3, s1^3, and the number of detected errors are input into global ECC logic 360. Fourth, Method 1000 replaces step 616 of Method 800 with step 416 of Method 400. That is, in step 416 of Method 1000, the corrected word, such as the corrected data, is extracted from the corrected codeword, and the parity bit generator 353 in the global ECC logic 360 encodes the corrected data with parity bits using a predefined parity check matrix according to the selected ECC type or scheme, and writes the corrected and encoded codeword back to the local macros 130a-n.

[0055] Figure 11 This is a block diagram illustrating an example ECC logic process 1100 for MRAM error correction, based on an embodiment. ECC logic process 1100 is similar to ECC logic process 900 above, except that the check bit generator 353 is no longer included in the global ECC logic 360, but rather in the local ECC logic 340. As described above... Figure 5 As described in the ECC logic processing 500, the difference offloads the operation of encoding parity bits to the corrected data and writes the resulting corrected codeword to the local memory array 102a to the local ECC logic 360 associated with the local memory array 102a, so that the global ECC logic is no longer responsible for encoding parity and writing the corrected codeword to the multiple memory macros 130a-n that share the global ECC logic 360.

[0056] Figure 12This is a flowchart of method 1200 for correcting MRAM errors using ECC logic processing 1100. Method 1200 is similar to method 1000 above, except that step 416 is replaced by step 616, such that the corrected word, such as the corrected data, is extracted from the corrected codeword, and the corrected data with parity bits is encoded using a predefined parity matrix according to the selected ECC type or scheme. The corrected and encoded codeword is then written back to the local memory array 102 associated with the local ECC logic 340, for example, using methods 600 and 800, instead of within the global ECC logic 360.

[0057] Figure 13 This is a block diagram illustrating an example ECC logic process 1300 for MRAM error correction, based on an embodiment. The ECC logic process 1300 is similar to the ECC logic process 1100 above, except that the corrector s1 generator 342, the corrector s3 generator 344, and the cube calculation circuit 351 are replicated within the global ECC logic 360. (As per the above...) Figure 7 The aforementioned method of replicating the corrector s1 generator 342, the corrector s3 generator 344, and the cubic calculation circuit 351 within the global ECC logic 360 can reduce the number of connections required within the entire hierarchical ECC scheme and also simplify the layout structure.

[0058] Figure 14 This is a flowchart of method 1400 for correcting MRAM errors using ECC logic processing 1300. Method 1400 is similar to method 1200 above, except that step 1406 replaces step 1006. In other words, the correctors s1 and s3, as well as s1^3, are calculated in global ECC logic 360, with copies of those quantities calculated within local ECC logic 340. This replaces the input of these quantities from local ECC logic 340 into global ECC logic 360, as done in step 1006 of method 1200. Thus, step 1406 of method 1400 includes inputting the read data and the number of errors detected from step 1004 into global ECC logic 360, and copying the calculations of s1, s3, and s1^3 within global ECC logic 360. This is similar to... Figure 7 ECC processing 700 associated Figure 8 The copying that occurs in method 800 shown.

[0059] Figure 15This is a block diagram illustrating an example ECC logic process 1500 for MRAM error correction, based on an embodiment. ECC logic process 1500 is similar to ECC logic process 900 above, except that the XOR circuit 354, inverse computation circuit 355, and GF multi-computation circuit 356 are included in local ECC logic 340 and are no longer included in the intrinsic global ECC logic 360. Including the XOR circuit 354, inverse computation circuit 355, and GF multi-computation circuit 356 in the local ECC logic 340 increases the computational utility and power of the local ECC logic. As described above, combining ECC process 900 and... Figure 9 The efficiency of the MRAM device 100 can be improved by increasing the number of locally executed operations as the data error rate increases, and by adjusting the balance between the area, energy consumption, and data latency associated with error checking. For example, this can be achieved by locally implementing more error checking circuitry within the local ECC circuitry 140a-n to reduce data latency and energy consumption associated with moving data to the shared global ECC circuitry 160. For instance, in ECC logic processing 1500, the local ECC logic 340 performs all ECC operations locally, except for error correction and encoding, and writing error-corrected data back to the local macro.

[0060] Figure 16 This is a flowchart of method 1600 for correcting MRAM errors using ECC logic processing 1500. Method 1600 is similar to method 1000 above, with five differences. First, method 1600 replaces step 1004 of method 1000 with step 1604. Step 1604 of method 1600 performs the same operation as step 1004 of method 1000, that is, based on the calculation of s1, s3, s1^3, and EN, it calculates within the local ECC logic 340 whether an error exists in the read data and the number of errors. The only difference is that if an error does exist in the read data, step 1604 proceeds to step 1610 of method 1600 instead of step 1006. This is due to the additional circuitry included within the local ECC logic 340 of ECC logic processing 1500. Second, step 1006 is not performed in method 1600, but as a third difference from method 1000, step 1610 is performed from step 1604 in method 1600. In step 1610, the XOR of s1^3 and s3 is calculated, for example, by XOR calculation circuit 354, and the inverse s1 is calculated, for example, by inverse calculation circuit 355 within local ECC logic 340. Fourth, in step 1612, GF multi is calculated within local ECC logic 340. Fifth, in step 1613, the read data, the number of detected errors, s1, and the GF multi calculation results are input into global ECC logic 360 and used to calculate the corrected codeword in step 414 of method 1600.

[0061] Figure 17 This is a block diagram illustrating an example ECC logic process 1700 for MRAM error correction, based on an embodiment. ECC logic process 1700 is similar to ECC logic process 1500 above, except that the check bit generator 353 is no longer included in the global ECC logic 360, but rather in the local ECC logic 340. As described above... Figure 5 and Figure 11 The difference described above in the ECC logic processing 1700 offloads the operation of encoding parity bits to the correction data and writes the resulting corrected codeword to the local memory array 102a to the local ECC logic 340 associated with the local memory array 102a, so that the global ECC logic 360 is no longer responsible for encoding parity and writing the corrected codeword to the multiple memory macros 130a-n that share the global ECC logic 360.

[0062] Figure 18 This is a flowchart of method 1800 for correcting MRAM errors using ECC logic processing 1700. Method 1800 is similar to method 1600 above, except that step 416 is replaced by step 616, such that the corrected word, for example, the corrected data, is extracted from the corrected codeword, and the corrected data with parity bits is encoded using a predefined parity matrix according to the selected ECC type or scheme. The corrected and encoded codeword is then written back to the local memory macro 130 associated with the local ECC logic 340. The local ECC logic 340 is executed within the local ECC logic 340, such as using methods 600, 800, 1200, and 1400, instead of within the global ECC logic 360.

[0063] Figure 19This is a flowchart of a method 1900 for correcting MRAM errors using hierarchical ECC logic processing according to some embodiments. Method 1900 begins at step 1902, where each of a plurality of memory macros (e.g., MRAM memory macros 130a-n) is provided, including at least an array of memory cells and local ECC logic circuitry. In some embodiments, the plurality of memory macros include local memory arrays 102a-n, each local memory array 102a-n including local ECC logic 140a-n. In step 1904, global ECC logic circuitry is provided, located away from the plurality of MRAM macros and coupled to each of the plurality of MRAM macros. In some embodiments, the global ECC logic circuitry includes global ECC logic 160. In step 1906, data from the local MRAM macros is examined, for example, as part of a refresh cycle, wherein portions of the local MRAM memory are examined during the refresh cycle, for example, for errors in read data or codewords in the local ECC logic circuitry. If no error is found in a particular codeword, the next codeword in the macro is examined, as part of a refresh cycle. Method 1900 then proceeds to step 1908, wherein if at least one error is found in the local macro memory array, the data with at least one error (e.g., a codeword with at least one error) is checked and found to be sent to the global ECC logic along with the output of the computation circuit within the local ECC logic circuit. In step 1910, the data with at least one error is corrected within the global ECC logic circuit, and in step 1912, the corrected data is written back to the local macro memory array.

[0064] Therefore, the disclosed examples provide error detection and correction for memory devices, more specifically, for short-retention memory devices such as MRAM that require periodic refresh. By using a hierarchical ECC approach, where some ECC functions are provided locally to memory macros and others globally, macro-area reduction and power reduction of MRAM devices can be achieved with sufficiently low error rates. Some disclosed embodiments include memory devices, such as MRAM memory devices, having multiple memory macros, each memory macro including an array of memory cells and a first ECC circuit. The first ECC circuit is configured to detect data errors in the corresponding memory macro. A second ECC circuit is located remotely from the multiple memory macros and communicatively coupled to each of the multiple memory macros. The second ECC circuit is configured to receive detected data errors from the first ECC circuit of the multiple memory macros and correct the data errors.

[0065] In the aforementioned memory devices, each memory macro includes a magnetic random access memory (MRAM) macro.

[0066] In the aforementioned memory device, each memory macro includes a magnetic random access memory (MRAM) macro, wherein each of the MRAM macros further includes: an array of MRAM bit cells, each MRAM bit cell including: a magnetic tunnel junction element; an access transistor coupled to the magnetic tunnel junction element; a first bit line coupled to the access transistor; a second bit line coupled to the magnetic tunnel junction element; a word line coupled to the gate of the access transistor; and local input / output circuitry coupled to the first bit line and the second bit line of the MRAM bit cell.

[0067] In the aforementioned memory device, each memory macro includes a magnetic random access memory (MRAM) macro, wherein each of the MRAM macros further includes: an array of MRAM bit cells, each MRAM bit cell including: a magnetic tunnel junction element; an access transistor coupled to the magnetic tunnel junction element; a first bit line coupled to the access transistor; a second bit line coupled to the magnetic tunnel junction element; a word line coupled to the gate of the access transistor; and local input / output circuitry coupled to the first bit line and the second bit line of the MRAM bit cell, wherein the first error correction code circuitry includes: a first corrector s1 generator coupled to the first bit line and the second bit line; a second corrector s3 generator coupled to the first bit line and the second bit line; and an error checking circuitry coupled to the output of each of the first corrector s1 generator and the second corrector s3 generator.

[0068] In the aforementioned memory device, each memory macro includes a magnetic random access memory (MRAM) macro, wherein each of the MRAM macros further includes: an array of MRAM bit cells, each MRAM bit cell including: a magnetic tunnel junction element; an access transistor coupled to the magnetic tunnel junction element; a first bit line coupled to the access transistor; a second bit line coupled to the magnetic tunnel junction element; a word line coupled to the gate of the access transistor; and a local input / output circuit coupled to the first bit line and the second bit line of the MRAM bit cell, wherein the first error correction code circuit includes: a first corrector s1 generator coupled to the first bit line and the second bit line; a second corrector s3 generator coupled to the first bit line and the second bit line; and an error checking circuit coupled to... The output of each of the first corrector s1 generator and the second corrector s3 generator is provided, wherein the second error correction code circuit includes: an encoder calculation circuit coupled to the local input / output circuit; a corrector s1^3 calculation circuit coupled to the output of the first corrector s1 generator; a corrector s1 inverse circuit coupled to the output of the first corrector s1 generator; a corrector comparator coupled to the outputs of the corrector s1^3 generator and the second corrector s3 generator; a Galois domain multi-computation circuit coupled to the outputs of the corrector comparator and the corrector s1 inverse circuit; an error correction circuit coupled to the local input / output circuit, the corrector s1 generator, and the Galois domain multi-computation circuit; and a parity bit generator circuit for correcting the magnetic random access memory bit cells with errors.

[0069] In the aforementioned memory device, each memory macro includes a magnetic random access memory (MRAM) macro, wherein each of the MRAM macros further includes: an array of MRAM bit cells, each MRAM bit cell including: a magnetic tunnel junction element; an access transistor coupled to the magnetic tunnel junction element; a first bit line coupled to the access transistor; a second bit line coupled to the magnetic tunnel junction element; a word line coupled to the gate of the access transistor; and a local input / output circuit coupled to the first bit line of the MRAM bit cell. The first error correction code circuit includes: a first corrector s1 generator coupled to the first bit line and the second bit line; a second corrector s3 generator coupled to the first bit line and the second bit line; an encoder calculation circuit coupled to the local input / output circuit; a corrector s1^3 calculation circuit coupled to the output of the first corrector s1 generator; and an error checking circuit coupled to the output of each of the first corrector s1 generator, the second corrector s3 generator, the encoder calculation circuit, and the corrector s1^3 calculation circuit.

[0070] In the aforementioned memory device, each memory macro includes a magnetic random access memory (MRAM) macro, wherein each of the MRAM macros further includes: an array of MRAM bit cells, each MRAM bit cell including: a magnetic tunnel junction element; an access transistor coupled to the magnetic tunnel junction element; a first bit line coupled to the access transistor; a second bit line coupled to the magnetic tunnel junction element; a word line coupled to the gate of the access transistor; and a local input / output circuit coupled to the first bit line and the second bit line of the MRAM bit cell, wherein the first error correction code circuit includes: a first corrector s1 generator coupled to the first bit line and the second bit line; a second corrector s3 generator coupled to the first bit line and the second bit line; an encoder calculation circuit coupled to the local input / output circuit; and a correction... A positron s1^3 calculation circuit is coupled to the output of the first positron s1 generator; an error checking circuit is coupled to the output of each of the first positron s1 generator, the second positron s3 generator, the encoder calculation circuit, and the positron s1^3 calculation circuit, wherein the second error correction code circuit includes: the positron s1 inverse circuit, coupled to the output of the first positron s1 generator; a positron comparator, coupled to the outputs of the positron s1^3 generator and the second positron s3 generator; a Galois domain multi-computation circuit, coupled to the outputs of the positron comparator and the positron s1 inverse circuit; an error correction circuit, coupled to the local input-output circuit, the positron s1 generator, and the Galois domain multi-computation circuit; and a parity bit generator circuit for correcting the magnetic random access memory bit cells with errors.

[0071] In the aforementioned memory device, each memory macro includes a magnetic random access memory (MRAM) macro, wherein each of the MRAM macros further includes: an array of MRAM bit cells, each MRAM bit cell including: a magnetic tunnel junction element; an access transistor coupled to the magnetic tunnel junction element; a first bit line coupled to the access transistor; a second bit line coupled to the magnetic tunnel junction element; a word line coupled to the gate of the access transistor; and a local input / output circuit coupled to the first bit line and the second bit line of the MRAM bit cell, wherein the first error correction code circuit includes: a first corrector S1 generator coupled to the first bit line and the second bit line; a second corrector S1 generator coupled to the first bit line and the second bit line; and a second corrector S1 generator coupled to the first bit line and the second bit line. A positive s3 generator coupled to the first bit line and the second bit line; an encoder calculation circuit coupled to the local input / output circuit; a corrector s1^3 calculation circuit coupled to the output of the first corrector s1 generator; an error checking circuit coupled to the output of each of the first corrector s1 generator, the second corrector s3 generator, the encoder calculation circuit, and the corrector s1^3 calculation circuit; a corrector s1 inverse circuit coupled to the output of the first corrector s1 generator; a corrector comparator coupled to the output of the corrector s1^3 generator and the output of the second corrector s3 generator; and a Galois domain multi-computation circuit coupled to the output of the corrector comparator and the output of the corrector s1 inverse circuit.

[0072] In the aforementioned memory device, each memory macro includes a magnetic random access memory (MRAM) macro, wherein each of the MRAM macros further includes: an array of MRAM bit cells, each MRAM bit cell including: a magnetic tunnel junction element; an access transistor coupled to the magnetic tunnel junction element; a first bit line coupled to the access transistor; a second bit line coupled to the magnetic tunnel junction element; a word line coupled to the gate of the access transistor; and a local input / output circuit coupled to the first bit line and the second bit line of the MRAM bit cell, wherein the first error correction code circuit includes: a first corrector S1 generator coupled to the first bit line and the second bit line; a second corrector S3 generator coupled to the first bit line and the second bit line; and an encoder calculation circuit coupled to the local input / output circuit. The second error correction code circuit comprises: a calibrator s1^3 calculation circuit coupled to the output of the first calibrator s1 generator; an error checking circuit coupled to the outputs of each of the first calibrator s1 generator, the second calibrator s3 generator, the encoder calculation circuit, and the calibrator s1^3 calculation circuit; a calibrator s1 inverse circuit coupled to the output of the first calibrator s1 generator; a calibrator comparator coupled to the outputs of the calibrator s1^3 generator and the second calibrator s3 generator; and a Galois domain multi-computation circuit coupled to the outputs of the calibrator comparator and the calibrator s1 inverse circuit, wherein the second error correction code circuit includes: an error correction circuit coupled to the local input / output circuit, the calibrator s1 generator, and the Galois domain multi-computation circuit; and a parity bit generator circuit for correcting the magnetic random access memory bit cells with errors.

[0073] According to other aspects, the ECC system includes a plurality of first ECC circuits. Each of the plurality of first ECC circuits is configured to be communicatively coupled to a corresponding memory array and configured to detect data errors in the corresponding memory array. A second ECC circuit is communicatively coupled to each of the plurality of first ECC circuits and configured to receive and correct the detected data errors from the plurality of first ECC circuits.

[0074] In the aforementioned ECC system, each of the plurality of first error correction code circuits includes: a first corrector s1 generator coupled to the first bit line and the second bit line; a second corrector s3 generator coupled to the first bit line and the second bit line; and an error checking circuit coupled to the output of each of the first corrector s1 generator and the second corrector s3 generator; and the second error correction code circuit includes: an encoder calculation circuit coupled to the local input / output circuit; a corrector s1^3 calculation circuit coupled to the output of the first corrector s1 generator; a corrector s1 inverse circuit coupled to the output of the first corrector s1 generator; a corrector comparator coupled to the output of the corrector s1^3 generator and the output of the second corrector s3 generator; a Galois domain multi-computation circuit coupled to the output of the corrector comparator and the output of the corrector s1 inverse circuit; an error correction circuit coupled to the local input / output circuit, the corrector s1 generator, and the Galois domain multi-computation circuit; and a check bit generator circuit for correcting memory cells with errors.

[0075] In the aforementioned ECC system, each of the plurality of first error correction code circuits includes: a first corrector s1 generator coupled to the first bit line and the second bit line; a second corrector s3 generator coupled to the first bit line and the second bit line; an encoder calculation circuit coupled to the local input / output circuit; a corrector s1^3 calculation circuit coupled to the output of the first corrector s1 generator; and an error checking circuit coupled to the output of each of the first corrector s1 generator, the second corrector s3, the encoder calculation circuit, and the corrector s1^3 calculation circuit; the second error correction code circuit includes: a corrector s1 inverse circuit coupled to the output of the first corrector s1 generator; a corrector comparator coupled to the output of the corrector s1^3 generator and the output of the second corrector s3 generator; a Galois domain multiplication calculation circuit coupled to the output of the corrector comparator and the output of the corrector s1 inverse circuit; an error correction circuit coupled to the local input / output circuit, the corrector s1 generator, and the Galois domain multiplication calculation circuit; and a check bit generator circuit for correcting memory cells with errors.

[0076] In the aforementioned ECC system, each of the plurality of first error correction code circuits includes: a first corrector s1 generator coupled to the first bit line and the second bit line; a second corrector s3 generator coupled to the first bit line and the second bit line; an encoder calculation circuit coupled to the local input / output circuit; a corrector s1^3 calculation circuit coupled to the output of the first corrector s1 generator; an error checking circuit coupled to the output of each of the first corrector s1 generator, the second corrector s3, the encoder calculation circuit, and the corrector s1^3 calculation circuit; a corrector s1 inverse circuit coupled to the output of the first corrector s1 generator; a corrector comparator coupled to the output of the corrector s1^3 generator and the output of the second corrector s3 generator; and a Galois domain multi-computation circuit coupled to the output of the corrector comparator and the output of the corrector s1 inverse circuit; the second error correction code circuit includes: an error correction circuit coupled to the local input / output circuit, the corrector s1 generator, and the Galois domain multi-computation circuit; and a check bit generator circuit for correcting memory cells with errors.

[0077] According to another aspect, a method includes providing a plurality of memory macros, each memory macro including an array of memory cells and a first ECC circuit. The method further includes providing a second ECC circuit that is remote from and communicatively coupled to each of the plurality of memory macros, and refreshing the memory array includes using the first ECC circuit to check for data errors in the memory array. If the first ECC circuit identifies a data error, the method further includes sending the detected data error to the second ECC circuit, correcting the data error via the second ECC circuit, and writing the corrected data into the memory array.

[0078] In the above method, the process of checking for data errors in the memory array using the first error correction code circuit includes: generating a corrector s1 based on data received from the memory array; generating a corrector s3 based on data received from the memory array; and performing error checking based on the corrector s1 and the corrector s3.

[0079] In the above method, checking for data errors in the memory array using the first error correction code circuit includes: generating a corrector s1 based on data received from the memory array; generating a corrector s3 based on data received from the memory array; and performing error checking based on the corrector s1 and the corrector s3. Correcting the data errors using the second error correction code circuit includes: generating an encoder based on data received from the memory array; generating a corrector s1^3 based on the corrector s1; generating a corrector s1 inverse based on the corrector s1; comparing the corrector s1^3 and the corrector s3; generating Galois domain multi-computation based on the corrector s1 inverse and the comparison of the corrector s1^3 and the corrector s3; generating a parity bit error correction based on the encoder, the corrector s1, and the Galois domain multi-computation; and writing the parity bit error correction into the memory array to correct the error.

[0080] In the above method, checking the data errors in the memory array using the first error correction code circuit includes: generating a corrector s1 based on data received from the memory array; generating a corrector s3 based on data received from the memory array; generating an encoder based on data received from the memory array; generating a corrector s^3 based on the corrector s1; and error checking based on the corrector s1, the corrector s3, the encoder, and the corrector s1^3.

[0081] In the above method, checking the data errors in the memory array using the first error correction code circuit includes: generating a corrector s1 based on data received from the memory array; generating a corrector s3 based on data received from the memory array; generating an encoder based on data received from the memory array; generating a corrector s^3 based on the corrector s1; and performing error checking based on the corrector s1, the corrector s3, the encoder, and the corrector s1^3. Correcting the data errors using the second error correction code circuit includes: generating a corrector s1 inverse based on the corrector s1; comparing the corrector s1^3 and the corrector s3; generating Galois domain multi-computation based on the corrector s1 inverse and the comparison of the corrector s1^3 and the corrector s3; generating a parity bit error correction based on the encoder, the corrector s1, and the Galois domain multi-computation; and writing the parity bit error correction into the memory array to correct the error.

[0082] In the above method, checking the data errors in the memory array using the first error correction code circuit includes: generating a corrector s1 based on data received from the memory array; generating a corrector s3 based on data received from the memory array; generating an encoder based on data received from the memory array; generating a corrector s1^3 based on the corrector s1; performing error checking based on the corrector s1, the corrector s3, the encoder, and the corrector s1^3; generating a corrector s1 inverse based on the corrector s1; comparing the corrector s1^3 and the corrector s3; and generating Galois domain multicomputation based on the corrector s1 inverse and the comparison between the corrector s1^3 and the corrector s3.

[0083] In the above method, checking the data errors in the memory array using the first error correction code circuit includes: generating a corrector s1 based on data received from the memory array; generating a corrector s3 based on data received from the memory array; generating an encoder based on data received from the memory array; generating a corrector s1^3 based on the corrector s1; performing error checking based on the corrector s1, the corrector s3, the encoder, and the corrector s1^3; generating a corrector s1 inverse based on the corrector s1; comparing the corrector s1^3 and the corrector s3; and generating Galois domain multicomputation based on the corrector s1 inverse and the comparison of the corrector s1^3 and the corrector s3. Correcting the data errors using the second error correction code circuit includes: generating a parity bit error correction based on the encoder, the corrector s1, and the Galois domain multicomputation; and writing the parity bit error correction into the memory array to correct the error.

[0084] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a base to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A memory device, comprising: Multiple memory macros, each memory macro including an array of memory cells and a first error correction code circuit, the first error correction code circuit being configured to detect data errors in the corresponding memory macro; A second error correction code circuit, located remotely from and communicatively coupled to each of the plurality of memory macros, is configured to receive detected data errors from the first error correction code circuit of each of the plurality of memory macros and write corrected data to the memory array. Each memory macro includes a magnetic random access memory macro, and each of the magnetic random access memory macros further includes: An array of magnetic random access memory bit cells, each of the magnetic random access memory bit cells comprising: Magnetic tunnel junction element; Access transistors are coupled to the magnetic tunnel junction element; The first line is coupled to the access transistor; The second bit line is coupled to the magnetic tunnel junction element; Word lines, coupled to the gate of the access transistor; and Local input / output circuitry, coupled to the first bit line and the second bit line of the magnetic random access memory bit cell. The first error correction code circuit includes: A first corrector s1 generator is coupled to the first bit line and the second bit line; The second corrector S3 generator is coupled to the first bit line and the second bit line; An error checking circuit is coupled to the output of each of the first corrector s1 generator and the second corrector s3 generator; The second error correction code circuit includes: The encoder calculation circuit is coupled to the local input / output circuit. The cubic calculation circuit of the corrector s1 is coupled to the output of the first corrector s1 generator; The inverse circuit of the calibrator s1 is coupled to the output of the first calibrator s1 generator; The comparator is coupled to the output of the cubic calculation circuit of the comparator s1 and the output of the generator of the second comparator s3; A Galois domain multi-computation circuit is coupled to the output of the comparator and the output of the inverse circuit of the comparator s1; Error correction circuitry, coupled to the local input / output circuitry, the first corrector s1 generator, and the Galois domain multicomputation circuitry; and A check bit generator circuit is used to correct the magnetic random access memory bit cells that have errors.

2. A memory device, comprising: Multiple memory macros, each memory macro including an array of memory cells and a first error correction code circuit, the first error correction code circuit being configured to detect data errors in the corresponding memory macro; A second error correction code circuit, located remotely from and communicatively coupled to each of the plurality of memory macros, is configured to receive detected data errors from the first error correction code circuit of each of the plurality of memory macros and write corrected data to the memory array. Each memory macro includes a magnetic random access memory macro, and each of the magnetic random access memory macros further includes: An array of magnetic random access memory bit cells, each of the magnetic random access memory bit cells comprising: Magnetic tunnel junction element; Access transistors are coupled to the magnetic tunnel junction element; The first line is coupled to the access transistor; The second bit line is coupled to the magnetic tunnel junction element; Word lines, coupled to the gate of the access transistor; and Local input / output circuitry, coupled to the first bit line and the second bit line of the magnetic random access memory bit cell. The first error correction code circuit includes: The encoder calculation circuit is coupled to the local input / output circuit. A first corrector s1 generator is coupled to the first bit line and the second bit line; The second corrector S3 generator is coupled to the first bit line and the second bit line; The cubic calculation circuit of the calibrator s1 is coupled to the output of the first calibrator s1 generator; and An error checking circuit is coupled to the output of each of the first corrector s1 generator, the second corrector s3 generator, the encoder calculation circuit, and the cubic calculation circuit of the corrector s1. The second error correction code circuit includes: The inverse circuit of the calibrator s1 is coupled to the output of the first calibrator s1 generator; The comparator is coupled to the output of the cubic calculation circuit of the comparator s1 and the output of the generator of the second comparator s3; A Galois domain multi-computation circuit is coupled to the output of the comparator and the output of the inverse circuit of the comparator s1; Error correction circuitry, coupled to local input / output circuitry, the first corrector s1 generator, and the Galois domain multicomputation circuitry; and A check bit generator circuit is used to correct the magnetic random access memory bit cells that have errors.

3. A memory device, comprising: Multiple memory macros, each memory macro including an array of memory cells and a first error correction code circuit, the first error correction code circuit being configured to detect data errors in the corresponding memory macro; A second error correction code circuit, located remotely from and communicatively coupled to each of the plurality of memory macros, is configured to receive detected data errors from the first error correction code circuit of each of the plurality of memory macros and write corrected data to the memory array. Each memory macro includes a magnetic random access memory macro, and each of the magnetic random access memory macros further includes: An array of magnetic random access memory bit cells, each of the magnetic random access memory bit cells comprising: Magnetic tunnel junction element; Access transistors are coupled to the magnetic tunnel junction element; The first line is coupled to the access transistor; The second bit line is coupled to the magnetic tunnel junction element; Word lines, coupled to the gate of the access transistor; and Local input / output circuitry, coupled to the first bit line and the second bit line of the magnetic random access memory bit cell. The first error correction code circuit includes: The encoder calculation circuit is coupled to the local input / output circuit. A first corrector s1 generator is coupled to the first bit line and the second bit line; The second corrector S3 generator is coupled to the first bit line and the second bit line; The cubic calculation circuit of the corrector s1 is coupled to the output of the first corrector s1 generator; The inverse circuit of the calibrator s1 is coupled to the output of the first calibrator s1 generator; The comparator is coupled to the output of the cubic calculation circuit of the comparator s1 and the output of the generator of the second comparator s3; and A Galois domain multi-computation circuit is coupled to the output of the comparator and the output of the inverse circuit of the comparator s1; An error checking circuit is coupled to the output of each of the first corrector s1 generator, the second corrector s3 generator, the encoder calculation circuit, and the cubic calculation circuit of the corrector s1.

4. The memory device according to claim 3, wherein, The second error correction code circuit includes: Error correction circuitry, coupled to the local input / output circuitry, the first corrector s1 generator, and the Galois domain multicomputation circuitry; and A check bit generator circuit is used to correct the magnetic random access memory bit cells that have errors.

5. An error correction code system, comprising: A plurality of first error correction code circuits, each of the plurality of first error correction code circuits being configured to be communicatively coupled to a corresponding memory array and configured to detect data errors in the corresponding memory array; as well as A second error correction code circuit is communicatively coupled to each of the plurality of first error correction code circuits and configured to receive detected data errors from the plurality of first error correction code circuits and correct the data errors. Each of the plurality of first error correction code circuits includes: The first corrector S1 generator is coupled to the first bit line and the second bit line; The second corrector S3 generator is coupled to the first bit line and the second bit line; An error checking circuit is coupled to the output of each of the first corrector s1 generator and the second corrector s3 generator; The second error correction code circuit includes: The encoder calculation circuit is coupled to the local input / output circuit. The cubic calculation circuit of the corrector s1 is coupled to the output of the first corrector s1 generator; The inverse circuit of the calibrator s1 is coupled to the output of the first calibrator s1 generator; The comparator is coupled to the output of the cubic calculation circuit of the comparator s1 and the output of the generator of the second comparator s3; A Galois domain multi-computation circuit is coupled to the output of the comparator and the output of the inverse circuit of the comparator s1; Error correction circuitry, coupled to the local input / output circuitry, the first corrector s1 generator, and the Galois domain multicomputation circuitry; and A parity bit generator circuit is used to correct memory cells with errors.

6. An error correction code system, comprising: A plurality of first error correction code circuits, each of the plurality of first error correction code circuits being configured to be communicatively coupled to a corresponding memory array and configured to detect data errors in the corresponding memory array; as well as A second error correction code circuit is communicatively coupled to each of the plurality of first error correction code circuits and configured to receive detected data errors from the plurality of first error correction code circuits and correct the data errors. Each of the plurality of first error correction code circuits includes: The encoder calculation circuit is coupled to the local input / output circuit. The first corrector S1 generator is coupled to the first bit line and the second bit line; The second corrector S3 generator is coupled to the first bit line and the second bit line; The cubic calculation circuit of the corrector s1 is coupled to the output of the first corrector s1 generator; Error checking circuitry, coupled to the output of each of the first corrector S1 generator, the second corrector S3 generator, the encoder calculation circuit, and the cubic calculation circuit of the corrector S1; and The second error correction code circuit includes: The inverse circuit of the calibrator s1 is coupled to the output of the first calibrator s1 generator; The comparator is coupled to the output of the cubic calculation circuit of the comparator s1 and the output of the generator of the second comparator s3; A Galois domain multi-computation circuit is coupled to the output of the comparator and the output of the inverse circuit of the comparator s1; Error correction circuitry, coupled to the local input / output circuitry, the first corrector s1 generator, and the Galois domain multicomputation circuitry; and A parity bit generator circuit is used to correct memory cells with errors.

7. An error correction code system, comprising: A plurality of first error correction code circuits, each of the plurality of first error correction code circuits being configured to be communicatively coupled to a corresponding memory array and configured to detect data errors in the corresponding memory array; as well as A second error correction code circuit is communicatively coupled to each of the plurality of first error correction code circuits and configured to receive detected data errors from the plurality of first error correction code circuits and correct the data errors. Each of the plurality of first error correction code circuits includes: The first corrector S1 generator is coupled to the first bit line and the second bit line; The second corrector S3 generator is coupled to the first bit line and the second bit line; The encoder calculation circuit is coupled to the local input / output circuit. The cubic calculation circuit of the corrector s1 is coupled to the output of the first corrector s1 generator; An error checking circuit is coupled to the output of each of the first corrector s1 generator, the second corrector s3 generator, the encoder calculation circuit, and the cubic calculation circuit of the corrector s1. The inverse circuit of the calibrator s1 is coupled to the output of the first calibrator s1 generator; The comparator is coupled to the output of the cubic calculation circuit of the comparator s1 and the output of the generator of the second comparator s3; and A Galois domain multi-computation circuit is coupled to the output of the comparator and the output of the inverse circuit of the comparator s1; The second error correction code circuit includes: Error correction circuitry, coupled to the local input / output circuitry, the first corrector s1 generator, and the Galois domain multicomputation circuitry; and A parity bit generator circuit is used to correct memory cells with errors.

8. A method for correcting error codes, comprising: Multiple memory macros are provided, each memory macro including an array of memory cells and a first error correction code circuit; A second error correction code circuit is provided that is remote from the plurality of memory macros and communicatively coupled to each of the plurality of memory macros; Refreshing the memory array includes using the first error correction code circuit to check for data errors in the memory array; If the first error correction code circuit detects a data error, it sends the detected data error to the second error correction code circuit. The data error is corrected by the second error correction code circuit; as well as The corrected data is written into the memory array. The use of the first error correction code circuit to check for data errors in the memory array includes: A corrector s1 is generated based on the data received from the memory array; A corrector s3 is generated based on the data received from the memory array; Error checking based on the corrector s1 and the corrector s3; The correction of the data error using the second error correction code circuit includes: An encoder is generated based on data received from the memory array; Generate a cube of the corrector s1 based on the corrector s1; Generate the inverse of the corrector s1 based on the corrector s1; Compare the cube of the corrector s1 with the corrector s3; Galois domain multicomputation is generated based on the inverse of the calibrator s1 and the comparison between the cube of the calibrator s1 and the calibrator s3; Based on the encoder, the corrector s1, and the Galois domain, multi-computation generation of check bit error correction is performed; and The error correction bit is written into the memory array to correct the error.

9. A method for correcting error codes, comprising: Multiple memory macros are provided, each memory macro including an array of memory cells and a first error correction code circuit; A second error correction code circuit is provided that is remote from the plurality of memory macros and communicatively coupled to each of the plurality of memory macros; Refreshing the memory array includes using the first error correction code circuit to check for data errors in the memory array; If the first error correction code circuit detects a data error, it sends the detected data error to the second error correction code circuit. The data error is corrected by the second error correction code circuit; as well as The corrected data is written into the memory array. The method of checking for data errors in the memory array using the first error correction code circuit includes: A corrector s1 is generated based on the data received from the memory array; A corrector s3 is generated based on the data received from the memory array; An encoder is generated based on data received from the memory array; Generate a cube of the corrector s1 based on the corrector s1; Error checking based on the cube of the corrector s1, the corrector s3, the encoder, and the corrector s1; The correction of the data error using the second error correction code circuit includes: Generate the inverse of the corrector s1 based on the corrector s1; Compare the cube of the corrector s1 with the corrector s3; Galois domain multicomputation is generated based on the inverse of the calibrator s1 and the comparison between the cube of the calibrator s1 and the calibrator s3; Based on the encoder, the corrector s1, and the Galois domain, multi-computation generation of check bit error correction is performed; and The error correction bit is written into the memory array to correct the error.

10. A method for correcting error codes, comprising: Multiple memory macros are provided, each memory macro including an array of memory cells and a first error correction code circuit; A second error correction code circuit is provided that is remote from the plurality of memory macros and communicatively coupled to each of the plurality of memory macros; Refreshing the memory array includes using the first error correction code circuit to check for data errors in the memory array; If the first error correction code circuit detects a data error, it sends the detected data error to the second error correction code circuit. The data error is corrected by the second error correction code circuit; as well as The corrected data is written into the memory array. The method of checking for data errors in the memory array using the first error correction code circuit includes: A corrector s1 is generated based on the data received from the memory array; A corrector s3 is generated based on the data received from the memory array; An encoder is generated based on data received from the memory array; Generate a cube of the corrector s1 based on the corrector s1; Error checking based on the cube of the corrector s1, the corrector s3, the encoder, and the corrector s1; Generate the inverse of the corrector s1 based on the corrector s1; Compare the cubic form of the corrector s1 with the corrector s3; and Galois domain multicomputation is generated based on the inverse of the calibrator s1 and the comparison between the cube of the calibrator s1 and the calibrator s3.

11. The method of claim 10, wherein, Correcting the data error using the second error correction code circuit includes: Based on the encoder, the corrector s1, and the Galois domain, multi-computation generation of check bit error correction is performed; and The error correction bit is written into the memory array to correct the error.

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