Semiconductor package manufacturing method

Abstract

A method for manufacturing a semiconductor package is provided, which can suppress an increase in the required man-hours. The method for manufacturing a semiconductor package includes the following steps: a groove forming step, in which a first cutting tool is used to cut along a predetermined dividing line from the upper surface side to a depth that does not completely cut off the semiconductor package substrate, and a processing groove having a first width is formed on at least the upper surface of the sealant, wherein the depth is greater than or equal to a depth that at least exposes a grounding line of the wiring substrate in the processing groove; a shielding layer forming step, in which a shielding layer is formed on the side and bottom of the processing groove and the upper surface of the sealant using a conductive material from above the sealant side; and a dividing step, in which, after the shielding layer forming step is performed, a second cutting tool is used to cut along the processing groove to a width that does not remove the shielding layer formed on the side, and the semiconductor package substrate is divided.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor package. Background Art

[0002] A semiconductor package substrate is generally formed by mounting a semiconductor chip on a wiring substrate and sealing the semiconductor chip with a sealant such as a resin (for example, see Patent Document 1). However, in recent years, in order to effectively utilize the space next to the solder balls bonded to the wiring substrate on the side opposite to the semiconductor chip, a semiconductor package substrate has emerged in which a semiconductor chip is further arranged between the solder balls and both sides of the wiring substrate are sealed with a sealant.

[0003] Patent Document 1: Japanese Patent Application No. 2017-084105

[0004] A semiconductor package substrate having semiconductor chips disposed on both surfaces of a wiring substrate is usually covered with a conductive shielding layer after being divided into individual semiconductor packages. The conductive shielding layer is formed on the outer surface of the semiconductor package by sputtering. The conventional method for manufacturing a semiconductor package in which the shielding layer is formed as described above has the following problems.

[0005] When a shielding layer is formed on a semiconductor package after singulation, the thickness of the semiconductor package is relatively thick, and accordingly, it is not easy to form a shielding layer of sufficient thickness on the bottom side, and the adhesion of the shielding layer on the bottom side tends to be weak. In addition, during sputtering, components of the shielding layer also adhere to the sputtering tape that supports the semiconductor package, so when the semiconductor package is picked up from the sputtering tape after sputtering, the shielding layer may be peeled off or burrs may be generated on the shielding layer, which may cause quality defects.

[0006] However, if the semiconductor chip on the lower side of the wiring substrate does not generate electromagnetic waves that affect other semiconductor chips, or generates electromagnetic waves of a frequency that is shielded by metal wiring or mounting solder balls within the wiring substrate, it is not necessary to form a shielding layer on the entire bottom side as long as a shielding layer connected to the ground wire of the wiring substrate is formed by covering the upper surface of the wiring substrate.

[0007] In addition, in the manufacturing method of the semiconductor package in which the shielding layer is formed by sputtering as described above, the semiconductor package after singulation needs to be replaced with the sputtering tape from the dicing tape used for supporting during singulation before sputtering, so the operation of replacing the semiconductor packages after singulation needs to be replaced one by one, which increases the required man-hours. Therefore, the manufacturing method of the semiconductor package in which the shielding layer is formed by sputtering as described above has the problem of increasing the required man-hours for manufacturing. In addition, the semiconductor package after singulation also has the disadvantage that the shielding layer cannot be applied due to the plating process. Summary of the invention

[0008] Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor package that can suppress an increase in required man-hours.

[0009] According to the present invention, a method for manufacturing a semiconductor package is provided, wherein a semiconductor package substrate is divided along a predetermined dividing line to manufacture a semiconductor package, wherein the semiconductor package substrate has a plurality of semiconductor chips mounted on an upper surface of a wiring substrate divided by a plurality of the predetermined dividing lines intersecting each other, and a plurality of solder balls mounted on a lower surface of the wiring substrate, and both surfaces of the wiring substrate are sealed by a sealant, and the method for manufacturing a semiconductor package comprises the following steps: a groove forming step, wherein a first cutting unit is used to cut along the predetermined dividing line from the upper surface side to a depth that does not completely cut the semiconductor package substrate, and a processing groove having a first width is formed on at least the upper surface of the sealant, wherein the depth is greater than or equal to a depth that at least exposes a grounding line of the wiring substrate in the processing groove; a shielding layer forming step, wherein a shielding layer is formed on the side surface and the bottom surface of the processing groove and the upper surface of the sealant by using a conductive material from above the sealant side after the groove forming step is performed; and a dividing step, wherein a second cutting unit is used to cut along the processing groove to a width that does not remove the shielding layer formed on the side surface after the shielding layer forming step is performed, and the semiconductor package substrate is divided.

[0010] Preferably, in the groove forming step, the processed groove is formed with an inclination on a side surface of the processed groove such that a first width of an upper surface is larger than a second width of a bottom surface.

[0011] The present invention has the effect of being able to suppress an increase in required man-hours. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a cross-sectional view schematically showing a semiconductor package manufactured by the method for manufacturing a semiconductor package according to the first embodiment.

[0013] Figure 2 This is a plan view of a portion of a semiconductor package substrate divided into semiconductor packages by the method for manufacturing a semiconductor package according to the first embodiment.

[0014] Figure 3 It is along Figure 2 Cross-sectional view along line III-III.

[0015] Figure 4 This is a flowchart showing the flow of the method for manufacturing the semiconductor package according to the first embodiment.

[0016] Figure 5 It is schematically shown in Figure 41 is a cross-sectional view showing a state where a semiconductor package substrate is supported by a dicing tape in a groove forming step of a method for manufacturing a semiconductor package.

[0017] Figure 6 It is schematically shown Figure 4 A cross-sectional view of a groove forming step in a method of manufacturing a semiconductor package is shown.

[0018] Figure 7 It is schematically shown Figure 4 FIG. 1 is a cross-sectional view of a semiconductor package substrate after a groove forming step in a method for manufacturing a semiconductor package.

[0019] Figure 8 It is schematically shown in Figure 4 A cross-sectional view showing a state in which a semiconductor package substrate is supported by a sputtering tape in a groove forming step of a method for manufacturing a semiconductor package shown.

[0020] Fig. 9 It is schematically shown Figure 4 FIG. 1 is a cross-sectional view of a semiconductor package substrate after a shield layer forming step in a method for manufacturing a semiconductor package.

[0021] Fig.10 It is schematically shown Figure 4 A cross-sectional view showing a dividing step in a method for manufacturing a semiconductor package is shown.

[0022] Fig.11 It is schematically shown Figure 4 FIG. 1 is a cross-sectional view of a semiconductor package substrate after a dividing step in a method for manufacturing a semiconductor package.

[0023] Fig.12 This is a cross-sectional view schematically showing a state where a semiconductor package substrate is supported by a dicing tape in a groove forming step of a method for manufacturing a semiconductor package according to a second embodiment.

[0024] Fig.13 It is a cross-sectional view schematically showing a dividing step in the method for manufacturing a semiconductor package according to the second embodiment.

[0025] Fig.14 It is a cross-sectional view schematically showing the semiconductor package substrate after the dividing step in the method for manufacturing the semiconductor package according to the second embodiment.

[0026] Description of symbols

[0027] 1: semiconductor package; 2: wiring substrate; 3: semiconductor chip; 4: solder ball; 6: sealant; 7: shielding layer; 9: processing groove; 10: semiconductor package substrate; 11: dividing predetermined line; 21: upper surface; 22: lower surface; 61: upper surface; 91: first width; 92: bottom surface; 93: second width; 94: side surface; 101: first cutting tool (first cutting unit); 111: second cutting tool (second cutting unit); ST1: groove forming process; ST2: shielding layer forming process; ST3: dividing process. DETAILED DESCRIPTION

[0028] Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited by the contents described in the following embodiments. In addition, the constituent elements described below include contents that can be easily thought of by those skilled in the art, and substantially the same contents. In addition, the structures described below can be appropriately combined. In addition, various omissions, substitutions or changes in the structure can be made within the scope of the gist of the present invention.

[0029] [First embodiment]

[0030] A method for manufacturing a semiconductor package according to a first embodiment of the present invention will be described with reference to the drawings. Figure 1 It is a cross-sectional view schematically showing a semiconductor package manufactured by the method for manufacturing a semiconductor package according to the first embodiment. Figure 2 This is a plan view showing a part of the semiconductor package substrate divided into semiconductor packages by the method for manufacturing the semiconductor package according to the first embodiment. Figure 3 It is along Figure 2 Cross-sectional view along line III-III. Figure 4 This is a flowchart showing the flow of the method for manufacturing the semiconductor package according to the first embodiment.

[0031] A method for manufacturing a semiconductor package according to a first embodiment is to manufacture Figure 1 The semiconductor package 1 manufactured by the semiconductor package manufacturing method of the first embodiment is a fully packaged semiconductor device that needs to be shielded due to so-called EMI (Electro-Magnetic Interference), and is configured to suppress electromagnetic noise leakage to the surroundings by a shield layer 7 on the outer surface.

[0032] like Figure 1As shown, the semiconductor package 1 has: a wiring substrate (also called an interposer substrate) 2; a plurality of semiconductor chips 3, which are mounted on the upper surface 21 of the wiring substrate 2; a plurality of solder balls 4, which are mounted on the lower surface 22 of the wiring substrate 2; a lower surface side semiconductor chip 5, which is mounted on the lower surface 22; a sealant 6, which seals the upper surface 21 and the lower surface 22 of the wiring substrate 2; and a shielding layer 7.

[0033] The wiring substrate 2 has an insulating insulating plate 23 and a grounding line 24 provided inside the insulating plate 23. The grounding line 24 is embedded inside the insulating plate 23 of the wiring substrate 2 and is made of a conductive metal. In addition, electrodes or various wirings connected to the semiconductor chips 3 and 5 are formed on the upper surface 21 and the lower surface 22 of the wiring substrate 2.

[0034] The semiconductor chip 3 and the lower surface side semiconductor chip 5 have IC (Integrated Circuit) or LSI (Large Scale Integration) or the like. In the first embodiment, nine semiconductor chips 3 are mounted at equal intervals on the upper surface 21 of the wiring substrate 2, and one lower surface side semiconductor chip 5 is mounted at the center of the lower surface 22 of the wiring substrate 2. In addition, in the first embodiment, the semiconductor chip 3 is mounted on the upper surface 21 of the wiring substrate 2 by flip chip bonding in which an electrode (not shown) provided on the lower surface thereof is directly connected to the upper surface 21 of the wiring substrate 2. In addition, in the first embodiment, the lower surface side semiconductor chip 5 is mounted on the lower surface 22 of the wiring substrate 2 by so-called wire bonding in which one end of the lead 8 is connected to the upper surface thereof and the other end of the lead 8 is connected to the lower surface of the wiring substrate 2. The solder ball 4 is made of a conductive metal and is provided in plurality around the lower surface side semiconductor chip 5 on the lower surface 22 of the wiring substrate 2. The solder ball 4 suppresses electromagnetic noise from the lower surface side semiconductor chip 5 from leaking to the surroundings.

[0035] The sealant 6 is made of an insulating synthetic resin, and seals (covers) the semiconductor chip 3, the lower surface semiconductor chip 5, the lead 8, and the base end of the solder ball 4 near the wiring substrate 2. The sealant 6 is made of epoxy resin, silicone resin, polyurethane resin, unsaturated polyester resin, acrylic polyurethane resin, or polyimide resin. In addition, the front end of the solder ball 4 away from the wiring substrate 2 is exposed outside the sealant 6.

[0036] The shielding layer 7 is composed of one or more conductive metals such as copper, titanium, nickel, and gold, and is a multilayer film with a film thickness of several μm or more. The shielding layer 7 is formed on the upper surface 61 of the sealant 6 parallel to the upper surface 21 of the wiring substrate 2, the outer side surface 62 of the sealant 6 connected to the upper surface 61 and closer to the upper surface 61 than the wiring substrate 2, and the outer side surface 25 of the wiring substrate 2, and is connected to the ground line 24. The outer side surface 62 gradually tilts toward the outside of the semiconductor package 1 as it moves from the upper surface 61 toward the lower surface 63 of the sealant 6. The shielding layer 7 is not formed on the lower surface 63 side of the sealant 6 closer to the wiring substrate 2. In addition, in the first embodiment, the shielding layer 7 is formed on the outer side 25 of the wiring substrate 2, but in the present invention, if it is connected to the ground line 24, it may not be set at a position on the lower surface 63 side of the wiring substrate 2 closer to the ground line 24. The shielding layer 7 suppresses the electromagnetic noise from the semiconductor chip 3 from leaking to the surroundings.

[0037] Will Figure 2 and Figure 3 The semiconductor package substrate 10 shown is divided along the predetermined dividing lines 11 and the shielding layer 7 is formed, thereby manufacturing the semiconductor package 1 of the above structure. Figure 2 and Figure 3 As shown, the semiconductor package substrate 10 has a plurality of semiconductor chips 3 mounted on the upper surface 21 of the wiring substrate 2 divided by a plurality of predetermined dividing lines 11, and a plurality of solder balls 4 mounted on the lower surface 22 of the wiring substrate 2, and the upper surface 21 and the lower surface 22 are sealed by a sealant 6. In the first embodiment, the semiconductor package substrate 10 has nine semiconductor chips 3 mounted on each area of ​​the upper surface 21 of the wiring substrate 2 divided by a plurality of predetermined dividing lines 11, and a lower surface side semiconductor chip 5 mounted on the lower surface 22 of each area divided by a plurality of predetermined dividing lines 11. In addition, Figure 2 and Figure 3 The semiconductor package substrate 10 shown in FIG. 1 is not formed with the shielding layer 7. Figure 2 and Figure 3 As shown, the semiconductor package substrate 10 is sealed with the semiconductor chip 6 and the like by the sealant 6 in a state where the outer edge of the wiring substrate 2 is exposed, and an alignment mark 26 for alignment in the groove forming step ST1 and the dividing step ST3 described later is formed on the upper surface 21 of the outer edge of the wiring substrate 2. In addition, in the first embodiment, the alignment mark 26 is formed on the upper surface 21 of the outer edge of the wiring substrate 2, but in the present invention, it can also be formed on the lower surface 22 of the outer edge of the wiring substrate 2, and can also be formed on both the upper surface 21 and the lower surface 22 of the outer edge of the wiring substrate 2.

[0038] A method for manufacturing a semiconductor package according to a first embodiment includes: Figure 2 and Figure 3 The semiconductor package substrate 10 is divided along the dividing lines 11 and the shielding layer 7 is formed to manufacture the semiconductor package 1. Figure 4 As shown, the method for manufacturing a semiconductor package includes a groove forming step ST1 , a shield layer forming step ST2 , and a dividing step ST3 .

[0039] (Groove Forming Process)

[0040] Figure 5 It is schematically shown in Figure 4 1 is a cross-sectional view showing a state where a semiconductor package substrate is supported by a dicing tape in a groove forming step of a method for manufacturing a semiconductor package. Figure 6 It is schematically shown Figure 4 A cross-sectional view of a groove forming step in a method of manufacturing a semiconductor package is shown. Figure 7 It is schematically shown Figure 4 FIG. 1 is a cross-sectional view of a semiconductor package substrate after a groove forming step in a method for manufacturing a semiconductor package.

[0041] The groove forming step ST1 is a step of cutting along the planned dividing line 11 from the upper surface 21 side to a depth that does not completely divide the semiconductor package substrate 10, thereby forming a processing groove 9 having a first width 91 on at least the upper surface 61 of the sealant 6, the depth of which is greater than or equal to at least Figure 5 The wiring substrate 2 shown in FIG. 2 has a ground line 24. Figure 6 The exposed depth in the machining groove 9 is shown.

[0042] The first cutting tool 101 used in the groove forming step ST1 is formed into a trapezoidal cross-section, and the center of the thickness direction of the cutting edge 102 protrudes toward the outer periphery and gradually becomes thinner toward the outer periphery. The cutting edge 102 of the first cutting tool 101 is formed flat along the axis of the first cutting tool 101, and is inclined in a direction in which the first cutting tool 101 is gradually thickened from the front end 103 toward the axis.

[0043] In the first embodiment, as Figure 5 As shown, in the groove forming step ST1, a dicing tape 200 larger than the plane shape of the semiconductor package substrate 10 is attached to the lower surface 63 of the sealant 6, and a ring frame 201 is attached to the outer periphery of the dicing tape 200. In the groove forming step ST1, the cutting device 100 is Figure 6As shown in the figure, the lower surface 63 side of the sealant 6 of the semiconductor package substrate 10 is sucked and held on the holding surface 105 of the chuck table 104 via the dicing tape 200. In the groove forming step ST1, the infrared camera (not shown) of the cutting device 100 photographs the upper surface 61 of the sealant 6 of the semiconductor package substrate 10, performs alignment, and aligns the semiconductor package substrate 10 with the first cutting tool 101. In addition, in the first embodiment, the alignment mark 26 formed on the outer edge of the upper surface 21 of the wiring substrate 2 is not sealed by the sealant 6 but exposed, so the alignment is performed based on the alignment mark 26.

[0044] like Figure 6 As shown, in the groove forming step ST1, the cutting device 100 causes the semiconductor package substrate 10 and the first cutting tool 101 to move relatively along the predetermined dividing line 11 while causing the first cutting tool 101 to cut from the upper surface 61 side until reaching the ground line 24 of the wiring substrate 2, thereby forming a processing groove 9 having a substantially V-shaped cross section on the upper surface 61 of the sealant 6 of the semiconductor package substrate 10. In the groove forming step ST1 of the first embodiment, the cutting device 100 causes the first cutting tool 101 to divide the wiring substrate 2 from the upper surface 61 of the sealant 6 and cut to a depth that is not cut into the sealant 6 on the side closer to the lower surface 63 of the wiring substrate 2, thereby forming the processing groove 9.

[0045] In the first embodiment, in the groove forming step ST1, the cutting device 100 causes the first cutting tool 101 to cut to a depth for dividing the wiring substrate 2. However, in the present invention, the first cutting tool 101 may be cut to a depth for exposing the grounding wire 24 of the wiring substrate 2 in the processed groove 9. If the semiconductor package substrate 10 is not completely divided, the first cutting tool 101 may be cut to a position of the sealant 6 closer to the lower surface 63 than the wiring substrate 2. In the present invention, the cutting depth of the first cutting tool 101 for not completely dividing the semiconductor package substrate 10 refers to a depth at which the front end 103 of the first cutting tool 101 is not exposed from the lower surface 63 but is located in the sealant 6. In addition, when the processed groove 9 is formed on the sealant 6 at the predetermined dividing line 11 of the semiconductor package substrate 10, the side surface 94 of the processed groove 9 is composed of the outer side surface 62 and the outer side surface 25 described above.

[0046] In the groove forming step ST1, the semiconductor package substrate 10 is provided with the processed grooves 9 on all the planned dividing lines 11. Figure 7 As shown, the machining groove 9 is formed along the outer shape of the cutting edge 102 of the first cutting tool 101, the first width 91 of the upper surface 61 of the sealant 6 is formed to be larger than the second width 93 of the bottom surface 92, and the side surface 94 of the machining groove 9 is formed to be inclined relative to the upper surface 61 and the bottom surface 92. Figure 7When the processed grooves 9 are formed on the upper surface 61 side of the sealant 6 at all the planned dividing lines 11 of the semiconductor package substrate 10 as shown, the method of manufacturing the semiconductor package proceeds to the shield layer forming step ST2 .

[0047] (Shielding layer forming step)

[0048] Figure 8 It is schematically shown in Figure 4 A cross-sectional view showing a state in which a semiconductor package substrate is supported by a sputtering tape in a groove forming step of a method for manufacturing a semiconductor package shown. Fig. 9 It is schematically shown Figure 4 FIG. 1 is a cross-sectional view of a semiconductor package substrate after a shield layer forming step in a method for manufacturing a semiconductor package.

[0049] The shielding layer forming step ST2 is a step of forming the shielding layer 7 on the side 94 of the processed groove 9, the bottom 92 of the processed groove 9, and the upper surface 61 of the sealant 6 from above the sealant 6 side using a metal as a conductive material. In the shielding layer forming step ST2, the dicing tape 200 is peeled off from the lower surface 63 of the sealant 6 of the semiconductor package substrate 10, as shown in FIG. Figure 8 As shown, a sputtering tape 210 larger than the planar shape of the semiconductor package substrate 10 is attached to the lower surface 63 of the sealant 6 , and a ring-shaped frame 211 is attached to the outer periphery of the sputtering tape 210 .

[0050] In the shielding layer forming step ST2, the semiconductor package substrate 10 is stored in the container, and the metal is attached to the semiconductor package substrate 10 from the upper surface 61 side of the sealant 6 by sputtering, thereby forming the shielding layer 7. In this way, in the first embodiment, the shielding layer forming step ST2 forms the shielding layer 7 by so-called sputtering, but in the present invention, the shielding layer 7 may also be formed by electroplating. Fig. 9 When the shielding layer 7 is formed as shown in FIG. 1 , the method for manufacturing the semiconductor package enters the dividing step ST3. In addition, after the shielding layer forming step ST2, the semiconductor package substrate 10 is Fig. 9 As shown, the shield layer 7 is formed on the side surfaces 94 and the bottom surface 92 of the processed grooves 9 formed on all the planned dividing lines 11 and on the upper surface 61 of the sealant 6 .

[0051] (Separation process)

[0052] Fig.10 It is schematically shown Figure 4 A cross-sectional view showing a dividing step in a method for manufacturing a semiconductor package is shown. Fig.11 It is schematically shown Figure 4 FIG. 1 is a cross-sectional view of a semiconductor package substrate after a dividing step in a method for manufacturing a semiconductor package.

[0053] The dividing step ST3 is a step of dividing the semiconductor package substrate 10 into individual semiconductor packages 1 by cutting along the processed groove 9 with a width that does not remove the shield layer 7 formed on the side surface 94 using the second cutting tool 111 as the second cutting means after the shield layer forming step ST2 is performed.

[0054] The tip 113 of the cutting edge 112 of the second cutting tool 111 used in the dividing step ST3 is formed to be substantially flat along the axis of the second cutting tool 111. In the first embodiment, the thickness of the second cutting tool 111 is formed to be equal to the interval 71 between the shielding layers 7 on the adjacent side surfaces 94 on the bottom surface 92 of the processed groove 9, but in the present invention, it is sufficient to be thinner than the interval 72 between the shielding layers 7 on the grounding wire 24 on the side surface 94 of the processed groove 9. In short, in the first embodiment, the width of the shielding layer 7 not removed is equal to the interval 71 between the shielding layers 7 on the adjacent side surfaces 94 on the bottom surface 92 of the processed groove 9, but in the present invention, it is sufficient to be less than or equal to the interval 72 between the shielding layers 7 on the grounding wire 24 on the side surface 94 of the processed groove 9. That is, in the present invention, the width of the shielding layer 7 not removed is a width that exceeds zero and is less than or equal to the interval 72 between the shielding layers 7 on the grounding wire 24 on the side surface 94 of the processed groove 9, and the portion of the shielding layer 7 connected to the grounding wire 24 remains after the dividing.

[0055] In the first embodiment, if Fig.10 As shown, in the dividing step ST3, the cutting device 110 attracts and holds the lower surface 63 side of the sealant 6 of the semiconductor package substrate 10 on the holding surface 115 of the chuck table 114 through the sputtering tape 210. In the dividing step ST3, the not-shown imaging unit of the cutting device 110 images the upper surface 61 of the sealant 6 of the semiconductor package substrate 10, performs alignment, and performs alignment between the semiconductor package substrate 10 and the second cutting tool 111. In addition, in the first embodiment, the alignment mark 26 formed on the outer edge of the upper surface 21 of the wiring substrate 2 is not sealed by the sealant 6 but exposed, so the alignment is performed based on the alignment mark 26. In addition, in the dividing step ST3, when the sputtering tape 210 is not suitable for cutting, it can also be replaced with a dicing tape.

[0056] In the dividing step ST3, the cutting device 110 moves the semiconductor package substrate 10 and the second cutting tool 111 relatively along the dividing predetermined line 11, and the second cutting tool 111 cuts from the upper surface 61 side to the bottom surface 92 of the processing groove 9 until it reaches the sputtering zone 210, thereby dividing the semiconductor package substrate 10 into individual semiconductor packages 1. Fig.11When the second cutting tool 111 cuts into the bottom surface 92 of the processing groove 9 of all the division planned lines 11 of the semiconductor package substrate 10 as shown, the manufacturing method of the semiconductor package is completed. In addition, each divided semiconductor package 1 is picked up from the sputtering belt 210 by a well-known pickup device or the like.

[0057] In the method for manufacturing a semiconductor package of the first embodiment, the first cutting tool 101 is cut to a depth that does not completely divide the semiconductor package substrate 10 in the groove forming step ST1, so that the time required for forming the shielding layer 7 in the shielding layer forming step ST2 can be reduced, and the time required for switching the semiconductor package substrate 10 from the dicing tape 200 to the sputtering tape 210 can be reduced. As a result, the method for manufacturing a semiconductor package has the effect of reducing the increase in the time required.

[0058] In addition, the method for manufacturing a semiconductor package of the first embodiment makes the first cutting tool 101 cut to a depth that does not completely split the semiconductor package substrate 10 in the groove forming step ST1, and forms the shielding layer 7 in the shielding layer forming step ST2, thereby preventing the shielding layer 7 from contacting the sputtering tape 210. As a result, the method for manufacturing a semiconductor package can prevent the shielding layer 7 from peeling off and the generation of burrs of the shielding layer 7.

[0059] In addition, in the method for manufacturing a semiconductor package of the first embodiment, the first cutting tool 101 is cut to a depth that does not completely divide the semiconductor package substrate 10 in the groove forming step ST1, and the shielding layer 7 is formed in the shielding layer forming step ST2, so that the shielding layer 7 is not formed near the lower surface 63. As a result, the method for manufacturing a semiconductor package of the first embodiment can prevent the thickness of the shielding layer 7 from being particularly thin near the lower surface 63, and can prevent the adhesion of the shielding layer 7 to the sealant 6 from being weakened.

[0060] In addition, the manufacturing method of the semiconductor package of the first embodiment implements the splitting process ST3 with the sputtering tape 210 pasted on the lower surface 63, but in the present invention, after the sputtering tape 210 is peeled off from the lower surface 63, the splitting process ST3 can also be implemented by pasting a dicing tape on the lower surface 63.

[0061] [Second embodiment]

[0062] A method for manufacturing a semiconductor package according to a second embodiment of the present invention will be described with reference to the drawings. Fig.12 This is a cross-sectional view schematically showing a state where a semiconductor package substrate is supported by a dicing tape in a groove forming step of a method for manufacturing a semiconductor package according to a second embodiment. Fig.13 It is a cross-sectional view schematically showing a dividing step in the method for manufacturing a semiconductor package according to the second embodiment. Fig.142 is a cross-sectional view schematically showing a semiconductor package substrate after a dividing step in a method for manufacturing a semiconductor package according to a second embodiment. Fig.12 , Fig.13 as well as Fig.14 In the present invention, the same parts as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

[0063] In the method for manufacturing a semiconductor package substrate of the second embodiment, the dividing step ST3 is different from that of the first embodiment, and the semiconductor package substrate 10 is the same as the first embodiment except that alignment marks 26 are formed on both the upper surface 21 and the lower surface 22 of the outer edge of the wiring substrate 2 that is not sealed by the sealant 6 and exposed. Fig.12 As shown, in the dividing step ST3 of the manufacturing method of the semiconductor package substrate of the second embodiment, a dicing tape 220 larger than the planar shape of the semiconductor package substrate 10 is adhered to the upper surface 61 side of the sealant 6, an annular frame 221 is adhered to the outer periphery of the dicing tape 220, and the sputtering tape 210 is peeled off from the lower surface 63 of the sealant 6 of the semiconductor package substrate 10.

[0064] In the second embodiment, Fig.13 As shown, in the dividing step ST3, the cutting device 110 attracts and holds the upper surface 61 side of the sealant 6 of the semiconductor package substrate 10 on the holding surface 115 of the chuck table 114 through the dicing tape 220. In the dividing step ST3, the infrared camera (not shown) of the cutting device 110 photographs the lower surface 63 of the sealant 6 of the semiconductor package substrate 10, performs alignment, and performs alignment between the semiconductor package substrate 10 and the second cutting tool 111. In addition, in the second embodiment, an alignment mark 26 is formed on the outer edge of the lower surface 22 of the wiring substrate 2, and the alignment mark 26 is not sealed by the sealant 6 but exposed, so alignment is performed based on the alignment mark 26.

[0065] In the dividing step ST3, the cutting device 110 moves the semiconductor package substrate 10 and the second cutting tool 111 relatively along the dividing line 11 while cutting the second cutting tool 111 from the lower surface 63 until it reaches the bottom surface 92 of the processing groove 9, thereby dividing the semiconductor package substrate 10 into individual semiconductor packages 1. Fig.14 When the second cutting tool 111 cuts into the bottom surface 92 of the processing groove 9 of all the division planned lines 11 of the semiconductor package substrate 10 as shown, the semiconductor package manufacturing method is completed. In addition, each divided semiconductor package 1 is picked up from the dicing tape 220 by a well-known pickup device or the like.

[0066] In the method for manufacturing a semiconductor package of the second embodiment, the first cutting tool 101 is cut to a depth that does not completely divide the semiconductor package substrate 10 in the groove forming step ST1, so that the time required for forming the shielding layer 7 in the shielding layer forming step ST2 can be reduced, and the time required for replacing the semiconductor package substrate 10 between the dicing tapes 200 and 220 and the sputtering tape 210 can be reduced. As a result, the method for manufacturing a semiconductor package has the effect of reducing the increase in the time required, similar to the first embodiment.

[0067] In addition, in the method for manufacturing a semiconductor package of the second embodiment, the first cutting tool 101 is cut to a depth that does not completely split the semiconductor package substrate 10 in the groove forming step ST1, and the shielding layer 7 is formed in the shielding layer forming step ST2, so that the shielding layer 7 can be prevented from contacting the sputtering tape 210. As a result, the method for manufacturing a semiconductor package can prevent the shielding layer 7 from peeling off and the generation of burrs of the shielding layer 7 in the same manner as in the first embodiment.

[0068] In addition, the present invention is not limited to the above-mentioned embodiments and the like. That is, various modifications can be made and implemented within the scope of the main purpose of the present invention. For example, when the alignment mark 26 is not formed on the upper surface 21 or the lower surface 22 of the outer edge of the wiring substrate 2, and when the upper surface 21 and the lower surface 22 including the outer edge of the wiring substrate 2 are sealed by the sealant 6 as a whole and the alignment mark 26 cannot be detected, the cutting device 100, 110 photographs the semiconductor package substrate 10 by an infrared camera or a photographing unit in the groove forming step ST1 and the dividing step ST3, and detects the dividing predetermined line 11 or the bottom surface 92 of the processing groove 9 to perform alignment.

Claims

1. A method for manufacturing a semiconductor package, wherein a semiconductor package substrate is divided along a predetermined dividing line to manufacture a semiconductor package, wherein a plurality of semiconductor chips are mounted on an upper surface of a wiring substrate divided by a plurality of intersecting predetermined dividing lines, a plurality of solder balls are mounted on a lower surface of the wiring substrate, a lower surface side semiconductor chip is mounted on the lower surface, the wiring substrate has an insulating insulating plate and a conductive grounding line provided inside the insulating plate, and both surfaces of the wiring substrate are sealed with a sealant, characterized in that: The method for manufacturing the semiconductor package comprises the following steps: A groove forming step, using a first cutting unit to cut along the predetermined dividing line from the upper surface side to a depth that does not completely cut the semiconductor package substrate, to form a processing groove having a first width on at least the upper surface of the sealant, wherein the depth is greater than or equal to a depth that exposes at least the grounding line of the wiring substrate in the processing groove; a shielding layer forming step of forming a shielding layer connected to the ground line on the side surface of the processed groove, the bottom surface of the processed groove and the upper surface of the sealant from above the sealant side using a conductive material after the groove forming step is performed; and In the dividing step, after the shield layer forming step is performed, the semiconductor package substrate is divided by cutting along the processed groove by a second cutting unit with a width that does not remove the shield layer formed on the side surface.

2. The method for manufacturing a semiconductor package according to claim 1, wherein: In this groove forming step, The processing groove is formed with an inclination on the side surface of the processing groove in such a manner that a first width of the upper surface is larger than a second width of the bottom surface.

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