Display device and method of manufacturing the same

Abstract

The present invention discloses a display device and a manufacturing method thereof. The display device includes: a base substrate including a display area in which an image is displayed and a peripheral area adjacent to the display area; a source / drain pattern on the base substrate, the source / drain pattern including a connection electrode in a pad portion of the peripheral area and an electrode of a thin film transistor in the display area; a planarization insulating layer on the base substrate, the planarization insulating layer contacting the side surface of the connection electrode and the side surface of the electrode of the thin film transistor and exposing the top surface of the connection electrode; a connection member contacting the connection electrode; and a driving member including a driving circuit, the driving member being connected to the connection member.

Description

Technical Field

[0001] Example embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0002] Recently, display devices that are lightweight and small in size have been manufactured. Due to performance and competitive price, cathode ray tube (CRT) display devices have been used. However, CRT display devices have weaknesses in size or portability. Therefore, display devices such as plasma display devices, liquid crystal display devices, or organic light emitting display devices that are small in size, lightweight, and have low power consumption are desired. Summary of the invention

[0003] An embodiment relates to a display device, comprising: a base substrate including a display area in which an image is displayed and a peripheral area adjacent to the display area; a source / drain pattern on the base substrate, the source / drain pattern including a connecting electrode in a pad portion of the peripheral area and an electrode of a thin film transistor in the display area; a planarization insulating layer on the base substrate, the planarization insulating layer contacting side surfaces of the connecting electrode and side surfaces of the electrode of the thin film transistor and exposing a top surface of the connecting electrode; a connecting member contacting the connecting electrode; and a driving member including a driving circuit, the driving member being connected to the connecting member.

[0004] The connection electrode may include a first layer pattern and a second layer pattern on the first layer pattern. A constituent material of the first layer pattern and a constituent material of the second layer pattern may be different from each other. A top surface of the second layer may contact the connection member.

[0005] The display device may further include a through-hole insulating layer on the planarization insulating layer and a first electrode on the through-hole insulating layer, the first electrode being electrically connected to the thin film transistor. The first electrode may include silver (Ag).

[0006] A top surface of the connection electrode has a smaller planar area than a bottom surface of the connection electrode, so that the connection electrode has a constant tapered cross-section.

[0007] The display device may further include: a through-hole insulating layer on the planarization insulating layer; a light emitting structure on the through-hole insulating layer, the light emitting structure being electrically connected to the thin film transistor; a thin film encapsulation layer on the light emitting structure; and a touch structure directly on the thin film encapsulation layer.

[0008] The display device may further include a stop layer pattern between the planarization insulating layer and the base substrate and between the planarization insulating layer and side surfaces of the source / drain pattern. The stop layer pattern may include a material different from that of the planarization insulating layer.

[0009] The stop layer pattern may include silicon oxide (SiOx) or silicon nitride (SiNx).

[0010] The stopping layer pattern may include an organic insulating material.

[0011] The source / drain pattern may be received in a recess on a top surface of the planarizing insulating layer. A side surface and a bottom surface of the connecting electrode may contact the planarizing insulating layer.

[0012] An embodiment also relates to a method for manufacturing a display device, comprising: forming a source / drain pattern on a base substrate, the base substrate comprising a display area in which an image is to be displayed and a peripheral area adjacent to the display area, the source / drain pattern comprising a connecting electrode in a pad portion of the peripheral area and an electrode of a thin film transistor arranged in the display area; forming an initial insulating layer on the base substrate on which the source / drain pattern is formed; forming a planarizing insulating layer, the planarizing insulating layer exposing a top surface of the connecting electrode by removing a portion of the insulating layer; and connecting the connecting electrode and the driving member using a connecting member between the connecting electrode and a driving member including a driving circuit.

[0013] Forming the source / drain pattern may include: sequentially forming a first layer and a second layer, the second layer being made of a material different from that of the first layer; and forming the source / drain pattern by etching the second layer and the first layer.

[0014] The method may further include forming a through hole insulating layer on the planarization insulating layer and forming a first electrode including silver (Ag) on ​​the through hole insulating layer.

[0015] Forming the planarized insulating layer may include removing a portion of the initial insulating layer disposed on the connection electrode through a chemical mechanical planarization (CMP) process to expose a top surface of the connection electrode.

[0016] The method may further include forming a stop layer on the source / drain pattern before forming the initial insulating layer. Forming the planarized insulating layer may include: removing a portion of the initial insulating layer disposed on the connection electrode by a chemical mechanical planarization (CMP) process to expose the stop layer; and removing a portion of the stop layer to expose the top surface of the connection electrode. For the CMP process for the planarized insulating layer, the stop layer may include a material having a lower CMP selectivity than the planarized insulating layer.

[0017] The stop layer may include silicon oxide (SiOx) or silicon nitride (SiNx).

[0018] The stop layer may include an organic insulating material.

[0019] The method may further include forming a through hole insulating layer on the planarization insulating layer, forming a light emitting structure on the through hole insulating layer, forming a thin film encapsulation layer on the light emitting structure, and directly forming a touch structure on the thin film encapsulation layer.

[0020] The method may further include forming a lower insulating layer on the base substrate before forming the source / drain pattern. The lower insulating layer and the preliminary insulating layer formed on the base substrate on which the source / drain pattern is formed may be formed of the same material.

[0021] The method may further include forming a through hole insulating layer on the planarization insulating layer, forming a light emitting structure on the through hole insulating layer, forming a thin film encapsulation layer on the light emitting structure, and directly forming a touch structure on the thin film encapsulation layer.

[0022] The connection member may include a conductive adhesive. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0024] Figure 1 A plan view showing a display device according to an exemplary embodiment;

[0025] Figure 2 Shown along Figure 1 A cross-sectional view taken along line II' in FIG.

[0026] Figure 3 A partial enlarged cross-sectional view of a display device is shown, wherein Figure 2 The pad portion is enlarged;

[0027] Figure 4 A cross-sectional view showing a display device according to an exemplary embodiment;

[0028] Figure 5 A cross-sectional view showing a display device according to an exemplary embodiment;

[0029] Figure 6 A partial enlarged cross-sectional view of a display device is shown, wherein Figure 5 The pad portion is enlarged;

[0030] Figure 7 A cross-sectional view showing a display device according to an exemplary embodiment;

[0031] FIG. 8A to FIG. 8F Show manufacturing Figure 2 A cross-sectional view of various stages of a method of displaying an apparatus;

[0032] FIG. 9A to FIG. 9G Show manufacturing Figure 4 A cross-sectional view of various stages of a method of displaying an apparatus;

[0033] FIG. 10A to FIG. 10C Show manufacturing Figure 5A cross-sectional view of various stages of a method of displaying an apparatus;

[0034] FIG. 11A to FIG. 11B Show manufacturing Figure 7 A cross-sectional view of various stages of a method of displaying an apparatus;

[0035] Fig.12 A block diagram illustrating an electronic device according to an example embodiment;

[0036] Fig.13A Show Fig.12 An example in which the electronic device is implemented as a television; and

[0037] Fig. 13B Shows Fig.12 The electronic device is implemented as an example of a smart phone. DETAILED DESCRIPTION

[0038] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, example embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey exemplary implementations to those skilled in the art.

[0039] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity. It should also be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or there can be intervening layers. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under, or there can be one or more intervening layers. In addition, it should be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. The same reference numerals refer to the same elements throughout.

[0040] Figure 1 A plan view of a display device according to an exemplary embodiment is shown.

[0041] refer to Figure 1 The display device may include a display area DA in which an image is displayed and a peripheral area PA, which is a non-display area surrounding the display area DA. As an example, the display area DA may have a suitable shape, such as a polygon, a polygon with rounded corners, an ellipse, or a circle. For example, Figure 1 As shown, the display area DA may have a rectangular shape on a plane formed by a first direction D1 and a second direction D2 perpendicular to the first direction D1.

[0042] The peripheral area PA may include a left peripheral area adjacent to the left side of the display area DA, a right peripheral area adjacent to the right side of the display area DA, an upper peripheral area adjacent to the upper side of the display area DA, and a lower peripheral area adjacent to the lower side of the display area DA.

[0043] The pad portion PAD may be formed in the lower peripheral area. A connection electrode for connecting a driving member for driving the display device may be provided in the pad portion PAD. The connection electrode may be a data pad, a gate pad, etc. for transmitting a data signal, a scan signal, etc. A portion of the peripheral area PA between the pad portion PAD and the display area DA may be formed with a bending area to allow the pad portion PAD to be provided on the back side of the display area DA.

[0044] In the display area, a plurality of pixels for displaying an image, signal lines such as scan lines, data lines, etc. may be provided. Each pixel may include a light emitting structure and a pixel circuit including a thin film transistor, a storage capacitor, etc.

[0045] Figure 2 Shown along Figure 1 A cross-sectional view taken along line II' in FIG.

[0046] refer to Figure 1 and Figure 2 The display device may include a base substrate 100, an active pattern ACT, a first insulating layer 110, a gate pattern, a second insulating layer 120, a source / drain pattern, a planarization insulating layer 130, a through-hole insulating layer 140, a light emitting structure 180, a pixel defining layer PDL, a thin film encapsulation layer TFE, and a connecting member CN.

[0047] The base substrate 100 may include a transparent insulating substrate. For example, the base substrate 100 may be a transparent resin substrate having flexibility. The transparent resin substrate may include a polyimide-based resin, an acrylic-based resin, a polyacrylate-based resin, a polycarbonate-based resin, a polyether-based resin, a sulfonic acid-based resin, a polyethylene terephthalate-based resin, etc. For example, the base substrate 100 may be a polyimide (PI) resin film.

[0048] The active pattern ACT may be disposed on the base substrate 100. The active pattern ACT may include amorphous silicon or polycrystalline silicon. In some example embodiments, the active pattern ACT may include an oxide of at least one substance selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The active pattern ACT may include a source region and a drain region doped with impurities and a channel region disposed between the source region and the drain region.

[0049] The display device may further include a buffer layer disposed between the base substrate 100 and the active pattern ACT.

[0050] The buffer layer can help prevent metal atoms and / or impurities from diffusing from the base substrate 100. In addition, the buffer layer can adjust the heat transfer rate of the continuous crystallization process of the active pattern ACT, thereby obtaining a substantially uniform active pattern ACT. In the case where the base substrate 100 has a relatively irregular surface, the buffer layer can improve the flatness of the surface of the base substrate 100. The buffer layer can be formed using a silicon compound. For example, the buffer layer may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), silicon carbonitride (SiCxNy), etc.

[0051] The first insulating layer 110 may be disposed on the base substrate 100 on which the active pattern ACT is disposed. The first insulating layer 110 may be uniformly formed on the base substrate 100 along the contour of the active pattern ACT. The first insulating layer 110 may include a silicon compound, a metal oxide, or the like.

[0052] The gate pattern may be disposed on the first insulating layer 110. The gate pattern may include a gate electrode GE, a storage electrode, and a signal line such as a gate line. The gate pattern may be formed using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, or the like.

[0053] The second insulating layer 120 may be disposed on the first insulating layer 110 on which the gate pattern is disposed. For example, the second insulating layer 120 may have a relatively large thickness to fully cover the gate pattern so that the second insulating layer 120 may have a substantially horizontal surface. In some embodiments, the second insulating layer 120 may be uniformly formed on the first insulating layer 110 along the contour of the gate pattern. The second insulating layer 120 may have a much smaller thickness along the contour of the gate pattern so that a step portion may be formed at a portion of the second insulating layer 120 adjacent to the gate pattern. The second insulating layer 120 may include a silicon compound, a metal oxide, etc. The second insulating layer 120 may be formed of multiple layers.

[0054] The source / drain pattern may be disposed on the second insulating layer 120. The source / drain pattern may include a source electrode SE, a drain electrode DE, and a signal line such as a data line disposed in the display area DA. The source / drain pattern may include a connection electrode 122 disposed in the pad area PAD of the peripheral area PA.

[0055] The source / drain pattern may be formed using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. The source / drain pattern may be formed of multiple layers. For example, the source / drain pattern may be a laminated structure including: a first layer including titanium (Ti), a second layer including aluminum (Al), and a third layer including titanium (Ti).

[0056] The source electrode SE may be electrically connected to the source region of the active pattern ACT through a contact hole formed through the first and second insulating layers 110 and 120. The drain electrode DE may be electrically connected to the drain region of the active pattern ACT through a contact hole formed through the first and second insulating layers 110 and 120.

[0057] The active pattern ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE may be included in a thin film transistor TFT which is a part of a pixel circuit.

[0058] The planarization insulating layer 130 may be disposed on the same layer as the source / drain pattern. For example, the planarization insulating layer 130 may be disposed on the second insulating layer 120 on which the source / drain pattern is disposed. The planarization insulating layer 130 may contact the side surface of the source / drain pattern without covering the top surface of the source / drain pattern.

[0059] The planarization insulating layer 130 may include an inorganic insulating material such as a silicon compound, a metal oxide, or an organic insulating material.

[0060] The through hole insulating layer 140 may be disposed on the source electrode SE, the drain electrode DE, and the planarization insulating layer 130 of the display area DA. The through hole insulating layer 140 may include an organic insulating material. The through hole insulating layer 140 may have a relatively large thickness to fully cover the source / drain pattern so that the through hole insulating layer 140 may be substantially horizontal.

[0061] The via insulating layer 140 is not formed in a portion of the pad portion PAD adjacent to the connection electrode 122. Therefore, a top surface of the connection electrode 122 may be exposed. The top surface of the connection electrode 122 may contact a connection member CN, which will be described below.

[0062] The light emitting structure 180 may be disposed in the display area DA and may include a first electrode 181 , a light emitting layer 182 , and a second electrode 183 .

[0063] The first electrode 181 may be disposed on the through-hole insulating layer 140. The first electrode 181 may be electrically connected to the thin film transistor TFT through a contact hole formed through the through-hole insulating layer 140.

[0064] Depending on the light emitting type of the display device, the first electrode 181 may include a reflective material or a transmissive material. For example, the first electrode 181 may be formed using aluminum, an alloy containing aluminum, aluminum nitride, silver, an alloy containing silver, tungsten, tungsten nitride, copper, an alloy containing copper, nickel, an alloy containing nickel, chromium, chromium nitride, molybdenum, an alloy containing molybdenum, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, indium zinc oxide, etc. These may be used alone or in combination. In an example embodiment, the first electrode 181 may have a single-layer structure or a multilayer structure, which may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive film.

[0065] In some embodiments, the first electrode 181 may have a laminated structure including a first layer including indium tin oxide (ITO), a second layer including silver (Ag), and a third layer including indium tin oxide (ITO).

[0066] The pixel defining layer PDL may be disposed on the through-hole insulating layer 140 on which the first electrode 181 is disposed. The pixel defining layer PDL may be formed using an organic material. For example, the pixel defining layer PDL may include a photoresist, an acrylic-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, and the like. In some example embodiments, an opening exposing the first electrode 181 may be formed by etching the pixel defining layer PDL. The light-emitting region and the non-light-emitting region of the display device may be defined by the opening of the pixel defining layer PDL. For example, a portion where the opening of the pixel defining layer PDL is disposed may correspond to a light-emitting region, and a portion adjacent to the opening of the pixel defining layer PDL may correspond to a non-light-emitting region.

[0067] The light emitting layer 182 may be disposed on the first electrode 181 exposed by the opening of the pixel defining layer PDL. In some embodiments, the light emitting layer 182 may extend on the sidewall of the opening of the pixel defining layer PDL. In some embodiments, the light emitting layer 182 may include an organic light emitting layer (EL), a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), an electron injection layer (EIL), etc. In some embodiments, the layers of the light emitting structure 180 including the hole injection layer, the hole transport layer, the electron transport layer and the electron injection layer but not including the organic light emitting layer may be formed together to correspond to a plurality of pixels. A plurality of organic light emitting layers may be formed using light emitting materials to generate light of different colors, such as red light, green light and blue light, according to the color pixels of the display device. In some exemplary embodiments, the organic light emitting layer of the light emitting layer 182 may include a plurality of stacked light emitting materials to generate red light, green light and blue light, thereby emitting white light. The elements of the light emitting layer 182 may be formed together to correspond to a plurality of pixels. Each pixel may be divided by a color filter layer.

[0068] The second electrode 183 may be disposed on the pixel defining layer PDL and the light emitting layer 182. Depending on the light emitting type of the display device, the second electrode 183 may include a transmissive material or a reflective material. For example, the second electrode 183 may be formed using aluminum, an alloy containing aluminum, aluminum nitride, silver, an alloy containing silver, tungsten, tungsten nitride, copper, an alloy containing copper, nickel, an alloy containing nickel, chromium, chromium nitride, molybdenum, an alloy containing molybdenum, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, indium zinc oxide, etc. These may be used alone or in combination. In an example embodiment, the second electrode 183 may have a single-layer structure or a multilayer structure, which may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive film.

[0069] The thin film encapsulation layer TFE may be disposed on the second electrode 183. The thin film encapsulation layer TFE may help prevent moisture and oxygen from penetrating from the outside. The thin film encapsulation layer TFE may include at least one organic layer and at least one inorganic layer. At least one organic layer and at least one inorganic layer may be alternately stacked. For example, the thin film encapsulation layer TFE may include two inorganic layers and an organic layer therebetween. In some embodiments, a sealing substrate may be provided instead of the thin film encapsulation layer to prevent moisture and oxygen from penetrating from the outside of the display device.

[0070] The driving member DR may be electrically connected to the connection electrode 122 of the pad area PAD through the connection member CN. The top surface of the connection electrode 122 may be exposed and not covered by an insulating layer such as a through-hole insulating layer 140, a pixel defining layer PDL, or a thin film encapsulation layer TFE. The connection electrode 122 and the driving member DR may be electrically connected to each other through the connection member CN.

[0071] The driving member DR may include a driving circuit for generating a driving signal for driving the display device, etc. The driving member DR may include a printed circuit board, a flexible circuit board, an IC chip, etc. The connecting member CN may include a conductive adhesive such as ACF (Anisotropic Conductive Film), etc.

[0072] Figure 3 A partial enlarged cross-sectional view of a display device is shown, in which the Figure 2 The pad portion shown in .

[0073] refer to Figure 2 and Figure 3 The connection electrode 122 may include at least two or more layers including different materials. The connection electrode 122 may include, for example, a first layer pattern 122a, a second layer pattern 122b, and a third layer pattern 122c.

[0074] For example, as described above with respect to the source / drain patterns, the first layer pattern 122 a and the third layer pattern 122 c may include titanium (Ti), and the second layer pattern 122 b may include aluminum (Al).

[0075] The connection electrode 122 may have a constant tapered cross-sectional shape in a third direction D3 perpendicular to the first and second directions D1 and D2. An angle θ between a bottom surface of the connection electrode 122 and a side surface of the connection electrode 122 may be an acute angle less than 90 degrees.

[0076] In addition, under the same etching conditions, the etching selectivities of the third layer pattern 122c including the top surface of the connection electrode 122 in contact with the connection member CN and the second layer pattern 122b may be different from each other. That is, under the etching conditions of the second layer pattern 122b, the etching selectivity of the third layer pattern 122c may be lower than the etching selectivity of the second layer pattern 122b. In addition, under the etching conditions of the first electrode 181, the etching selectivity of the third layer pattern 122c may be lower than the etching selectivity of the first electrode 181.

[0077] According to the present embodiment, the planarization insulating layer 130 is in contact with the side surface of the connection electrode 122. A separate insulating layer is not formed in contact with the top surface of the connection electrode 122. Therefore, regardless of the distance h1 between the driving member DR and the connection electrode 122, the driving member DR can be easily connected or coupled to the connection electrode 122 using the connection member CN.

[0078] Figure 4 A cross-sectional view of a display device according to an exemplary embodiment is shown.

[0079] refer to Figure 4 , in addition to further including the stop layer pattern 125, the display device may be Figures 1 to 3 Therefore, the display device will not be repeated. Figures 1 to 3 Description of features that are identical to the features of

[0080] The display device may include a base substrate 100, an active pattern ACT, a first insulating layer 110, a gate pattern, a second insulating layer 120, a stop layer pattern 125, a source / drain pattern, a planarization insulating layer 130, a through-hole insulating layer 140, a light emitting structure 180, a pixel defining layer PDL, a thin film encapsulation layer TFE, a driving member DR, and a connection member CN. The gate pattern may include a gate electrode GE. The source / drain pattern may include a source electrode SE and a drain electrode DE disposed in the display area DA and a connection electrode 122 disposed in a pad portion PAD of the peripheral area PA. The active pattern ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE may be included in a thin film transistor TFT constituting a pixel circuit.

[0081] The stop layer pattern 125 may be disposed between the second insulating layer 120 and the planarizing insulating layer 130 and between the source / drain pattern and the planarizing insulating layer 130. For example, the stop layer pattern 125 may cover only side surfaces of the source / drain pattern without covering top surfaces of the source / drain pattern.

[0082] The stop layer pattern 125 may include a material different from the planarization insulating layer 130. For example, for a CMP (chemical mechanical polishing) process for the planarization insulating layer 130, the stop layer pattern 125 may include a material having a lower CMP selectivity than the planarization insulating layer 130.

[0083] The stop layer pattern 125 may include an inorganic insulating material or an organic insulating material. For example, when the stop layer pattern 125 includes an inorganic insulating material, the stop layer pattern 125 may include silicon oxide (SiOx) or silicon nitride (SiNx). When the planarization insulating layer 130 includes silicon oxide (SiOx), the stop layer pattern 125 may include silicon nitride (SiNx).

[0084] Figure 5 A cross-sectional view of a display device according to an exemplary embodiment is shown. Figure 6 A partial enlarged cross-sectional view of a display device is shown, wherein Figure 5 The pad portion is enlarged.

[0085] refer to Figure 5 and Figure 6 In addition to forming the second insulating layer and the planarizing insulating layer into one planarizing insulating layer 135, the display device may be Figures 1 to 3 The display device shown in FIG. 1 is substantially the same as that shown in FIG. 1 . Therefore, the same Figures 1 to 3 Description of features that are the same as those shown in .

[0086] The display device may include a base substrate 100, an active pattern ACT, a first insulating layer 110, a gate pattern, a planarizing insulating layer 135, a source / drain pattern, a through-hole insulating layer 140, a light emitting structure 180, a pixel defining layer PDL, a thin film encapsulation layer TFE, a driving member DR, and a connecting member CN. The gate pattern may include a gate electrode GE. The source / drain pattern may include a source electrode SE and a drain electrode DE disposed in a display area DA and a connecting electrode 122 disposed in a pad portion PAD of a peripheral area PA. The active pattern ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE may be included in a thin film transistor TFT constituting a pixel circuit.

[0087] A recess may be formed in the planarization insulating layer 135 to accommodate the source / drain pattern. The recess may have a length from the top surface of the planarization insulating layer 135 in the third direction D3 (see FIG. Figure 6 ) in a direction opposite to the concave portion. The source / drain pattern may be accommodated in the concave portion.

[0088] The planarization insulating layer 135 may include an inorganic insulating material such as a silicon compound or a metal oxide, or an organic insulating material.

[0089] refer to Figure 6 The connection electrode 122 may include a first layer pattern 122 a , a second layer pattern 122 b , and a third layer pattern 122 c . Side surfaces and a bottom surface of the connection electrode 122 may contact the planarization insulating layer 135 .

[0090] The connection electrode 122 may have a constant tapered cross-sectional shape in a third direction D3 perpendicular to the first and second directions D1 and D2. An angle between a bottom surface of the connection electrode 122 and a side surface of the connection electrode 122 may be an acute angle θ less than 90 degrees.

[0091] Figure 7 A cross-sectional view of a display device according to an exemplary embodiment is shown.

[0092] refer to Figure 7 In addition to further including a touch structure TS disposed on the thin film encapsulation layer TFE, the display device and Figures 1 to 3 Therefore, the display device will not be repeated. Figures 1 to 3 Description of features that are the same as those shown in .

[0093] The display device may include a base substrate 100, an active pattern ACT, a first insulating layer 110, a gate pattern, a second insulating layer 120, a source / drain pattern, a planarization insulating layer 130, a through-hole insulating layer 140, a light emitting structure 180, a pixel defining layer PDL, a thin film encapsulation layer TFE, a touch structure TS, a driving member DR, and a connection member CN. The gate pattern may include a gate electrode GE. The source / drain pattern may include a source electrode SE and a drain electrode DE disposed in the display area DA and a connection electrode 122 disposed in a pad portion PAD of the peripheral area PA. The active pattern ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE may be included in a thin film transistor TFT constituting a pixel circuit.

[0094] The touch structure TS may be formed directly on the thin film encapsulation layer TFE. The touch structure TS may include a first touch pattern TE1, an insulating layer 190, and a second touch pattern TE2. The touch structure TS may be a suitable touch structure for touch recognition of a user. The touch structure TS may be formed directly on the thin film encapsulation layer TFE. In some embodiments, the first touch pattern TE1 and the second touch pattern TE2 may be formed as two layers with an insulating layer 190 therebetween. In some embodiments, the touch structure TS may be composed of an insulating layer and a touch pattern of one layer.

[0095] According to the present embodiment, the formation of impurities due to oxidation / reduction reaction in the process before forming the touch structure TS can be prevented. Therefore, defects such as wiring short circuits caused by impurities in the process of forming the touch structure TS can be prevented. Therefore, it is possible to reduce defects of the display device, improve display quality, and improve process yield.

[0096] FIG. 8A to FIG. 8F Shows the manufacturing Figure 2 A cross-sectional view of a display device at various stages of the method.

[0097] refer to Fig. 8A , an active pattern ACT may be formed on the base substrate 100. A first insulating layer 110 may be formed on the base substrate 100 on which the active pattern ACT is formed. A gate pattern may be formed on the first insulating layer 110. The gate pattern may include a gate electrode GE of the thin film transistor TFT. A second insulating layer 120 may be formed on the first insulating layer 110 on which the gate pattern is formed. Thereafter, a contact hole may be formed through the second insulating layer 120 to expose a portion of the active pattern ACT.

[0098] The second insulating layer 120 may be formed by a chemical vapor deposition process, a spin coating process, a plasma enhanced chemical vapor deposition process, a sputtering process, a vacuum deposition process, a high density plasma-chemical vapor deposition process, a printing process, etc., depending on its constituent materials.

[0099] A source / drain pattern may be formed on the second insulating layer 120. The source / drain pattern may include a connection electrode 122 disposed in the pad portion PAD of the peripheral area PA and a source electrode SE and a drain electrode DE disposed in the display area DA.

[0100] The source / drain pattern may be obtained by forming a conductive layer on the second insulating layer 120 and then patterning the conductive layer using a photolithography process or an etching process using an additional etching mask. The conductive layer may be formed using a printing process, a sputtering process, a chemical vapor deposition process, a pulsed laser deposition (PLD) process, a vacuum deposition process, an atomic layer deposition (ALD) process, etc.

[0101] The conductive layer may be formed of multiple layers including different constituent materials. For example, the conductive layer may include: a first layer including titanium (Ti), a second layer including aluminum (Al), and a third layer including titanium (Ti). The first to third layers may be collectively etched and patterned. In one example, forming a source / drain pattern may include: sequentially forming a first layer and a second layer, the second layer being made of a material different from the first layer; and forming a source / drain pattern by etching the second layer and the first layer.

[0102] refer to Figure 8B , a preliminary insulating layer 130a may be formed on the source / drain pattern and the second insulating layer 120. The preliminary insulating layer 130a may be formed by a chemical vapor deposition process, a spin coating process, a plasma enhanced chemical vapor deposition process, a sputtering process, a vacuum deposition process, a high density plasma-chemical vapor deposition process, a printing process, etc., depending on its constituent materials.

[0103] refer to Figure 8C , a planarization insulating layer 130 may be formed to remove the initial insulating layer 130a (see Figure 8B ) where the source / drain pattern forms a step to expose a top surface of the source / drain pattern.

[0104] For example, a portion of the preliminary insulating layer 130a disposed above the connection electrode 122 of the pad portion PAD of the peripheral area PA may be removed by a planarization process such as a chemical mechanical planarization (CMP) process, so that the top surface of the connection electrode 122 is exposed. A portion of the preliminary insulating layer 130a disposed on the source electrode SE and the drain electrode DE in the display area DA may be removed to expose the source electrode SE and the drain electrode DE.

[0105] refer to Fig.8D , a through-hole insulating layer 140 may be formed on the planarization insulating layer 130 and on the source electrode SE and the drain electrode DE. A contact hole may be formed in the through-hole insulating layer 140 to expose a portion of the drain electrode DE. The through-hole insulating layer 140 may be formed by forming a photoresist layer on the planarization insulating layer 130, and then performing exposure and development.

[0106] The first electrode 181 may be formed on the via insulating layer 140. The first electrode 181 may be obtained by forming a conductive layer on the via insulating layer 140 and then patterning the conductive layer using a photolithography process or an etching process using an additional etching mask. The conductive layer may be formed using a printing process, a sputtering process, a chemical vapor deposition process, a pulsed laser deposition (PLD) process, a vacuum deposition process, an atomic layer deposition (ALD) process, or the like.

[0107] The conductive layer may be formed of multiple layers including different constituent materials. For example, the conductive layer may include: a first layer including indium tin oxide (ITO), a second layer including silver (Ag), and a third layer including indium tin oxide (ITO). The first to third layers may be collectively etched and patterned.

[0108] When the first electrode 181 is formed according to a general process, there is a risk that the etching process for patterning the first electrode 181 may affect the conductive pattern other than the first electrode 181. For example, in the process of patterning the first electrode 181, impurities due to an oxidation / reduction reaction may be formed on the surface of the connection electrode 122. When the first electrode 181 includes silver (Ag), silver particles may be deposited on the surface of the connection electrode 122. In addition, it has been found through experiments that impurities may also be precipitated on the conductive pattern at a portion where an edge portion of the through-hole insulating layer 140 contacts the conductive pattern.

[0109] Impurities such as silver particles may affect the patterning process of subsequent conductive patterns, for example, the patterning process of the second electrode, etc., which may cause defects in the display device, thereby reducing display quality and process yield. To solve this problem, when the first electrode 181 is patterned according to the present embodiment, only the top surface of the third layer of the connection electrode 122 is exposed (see Figure 3 The third layer pattern 122c may be formed of titanium, which is less affected by the patterning of the first electrode 181. The second layer pattern 122c may be formed of aluminum, which may be greatly affected by the patterning of the first electrode 181 (see Figure 3 The side surface of the connection electrode 122b) is covered by the planarization insulating layer 130 and is not exposed. Therefore, the precipitation of impurities on the surface of the connection electrode 122 can be minimized.

[0110] Therefore, impurities that affect subsequent processes can be minimized, defects of the display device can be reduced, display quality can be improved, and process yield can be increased.

[0111] refer to Fig. 8E A pixel defining layer PDL defining an opening may be formed on the through hole insulating layer 140 on which the first electrode 181 is formed. A light emitting layer 182 may be formed on the first electrode 181 in the opening of the pixel defining layer PDL.

[0112] The second electrode 183 may be formed on the light emitting layer 182. The second electrode 183 may be formed by forming a conductive layer on the light emitting layer 182 and the pixel defining layer PDL, and then patterning the conductive layer using a photolithography process or an etching process using an additional etching mask. The conductive layer may be formed using a printing process, a sputtering process, a chemical vapor deposition process, a pulsed laser deposition (PLD) process, a vacuum deposition process, an atomic layer deposition (ALD) process, or the like.

[0113] A thin film encapsulation layer TFE may be formed on the second electrode 183 .

[0114] refer to Figure 8F By using the connection member CN, the driving member DR can be connected to the connection electrode 122 of the pad portion PAD. Therefore, the display device can be manufactured. The connection member CN may include a conductive adhesive such as ACF (Anisotropic Conductive Film) or the like.

[0115] The top surface of the connection electrode 122 may be at the same level as the top surface of the planarization insulating layer 130 adjacent to the connection electrode 122. Therefore, the driving member DR may be easily connected to the connection electrode 122 using the connection member CN.

[0116] FIG. 9A to FIG. 9G Shows the manufacturing Figure 4 The method is similar to the method of forming a display device in various stages except that the stop layer 125a and the stop layer pattern 125 are formed. FIG. 8A to FIG. 8F Therefore, we will not repeat the FIG. 8A to FIG. 8F The stages are the same as those shown in the description of the stages.

[0117] refer to Fig.9A , an active pattern ACT, a first insulating layer 110 , a gate pattern including a gate electrode GE, and a second insulating layer 120 may be formed on a base substrate 100 .

[0118] A source / drain pattern may be formed on the second insulating layer 120. The source / drain pattern may include the connection electrode 122 in the pad portion PAD of the peripheral area PA and the source electrode SE and the drain electrode DE in the display area DA.

[0119] refer to Fig. 9B , a stop layer 125 a and a preliminary insulating layer 130 a may be sequentially formed on the source / drain patterns and the second insulating layer 120 .

[0120] The stop layer 125a and the preliminary insulating layer 130a may be formed by chemical vapor deposition, spin coating, plasma enhanced chemical vapor deposition, sputtering, vacuum deposition, high density plasma-chemical vapor deposition, printing, etc., depending on their constituent materials.

[0121] refer to Fig. 9C , a portion of the preliminary insulating layer 130a where a step is formed by the source / drain pattern may be removed to expose a portion of the stop layer 125a on the source / drain pattern.

[0122] For example, a portion of the initial insulating layer 130a on the connection electrode 122 in the pad portion PAD of the peripheral area PA may be removed by a planarization process such as a chemical mechanical planarization (CMP) process, etc. Portions of the initial insulating layer 130a on the source electrode SE and the drain electrode DE disposed in the display area DA may also be removed.

[0123] Here, in the CMP process for the initial insulating layer 130a, the stop layer 125a may include a material having a lower CMP selectivity than the initial insulating layer 130a. For example, in the CMP process for removing a portion of the initial insulating layer 130a, the stop layer 125a may be left without being removed. For example, when the initial insulating layer 130a includes silicon oxide (SiOx), the stop layer 125a may include silicon nitride (SiNx). Therefore, the stop layer 125a may not be removed by the CMP process, and the CMP process for removing the initial insulating layer 130a may be performed until the stop layer 125a is exposed.

[0124] The stop layer 125a may include an inorganic insulating material or an organic insulating material. For example, when the stop layer 125a includes an inorganic insulating material, the stop layer 125a may include silicon oxide (SiOx) or silicon nitride (SiNx).

[0125] refer to Fig.9D , a portion of the stop layer 125a exposed by the planarization insulating layer 130 may be removed to expose the connection electrode 122 and the source electrode SE and the drain electrode DE. This may be accomplished by another process (eg, a separate polishing process) to form a stop layer pattern 125 exposing the connection electrode 122.

[0126] According to the present embodiment, the CMP process for forming the planarization insulating layer 130 can be performed while the top surface of the connection electrode 122 is covered by the stop layer 125a. A portion of the stop layer 125a is removed by a separate process, so that the damage to the connection electrode 122 by the CMP process on the initial insulating layer 130a can be reduced or prevented.

[0127] refer to Fig.9E , a through hole insulating layer 140 may be formed on the planarization insulating layer 130 and the source and drain electrodes SE and DE. Thereafter, a first electrode 181 may be formed on the through hole insulating layer 140.

[0128] refer to Fig.9F , a pixel defining layer PDL defining an opening may be formed on the through hole insulating layer 140 on which the first electrode 181 is formed. A light emitting layer 182 may be formed on the first electrode 181 in the opening of the pixel defining layer PDL. A second electrode 183 may be formed on the light emitting layer 182. A thin film encapsulation layer TFE may be formed on the second electrode 183.

[0129] refer to Figure 9G , the driving member DR may be connected to the connection electrode 122 of the pad portion PAD by using the connection member CN. Therefore, the display device may be manufactured.

[0130] FIG. 10A to FIG. 10C It shows the manufacturing Figure 5 The method is similar to the method of planarizing the insulating layer 135 except that the insulating layer 135 is planarized. FIG. 8A to FIG. 8F Therefore, the description of the stages that are the same as the above stages will not be repeated.

[0131] refer to Fig. 10A , an active pattern ACT, a first insulating layer 110, and a gate pattern including a gate electrode GE may be formed on the base substrate 100. A lower insulating layer 135a may be formed on the first insulating layer 110 on which the gate pattern is formed.

[0132] After forming a contact hole through the lower insulating layer 135 a , a source / drain pattern including a source electrode SE and a drain electrode DE may be formed on the lower insulating layer 135 a .

[0133] refer to Fig. 10B , an upper insulating layer 135b may be formed on the lower insulating layer 135a on which the source / drain patterns are formed. The upper insulating layer 135b may be formed of the same material as the lower insulating layer 135a.

[0134] refer to Fig. 10C , a planarization insulating layer 135 may be formed to expose a top surface of the source / drain pattern by removing a portion of the upper insulating layer 135 b where a step is formed by the source / drain pattern.

[0135] For example, the upper insulating layer 135b disposed over the connection electrode 122 of the pad portion PAD of the peripheral area PA may be removed by a planarization process such as a chemical mechanical planarization (CMP) process. Fig. 10B ) portion so that the top surface of the connection electrode 122 may be exposed. In addition, the upper insulating layer 135b (see Fig. 10B ) portion to expose the source electrode SE and the drain electrode DE.

[0136] Afterwards, you can FIG. 8D to FIG. 8F The display device is manufactured in the same manner as shown in the manufacturing method.

[0137] FIG. 11A to FIG. 11B It shows the manufacturing Figure 7In addition to further forming a touch structure TS on the thin film encapsulation layer TFE, the method is similar to FIG. 8A to FIG. 8F Therefore, the description of the above stages will not be repeated.

[0138] refer to Fig.11A An active pattern ACT, a first insulating layer 110, a gate pattern including a gate electrode GE, a second insulating layer 120, a source / drain pattern including a source electrode SE and a drain electrode DE, and a connecting electrode 122, a planarizing insulating layer 130, a through-hole insulating layer 140, a light emitting structure 180, a pixel defining layer PDL, and a thin film encapsulation layer TFE can be formed on a base substrate 100.

[0139] The touch structure TS may be formed on the thin film encapsulation layer TFE. For example, the touch structure TS may be formed by forming the first touch electrode TE1, the insulating layer 190, and the second touch electrode TE2 on the thin film encapsulation layer TFE.

[0140] The formation of impurities due to oxidation / reduction reaction during the formation of the first electrode 181 can be reduced or prevented, and as described above, defects such as wiring short circuits caused by impurities during the formation of the touch structure TS can be reduced or prevented. Therefore, it is possible to reduce defects in the display device, improve display quality, and improve process yield.

[0141] refer to Fig. 11B , the driving member DR may be connected to the connection electrode 122 of the pad portion PAD by using the connection member CN. Therefore, the display device may be manufactured.

[0142] According to an exemplary embodiment, a method for manufacturing a display device includes: forming a source / drain pattern on a base substrate, the base substrate including a display area in which an image is displayed and a peripheral area adjacent to the display area, the source / drain pattern including a connection electrode in a pad portion of the peripheral area and an electrode of a thin film transistor disposed in the display area; forming an insulating layer on the base substrate on which the source / drain pattern is formed; forming a planarizing insulating layer that exposes a top surface of the connection electrode by removing a portion of the insulating layer; and connecting the connection electrode and the driving member using a connection member between the connection electrode and the driving member including a driving circuit. At this time, impurity precipitation on the surface of the connection electrode during the manufacturing process can be minimized, thereby reducing defects caused by impurities in subsequent processes.

[0143] Fig.12 is a block diagram illustrating an electronic device according to an example embodiment. Fig.13A It is shown Fig.12 The electronic device is implemented as an example of a television. Fig. 13B It is shown Fig.12 The electronic device is implemented as an example of a smart phone.

[0144] refer to Figures 12 to 13B , the electronic device 500 may include a processor 510, a memory device 520, a storage device 530, an input / output (I / O) device 540, a power supply 550, and a display device 560. The display device 560 may correspond to Figure 1 The electronic device 500 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc. The electronic device 500 may be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet computer, a car navigation system, a computer monitor, a laptop computer, a head mounted display (HMD), etc. As described above, the electronic device 500 may be implemented as Fig.13A and Fig. 13B TV or smartphone as shown.

[0145] Reference again Fig.12 , the processor 510 can perform various computing functions. The processor 510 can be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 510 can be coupled to other components via an address bus, a control bus, a data bus, etc. The processor 510 can be coupled to an expansion bus, such as a peripheral component interconnect (PCI) bus. The memory device 520 can store data for the operation of the electronic device 500. For example, the memory device 520 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device. The storage device 530 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 540 may include an input device such as a keyboard, a keypad, a mouse device, a touch pad, a touch screen, etc. or an output device such as a printer, a speaker, etc. The power supply 550 may provide power for the operation of the electronic device 500.

[0146] The display device 560 may be coupled to other components via a bus or other communication link. In some example embodiments, the display device 560 may be included in the I / O device 540. As described above, the display device 560 may include a planarization insulating layer.

[0147] By summarizing and reviewing, various efforts have been made to improve the process yield of the manufacturing process or improve the display quality of the display device by changing the manufacturing process or layered structure of the display device. An embodiment provides a display device capable of improving display quality. An embodiment also provides a method for manufacturing a display device capable of improving process yield. During the manufacturing process, the side surface of the connecting electrode can be covered to minimize the precipitation of impurities on the surface of the connecting electrode. Defects in the manufacturing process can be reduced, and the driving member can be easily connected to the connecting electrode using a connecting member.

[0148] Embodiments of the display device and the method for manufacturing the display device disclosed herein can be applied to display devices and various electronic devices including the display device. For example, the embodiments can be applied to mobile phones, smart phones, video phones, smart tablets, smart watches, tablet computers, car navigation systems, televisions, computer monitors, notebooks, etc.

[0149] Example embodiments have been disclosed so far, and although specific terms are used, they are used only in a general, descriptive sense and can only be interpreted in a general, descriptive sense, and they are not intended to be limiting. In some cases, as will be apparent to one of ordinary skill in the art at the time of filing this application, unless otherwise specifically noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

1. A display device, comprising: a base substrate including a display area in which an image is displayed and a peripheral area adjacent to the display area; a source / drain pattern on the base substrate, the source / drain pattern including a connection electrode in a pad portion of the peripheral region and an electrode of a thin film transistor in the display region; a planarization insulating layer on the base substrate, the planarization insulating layer contacting a side surface of the connection electrode and a side surface of the electrode of the thin film transistor and exposing an entire top surface of the connection electrode; a connecting member in contact with the connecting electrode; and A driving member including a driving circuit is connected to the connecting member.

2. The display device according to claim 1, wherein: The connecting electrode includes a first layer pattern and a second layer pattern on the first layer pattern, The constituent material of the first layer pattern and the constituent material of the second layer pattern are different from each other, and A top surface of the second layer pattern contacts the connection member.

3. The display device according to claim 2, further comprising: a through-hole insulating layer on the planarized insulating layer; and a first electrode on the through-hole insulating layer, the first electrode being electrically connected to the thin film transistor, and The first electrode comprises silver. 4 . The display device according to claim 1 , wherein a top surface of the connection electrode has a smaller planar area than a bottom surface of the connection electrode so that the connection electrode has a constant tapered cross-section.

5. The display device according to claim 1, further comprising: a through-hole insulating layer on the planarized insulating layer; a light emitting structure on the through hole insulating layer, the light emitting structure being electrically connected to the thin film transistor; a thin film encapsulation layer on the light emitting structure; and A touch structure directly on the thin film encapsulation layer.

6. The display device according to claim 1, further comprising: A stop layer pattern between the planarization insulating layer and the base substrate and between the planarization insulating layer and side surfaces of the source / drain pattern, the stop layer pattern including a material different from that of the planarization insulating layer. The display device according to claim 6 , wherein the stop layer pattern comprises silicon oxide or silicon nitride. The display device of claim 6 , wherein the stop layer pattern comprises an organic insulating material.

9. The display device according to claim 1, wherein: The source / drain pattern is received in a recess on a top surface of the planarization insulating layer, and The side surface and the bottom surface of the connection electrode contact the planarization insulating layer.

10. A method for manufacturing a display device, the method comprising: forming a source / drain pattern on a base substrate, the base substrate including a display area in which an image is to be displayed and a peripheral area adjacent to the display area, the source / drain pattern including a connection electrode in a pad portion of the peripheral area and an electrode of a thin film transistor disposed in the display area; forming an initial insulating layer on the base substrate on which the source / drain pattern is formed; forming a planarized insulating layer, the planarized insulating layer exposing the entire top surface of the connecting electrode by removing a portion of the initial insulating layer; and The connection electrode and the driving member are connected using a connection member between the connection electrode and the driving member including a driving circuit.

11. The method according to claim 10, wherein forming the source / drain pattern comprises: sequentially forming a first layer and a second layer, the second layer being made of a material different from that of the first layer; and The source / drain pattern is formed by etching the second layer and the first layer.

12. The method according to claim 11, further comprising: forming a through-hole insulating layer on the planarized insulating layer; and A first electrode including silver is formed on the through hole insulating layer.

13. The method according to claim 10, wherein forming the planarization insulating layer comprises: A portion of the initial insulating layer disposed on the connection electrode is removed by a chemical mechanical planarization process to expose a top surface of the connection electrode.

14. The method according to claim 10, further comprising: Before forming the initial insulating layer, a stop layer is formed on the source / drain pattern, and The forming of the planarization insulating layer comprises: removing a portion of the initial insulating layer disposed on the connection electrode to expose the stop layer by a chemical mechanical planarization process; and removing a portion of the stop layer to expose a top surface of the connection electrode, For the chemical mechanical planarization process for the planarization insulating layer, the stop layer includes a material having a lower chemical mechanical planarization selectivity than that of the planarization insulating layer. The method of claim 14 , wherein the stop layer comprises silicon oxide or silicon nitride. The method according to claim 14 , wherein the stop layer comprises an organic insulating material.

17. The method according to claim 10, further comprising: forming a through-hole insulating layer on the planarized insulating layer; forming a light emitting structure on the through hole insulating layer; forming a thin film encapsulation layer on the light emitting structure; and A touch structure is directly formed on the thin film encapsulation layer.

18. The method according to claim 10, further comprising: Before forming the source / drain pattern, a lower insulating layer is formed on the base substrate, and The lower insulating layer and the preliminary insulating layer formed on the base substrate on which the source / drain pattern is formed are formed of the same material. The method of claim 10 , wherein the connecting member comprises a conductive adhesive.

Images