Direct Memory Access

Abstract

Embodiments of the present disclosure relate to direct memory access. A memory includes a linked list of records, the linked list of records representing multiple data transfers via a direct memory access control circuit. Each record represents parameters of an associated data transfer in the multiple data transfers. The parameters of each record include a transfer start condition of the associated data transfer and a transfer end event of the associated data transfer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to French Patent Application No. 1871349 filed on November 2, 2018 and French Patent Application No. 1856705 filed on July 19, 2018, which are incorporated herein by reference. U.S. Patent Application No. 16 / 511,362 filed on July 15, 2019 also claims priority to French Patent Application No. 1856705 and is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to electronic systems and, in particular embodiments, to electronic systems that utilize data transfer via direct memory access (DMA). Background Art

[0004] Direct memory access is a method in an electronic system that enables data to be transferred between a peripheral device and memory, between two peripheral devices, or between two memories without central processing unit (CPU) intervention (other than starting and ending the transfer).

[0005] Direct memory access is usually implemented by a direct memory access control circuit. To perform a data transfer, the circuit reads a record in a linked list of records (LLI - "Linked List Item") from the memory to obtain the parameters of the transfer. The read parameters are temporarily stored in a register component or register bank of the circuit. The circuit then performs the transfer according to the stored parameters. Summary of the invention

[0006] The present disclosure relates generally to electronic systems. Certain embodiments relate to electronic systems in which the execution of tasks (eg, data transfer via direct memory access (DMA)) is parameterized by a linked list of records stored in memory.

[0007] Some embodiments may overcome at least some disadvantages of known electronic systems. For example, embodiments overcome at least some disadvantages of electronic circuits in which tasks are parameterized by registers that are programmed according to a linked list of records stored in a memory. As another example, embodiments overcome at least some disadvantages of electronic systems in which tasks parameterized by registers are data transfers performed by direct memory access.

[0008] According to a first aspect, one embodiment provides a memory comprising at least one linked list of records, each record comprising a first field determining a number of fields of a next record.

[0009] According to one embodiment, each field of the record represents the content to be programmed in a register of the register bank.

[0010] According to one embodiment, the first field determines in which registers the content should be programmed.

[0011] According to one embodiment, the first field includes a plurality of bits, each bit of the plurality of bits identifies a register, and values ​​of the plurality of bits determine a field of the record to be programmed.

[0012] According to one embodiment, each record represents a parameter of the execution of a task.

[0013] According to one embodiment, the task is a data transfer performed by a direct memory access control circuit.

[0014] According to one embodiment, for each record representing a data transfer, the parameters of the execution of the transfer include a transfer start condition and a transfer end event.

[0015] According to one embodiment, the parameters of the execution transmitted also include, for each record, an indication of at least one time when the condition should be detected and at least one time when the event should be generated.

[0016] According to one embodiment, the memory contains a first linked list of records and a second linked list of records, the start condition of the records of the first list corresponding to the detection of an event of the records of the second list.

[0017] According to one embodiment, the memory is of SRAM type.

[0018] According to a first aspect, an embodiment provides a method comprising continuously updating a register set based on a linked list of records contained in a memory such as previously defined.

[0019] According to one embodiment, each record determines one of the consecutive updates.

[0020] According to one embodiment, the method includes: reading a register programmed according to a first field of a current record; for each register, inferring therefrom whether a next record includes a field according to which the register should be programmed during a next programming of a register group; and during the next programming of the register group, programming the corresponding register in the register group based on each field of the next record.

[0021] According to a first aspect, an embodiment provides an electronic system comprising a memory such as defined above, and a circuit provided with a register set, the circuit being configured to implement the method defined above.

[0022] According to one embodiment, the circuit is a direct memory access controller.

[0023] According to a second aspect, an embodiment provides a memory comprising a linked list of at least one record, each record representing parameters of a data transfer performed by a direct memory access control circuit, the parameters comprising a transfer start condition and a transfer end event.

[0024] According to one embodiment, for each record, the parameters include an indication of the client that passed.

[0025] According to one embodiment, the transfer start condition is at least partially determined by the client of the transfer.

[0026] According to one embodiment, for each recording, the parameters include an identification of a transfer start signal, the condition being at least partially determined by the transfer start signal.

[0027] According to one embodiment, the parameters include, for each record, an indication of at least one of a time when the condition should be detected or a time when the condition should not be detected.

[0028] According to one embodiment, for each record, the parameters comprise an indication of at least one of a time when an event should be generated or a time when an event should not be generated, the event preferably being a modification of the delivery end signal.

[0029] According to one embodiment, each record comprises a first field determining the number of fields of the next record, each field of the record representing the content to be programmed in a register of a register bank of the direct memory access control circuit.

[0030] According to one embodiment, the first field determines in which registers the content should be programmed, the first field preferably comprising a plurality of bits, each of the plurality of bits identifying a register, the values ​​of the plurality of bits determining the fields of the record to be programmed.

[0031] According to one embodiment, for each record, the parameters include an indication of whether the transfer is a fragment of data, a plurality of data, a block of data, or a plurality of blocks of data.

[0032] According to one embodiment, the indication of at least one time is selected from: before each delivery of a segment of data, just before delivery of a first segment of data, before delivery of each block of data, and just before delivery of a first block of data.

[0033] According to one embodiment, the parameters further comprise, for each record, an indication of at least one time when the condition should be detected and an indication of at least one time when the event should be generated.

[0034] According to one embodiment, the memory contains a first linked list of records and a second linked list of records, the start condition of the records of the first list corresponding to the detection of an end event of the records of the second list.

[0035] According to one embodiment, each record contains a first field that determines the number of fields of the next record.

[0036] According to one embodiment, each field of the record represents the content to be programmed in a register of the register bank.

[0037] According to one embodiment, the first field determines in which registers the content should be programmed.

[0038] According to one embodiment, the first field includes a plurality of bits, each bit of the plurality of bits identifies a register, and values ​​of the plurality of bits determine a field of the record to be programmed.

[0039] According to one embodiment, the first record in the list contains as many fields as there are registers.

[0040] According to one embodiment, the memory is of SRAM type.

[0041] According to a second aspect, an embodiment provides a method of data transfer by direct memory access, wherein data transfers are performed on a channel of a direct memory access control circuit, each first data transfer on the channel being parameterized by a corresponding record of a list of memories such as defined previously.

[0042] According to one embodiment, each record in the list corresponds to an update of a register set associated with a channel.

[0043] According to one embodiment, the current contents of the register set parameterize the corresponding transfer on the channel.

[0044] According to one embodiment, for each record, the corresponding delivery is started only when a delivery start condition is detected.

[0045] According to a second aspect, another embodiment provides a method for data transfer via direct memory access, wherein a first transfer is performed on a first channel of a direct memory access control circuit and a second transfer is performed on a second channel of the circuit, each first transfer being parameterized by a corresponding record of a first list of memory such as defined previously.

[0046] According to one embodiment, each record in the first list corresponds to an update of a first register set associated with a first channel, and each record in the second list corresponds to an update of a second register set associated with a second channel.

[0047] According to one embodiment, the current contents of each register set parameterizes the corresponding transfer on the channel having the register set associated therewith.

[0048] According to one embodiment, for each record, the corresponding transfer is started only when the start condition of the record is detected.

[0049] According to a second aspect, an embodiment provides an electronic system comprising a memory such as defined above, and a direct memory access control circuit having a plurality of channels, each of the plurality of channels being associated with a register set, the circuit being configured to implement one of a plurality of methods such as defined above.

[0050] The foregoing as well as other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] As an example, Figure 1 There is shown very schematically in block form an embodiment of an electronic circuit 1 of the type to which the embodiments to be described are applicable;

[0052] Figure 2 is a flow chart illustrating, in block form, one embodiment of a method for data transfer via direct memory access;

[0053] Figure 3 One embodiment of a register bank of a direct memory access control circuit is schematically shown in block form;

[0054] Figure 4 Schematically shows a circuit comprising a Figure 3 A memory of an embodiment of a linked list of programmable register records;

[0055] Figure 5 A more detailed diagram Figure 2 A flowchart of one embodiment of the steps of the method;

[0056] Figure 6 Another embodiment of a register bank of a direct memory access control circuit is schematically illustrated in block form;

[0057] Figure 7 is a timing diagram illustrating one embodiment of a method for data transfer via direct memory access;

[0058] Figure 8 The diagram is schematically shown in the form of a box. Figure 6 An example of a register set of a direct memory access control circuit of an embodiment of the present invention;

[0059] Fig. 9 The diagram is schematically shown in the form of a box. Figure 8 An alternative embodiment of the register set of; and

[0060] Fig.10The diagram is schematically shown in the form of a box. Figure 6 Another example of a register set of a direct memory access control circuit of an embodiment. DETAILED DESCRIPTION

[0061] In different drawings, the same elements are designated by the same reference numerals. In particular, structural and / or functional elements common to different embodiments may be designated by the same reference numerals and may have the same structure, size and material properties.

[0062] For the sake of clarity, only those steps and elements that are useful for understanding the described embodiments are shown and described in detail. In particular, various parameters currently used for data transfer via direct memory access are not described in detail, and the described embodiments are compatible with these common parameters. In addition, various electronic systems in which direct memory access controllers are provided are not described in detail, and the described embodiments are compatible with most of these common electronic systems.

[0063] Throughout this disclosure, the term “connected” is used to specify a direct electrical connection between circuit elements with no intervening elements other than conductors, while the term “coupled” is used to specify an electrical connection between circuit elements that may be direct or may be via one or more intervening elements.

[0064] In the following description, when referring to terms that define absolute positions (such as terms "front", "back", "up", "down", "left", "right", etc.) or relative positions (such as terms "above", "below", "over", "under", etc.), or terms that define directions (such as "horizontal", "vertical", etc.), unless otherwise specified, this refers to the orientation of the figure.

[0065] The terms "about," "substantially," "approximately," and "approximately" are used herein to designate a tolerance of plus or minus 10%, preferably plus or minus 5%, of the value in question.

[0066] As an example, Figure 1 There is shown very schematically in block form an embodiment of an electronic circuit 1 of the type to which the embodiments to be described are applicable.

[0067] The electronic system 1 includes a central processing unit 11 (CPU), such as a state machine, a microprocessor, a programmable logic circuit, etc. One or more memories are included in the system (at least one of which is a RAM 12 (MEM) of the SRAM type, for example). At least one input / output interface 13 (I / O) for communication (for example, a serial bus type) can communicate with the outside of the system 1. The system also includes a direct memory access control circuit 14 (DMA), one or more data, address and / or control buses between different elements inside the system 1 (here shown in the form of a single bus 15).

[0068] In addition, the system 1 may integrate other functions represented by the block 16 (FCT), such as a processor dedicated to image processing, other interfaces, other memories, etc., depending on the application.

[0069] The system 1 is configured to perform various applications, such as image processing, video encoding and / or decoding, processing of data originating from sensors, etc. Such applications require data transfer between elements inside the system 1 via a bus 15. In order to make the operation of the system 1 smooth and reduce the load of the central processing unit 11, such data transfer is performed by direct memory access under the control of the circuit 14. In this embodiment, the circuit 14 includes a plurality of data transfer channels. Each channel of the circuit 14 enables data transfer to be performed between two elements (circuits and / or memories) of the system 1. Each channel is associated with a register group, which stores the parameters of the transfer for each data transfer performed on the channel.

[0070] When an application must be executed by the system 1, the central processing unit 11 configures the circuit 14 so that the circuit 14 reserves one of these channels for the application. All data transfers of the application are then performed via the channel reserved for the application. In the described embodiment, the source element and / or the destination element of the data to be transferred can change during the execution of the application.

[0071] Figure 2 is a flowchart illustrating an embodiment of a method for data transfer via direct memory access in block form. More specifically, Figure 2 The diagram illustrates that for a given application, the sequential updates and Figure 1 A method of associating register groups with channels of circuit 14.

[0072] In an initial step 200 (allocate channel), a channel is assigned to an application by programming a register set associated with the channel with the parameters of the first data transfer of the application. This step is equivalent to indicating to the circuit 14 which linked list of records should be used to parameterize the transfer that will occur on the channel. Each record in the list determines the memory address of the next record. Each record also determines the parameters of the corresponding data transfer, such as an indication that the transfer involves data or data blocks, the starting address of the address range of the source storing the data or data blocks to be transferred, the starting address of the address range of the destination to which the transferred data or data blocks should be copied, the number of data or data blocks to be transferred, the size of the data, the number of data per block, the address offset between two consecutive data or between two consecutive blocks to be transferred, etc. Therefore, each record can correspond to the transfer of a fragment of data, a plurality of data, a data block or a plurality of blocks between a source and a destination.

[0073] According to one embodiment, at step 200 the register set is programmed by reading a first record in the list from the memory 12 at a memory address provided by the central processing unit 11 and by programming the register set based on this record.

[0074] According to another embodiment, at step 200, the register set is directly programmed, for example, at initialization of the system 1 or by the central processing unit 11, without reading the record from the memory 12. Specifically, then, the record of the first record in the list is programmed in the register set.

[0075] After the register set is programmed to allocate the channel to the application, the central processing unit 11 indicates to the circuit 14 that the data transfer for executing the application can start.

[0076] At the next step 202 (Execute Transfer), the circuit 14 performs a data transfer parameterized by the contents of the register set of the channel on the channel reserved for the application, it being understood that such a transfer may involve multiple data or multiple blocks of data.

[0077] A test 203 (REPEAT?) is then performed to determine, from the contents of the register set, whether the data transfer performed at the previous step 202 should be repeated and its parameters stored in the register set.

[0078] If the transfer must be repeated (output of block 203 is yes), the method continues with step 202. It can thus be understood that the transfer is performed in a loop, since the contents of the register set are not modified.

[0079] If the last transfer does not have to be repeated (no output of block 203), the method continues with test 204 (next LLI?). This test determines whether there is a next record in the list based on the current content of the register set, in other words, whether there is still at least one transfer to be performed for the application.

[0080] If there is no next record in the list (no output of block 204), test 204 is followed by step 206 (END), where the channel is released and can thus be allocated to a new application.

[0081] If there is a next record (output of block 204 is yes), test 204 is followed by step 208 (load next LLI) in which the next record is read from memory 12 by circuit 14 and the register set is updated with parameters for the next data transfer to be applied. The method then proceeds to step 202.

[0082] It should be noted that you can modify Figure 2 In particular, test 203 and test 204 may be performed simultaneously.

[0083] As an example, consider in the remainder of this disclosure the case where the transfer that should occur on the channel is not performed at the data block level, but only at the data level. Also consider when the transfer corresponds to the transfer of multiple data, the data are stored one by one in the source address range and copied one by one to the destination address range.

[0084] Figure 3 An embodiment of a register bank associated with a data transfer channel of the circuit 14 is schematically shown in block form.

[0085] In this example, the register set includes five registers R1, R2, R3, R4 and R5, which enable temporary storage of parameters for data transfer. Registers R1, R2, R3, R4 and R5 are intended to store the starting address S@ of the source of the data to be transferred, the starting address D@ of the address range of the destination of the data to be transferred, the number NB of the data to be transferred, the size BL of the data to be transferred, and the address NLLI@ of the next record in the memory 12, respectively. In the rest of the present disclosure, a linked list register or LLR register designates a register for storing information related to a linked list of records, specifically the address NLLI@. Preferably, register LLR is the last register in the register set, in this example register R5.

[0086] In this embodiment, one of the plurality of registers (preferably, an LLR register) is also intended to store information related to the next record in the list. This information determines the number of fields of the next record in the list. Each field of the record, for example, represents the content to be programmed in the corresponding register at the next update of the register group. Preferably, during this update, each field is directly copied to the corresponding register. The information related to the next record in the list also determines the register to which each field of the next record is assigned. This information is stored by the bits (e.g., five bits U1, U2, U3, U4 and U5) of the LLR register R5. In this embodiment, bits U1, U2, U3, U4 and U5 are assigned to registers R1, R2, R3, R4 and R5, respectively, and the value of each bit U1, U2, U3, U4, U5 determines whether the next record includes a field representing the content to be programmed in the register (respectively R1, R2, R3, R4, R5). For example, if bit U1 is at a first binary value, eg '1', the next record comprises a field representing what is to be programmed in register R1, and if the bit is at a second binary value, eg '0', the next record comprises no such field.

[0087] As an example, regarding Figure 2The test 203 described consists in verifying that all bits U1 to U5 are at '0' and that the address @NLLI is not empty. If this is true, this means that the register set does not have to be updated and the last performed pass should be repeated.

[0088] Still as an example, about Figure 2 The test 204 described consists of verifying whether the address @NLLI is empty. If this is true, this means that there is no next record and all passes of the application have been performed.

[0089] It should be noted that, as an example, information related to the number of fields of the next record and the register to which each of these fields is allocated, an indication that the transmission should be repeated and / or an indication that the list does not contain the next record may be represented in a form different from that described above.

[0090] Figure 4 Schematically shows a circuit comprising a Figure 3 A memory of an embodiment of a linked list of registers for programming records (e.g., Figure 1 of memory).

[0091] The memory 12 is divided into a plurality of memory words 41 of a fixed size (e.g. 4 bytes), each memory word being associated with a memory address 43. In this example, the memory 12 contains a linked list of records formed by three records LLI-1, LLI-2 and LLI-3. The fields of the same record are recorded one after another in the memory 12 (here starting from the memory address of the first field of the record). In this example, each field occupies one memory word 41. As a variant, each field may require more than one memory word for its memory storage, or a memory word may contain more than one field. Preferably, the fields of each record follow each other in the same order as the corresponding registers of the register group. In this example, the memory address of a record corresponds to the address of the first field of the record.

[0092] In this example, consider the following situation: Figure 2 At step 200, the register set is programmed based on the first record LLI-1 in the list. Figure 4As shown in , the first record LLI-1 then includes as many fields as registers, five in this example, so that each register can be programmed using the fields of the record. More specifically, the record LLI-1 includes consecutive fields C1, C2, C3, C4 and C5, representing the content to be programmed in the registers (R1, R2, R3, R4 and R5, respectively). In this example, the fields C1, C2, C3 and C4 of the record LLI-1 represent the address S1@, the address D1@, the number NB-1 and the size BL-1, respectively. The field C5 of the record represents the address @k2 of the next record LLI-2 in the memory 12, as well as information related to the next record LLI-2. In this example, the information related to the next record is in the form of five bits with values ​​'1', '0', '1', '0' and '1', which correspond to the bits U1, U2, U3, U4 and U5 of the record R5, respectively. In this example, the first field C1 of record LLI-1 is recorded in the address memory word @k1, and the following fields C2, C3, C4 and C5 are recorded in the following memory words of the corresponding addresses @k1+4, @k1+8, @k1+12 and @k1+16, where each memory word occupies 4 bytes.

[0093] The second record LLI-2 comprises consecutive fields C1, C3 and C5, which represent the contents to be programmed in registers R1, R3 and R5, respectively. Fields C1 and C2 represent the address S2@ and the number NB-2, respectively, and field C5 represents the address @k3 of the next record LLI-3 and five bits with values ​​'0', '1', '1', '1' and '1', which correspond to bits U1, U2, U3, U4 and U5 of register R5, respectively. In this example, the first field C1 of the record LLI-2 is recorded in the address memory word @k2, and the following fields C3 and C5 are recorded in the following memory words at the corresponding addresses @k2+4 and @k2+8.

[0094] The third record LLI-3 includes consecutive fields C2, C3, C4 and C5, which represent the contents to be programmed in registers R2, R3, R4 and R5, respectively. Fields C2, C3 and C4 represent the address D3@, the number NB-3 and the size BL-3, respectively. In the example shown, field C5 represents the zero address @NULL and the five bits U1 to U5 with the value "0", which indicates that the record LLI-3 is the last one in the list and the transfer corresponding to this record does not have to be repeated. In this example, the first field C2 of the record LLI-3 is recorded in the address memory word @k3, and the following fields C3, C4 and C5 are recorded in the following memory words of the corresponding addresses @k3+4, @k3+8 and @k3+12.

[0095] In the above list, at least some of the records stored in the memory contain a number of fields that is smaller than the number of registers of the register set that are updated based on these records. Therefore, the storage capacity of the memory 12 can be reduced relative to the storage capacity of a memory in which each record of the linked list has as many fields as registers of the register set. The reduction in the storage capacity of the memory 12 results in a reduction in its surface area and static power consumption.

[0096] Figure 5 The above description is illustrated in the form of a flow chart Figure 2 Step 208 of the method is to update the register set based on the records in the linked list of records stored in the memory.

[0097] At initialization step 500 (i=1), in this example, a loop variable i (i is an integer) is initialized to 1.

[0098] At the next test step 502 (Ui=1?), circuit 14 tests the current value of bit Ui of LLR register R5 to determine whether the next record contains a field Ci representing the content to be programmed in register Ri.

[0099] During step 502, if the current value of the bit Ui of the LLR register R5 is '1' (output of block 502 is yes), this means that the next record includes a field Ci representing the content to be programmed in the register Ri. This test is then followed by a step 504 for programming the register Ri with this content (Ri<=Ci). Step 504 is followed by a test 508 (i=5?), during which it is verified whether the current value of each bit Ui of the register R5 has been tested. If so (output of block 508 is yes), the update of the register group based on the next record is completed (end of block, 510). Otherwise (output of block 508 is no), the method continues at step 512 (i=i+1), where the variable i is incremented, after which the method loops back to step 502.

[0100] During step 502, if the current value of bit Ui of LLR register R5 is '0' (output of block 502 is No), this means that the next record does not include a field Ci representing the content to be programmed in register Ri. The method then proceeds directly to step 508 and the content of register Ri remains unchanged.

[0101] When from Figure 4When updating a register group associated with a channel, the above method makes it possible to update only certain registers in the register group, preferably only registers with modified content between two consecutive passes. This results in a reduction in the number of accesses to the memory 12 relative to the case where all registers in the group would be updated. This reduction in the number of accesses to the memory 12 results in a reduction in the dynamic power consumption of the memory 12 and, more generally, Figure 1 The dynamic power consumption of system 1 is reduced. The advantage here lies in the fact that two consecutive data transfers on the channel reserved for the application usually have certain identical parameters.

[0102] It should be noted that the order and / or number of steps of the above method may be modified. For example, all bits Ui may be read first, and then all updates of the registers may be performed according to the values ​​of the read bits.

[0103] In addition, about Figures 1 to 5 The described embodiments are applicable to register sets of other circuits than direct memory access controllers to parameterize the execution of tasks by that circuit.

[0104] In the above embodiment, as in the case of the direct memory access control circuit, once the channel is allocated to the application (step 200, Figure 2 ) and the central processing unit 11 has authorized the circuit 14 to perform the transfers of the application, the circuit 14 automatically performs all these transfers without intervention of the central processing unit 11. After performing all the transfers, the circuit 14 notifies the central processing unit 11, which can then assign the channel to another application. Therefore, the synchronization between two applications executed on two different channels of the circuit 14 can only be performed by the central processing unit 11 at the beginning of the execution of one of the two applications, or at the end of the execution of one of the two applications (when all the records corresponding to the data transfers of the application have been read and the corresponding transfers have been performed).

[0105] Figure 6 An example of another embodiment of a register set of a data transfer channel of the circuit 14 is schematically shown in block form.

[0106] Here Figure 6 The register set includes six registers R1, R2, R3, R4, R5 and R6. In this example, Figure 6 The registers R1, R2, R3 and R4 are similar to Figure 3 The registers R1, R2, R3 and R4 of the register bank are shown in FIG. 1 . The register R5 here is intended to store the transfer start condition ctrl-in and the transfer end event ctrl-out. The register R6 forms a linked list register (LLR) of the register bank and is as follows: Figure 3 , it is intended to store the address NLLI@ of the next record and information related to the next record, in particular the number of fields of the record and to which register each field of the next record is allocated. This information is here stored in the form of six bits U1, U2, U3, U4, U5 and U6 associated with registers R1, R2, R3, R4, R5 and R6 respectively.

[0107] About Figures 1 to 5 The description is similar to that of performing a record-based query on a linked list of records. Figure 6 The update of the register group of the register R6, the records in the list are adjusted accordingly. In particular, each record may include an additional field C6 (not shown) representing the content to be programmed in the register R6. In addition, for each record, the field C6 of the record may then include six bits corresponding to the six bits U1 to U6 of the register R6.

[0108] In an alternative embodiment, the condition ctrl-in and the event ctrl-out are stored in one of the registers R1 to R4 and R6, and the condition ctrl-in can be stored in another register other than the one storing the event ctrl-out. For example, this variation is implemented when one or more of the registers R1 to R4 and R6 contain unused bits, thereby enabling the storage of information ctrl-in and ctrl-out. This makes it possible to suppress the register R5, the LLR register R6 from being assigned the number R5 at this time.

[0109] Figure 7 is a flow chart illustrating an embodiment of data transfer via direct memory access. More specifically, Figure 7 A more detailed illustration Figure 2 Step 202 of the method.

[0110] In a step 801 (ctrl-in?) implemented by the circuit 14, all parameters of the data transfer to be performed are stored in registers of the register bank. Step 801 consists in detecting a transfer start condition ctrl-in (stored in register R5 in this example). As long as the condition ctrl-in is not detected (output of block 801 is no), step 801 is repeated. When the condition ctrl-in is detected (output of block 801 is yes), the method proceeds with step 802 (carry out transfer), during which a data transfer parameterized by the contents of the register bank is performed, and then, once the transfer is completed, during a step 804 (generate ctrl-out), the circuit 14 generates an event ctrl-out.

[0111] In this embodiment, when the end of a first data transfer on a first channel reserved for a first application generates an event ctrl-out, and a condition ctrl-in for starting a second transfer on a second channel reserved for a second application corresponds to the detection of an event ctrl-out, the second transfer can only be started after the generation of the event ctrl-out for the first transfer. Thus, the first and second transfers and therefore the first and second applications can be synchronized with each other directly at the level of the circuit 14, without the intervention of the central processing unit 11 and while these applications are being executed. More generally, providing condition ctrl-in and event ctrl-out for at least some of the data transfers of a plurality of applications executed by the system 1 makes it possible to synchronize these applications together without using a central processing unit, which can be set to standby or even switched off during the execution of these applications.

[0112] In an alternative embodiment, an additional parameter is provided indicating at what time during the transfer of multiple data the condition ctrl-in should be detected, for example before the first fragment of the transferred data or before each fragment of the transferred data. Similarly, an additional parameter is provided indicating at what time during the transfer of multiple data the event ctrl-out should be generated, for example after the last fragment of the transferred data or after each fragment of the transferred data. The registers and records in the list are then adjusted to integrate such additional parameters. The Figure 7 For example, during the transfer of multiple data, if the condition ctrl-in is detected before the transfer of a fragment of data and the event ctrl-out is generated after the transfer of the fragment of data, steps 801, 802 and 804 are implemented for each piece of data transferred, and step 802 corresponds to the transfer of the fragment of data.

[0113] Providing one or more additional parameters to indicate when the passing of the condition ctrl-in should be detected and when the event ctrl-out should be generated enables control of the granularity with which synchronization between applications executed in parallel by the system 1 is performed.

[0114] It should be noted that the condition ctrl-in of a transfer on a channel may correspond to the detection of an event other than the event ctrl-out generated during a transfer on another channel, for example, to the detection of an event generated in system 1, for example originating from block 13 (I / O) of system 1.

[0115] As an example, each condition ctrl-in may correspond to the detection of a level change, for example, the signal corresponding to the condition changes from a high level to a low level or vice versa. For example, each event ctrl-out includes changing the level of the signal corresponding to the event.

[0116] It should be noted that it is possible to implement without bits U1 to U6 Figure 6 and Figure 7 In this case, since there are no conditional updates of registers, each record in the linked list contains as many fields as there are registers.

[0117] In an alternative embodiment, in combination with Figures 3 to 7 The described registers and records may integrate one or more additional parameters to manage the transfer of data blocks, and / or source and / or destination address ranges, address shifts between two consecutive data or two data blocks to be transferred.

[0118] In addition, in the case where registers and records are capable of managing the transfer of data blocks, it can be considered that during the transfer of multiple data blocks, the condition ctrl-in is detected before the transfer of each block and / or the event ctrl-out is generated after the transfer of each block. The parameters indicating the time when the condition ctrl-in should be detected and / or the time when the event ctrl-out should be generated will then be adjusted accordingly, as well as the combination of Figure 7 Describe the method.

[0119] Figure 8 The diagram is schematically shown in the form of a box. Figure 6 An example of a register set of a direct memory access control circuit of an embodiment of the present invention. Figure 8 In the example, only register R5 is shown, and registers R1 to R4 and R6 are similar to those in Figure 6 Same as those described.

[0120] In this embodiment, Figure 6 The described condition ctrl-in comprises a parameter ctrl-in-req which represents the identity of the client of the transfer parameterized by the content of a register in the register set associated with the channel of the transfer. In other words, the parameter ctrl-in-req represents the identity of the element of the system 1 (e.g. the functional block 16 (FTC)) that requires the transfer of data. Thus, for each transfer of a record corresponding to the linked list of records, the client of the transfer is dynamically associated with the channel on which the transfer should take place.

[0121] More specifically, the identification of the client of the transfer is equivalent to identifying which is the request signal that will cause the transfer. Thus, when the data transfer has been parameterized by programming the register set associated with the transfer channel according to the corresponding record of the linked list of records, the transfer can only start after the client of the transfer transmits a request, or in other words, the start of the transfer is conditional on the request.

[0122] In this embodiment, the circuit 14 thus receives memory access requests directly from clients of data transfers taking place on channels of the circuit 14. The requests are then processed directly in the circuit 14 which, based on the information contained in the register set associated with the transfer channel, is able to know to which channel each request should be transmitted, or in other words, for each request, which is the channel on which the planned transfer is to be started conditional on the reception of the request.

[0123] By comparison, in an embodiment not including the parameter ctrl-in-req, in order for the channels of the circuit 14 to know the clients of the transfers on the channels, each potential client of the data transfer (i.e. each element of the system 1 capable of requesting the data transfer) is statically associated with at least one given channel of the circuit 14, for example, at the initialization of the system 1, and multiple clients can be associated with the same channel. The system 1 then comprises a request routing circuit external to the DMA circuit 14, which is configured to receive all data transfer requests and, according to the static client / channel assignment, transmit each received request to each channel having a client that has transmitted a request associated therewith.

[0124] Embodiments including the parameter ctrl-in-req have advantages over those embodiments not including the parameter ctrl-in-req.

[0125] In particular, the provision of the parameter ctrl-in-req enables the use of additional circuitry for routing data transfer requests to be avoided, whereby the system 1 consumes less power and occupies a reduced surface area relative to the case where such routing circuitry is provided.

[0126] Additionally, in embodiments including the parameter ctrl-in-req, the application may include multiple clients dynamically associated with a channel reserved by the application. However, in embodiments without the parameter ctrl-in-req, the application may only include a single client due to the static client / channel assignment. This difference and the resulting advantages will be further detailed below with reference to the following example execution, wherein:

[0127] The first client performs first data transfers using the memory 12, each first transfer corresponding to writing a segment of data from the first client to the memory;

[0128] the second client performs a second data transfer using the memory 12, each second transfer corresponding to a segment of the data stored in the memory being read out by the second client; and

[0129] After each writing of a segment of data to the memory during a first transfer, the segment of data is read from the memory during a second transfer, so that the second transfer can only occur after the first corresponding transfer.

[0130] In an embodiment including the parameter ctrl-in-req, the implementation of the example of the above execution can be performed by means of a single application including the first and second transfers (and therefore the first and second clients). In other words, the same linked list of records can be used to configure the first and second transfers on the same channel. More specifically, the first transfer is configured by programming the parameters of the first transfer (specifically, the parameter ctrl-in-req) in the registers of the register bank of the channel. Then, the transmission of the request of the first client causes the first transfer to be implemented on the channel, after which the second transfer is configured on the same channel by programming the parameters of the second transfer (specifically, the parameter ctrl-in-req) in the registers of the register bank of the channel. Then, the transmission of the request of the second client causes the second transfer to be implemented on the channel. Execution continues by repeating the following steps for the channel: programming the registers with the parameters of the first transfer, receiving the request from the first client, implementing the first transfer on the channel, programming the registers with the parameters of the second transfer, receiving the request from the second client, and implementing the second transfer on the channel.

[0131] However, in an embodiment that does not include the parameter ctrl-in-req, the implementation of this example is performed by means of a first application corresponding to the first transfer (i.e., corresponding to the first client) and a second application corresponding to the second transfer (and therefore corresponding to the second client). In other words, the first linked list of records is used to configure the first transfer on the first channel, the first channel having the first client statically associated therewith, and the second linked list of records is used to configure the second transfer on the second channel, the second channel having the second client statically associated therewith. As a result, during the first transfer on the first channel, the second channel is reserved by the second application but is not used.

[0132] As can be understood from the above examples, the provision of the parameter ctrl-in-req enables the dynamic association of a client with a channel of the circuit 14, which results in a reduction in the time that the channel is reserved when the channel is not used and / or a reduction in the number of necessary channels. In particular, the reduction in the number of channels of the circuit 14 results in a reduction in the power consumption and surface of the circuit 14 (and more generally, the system 1).

[0133] Fig. 9 The diagram is schematically shown in the form of a box. Figure 8 An alternative embodiment of a register set.

[0134] In this variant, in addition to the parameter ctrl-in-req, the condition ctrl-in includes a parameter ctrl-in-req-mode, which indicates at least the time of the transfer when the request from the parameter ctrl-in-req identified should be received for the transfer parameterized by the content of the register group. In other words, when the transfer parameterized by the content of the register group corresponds to a plurality of similar transfers (e.g., a plurality of data transfers or data block transfers), the parameter ctrl-in-req-mode indicates which of the similar transfers are conditional on receiving a request from the client of the transfer. For example, for a transfer comprising the transfer of a plurality of data or a plurality of data blocks, the parameter ctrl-in-req-mode indicates that the request from the client should be received before each data transfer, before each data block transfer, or only before the transfer of the first fragment or the first data block of the data. In this last case, the data transfer or the data block transfer can be performed after the first fragment or the first data block of the data is transferred, without the need for the client of the transfer to transmit a request.

[0135] Multiple similar transfers, for example, multiple transfers of fragments or blocks of data with the same client are considered as examples, and it is further considered that each of the similar transfers should only be started after the circuit 14 receives a request from the client, or in other words, each of the transfers is conditional on the client transmitting a request. The provision of the parameter ctrl-in-req-mode enables such similar transfers to be collected in the form of a single record of a linked list of records, and then a single update of the register group associated with the transfer channel is performed to parameterize all similar transfers. In the absence of the parameter ctrl-in-req-mode, each of the similar transfers should correspond to a different record in the list.

[0136] Therefore, about Fig. 9 The alternative embodiment described makes it possible to reduce the number of records in the list, which can make it possible to reduce the size of the memory 12. This variation also makes it possible to reduce the number of accesses to the memory 12 and the number of updates to the register groups associated with the channels of the circuit 14.

[0137] Fig.10 The diagram is schematically shown in the form of a box. Figure 6 Another example of a register set of a direct memory access control circuit of an embodiment of the present invention. Fig.10 In the example, only register R5 is shown, and registers R1 to R4 and R6 are similar to those in Figure 6 Same as those described.

[0138] About Figure 8Compared to the described embodiment, the transfer start condition ctrl-in includes, in addition to the parameter ctrl-in-req, the parameter ctrl-in-trig, the parameter ctrl-in-trig-mode and the optional parameter ctrl-in-trig-pol, the parameter ctrl-in-trig indicating the identification of the signal that is conditional on the transfer start, the parameter ctrl-in-trig-mode indicating the time when the modification of the signal should be detected, and the parameter ctrl-in-trig-pol indicating the type of modification, i.e., the rising edge, the falling edge or the level change of the signal that is the condition for the transfer start. In other words, when the transfer parameterized by the content of the register group corresponds to a plurality of similar transfers (e.g., a plurality of data transfers or a data block transfer), the parameter ctrl-in-trig-mode indicates which of the similar transfers is conditional on the detection of the modification of the signal identified by the parameter ctrl-in-trig, the type (or polarity) of the modification being indicated here by the parameter ctrl-in trig-pol. For example, for a transfer comprising transferring a plurality of data or a plurality of data blocks, the parameter ctrl-in-trig-mode indicates that a modification of the signal identified by the parameter ctrl-in-trig should be detected before each data transfer, before each data block transfer, or only before the transfer of the first fragment of data or the first data block. In addition, the parameter ctrl-in-trig-mode may also indicate that, for the current transfer parameterized by the contents of the register group associated with the transfer channel, the transfer is not conditional on the detection of a modification of the signal identified by the parameter ctrl-in-trig.

[0139] In this embodiment, the data transfer parameterized by the content of the register group associated with the transfer channel can only start after the client receives a request for transfer by the circuit 14, and most likely after the circuit 14 detects a modification of the signal identified by the parameter ctrl-in-trig, the type of modification in this example being indicated by the parameter ctrl-in-trig-pol. In addition, according to the parameters ctrl-in-trig-mode and / or ctrl-in-req-mode, when the transfer corresponds to a plurality of similar transfers, the start of each of the similar transfers may or may not be conditional on the receipt of a request originating from the client of the transfer and / or the detection of a modification of the signal identified by the parameter ctrl-in-trig.

[0140] In this embodiment, it is further considered that, for each channel, the transfer end event ctrl-out is a modification of the transfer end signal associated with the channel. Here, the event ctrl-out includes a parameter ctrl-out-mode and an optional parameter ctrl-out-pol, the parameter ctrl-out-mode indicating the time when the transfer end signal of the channel should be modified, and the parameter ctrl-out-pol indicating the modification polarity of the signal, that is, whether the transfer end event is a rising edge, a falling edge, or a change in level of the transfer end signal associated with the channel under consideration.

[0141] As an example, the parameter ctrl-out-mode indicates when the conditional ctrl-out should be generated, i.e., when the transfer end signal associated with the channel should be modified, which occurs only after the last fragment or the last block of data is transferred, after each fragment or each block of data is transferred, or not at all during transfer.

[0142] As an example, the signal identified by the parameter ctrl-in-trig may be a transfer end signal of a channel or any other signal internal to the system 1 , such as an event signal provided by an element of the system 1 for example a counter of the system 1 .

[0143] Can be combined with about Figures 6 to 10 Examples of embodiments and alternative embodiments are described, and other variations will occur to those skilled in the art.

[0144] In particular, regarding Fig. 9 The described alternative embodiments are applicable to Fig.10 Described embodiments.

[0145] In other alternative embodiments, in the same manner as the parameter ctrl-in-trig-pol may be provided to indicate the type of modification of the signal identified by the parameter ctrl-in-trig as a condition for data transfer, the parameter ctrl-in-req-pol may be provided to indicate which type of modification of the request signal forms the request from the client associated with the request signal. In addition, each of the parameters ctrl-in-trig-pol and ctrl-in-req-pol may represent not only a given type of modification (rising edge, falling edge, or level change) but also a high level or a low level detected on the corresponding signal or request. It should be noted that in the absence of the parameter ctrl-in-trig-pol and / or the parameter ctrl-in-req-pol, the polarity may be defined by default.

[0146] In other alternative embodiments, although not described in detail, the parameters ctrl-in-trig, ctrl-in-trig-mode, ctrl-in-trig-pol, ctrl-in-req, ctrl-in-req-mode, ctrl-in-req-pol, ctrl-out-mode, and ctrl-out-pol may be omitted. In particular, the parameters ctrl-in-trig, ctrl-in-trig-mode, ctrl-in-trig-pol, ctrl-out-mode, and / or ctrl-out-pol may be provided independently of the parameters ctrl-in-req, ctrl-in-req-mode, ctrl-in-req-pol, and vice versa.

[0147] Although the parameters ctrl-in-trig, ctrl-in-trig-mode, ctrl-in-trig-pol, ctrl-in-req, ctrl-in-req-mode, ctrl-in-req-pol, ctrl-out-mode and / or ctrl-out-pol are preferably stored in the same register, or in other words, the same fields of a record originating from a linked list of records, the parameters may be stored in different registers.

[0148] Can be implemented without bits U1 to U6 Figure 8 , Fig. 9 and Fig.10 In this case, since there is no conditional update of registers, each record in the linked list contains as many fields as registers.

[0149] From the above about Figures 7 to 10 It can be understood from the description that the condition ctrl-in is actually at least partially determined by the parameter ctrl-in-req and / or at least partially determined by the parameter ctrl-in-trig. In addition, the time or multiple times of detecting the condition ctrl-in (especially during the transfer corresponding to multiple similar transfers) are at least partially determined by the parameter ctr-in-req-mode and / or at least partially determined by the parameter ctrl-in-trig-mode.

[0150] Based on the functional instructions given above, Figure 7 Methods and about Figures 1 to 5 The records described can be applied to Figure 8 , Fig. 9 and Fig.10 Described embodiments and variations.

[0151] More generally, specific embodiments have been described, and those skilled in the art may combine various elements of these various embodiments and variations without showing any inventive step. In addition, those skilled in the art will recognize various changes and modifications. In particular, the number of registers, the number of parameters stored by the register group, and / or the number of parameters stored by each register may vary.

[0152] In addition, other parameters may be provided. For example, in the case of data transfer via direct memory access, the parameters may indicate whether the data and / or data blocks corresponding to the transfer of the record should be transferred one by one or in a burst manner.

[0153] These changes, modifications and improvements are intended to be part of this disclosure and are intended to fall within the spirit and scope of the present invention. Therefore, the foregoing description is only exemplary and not restrictive. The present invention is limited only by the following claims and their equivalents.

Claims

1. An electronic system comprising: Direct memory access control circuit; and a memory comprising a linked list of records, the linked list of records representing a plurality of data transfers via the direct memory access control circuit, each record representing parameters of an associated data transfer of the plurality of data transfers, the parameters of each record comprising a transfer start condition of the associated data transfer and a transfer end event of the associated data transfer; Therein, for each record, the parameters include an indication of whether the data transfer is a transfer of a fragment of data, a plurality of data, a block of data, or a plurality of blocks of data.

2. The system of claim 1, wherein for each record, the parameters include an indication of a client of the associated data transfer.

3. The system of claim 2, wherein the transfer start condition is at least partially determined by the client of the associated data transfer.

4. The system of claim 1, wherein for each record, the parameters include an identification of a transfer start signal, the transfer start condition being determined at least in part by the transfer start signal.

5. The system of claim 1, wherein the parameter includes, for each record, an indication of a time when the transfer start condition should be detected or a time when the transfer start condition should not be detected.

6. The system of claim 1, wherein the parameters include, for each record, an indication of a time when the end-of-delivery event should be generated or a time when the end-of-delivery event should not be generated. The system of claim 6 , wherein the end-of-delivery event is a modification of an end-of-delivery signal.

8. The system of claim 1 , wherein each record comprises a first field having information for determining the number of fields of the next record in the linked list of records, each field of a record representing content to be programmed in a register of a register bank of the direct memory access control circuit.

9. The system of claim 8, wherein the first field includes information for determining in which registers the content should be programmed.

10. The system of claim 9, wherein the first field comprises a plurality of bits, wherein each bit of the plurality of bits identifies a register, and values ​​of the plurality of bits determine the field of the record to be programmed.

11. A system according to claim 1, wherein for each record, the parameter includes an indication of a time when the transfer start condition should be detected or a time when the transfer start condition should not be detected, and the time when the transfer start condition should be detected is a time selected from the following: before each data transfer, only before the transfer of the first fragment of data, before the transfer of each data block, or only before the transfer of the first data block.

12. A memory comprising a linked list of records, the linked list of records representing a plurality of data transfers via a direct memory access control circuit, each record representing parameters of an associated data transfer of the plurality of data transfers, the parameters of each record comprising a transfer start condition of the associated data transfer and a transfer end event of the associated data transfer; Therein, for each record, the parameters include an indication of whether the data transfer is a transfer of a fragment of data, a plurality of data, a block of data, or a plurality of blocks of data.

13. A memory according to claim 12, wherein for each record, the parameters include an indication of a client of the associated data transfer.

14. The memory of claim 13, wherein the transfer start condition is determined at least in part by the client of the associated data transfer.

15. The memory of claim 12, wherein for each record, the parameters include an identification of a transfer start signal, the transfer start condition being determined at least in part by the transfer start signal.

16. The memory of claim 12, wherein the parameter includes, for each record, an indication of a time when the transfer start condition should be detected or a time when the transfer start condition should not be detected.

17. The memory of claim 12, wherein the parameters include, for each record, an indication of a time when the end-of-delivery event should be generated or a time when the end-of-delivery event should not be generated.

18. The memory according to claim 12, wherein each record includes a first field having information for determining the number of fields of a next record, each field of a record representing content to be programmed in a register of a register group of the direct memory access control circuit.

19. A method of operating a system comprising a first component and a second component, the method comprising performing a data transfer from the first component to the second component via direct memory access, wherein the data transfer is performed on a channel of a direct memory access circuit, the data transfer on the channel being parameterized by a corresponding record in a linked list of records stored in a memory, the linked list of records representing a plurality of data transfers via the direct memory access control circuit, each record representing parameters of an associated data transfer of the plurality of data transfers, the parameters of each record comprising a transfer start condition of the associated data transfer and a transfer end event of the associated data transfer; Therein, for each record, the parameters include an indication of whether the data transfer is a transfer of a fragment of data, a plurality of data, a block of data, or a plurality of blocks of data.

20. The method of claim 19, wherein each record in the linked list corresponds to an update of a register set associated with the channel.

21. The method of claim 20, wherein the current contents of the register set parameterize a corresponding transfer on the channel.

22. The method of claim 21, wherein for each record, the corresponding transfer is started only when the transfer start condition is detected.

Images