Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package includes a substrate having a surface, and a conductive element on the first surface and electrically coupled to the substrate. The conductive element has a principal axis forming an angle of less than 90 degrees with the surface.

Description

Technical Field

[0001] This disclosure relates to a semiconductor package and a method of manufacturing the same, and more particularly to a semiconductor package having a conformal shield. Background Technology

[0002] As operating speeds increase and device sizes decrease, semiconductor packaging may encounter electromagnetic shielding issues. For example, higher clock speeds result in more frequent signal transitions between different layers and increase the intensity of electromagnetic emissions at high frequencies or short wavelengths. Electromagnetic emissions can radiate from one semiconductor device to adjacent semiconductor devices. When electromagnetic emissions from adjacent semiconductor devices are of high intensity, electromagnetic interference (EMI) can adversely affect the operation of the semiconductor devices. If the electronic system has a high density of semiconductor devices, the EMI within the semiconductor devices becomes even worse.

[0003] Along with vehicle applications, machine-to-machine applications, and wearable smart device applications, devices or modules operating at high speeds can implement conformal shielding between systems and modules or between individual modules. Some comparative conformal shielding operations use plastic encapsulations and conductive materials, as well as sputtering or spraying, to achieve segmented shielding and electromagnetic shielding. Some manufacturing processes for such devices have low throughput and high manufacturing costs. Summary of the Invention

[0004] Some embodiments of this disclosure provide a semiconductor package comprising a substrate having a surface, and a conductive element on the first surface and electrically coupled to the substrate. The conductive element has a principal axis forming an angle of less than 90 degrees with the surface.

[0005] Some embodiments of this disclosure provide a semiconductor package comprising a substrate having a first surface; a conductive element on the first surface, the conductive element having side surfaces; and an encapsulation covering the side surfaces of the conductive element. A second surface extends through the conductive element and the encapsulation. The second surface is parallel to the first surface, and the conductive element on the second surface is elliptical in shape.

[0006] Some embodiments of this disclosure provide a method for manufacturing a semiconductor package. The method includes providing a substrate having a surface, and placing a conductive element having a main axis on the surface of the substrate. Placing the conductive element includes picking it up using electrostatic force and releasing it from a position on the surface of the substrate. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, various aspects of this disclosure will be readily understood from the following detailed description. It should be noted that the features may not be drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1A This is a top view of a plurality of semiconductor module regions 10, 20, 30, 40, 50 and 60 on a semiconductor substrate 100 according to some embodiments of the present disclosure.

[0009] Figure 1B It is according to some embodiments of this disclosure along Figure 1A A cross-sectional view of plane AA' in one of the multiple semiconductor module regions.

[0010] Figure 2A This is a top view of a semiconductor package during an intermediate manufacturing stage according to some embodiments of the present disclosure.

[0011] Figure 2B It is according to some embodiments of this disclosure along Figure 2A A cross-sectional view of the planar BB' of the semiconductor package.

[0012] Figure 3A This is a top view of a semiconductor package during an intermediate manufacturing stage according to some embodiments of the present disclosure.

[0013] Figure 3B It is according to some embodiments of this disclosure along Figure 3A A cross-sectional view of the planar CC' of a semiconductor package.

[0014] Figure 4A This is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0015] Figure 4B It is according to some embodiments of this disclosure along Figure 4A A top view of the planar semiconductor package DD'.

[0016] Figure 4C It is according to some embodiments of this disclosure along Figure 4A A top view of the planar semiconductor package DD'.

[0017] Figure 4D It is according to some embodiments of this disclosure along Figure 4A A top view of the planar semiconductor package DD'.

[0018] Figure 5A This is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0019] Figure 5BThis is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0020] Figure 6 This is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0021] Figure 7A This is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure, showing... Figure 6 An enlarged view of the top of the conductive element.

[0022] Figure 7B This is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure, showing... Figure 6 An enlarged view of the top of the conductive element.

[0023] Figure 8A This invention describes an electrostatic (ES) plate for manufacturing semiconductor packages according to some embodiments of the present disclosure.

[0024] Figure 8B Description of some embodiments according to this disclosure Figure 8A A top view of the isolation layer of the electrostatic (ES) plate.

[0025] Figure 9A This invention describes an electrostatic (ES) plate and conductive element for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0026] Figure 9B and Figure 9C This describes the formation of conductive elements for manufacturing semiconductor packages according to some embodiments of the present disclosure.

[0027] Figure 10A This disclosure describes an electrostatic (ES) plate, conductive element, and mask for manufacturing semiconductor packages according to some embodiments.

[0028] Figure 10B Description of some embodiments according to this disclosure Figure 10A A top view of the mask.

[0029] Figure 11A This illustration shows cross-sectional views of a mask, conductive elements, and solder elements during a reflow operation, according to some embodiments of the present disclosure.

[0030] Figure 11B A cross-sectional view illustrating the placement operation of masks, conductive elements, and solder elements according to some embodiments of this disclosure.

[0031] Figure 12A This is a cross-sectional view of a semiconductor package after an encapsulation operation, according to some embodiments of the present disclosure.

[0032] Figure 12BThis is a cross-sectional view of a semiconductor package after a carrier removal operation, according to some embodiments of the present disclosure.

[0033] Figure 13A This is according to some embodiments of the present disclosure after a thinning operation. Figure 12A A cross-sectional view of a semiconductor package.

[0034] Figure 13B This is according to some embodiments of the present disclosure after a laser drilling operation. Figure 12B A cross-sectional view of a semiconductor package.

[0035] Figure 14A This refers to the process following the half-cutting and conductive layer formation operations according to some embodiments of this disclosure. Figure 13A A cross-sectional view of a semiconductor package.

[0036] Figure 14B This refers to the process following the half-cutting and conductive layer formation operations according to some embodiments of this disclosure. Figure 13B A cross-sectional view of a semiconductor package.

[0037] Figure 15A This is according to some embodiments of the present disclosure after the complete dicing and conductive layer formation operations. Figure 14A A cross-sectional view of a semiconductor package.

[0038] Figure 15B This is according to some embodiments of the present disclosure after the complete dicing and conductive layer formation operations. Figure 14B A cross-sectional view of a semiconductor package. Detailed Implementation

[0039] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. In this disclosure, the description in the following description of a first feature forming on or above a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for the purpose of simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0040] Embodiments of this disclosure are described in detail below. However, it should be understood that many applicable concepts provided in this disclosure can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0041] In some integrated circuits (ICs), via structures connecting interconnect metal lines in adjacent layers have diameters ranging from approximately 50 micrometers (μm) to approximately 90 μm. The diameter of the via structure affects the series resistance and heat dissipation of the interconnects. In high-power IC applications, it is necessary to reduce series resistance and improve heat dissipation to achieve better device performance.

[0042] Some comparative conformal shielding techniques involve connecting a ground layer to the edge of the substrate by exposing the shielding layer, or forming conductive pillars connected to a ground pad by laser-drilling the encapsulation and filling the drilled holes in the encapsulation with conductive material. However, the former technique involves extending the ground layer to the edge of the substrate, thus occupying space and the coverage area of ​​the functional metal lines, while the latter technique must address the problem of voids that may be created when filling the drilled holes in the encapsulation with conductive material.

[0043] This disclosure provides conductive elements that connect to a ground pad on a substrate. The conductive elements can be located at locations other than the edges of the substrate in a semiconductor package, and can be positioned prior to the formation of the encapsulation, thus eliminating the need for laser drilling. Some semiconductor packages may include active and passive electronics integrated on the substrate in a fan-out manner.

[0044] Figure 1A This is a top view of a semiconductor substrate 100 having multiple semiconductor module regions 10, 20, 30, 40, 50, and 60 according to some embodiments of the present disclosure. In some embodiments, each of the semiconductor module regions, defined by dashed lines, has similar or identical device and wiring layouts. For example, each of the semiconductor module regions has a first region exposing conductive terminals 105 configured to receive or bond to an active chip 101 manufactured by wafer-level chip-scale packaging. Since in the depicted example, the active chip 101 may not yet be bonded to the semiconductor substrate 100, the top view of the active chip 101 is depicted with dashed lines. Each of the semiconductor module regions may also have a second region exposing conductive terminals 105 configured to receive or bond to multiple passive devices 102. Since in the depicted example, the passive devices 102 may also not yet be bonded to the semiconductor substrate 100, the top view of the passive devices 102 is depicted with dashed lines. Each of the semiconductor module regions may also have a third region exposing a plurality of conductive terminals 105. The conductive terminals 105 in the third region are not configured to be bonded to any of the electronic or optical devices. In some embodiments, the conductive terminals 105 in the third region are configured to be bonded to conductive elements, as will be discussed later in this disclosure. Although depicted at the edge of the semiconductor module region 50, the conductive terminals 105 in the third region may be located in regions other than the said edge, for example, between the active chip 101 and the passive device 102.

[0045] Figure 1B It is according to some embodiments of this disclosure along Figure 1A A cross-sectional view of plane AA' in one of the multiple semiconductor module regions. (See figure) Figure 1B The conductive terminal 105 described herein may include solder bumps located on and exposed corresponding conductive pads in a first surface 100A of the semiconductor substrate 100, adjacent to or embedded in the semiconductor substrate 100. In some embodiments, the conductive terminal 105 may include conductive pads of the semiconductor substrate 100 but may omit solder bumps. Each of the semiconductor module regions 10, 20, 30, 40, 50 and 60 may have different means and wiring layouts. A sawing track 1020 is located between semiconductor module regions 10 and 20 and is configured to receive a saw blade during a half-cut or full-cut single-piece operation to separate semiconductor module regions 10, 20, 30, 40, 50 and 60 after semiconductor packaging on the semiconductor substrate 100 is completed.

[0046] exist Figure 1A and Figure 1B In this embodiment, semiconductor substrate 100 is a fan-out substrate. A fan-out substrate is provided for a fan-out wafer-level package (FOWLP) for a device having multiple chips. In one embodiment, the fan-out substrate includes one or more redistribution layers (RDLs) comprising one or more conductor portions and one or more insulator or dielectric portions. In one embodiment, the fan-out substrate may include through-hole wiring after being assembled using a wafer-level packaging (WLP) process to form a structure that can be viewed as inserted into the FOWLP. Multiple chips may be provided on the fan-out substrate, and one or more integrated circuits may be embedded in each of the chips in the FOWLP.

[0047] Figure 2A This is a top view of a semiconductor package 20 during an intermediate manufacturing stage according to some embodiments of the present disclosure. (As shown in...) Figure 1A and Figure 1B As previously discussed, the active chip 101, passive device 102, and conductive element 103 are bonded to the semiconductor substrate 100 via conductive terminals 105, and these components are encapsulated by an encapsulant 107 or a molding compound. Figure 2A As shown, the top view of the conductive element 103 at the flattened surface 107A of the encapsulation 107 can be attributed to the fact that the conductive element 103 can be tilted during the manufacturing operation, thus having an elliptical shape.

[0048] Figure 2B It is according to some embodiments of this disclosure along Figure 2AA cross-sectional view of the planar BB' of the semiconductor package 20. In some embodiments, the conductive element 103 may be a metal lead comprising a metal conductor such as copper (Cu), a Cu alloy in which iron (Fe) and Cu are mixed in a ratio ranging from about 0.1% to about 20%, gold (Au), silver (Ag), or aluminum (Al), or an alloy thereof. The conductive element 103 may be a lead having an average diameter of about 50 μm. The conductive element 103 is connected via solder bumps to a conductive pad that is close to, adjacent to, or embedded in and exposed on a first surface 100A of the semiconductor substrate 100. The width of the conductive pad may be at least about 50 μm larger than the diameter of the conductive element 103. For example, the widest dimension of the conductive pad housing the conductive element is about equal to or greater than about 100 μm. As another example, the widest dimension of the ground conductive pad housing the conductive element is about equal to or greater than about 200 μm.

[0049] Figure 3A This is a top view of a semiconductor package 30 during an intermediate manufacturing stage according to some embodiments of the present disclosure. As previously stated in Figure 1A and Figure 1B As described, the active chip 101, passive device 102, and first conductive element 103 are bonded to the semiconductor substrate 100 via conductive terminals 105, and these components are encapsulated by an encapsulant 107 or a molding compound. Figure 3A As shown, the top view of the first conductive element 103 and the second conductive element 103' at the planarized surface 107A of the encapsulation 107 can be attributed to the fact that the first conductive element 103 and the second conductive element 103' can be tilted during the manufacturing operation, thus having an elliptical shape. However, if one of the first conductive element 103 and the second conductive element 103' is not tilted during the manufacturing operation, then one of the first conductive element 103 and the second conductive element 103' can have a circular shape at the planarized surface 107A of the encapsulation 107.

[0050] Figure 2A and Figure 3A The difference lies in the bonding of the second conductive element 103' to the top surface of the passive device 102. In some embodiments, the second conductive element 103' is shorter than the first conductive element 103 in the main direction, and the second conductive element 103' is electrically connected to the semiconductor substrate 100 via a solder point at the top surface of the passive device 102. However, the second conductive element 103' is not limited to the embodiments explicitly described herein. The second conductive element 103' may be electrically connected to or directly bonded to any of the semiconductor chips or devices integrated with the semiconductor substrate 100.

[0051] Figure 3B It is according to some embodiments of this disclosure along Figure 3AA cross-sectional view of the planar CC' of the semiconductor package 30. In some embodiments, the first conductive element 103 and the second conductive element 103' may be metal leads comprising a metal conductor such as Cu, a Cu alloy in which Fe is mixed into Cu at a ratio ranging from about 0.1% to about 20%, Au, Ag, or Al or alloys thereof. The first conductive element 103 and / or the second conductive element 103' may be metal leads having an average diameter of about 50 μm. The first conductive element 103 is connected to the conductive pad of the semiconductor substrate 100 via solder bumps. The second conductive element 103' is connected to the passive device 102 or an active device (not in the planar ... Figure 3B The conductive pad (shown in the diagram) has a width that is at least about 50 μm larger than the diameter of the first conductive element 103 and the second conductive element 103'. For example, the widest dimension of the conductive pad accommodating the first conductive element 103 and the second conductive element 103' is about equal to or greater than about 100 μm. As another example, the widest dimension of the grounding conductive pad accommodating the conductive elements is about equal to or greater than about 200 μm.

[0052] like Figure 3B As illustrated, the first conductive element 103 may tilt to the right, while the second conductive element 103' may tilt in a different direction, such as to the left. The tilting action of the first conductive element 103 and the second conductive element 103' occurs during a solder reflow operation, as will be illustrated later in FIG. 11 of this disclosure. In some embodiments, the tilt angle θ, i.e., the acute angle, measured between the first conductive element 103 and the first surface 100A of the semiconductor substrate 100 is from about 85 degrees to less than about 90 degrees (e.g., from about 86 degrees to about 89 degrees, or from about 87 degrees to about 88 degrees). The tilt angle can be determined by the opening of a mask used during manufacturing, opposite to the diameter of the first conductive element 103, as will be illustrated later in this disclosure. Figure 10A This is explained in the text.

[0053] Figure 4A This is a cross-sectional view of a semiconductor package 40 according to some embodiments of the present disclosure. The semiconductor substrate 400 may be a fan-out substrate, as previously described... Figure 1B As described herein. The semiconductor substrate 400 has a first surface 401 that houses the active device 101, the passive device 102, and the conductive element 403. (As described...) Figure 4AAs shown, conductive element 403 has a principal axis I intersecting the first surface 401. The principal axis I and the first surface 401 form an acute angle or angle θ less than about 90 degrees (e.g., from about 86 degrees to about 89 degrees, or from about 87 degrees to about 88 degrees). Active device 101, passive device 102, and conductive element 403 are encapsulated in an encapsulant 405, such as a polymeric material or molding compound. The encapsulant 405 covers the side surface or lateral surface of conductive element 403 and the first surface 401 of semiconductor substrate 400. Active device 101, passive device 102, and conductive element 403 are electrically coupled to at least one of the RDLs of semiconductor substrate 400. Figure 4A As shown, the vertical height of the conductive element 403 is approximately the same as the vertical height of the encapsulation 405.

[0054] exist Figure 4A In this embodiment, a conductive layer 407 is conformally formed on the top and sides of the encapsulation 405 and on the first surface 401 of the semiconductor substrate 400. When in physical contact with a conductive element 403, the conductive layer 407 is electrically coupled to at least one of the RDLs of the semiconductor substrate 400. In some embodiments, the conductive layer 407 acts as a conformal shield for the semiconductor package 40, wherein the conductive terminals 105 housing the conductive element 403 are grounded. In some embodiments, a misaligned conductive element 403 embedded in the encapsulation 405 can be detected non-destructively, for example, by X-ray screening.

[0055] Figure 4B It is according to some embodiments of this disclosure along Figure 4A A top view of the planar DD' of a semiconductor package 40. Figure 4B Show parallel to Figure 4A The second surface 405A of the semiconductor package 40 has a first surface 401. The second surface 405A does not need to be exposed outside the semiconductor package 400 and can be a virtual plane. The second surface 405A includes at least the encapsulation 405 and the conductive element 403. In some embodiments, any surface or plane between the top surface of the encapsulation 405 and the first surface 401 can be the second surface 405A. The conductive element 403 exposes an elliptical region 403A at the second surface 405A (e.g., due to the fact that the conductive element 403 is tilted during manufacturing operations). The orientation of the major axis of the elliptical region 403A depends on the degree to which the conductive element 403 is tilted during manufacturing operations. For example, in Figure 4B In the elliptical region 403A, the major axis extends from left to right, and therefore the corresponding conductive element 403 can be tilted to the left or right. Figure 4C In the elliptical region 403A, the major axis extends from the lower left to the upper right, and therefore the corresponding conductive element 403 can be tilted towards the lower left or the upper right. Figure 4DIn the elliptical region 403A, the major axis extends from the upper left to the lower right, and therefore the corresponding conductive element 403 can be tilted towards the upper left or the lower right.

[0056] Figure 5A This is a cross-sectional view of a semiconductor package 50A according to some embodiments of the present disclosure. Figure 4A Compared to semiconductor package 40, semiconductor package 50A has an additional second conductive element 403' located on passive device 102. The first conductive element 403 and the second conductive element 403' have different lengths in the principal directions I and I'. In some embodiments, a conductive layer 407 is conformally formed on the top and sides of encapsulation 405 and on the first surface 401 of semiconductor substrate 400. When in physical contact with the first conductive element 403 and the second conductive element 403', the conductive layer 407 is electrically coupled to at least one of the RDLs of semiconductor substrate 400. In some embodiments, the conductive layer 407 acts as a conformal shield for semiconductor package 50A, wherein the conductive terminals 105 housing the first conductive element 403 and / or the conductive terminals housing the second conductive element 403' on passive device 102 are grounded. The ground terminal on passive device 102 can be connected to an end of the second conductive element 403'. In some embodiments, the first conductive element 403 and the second conductive element 403' are metal rods, each having a substantially uniform diameter from one end to the other.

[0057] Figure 5B This is a cross-sectional view of a semiconductor package 50B according to some embodiments of the present disclosure. The difference between semiconductor package 50B and semiconductor package 50A includes in semiconductor package 50B that the first conductive element 403 and the second conductive element 403' are tapered metal rods, each having a first end contacting the conductive layer 407 and a second end contacting the solder bump. The first conductive element 403 and the second conductive element 403' are tapered along principal axes I and I'. In some embodiments, it is assumed that the tapered rod has a wider base and a narrower top, with the first end being narrower than the second end. The tapered conductive element is advantageous for maintaining an upright position of the conductive element during reflow operations because the configuration of a wider base and a narrower top is less likely to tilt when joined to molten solder. The tapered metal rod can be manufactured using a forging operation combined with electrostatic (ES) force manipulation, as will be described in this disclosure. Figure 9B and Figure 9C The discussion in the text.

[0058] Figure 6 This is a cross-sectional view of a semiconductor package 60 according to some embodiments of the present disclosure. Figure 5ACompared to semiconductor package 50A, the height 405H of the encapsulant 405 in semiconductor package 60 is greater than the vertical height 403H of the first conductive element 403 that contacts at least one of the RDLs of the semiconductor substrate 400. In semiconductor package 50A, the encapsulant 405, the first conductive element 403, and the second conductive element 403' have coplanar top surfaces due to a planarization operation that simultaneously thins the encapsulant 405, the first conductive element 403, and the second conductive element 403'. On the other hand, in semiconductor package 60, the encapsulant 405, the first conductive element 403, and the second conductive element 403' do not share coplanar surfaces. The encapsulant 405 defines a recess near the top of the first conductive element 403 and the top of the second conductive element 403'. Figure 7A and Figure 7B The details of the recess of the encapsulation 405 are further described in the text.

[0059] Figure 7A and Figure 7B This is a cross-sectional view of a semiconductor package 60A according to some embodiments of the present disclosure, showing... Figure 6 An enlarged view of the top of the first conductive element 403 and the second conductive element 403'. In some embodiments, the recess of the encapsulation 405 exposes at least a portion of the first conductive element 403 and the second conductive element 403' and covers another portion (e.g., the remaining portion) of the first conductive element 403 and the second conductive element 403'. Figure 7B As described, portions 703 of the first conductive element 403 and the second conductive element 403' are not exposed from the recess of the encapsulation 405. In some embodiments, the recess exposes the kinks (e.g., corners or protrusions) of the first conductive element 403 and the second conductive element 403'. Figure 7A and Figure 7B As described, the kink 701 between the first conductive element 403 and the second conductive element 403' is due to the fact that the recess of the encapsulation 405 is not aligned with the tops of the first conductive element 403 and the second conductive element 403', thus exposing it from the recess, and the kink 701 defines the tops and sidewalls of the first conductive element 403 and the second conductive element 403'. In some embodiments, the recess exposes the inclined surfaces of the first conductive element 403 and the second conductive element 403'. For example, Figure 7A The inclined surface 702 of the second conductive element 403' is exposed by the recess due to good alignment between the recess and the lower second conductive element 403'. The conductive layer 407 is then deposited over the encapsulation 405 and the exposed portions of the first conductive element 403 and the second conductive element 403', which outlines the top profile of the semiconductor package.

[0060] In some embodiments, recesses in the encapsulation 405 can be formed by laser drilling. Additionally, laser drilling using a specific wavelength band can selectively remove polymeric or organic materials, such as the encapsulation 405, without removing the first conductive element 403 and the second conductive element 403', which may contain, for example, copper or a copper alloy. Therefore, depending on the alignment of the laser drill hole, kinked or tilted surfaces or unexposed portions of the first conductive element 403 and the second conductive element 403' may appear.

[0061] According to some embodiments of this disclosure Figure 8A This describes an electrostatic discharge (ES) plate used in the manufacture of semiconductor packages, and Figure 8B illustrate Figure 8A A top view of the isolation layer of the electrostatic (ES) plate. Figure 8A The ES board includes a dielectric plate 800 with a top electrode 801 and a bottom electrode 803. Two opposing terminals of an ES generator 807 are coupled to the top electrode 801 and the bottom electrode 803, respectively, and generate electrostatic charge on their surfaces. The amount of ES charge on the top electrode 801 and the bottom electrode 803 can be tuned by the ES generator. A patterned isolation layer 805 is located on the surface of the bottom electrode 803. Figure 8B The diagram shows a plurality of openings 805A, 805B in the insulating layer 805 configured to expose predetermined portions of the bottom electrode 803. The portions of the bottom electrode 803 exposed through the openings 805A, 805B can induce polarization of the object to be attracted and apply an ES force to the object to be attracted. Figure 8A As illustrated, for example, the bottom electrode 803 carries a negative static charge, while the top electrode 801 carries a positive static charge.

[0062] Compared to magnetic force, the ES force proposed in this disclosure can be applied to insulators or non-magnetic materials such as copper, while magnetic force can be used to manipulate insulators or non-magnetic objects. When the conductive element 403 is a copper rod or copper needle, the ES force is better suited to perform existing operations.

[0063] In some embodiments, the positions of the patterned openings 805A, 805B are predetermined to match the positions of the conductive elements within the semiconductor package as described herein. The patterned openings 805A, 805B are also predetermined to match another set of openings in the mask, which facilitates proper placement of the conductive elements within the semiconductor package as described herein. Thus, the areas of the openings 805A, 805B are large enough to accommodate conductive elements at their ends, but small enough to prevent multiple conductive elements from being attached to or accommodated within individual openings 805A, 805B.

[0064] Figure 9AThis description describes an electrostatic discharge (ES) plate and a conductive element 403 for manufacturing a semiconductor package according to some embodiments of the present disclosure. The conductive element 403 is disposed on a stage 900 and is attracted by an ES force. When the bottom electrode 803 of the ES plate, carrying a negative electrostatic charge, approaches the conductive element 403, carrying a positive electrostatic charge, the end of the conductive element 403 tends to attach to the exposed portion of the bottom electrode 803 through an opening in the insulating layer 805.

[0065] Figure 9B and Figure 9C This describes the formation of conductive elements for manufacturing semiconductor packages according to some embodiments of the present disclosure. Figure 9B The die 901 is provided with an infeed end 901A and an outlet end 901B. A conductive material 4031, such as a metal rod or needle, is fed into the infeed end 901A of the die 901, followed by a forging operation to reshape the conductive element 403 from a rod or needle shape into a tapered rod or tapered needle shape, such as... Figure 9C As shown in the diagram. In some embodiments, a set of sleeves 903 enters the discharge end 901B to discharge the tapered rod or tapered needle-shaped conductive element 403 from the mold sleeve 901. As previously discussed, the discharged tapered rod or tapered needle-shaped conductive element 403 can then be picked up by the ES force applied from the ES plate. The tapered feed end 901A of the mold sleeve 901 facilitates the demolding or discharge of the tapered rod or tapered needle-shaped conductive element 403.

[0066] Return to reference Figure 5B The wider end of the tapered rod or tapered needle-shaped conductive element 403 can engage with solder bumps on the substrate 400, while the narrower end of the tapered rod or tapered needle-shaped conductive element 403 extends away from the substrate 400 and is electrically connected to the conductive layer 407.

[0067] Figure 10A This describes the electrostatic discharge (ES) plate, conductive element 403, carrier 410, and mask 1000 used in the manufacture of semiconductor packages. Figure 10B Description of some embodiments according to this disclosure Figure 10A A top view of mask 1000. After using ES force to attract the first conductive element 403 at the bottom electrode 803, it has the following characteristics: Figure 10B The corresponding shown is as follows Figure 8BA first mask 1000 of a first pattern of the isolation layer 805 shown is placed between the ES board and the semiconductor package to be manufactured. For the sake of simplicity, the first pattern of the first mask 1000 includes two square openings 1001, but other embodiments may have a different number of openings. The conductive element 403 has an average diameter W403, while the square openings 1001 have a width W1001. Considering an acceptable alignment window, the width W1001 is greater than or wider than the diameter W403, such that when the ES board is grounded, the first conductive element 403 can fall from the bottom electrode 803 through the square openings 1001 onto the substrate 400. Solder paste or solder bumps 105' can be positioned on the substrate 400 at the location where the conductive element 403 will fall before grounding the ES board and allowing the first conductive element 403 to fall.

[0068] In some embodiments, reversing the polarity of the ES generator 807 can generate a relative charge (e.g., a positive charge) on the bottom electrode 803, thereby repelling the positively charged conductive element 403 and causing a downward acceleration of the positively charged conductive element. In such operation, the orientation of the conductive element 403 can be controlled.

[0069] exist Figure 10A In this design, since both first conductive elements 403 lie on the first surface 401 of the substrate 400, the two first conductive elements 403 can have substantially the same length along the main axis of the rod or needle. However, the two first conductive elements 403 are not limited to having the same length along the main axis. For example, the length difference between the two conductive elements 403 can be attributed to manufacturing variations and is within 5%.

[0070] Figure 11A This illustration shows a cross-sectional view of a first mask 1000, a first conductive element 403, and a solder element 105' during a reflow operation, according to some embodiments of the present disclosure. After the first conductive element 403 is placed at a predetermined position on the semiconductor substrate 400, a reflow operation is performed to bond the first conductive element 403 to the semiconductor substrate 400 via soldering. Figure 11A As described, the first mask 1000 is positioned during the reflow operation to provide lateral restraint on the first conductive element 403. The tip of the first conductive element 403 is surrounded by the sidewalls of the opening 1001 in the first mask 1000. When the solder paste or solder bump 105' reaches a molten state, the metal rod or pin falling on it may lack mechanical support and may skew / tilt. With the restraint of the first mask, the degree of skew can be controlled within a few degrees (e.g., within about 5 degrees), thus achieving an acute angle θ between the first conductive element 403 and the first surface 401 from about 85 to less than about 90 degrees (e.g., from about 86 to about 89 degrees, or from about 87 to about 88 degrees). Figure 4AAs shown in the figure. In some embodiments, the first mask 1000 is removed after the solder paste or solder bump 105' has solidified.

[0071] like Figure 11A As shown, the opening 1001 of the mask may have a narrower neck 1001A and a wider bevel 1001B. The neck 1001A is configured to provide lateral confinement of the conductive element 403 during reflow operations, while the bevel 1001B is configured to have a wider reception angle for the conductive element 403 from the ES board.

[0072] Figure 11B The illustration shows a cross-sectional view of the second mask 1000', the second conductive element 403', and the solder element 105' during a placement operation according to some embodiments of the present disclosure. Figure 11B This is an optional operation in which the second conductive element 403' falling onto the electronic device 104 is included in the semiconductor package. After the second conductive element 403' is attracted at the bottom electrode 803 using an ES force, a second mask 1000' having a second pattern corresponding to the pattern of the isolation layer 805' is placed between the ES plate and the semiconductor package to be manufactured. To convey a simplified concept, the first pattern of the first mask 1000 includes an opening 1001', but in other embodiments, it may include a different number of openings. The second conductive element 403' has an average diameter W403', while the opening 1001' has a width W1001'. Considering an acceptable alignment window, the width W1001' is greater than or wider than the diameter W403', such that when the ES plate is grounded, the first conductive element 403' can fall from the bottom electrode 803 through the opening 1001' onto the electronic device 104. Solder paste or solder bumps 105' may be positioned at the location where the conductive element 403' of the electronic device 104 will fall before grounding the ES board and allowing the second conductive element 403' to fall. In some embodiments, the second conductive element 403' is at least one height shorter than the first conductive element 403 on the main axis of the electronic device 104. Solder paste or solder bumps 105' on the electronic device 104 may be grounded.

[0073] For the sake of brevity, a detailed description of the reflow operation after the second conductive element 403' falls onto the electronic device 104 is omitted from this disclosure, but the reflow operation may be performed.

[0074] Figure 12A and Figure 12B These are cross-sectional views of a semiconductor package after encapsulation operations, according to some embodiments of this disclosure. (The images are shown separately.) Figure 11A and Figure 11BFollowing the placement operation, an encapsulation 405 is formed on a first surface 401 of the semiconductor substrate 400 and completely covers the electronic devices and conductive elements 403, 403' thereon. In some embodiments, the encapsulation thus formed is cast to have a first height greater than the height of any one of the electronic devices and conductive elements 403, 403'. The encapsulation operation includes, for example, using a resin sheet laminate in a softened state, liquid resin transfer molding, coating with liquid resin, or other suitable methods. It should be noted that in Figure 12A and Figure 12B In the process, after the encapsulation 405 is formed, the carrier 410 supporting the semiconductor substrate 400 can be removed and bonded.

[0075] Figure 13A This is according to some embodiments of the present disclosure after a thinning operation. Figure 12A A cross-sectional view of a semiconductor package. As previously shown in Figure 12A As described, the height of the encapsulation 405 thus formed is greater than the height of the conductive element 403. The thinning operation may include a planarization or polishing operation that removes the encapsulation 405 from the top surface until the conductive element 403 is exposed. (Return to Reference) Figure 3A and Figure 3B In the event that the conductive element 403 is skewed or tilted during the reflow operation, the exposed conductive element 403 may have an elliptical region.

[0076] Figure 13B This is according to some embodiments of the present disclosure after a laser drilling operation. Figure 12B A cross-sectional view of a semiconductor package. As previously shown in Figure 12B As described above, the height of the encapsulation 405 is greater than the height of the conductive elements 403, 403'. A laser drilling operation can form multiple recesses 405' on the encapsulation 405 until the tops of the conductive elements 403, 403' are exposed. Optionally, a decontamination operation is performed in the recesses using a suitable chemical solution. Adjustments to the laser output and the alignment of the drill point can be performed as needed. As previously discussed, laser drilling selectively removes polymer or epoxy material, and therefore the conductive elements 403, 403' are unaffected by the laser drilling. In some embodiments, when the height of the encapsulation 405 is significantly greater than the height of the conductive elements 403, 403', the semiconductor package is subjected to... Figure 13A The thinning operation described in the text is followed by Figure 13B The laser drilling operation described in the text.

[0077] Figure 14A and Figure 14B This refers to the processes following the half-cutting and conductive layer formation operations, according to some embodiments of this disclosure. Figure 13A and Figure 13B A cross-sectional view of a semiconductor package. As shown in this article relative to... Figure 1A As described, assemblies of multiple semiconductor module regions 10, 20, 30, 40, 50, and 60 can be manufactured simultaneously and then the assemblies can be divided into individual packages. Figure 14A and Figure 14B In this process, a half-cutting operation is performed to divide each semiconductor module region 10, 20, 30, 40, 50, and 60 from the encapsulation 405, and then a conductive layer 407 is formed over the encapsulation 405, conductive elements 403, 403', and semiconductor substrate 400. In some embodiments, the conductive layer 407 may comprise copper, stainless steel, or a combination thereof. In such operations, after complete separation at the semiconductor substrate 400, the conductive layer 407 can be sensed at the first surface 401 of the semiconductor substrate 400, rather than at the sidewalls.

[0078] Figure 15A and Figure 15B These are, according to some embodiments of this disclosure, respectively, after the complete dicing and conductive layer formation operations. Figure 13A and Figure 13B A cross-sectional view of a semiconductor package. As shown in this article relative to... Figure 1A As described, assemblies of multiple semiconductor module regions 10, 20, 30, 40, 50, and 60 can be manufactured simultaneously and then the assemblies can be divided into individual packages. Figure 15A and Figure 15B In this process, a complete dicing operation is performed to divide each semiconductor module region 10, 20, 30, 40, 50, and 60, and then a conductive layer 407 is formed over the encapsulation 405, conductive elements 403, 403', and semiconductor substrate 400. In some embodiments, the conductive layer 407 may comprise copper, stainless steel, or a combination thereof. In such operations, the conductive layer 407 is perceptible at the sidewall 402 of the semiconductor substrate 400.

[0079] As used herein, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “lower,” “left,” “right,” etc., may be used to describe the relationship between one element or feature and another element or feature as illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to said other element, or there may be an intermediate element.

[0080] As used herein, the terms “approximately,” “substantially,” “largely,” and “about” are used to describe and account for small variations. When used in conjunction with an event or situation, the terms can refer to a situation in which the event or situation has clearly occurred or is very close to occurring. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints. The term “substantially coplanar” can refer to two surfaces located along the same plane within a few micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm. When referring to the same numerical value or characteristic, the term can refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said value.

[0081] The foregoing outlines several embodiments and detailed features of this disclosure. The embodiments described in this disclosure can readily serve as the basis for designing or modifying other processes and structures for performing the same or similar purposes and / or obtaining the same or similar advantages of the embodiments introduced herein. These equivalent constructions do not depart from the spirit and scope of this disclosure and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor package comprising: Substrate, which has a surface; A first solder bump is present on the surface. and A first conductive element is electrically coupled to the substrate on the surface and via the first solder bump, the first conductive element having a principal axis forming an angle of less than 90 degrees with the surface; An encapsulation material that surrounds the side of the first conductive element and covers the surface of the substrate; and A conductive layer that covers the top surface and sidewalls of the encapsulation and is electrically coupled to the conductive layer of the substrate via the first conductive element and the first solder bump. The first solder bump and the first conductive element are made of different materials, and an interface is formed between the first solder bump and the bottom surface of the first conductive element. The bottom surface of the first conductive element is not parallel to the surface of the substrate. The top surface of the first conductive element and the side surface define a first corner that is exposed from the encapsulation, and the conductive layer covers the first corner along the contour of the first corner.

2. The semiconductor package of claim 1, wherein the encapsulation has a height greater than the height of the first conductive element, and the second corner defined by the top surface and the side surface of the first conductive element is covered by the encapsulation.

3. The semiconductor package according to claim 1, further comprising: Electronic components on the surface of the substrate; A second solder bump is located on the electronic component; and A second conductive element is present on the electronic component and electrically coupled to the electronic component via the second solder bump.

4. The semiconductor package of claim 3, wherein the encapsulation surrounds the side of the second conductive element and covers the surface of the substrate, wherein the encapsulation has a recess from which the top surface of the second conductive element is exposed.

5. The semiconductor package of claim 4, wherein the top surface of the second conductive element is substantially parallel to the surface of the substrate, and the bottom surface of the second conductive element is not parallel to the surface of the substrate.

Images