Utilization metrics for processing engines

Abstract

In one embodiment, a processor includes a plurality of processing engines and a power control unit. The power control unit is configured to: maintain a first utilization metric of a first processing engine; detect a thread transfer from the first processing engine to a second processing engine; and generate a second utilization metric of the second processing engine using the first utilization metric of the first processing engine. Other embodiments are described and claimed.

Description

Technical Field

[0001] Embodiments relate generally to computer processors and more particularly to power management in computer processors. Background Art

[0002] Advances in semiconductor processing and logic design have allowed for an increase in the amount of logic that can be present in integrated circuit devices. As a result, computer system configurations have evolved from single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and / or complete systems on each integrated circuit. Furthermore, as the density of integrated circuits has increased, the power requirements of computing systems have also increased. Consequently, there is a pressing need for energy efficiency and conservation associated with integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram of a portion of a system according to an embodiment of the present invention.

[0004] Figure 2 is a block diagram of a processor according to an embodiment of the present invention.

[0005] Figure 3 is a block diagram of a multi-domain processor according to another embodiment of the present invention.

[0006] Figure 4 is an embodiment of a processor comprising multiple cores.

[0007] Figure 5 is a block diagram of a microarchitecture of a processor core according to one embodiment of the present invention.

[0008] Figure 6 is a block diagram of a microarchitecture of a processor core according to another embodiment.

[0009] Figure 7 is a block diagram of a microarchitecture of a processor core according to yet another embodiment.

[0010] Figure 8 is a block diagram of a microarchitecture of a processor core according to yet another embodiment.

[0011] Figure 9 is a block diagram of a processor according to another embodiment of the present invention.

[0012] Figure 10 is a block diagram of a representative SoC according to an embodiment of the present invention.

[0013] Figure 11 is a block diagram of another example SoC according to an embodiment of the present invention.

[0014] Figure 12 is a block diagram of an example system that can be used with embodiments.

[0015] Figure 13 is a block diagram of another example system that can be used with embodiments.

[0016] Figure 14 is a block diagram of a representative computer system.

[0017] Figure 15 is a block diagram of a system according to an embodiment of the present invention.

[0018] Figure 16 is a block diagram illustrating an IP core development system for fabricating an integrated circuit to perform operations, according to an embodiment.

[0019] Figures 17A-17B is a block diagram illustrating a general vector friendly instruction format and instruction templates thereof according to an embodiment of the present invention.

[0020] Figures 18A-18D is a block diagram illustrating an exemplary specific vector friendly instruction format according to an embodiment of the present invention.

[0021] Figure 19 is a block diagram of a register architecture according to one embodiment of the present invention.

[0022] Figure 20A is a block diagram illustrating an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to an embodiment of the present invention.

[0023] Figure 20B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to an embodiment of the present invention.

[0024] Figures 21A-21B A block diagram illustrating a more specific exemplary in-order core architecture, which would be one of several logic blocks in a chip (including other cores of the same and / or different types).

[0025] Figure 22 is a block diagram of a processor according to an embodiment of the present invention, which may have more than one core, may have an integrated memory controller, and may have integrated graphics.

[0026] Figure 23-24 is a block diagram of an exemplary computer architecture.

[0027] Figure 25 is a block diagram comparing the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set according to an embodiment of the present invention.

[0028] Figure 26is a diagram of an example system in accordance with one or more embodiments.

[0029] Figures 27A-27B is an illustration of example thread transfer operations in accordance with one or more embodiments.

[0030] Figures 28A-28B is an illustration of example thread transfer operations in accordance with one or more embodiments.

[0031] Figure 29A-29B is a description of example thread-level registers in accordance with one or more embodiments.

[0032] Figure 30 is a flowchart of an example method according to one or more embodiments. DETAILED DESCRIPTION

[0033] Some computer processors may include multiple processing engines or "cores". In some examples, a processing engine may be able to operate at a different power and / or performance state than other processing engines. For example, a first processing engine may operate at a relatively high voltage and / or a high operating frequency (also referred to as a "clock frequency"), while a second processing engine may simultaneously operate at a relatively low voltage and / or a low clock frequency. In some examples, the power state of a processing engine may be changed based on a utilization metric associated with the processing engine. As used herein, a "utilization metric" refers to information indicating the level of activity or usage of a processor or its components. For example, a utilization metric may include one or more of the following: the percentage of time used during processing, the number or proportion of clock cycles used during processing, whether a particular component (e.g., execution unit, memory, etc.) was used during a time period, whether a particular pattern of memory access was used, etc.

[0034] In some examples, thread transfers may affect the utilization of a processing engine. As used herein, the term "thread transfer" refers to data dependencies between processing engines or thread migration between processing engines. For example, a thread transfer may include a consumer thread waiting for data or a signal from a producer thread on another processing engine. In another example, a thread transfer may include a software thread executing on a first processing engine being migrated to execute on a second processing engine. In these examples, upon receiving the thread transfer, the processing engine may appear to have low utilization (or zero utilization) and may therefore be placed in a low power state (e.g., a relatively low clock frequency). However, this low utilization may not accurately reflect the level of activity associated with the thread transfer. Therefore, the processing engine may be in a power state that is too low for the thread transfer and may therefore result in relatively poor performance when performing the thread transfer.

[0035] According to some embodiments, a power control unit may maintain a utilization metric for a first processing engine of a processor. The power control unit may detect or receive an indication of a thread transfer from the first processing engine to a second processing engine. The power control unit may use the utilization metric of the first processing engine to generate a utilization metric for the second processing engine. Furthermore, the power control unit may use this generated utilization metric to control the power state of the second processing engine. Thus, in some embodiments, the second processing engine may operate in a power state that more accurately reflects the activity associated with the thread transfer, and the execution performance of the thread transfer may therefore be improved. Figures 26-30 Further details of some embodiments are described. Figure 1-Figure 25 Describes exemplary systems and architectures.

[0036] Exemplary Systems and Architectures

[0037] Although the following embodiments are described with reference to specific implementations, the embodiments are not limited thereto. In particular, it is contemplated that similar techniques and teachings of the embodiments described herein can be applied to other types of circuits, semiconductor devices, processors, systems, and the like. For example, the disclosed embodiments can be implemented in any type of computer system, including server computers (e.g., tower servers, rack servers, blade servers, micro servers, etc.), communication systems, storage systems, desktop computers of any configuration, laptop computers, notebook computers, and tablet computers (including 2:1 tablets, tablet phones, etc.).

[0038] In addition, the disclosed embodiments may also be used in other devices, such as handheld devices, system on chip (SoC) and embedded applications. Some examples of handheld devices include cellular phones, such as smart phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs) and handheld PCs. Embedded applications may typically include microcontrollers, digital signal processors (DSPs), network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, wearable devices, or any other system that can perform the functions and operations taught below. In addition, embodiments may be implemented in mobile terminals with standard voice capabilities (e.g., mobile phones, smart phones and tablet phones) and / or in non-mobile terminals without standard wireless voice communication capabilities (e.g., many wearable devices, tablets, notebooks, desktops, micro servers, servers, etc.).

[0039] Now refer to Figure 1 , shows a block diagram of a portion of a system according to an embodiment of the present invention. Figure 1As shown, system 100 may include various components including processor 110, which is shown as a multi-core processor. Processor 110 may be coupled to power supply 150 via external voltage regulator 160, which may perform a first voltage conversion to provide a primary regulated voltage Vreg to processor 110.

[0040] As seen, the processor 110 can be a single-die processor that includes multiple cores 120a-120n. In addition, each core can be associated with an integrated voltage regulator (IVR) 125a-125n that receives a primary regulated voltage and generates an operating voltage to be provided to one or more agents of the processor associated with the IVR. Thus, providing an IVR implementation can allow for fine-grained control over the voltage of each individual core, and therefore power and performance. Thus, each core can operate at an independent voltage and frequency, thereby enabling great flexibility and providing a wide range of opportunities for balancing power consumption and performance. In some embodiments, the use of multiple IVRs enables the grouping of components into separate power planes, such that power is regulated by the IVR and provided to only those components in the group. During power management, when the processor is placed in a low-power state, a given power plane of one IVR can be powered down or shut down, while another power plane of another IVR remains active or fully powered. Similarly, the cores 120 may include or be associated with independent clock generation circuitry (eg, one or more phase-locked loops (PLLs)) to independently control the operating frequency of each core 120 .

[0041] Still refer to Figure 1 , there may be other components within the processor, including an input / output interface (IF) 132, another interface 134, and an integrated memory controller (IMC) 136. As can be seen, each of these components may be powered by another integrated voltage regulator 125 x In one embodiment, the interface 132 can be used to The operation of the Quick Path Interconnect (QPI) interconnect is made possible, and the QPI interconnect provides a point-to-point (PtP) link in a cache coherence protocol including multiple layers (including a physical layer, a link layer, and a protocol layer). In turn, the interface 134 can be connected via a peripheral component interconnect express (PCIe TM ) protocol for communication.

[0042] Also shown is a power control unit (PCU) 138, which may include circuitry including hardware, software, and / or firmware for performing power management operations on processor 110. As shown, PCU 138 provides control information to external voltage regulator 160 via digital interface 162 to cause the voltage regulator to generate an appropriate regulated voltage. PCU 138 also provides control information to IVR 125 via another digital interface 163 to control the generated operating voltage (or to disable the corresponding IVR in a low-power mode). In various embodiments, PCU 138 may include various power management logic units for performing hardware-based power management. Such power management may be fully processor-controlled (e.g., through various processor hardware, and may be triggered by workload and / or power, thermal, or other processor constraints), and / or power management may be performed in response to external sources (e.g., platform or power management resources or system software).

[0043] exist Figure 1 , PCU 138 is shown as existing as separate logic from the processor. In other cases, PCU 138 may execute on a given core or cores 120. In some cases, PCU 138 may be implemented as a microcontroller (dedicated or general purpose) or other control logic configured to execute its own dedicated power management code (sometimes also referred to as P-code). In still other embodiments, the power management operations to be performed by PCU 138 may be implemented external to the processor, such as by a separate power management integrated circuit (PMIC) or another component external to the processor. In still other embodiments, the power management operations to be performed by PCU 138 may be implemented within BIOS or other system software.

[0044] Although Figure 1 Not shown, but in some embodiments, processor 110 and / or core 120 may include the following reference Figures 26-30 All or part of the components and / or processes described.

[0045] Embodiments may be particularly well-suited for multi-core processors in which each of the multiple cores may operate at independent voltage and frequency points. As used herein, the term "domain" is used to refer to a collection of hardware and / or logic that operates at the same voltage and frequency points. In addition, a multi-core processor may also include other non-core processing engines, such as fixed function units, graphics engines, etc. Such a processor may include independent domains in addition to the cores, such as one or more domains associated with a graphics engine (referred to herein as graphics domains) and one or more domains associated with non-core circuits (referred to herein as system agents). Although many implementations of multi-domain processors can be formed on a single semiconductor die, other implementations can be achieved through multi-chip packaging in which different domains can exist on different semiconductor dies in a single package.

[0046] Although not shown for ease of illustration, it should be understood that additional components may exist within processor 110, such as uncore logic and other components (e.g., internal memory (e.g., one or more levels in a cache memory hierarchy, etc.)). Figure 1 The implementation of FIG1 is shown with an integrated voltage regulator, but the embodiments are not limited thereto. For example, other regulated voltages may be provided to the on-chip resources from the external voltage regulator 160 or one or more additional external regulated voltage sources.

[0047] Note that the power management techniques described herein can be independent of and complementary to operating system (OS)-based power management (OSPM) mechanisms. According to one exemplary OSPM technique, a processor can operate in various performance states or levels (so-called P-states, i.e., from P0 to PN). Typically, the P1 performance state can correspond to the highest guaranteed performance state that the OS can request. In addition to this P1 state, the OS can further request a higher performance state (i.e., the P0 state). Thus, the P0 state can be an opportunistic, overclocked, or turbo mode state in which the processor hardware can configure the processor, or at least a portion thereof, to operate at a frequency higher than the guaranteed frequency when power and / or thermal budget is available. In many implementations, a processor can include multiple so-called bin frequencies above the P1 guaranteed maximum frequency, exceeding the maximum peak frequency of a particular processor that is integrated or programmed into the processor during manufacturing. Furthermore, according to an OSPM mechanism, a processor can operate in various power states or levels. With respect to power states, the OSPM mechanism can specify different power consumption states (commonly referred to as C-states: C0, C1, through Cn states). When a core is active, it runs in the C0 state, and when a core is idle, it can be placed into core low power states, also known as core non-zero C-states (e.g., C1-C6 states), where each C-state is at a lower power consumption level (such that C6 is a lower low power state than C1, and so on).

[0048] It should be understood that many different types of power management techniques may be used, alone or in combination, in different embodiments. As a representative example, the power controller may control the processor to perform power management through some form of dynamic voltage frequency scaling (DVFS), in which the operating voltage and / or operating frequency of one or more cores or other processor logic may be dynamically controlled to reduce power consumption in certain situations. In an example, Enhanced Intel SpeedStep 5 available from Intel Corporation of Santa Clara, California may be used. TM Technology performs DVFS to provide the best performance at the lowest power level. In another example, Intel TurboBoost can be used TM The technique implements DVFS to enable one or more cores or other compute engines to operate at a higher than guaranteed operating frequency based on conditions (eg, workload and availability).

[0049] Another power management technique that can be used in some examples is to dynamically swap workloads between different compute engines. For example, a processor can include asymmetric cores or other processing engines that operate at different power consumption levels, so that in a power constraint situation, one or more workloads can be dynamically switched to execute on a lower power core or other compute engine. Another example power management technique is hardware duty cycling (HDC), which can cause cores and / or other compute engines to be periodically enabled and disabled according to a duty cycle, so that one or more cores can be inactive during an inactive period of the duty cycle and active during an active period of the duty cycle.

[0050] Power management techniques can also be used when constraints exist in the operating environment. For example, when encountering power and / or thermal constraints, power can be reduced by reducing the operating frequency and / or voltage. Other power management techniques include regulating the execution rate of instructions or limiting the scheduling of instructions. Furthermore, the instructions of a given instruction set architecture may include explicit or implicit guidance regarding power management operations. Although described using these specific examples, it should be understood that many other power management techniques may be used in certain embodiments.

[0051] Embodiments may be implemented in processors for various markets, including server processors, desktop processors, mobile processors, etc. Figure 2 , shows a block diagram of a processor according to an embodiment of the present invention. Figure 2 As shown, the processor 200 may include multiple cores 210 a –210 nIn one embodiment, each such core may have an independent power domain and may be configured to enter and exit an active state and / or a maximum performance state based on workload. One or more cores 210 may be heterogeneous with the other cores, e.g., having different microarchitectures, instruction set architectures, pipeline depths, power, and performance capabilities. The various cores may be coupled to a system agent 220 comprising various components via an interconnect 215. As seen, the system agent 220 may include a shared cache 230, which may be a last level cache. In addition, the system agent may include an integrated memory controller 240 to communicate with system memory (e.g., via a memory bus) for example. Figure 2 System agent 220 also includes various interfaces 250 and a power control unit 255 (which may include logic for performing the power management techniques described herein).

[0052] In addition, various off-chip components (eg, peripheral devices, mass storage, etc.) can be connected via interfaces 250a-250n. Figure 2 The embodiments are shown by this specific implementation, but the scope of the present invention is not limited to this.

[0053] Although Figure 2 Not shown, but in some embodiments, the processor 200 may include the following reference Figures 26-30 All or part of the components and / or processes described.

[0054] Now refer to Figure 3 , shows a block diagram of a multi-domain processor according to another embodiment of the present invention. Figure 3 As shown in the embodiment of the present invention, the processor 300 includes multiple domains. Specifically, the core domain 310 may include multiple cores 310a-310n, the graphics domain 320 may include one or more graphics engines, and there may also be a system agent domain 350. In some embodiments, the system agent domain 350 can be executed at a frequency independent of the core domain and can always remain powered on to handle power control events and power management, so that the domains 310 and 320 can be controlled to dynamically enter and exit high-power states and low-power states. Each of the domains 310 and 320 can operate at different voltages and / or powers. Note that although only three domains are shown, it should be understood that the scope of the present invention is not limited to this, and additional domains may be present in other embodiments. For example, there may be multiple core domains, each core domain including at least one core.

[0055] Typically, in addition to the various execution units and additional processing elements, each core 310a-310n may also include a low-level cache. Furthermore, the various cores may be coupled to each other and to a shared cache memory formed by multiple units of the last level cache (LLC) 340a-340n. In various embodiments, the LLC 340 may be shared between the cores and the graphics engine and various media processing circuits. As can be seen, the ring interconnect 330 thus couples the cores together and provides an interconnect between the cores, the graphics domain 320, and the system agent domain 350. In one embodiment, the interconnect 330 may be part of the core domain. However, in other embodiments, the ring interconnect may have its own domain.

[0056] As can also be seen, the system agent domain 350 can include a display controller 352, which can provide control and interface to an associated display. As can also be seen, the system agent domain 350 can include a power control unit 355, which can include logic for performing the power management techniques described herein.

[0057] exist Figure 3 As can be seen in FIG, the processor 300 may also include an integrated memory controller (IMC) 370 that can provide an interface to system memory (e.g., dynamic random access memory (DRAM)). There may be multiple interfaces 380a-380n to enable interconnection between the processor and other circuits. For example, in one embodiment, at least one direct media interface (DMI) interface and one or more PCIe TM Furthermore, to provide communication between other agents (e.g., additional processors or other circuits), one or more QPI interfaces may also be provided. Figure 3 The embodiments are shown at this high level, but it should be understood that the scope of the present invention is not limited in this regard.

[0058] Although Figure 3 Not shown, but in some embodiments, the processor 300 may include the following reference Figures 26-30 All or part of the components and / or processes described.

[0059] Reference Figure 4 , shows an embodiment of a processor including multiple cores. Processor 400 includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system on a chip (SoC), or other device for executing code. In one embodiment, processor 400 includes at least two cores: cores 401 and 402, which may include asymmetric cores or symmetric cores (the embodiment shown). However, processor 400 may include any number of processing elements that may be symmetric or asymmetric.

[0060] In one embodiment, a processing element refers to hardware or logic for supporting a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and / or any other element capable of maintaining the state of a processor (e.g., an execution state or an architectural state). In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with code (e.g., a software thread, an operating system, an application, or other code). A physical processor typically refers to an integrated circuit that potentially includes any number of other processing elements (e.g., cores or hardware threads).

[0061] A core often refers to logic located on an integrated circuit that is capable of maintaining an independent architectural state, where each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast, a hardware thread typically refers to any logic located on an integrated circuit that is capable of maintaining an independent architectural state, where the independently maintained architectural states share access to execution resources. As can be seen, when some resources are shared and other resources are dedicated to an architectural state, the line between hardware thread and core nomenclature overlaps. Typically, an operating system views a core and a hardware thread as separate logical processors, where the operating system can schedule operations on each logical processor independently.

[0062] like Figure 4 As shown, physical processor 400 includes two cores: core 401 and 402. Here, cores 401 and 402 are considered symmetric cores (i.e., cores having the same configuration, functional units, and / or logic). In another embodiment, core 401 comprises an out-of-order processor core, while core 402 comprises an in-order processor core. However, cores 401 and 402 may be individually selected from any type of core (e.g., a native core, a software-managed core, a core adapted to execute a native instruction set architecture (ISA), a core adapted to execute a translated ISA, a co-designed core, or other known cores). Again for further discussion, the functional units shown in core 401 are described in more detail below, as the units in core 402 operate in a similar manner.

[0063] As depicted, core 401 includes two hardware threads 401a and 401b, which may also be referred to as hardware thread slots 401a and 401b. Thus, in one embodiment, a software entity (e.g., an operating system) potentially views processor 400 as four separate processors (i.e., four logical processors or processing elements capable of concurrently executing four software threads). As mentioned above, a first thread is associated with architecture state register 401a, a second thread is associated with architecture state register 401b, a third thread may be associated with architecture state register 402a, and a fourth thread may be associated with architecture state register 402b. Here, each architecture state register (401a, 401b, 402a, and 402b) may be referred to as a processing element, thread slot, or thread unit, as described above. As shown, architecture state register 401a is replicated in architecture state register 401b so that separate architecture states / contexts can be stored for both logical processor 401a and logical processor 401b. In core 401, other smaller resources, such as the instruction pointer and renaming logic in allocator and renamer block 430, may also be replicated for threads 401a and 401b. Some resources, such as the reorder buffer, branch target buffer, and instruction translation lookaside buffer (BTB and I-TLB) 420, load / store buffers, and queues in reorder / retirement unit 435, may be shared through partitioning. Other resources, such as general internal registers, page table base registers, low-level data cache and data TLB 450, execution units 440, and portions of reorder / retirement unit 435, may potentially be fully shared.

[0064] Processor 400 often includes other resources (which may be fully shared, shared through partitioning, or dedicated by / to processing elements). Figure 4 , an embodiment of a purely exemplary processor is shown with illustrative logical units / resources of the processor. Note that the processor may include or omit any of these functional units, and include any other known functional units, logic, or firmware not depicted. As shown, core 401 comprises a simplified representative out-of-order (OOO) processor core. However, in different embodiments, an in-order processor may be utilized.

[0065] Core 401 also includes a decode module 425, which is coupled to the prefetch unit to decode the prefetched elements. In one embodiment, the prefetch logic includes a separate sequencer associated with thread slots 401a and 401b, respectively. Typically, core 401 is associated with a first ISA that defines / specifies instructions executable on processor 400. Typically, machine code instructions that are part of the first ISA include the portion of the instruction (called an opcode) that references / specifies the instruction or operation to be performed. Decode module 425 includes circuitry that identifies instructions from their opcodes and passes the decoded instructions through the pipeline for processing as defined by the first ISA. For example, in one embodiment, decode module 425 includes logic designed or adapted to recognize specific instructions (e.g., transactional instructions). As a result of the recognition by decode module 425, the architecture or core 401 takes specific predefined actions to perform the task associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein can be performed in response to a single or multiple instructions (some of which may be new or old instructions).

[0066] In one example, the allocator and renamer block 430 includes an allocator for reserving resources (e.g., a register file) to store instruction processing results. However, threads 401a and 401b are potentially capable of out-of-order execution, wherein the allocator and renamer block 430 also reserves other resources (e.g., a reorder buffer) to track instruction results. The renamer block 430 may also include a register renamer for renaming program / instruction reference registers to other registers within the processor 400. The reorder / retirement unit 435 includes components (e.g., the reorder buffer, load buffer, and store buffer mentioned above) for supporting out-of-order execution of instructions executed out-of-order and later in-order retirement.

[0067] In one embodiment, scheduler and execution unit block 440 includes a scheduler unit for scheduling instructions / operations on execution units. For example, a floating-point instruction is scheduled on a port of an execution unit that has an available floating-point execution unit. A register file associated with each execution unit is also included to store information and instruction processing results. Exemplary execution units include a floating-point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.

[0068] A low-level data cache and data translation lookaside buffer (D-TLB) 450 are coupled to the execution unit 440. The data cache is used to store recently used / operated elements (e.g., data operands), which are potentially kept in a memory consistency state. The D-TLB is used to store recent virtual / linear to physical address translations. As a specific example, the processor may include a page table structure for splitting physical memory into multiple virtual pages.

[0069] Here, cores 401 and 402 share access to a higher level or further-out cache 410 for caching recently prefetched elements. Note that higher level or further-out refers to cache levels increasing or further from the execution units. In one embodiment, higher level cache 410 is a last level data cache - the last cache in the memory hierarchy architecture on processor 400 - such as a second or third level data cache. However, higher level cache 410 is not limited to this, as it can be associated with or include an instruction cache. A trace cache (a type of instruction cache) can instead be coupled after decode module 425 to store recently decoded traces.

[0070] In the depicted configuration, processor 400 also includes a bus interface 405 and a power control unit 460 (which can perform power management according to embodiments of the present invention). In this case, bus interface 405 is used to communicate with devices external to processor 400 (e.g., system memory and other components).

[0071] Memory controller 470 can interface with other devices (e.g., one or more memories). In an example, bus interface 405 includes a ring interconnect with a memory controller for interfacing with the memory and a graphics controller for interfacing with the graphics processor. In an SoC environment, even more devices (e.g., a network interface, a coprocessor, memory, a graphics processor, and any other known computer devices / interfaces) can be integrated on a single die or integrated circuit to provide a small form factor with high functionality and low power consumption.

[0072] Although Figure 4 Not shown, but in some embodiments, the processor 400 may include the following reference Figures 26-30 All or part of the components and / or processes described.

[0073] Now refer to Figure 5 , shows a block diagram of the micro-architecture of a processor core according to an embodiment of the present invention. Figure 5 As shown, the processor core 500 may be a multi-stage pipelined out-of-order processor. The core 500 may operate at various voltages based on a received operating voltage (which may be received from an integrated voltage regulator or an external voltage regulator).

[0074] As in Figure 5As can be seen in FIG, core 500 includes a front end unit 510 that can be used to prefetch instructions to be executed and prepare them for use later in the processor pipeline. For example, the front end unit 510 can include a prefetch unit 501, an instruction cache 503, and an instruction decoder 505. In some implementations, the front end unit 510 can also include a trace cache and a microcode store and a micro-operation store. The prefetch unit 501 can, for example, prefetch macroinstructions from a memory or instruction cache 503 and feed them to the instruction decoder 505 to decode them into primitives (i.e., micro-operations for execution by the processor).

[0075] Coupling between the front end unit 510 and the execution unit 520 is an out-of-order (OOO) engine 515, which can be used to receive microinstructions and prepare them for execution. More specifically, the OOO engine 515 may include various buffers for reordering the microinstruction stream and allocating the various resources required for execution, and for renaming logical registers to storage locations in various register files (e.g., register file 530 and extended register file 535). The register file 530 may include separate register files for integer operations and floating-point operations. For the purpose of configuration, control, and additional operations, a set of machine-specific registers (MSRs) 538 may also be present and accessible to various logics in the core 500 (and outside of the core).

[0076] Various resources may be present in execution units 520, including, in addition to dedicated hardware, various integer, floating point, and single instruction multiple data (SIMD) logic units, for example. For example, in addition to these execution units, these execution units may include one or more arithmetic logic units (ALUs) 522 and one or more vector execution units 524.

[0077] Results from the execution units may be provided to the retirement logic (i.e., re-order buffer (ROB) 540). More specifically, ROB 540 may include various arrays and logic for receiving information associated with the executed instructions. ROB 540 then examines this information to determine whether the instruction can be effectively retired and the result data delivered to the processor's architectural state, or whether one or more exceptions have occurred that prevent the correct retirement of the instruction. Of course, ROB 540 may also handle other operations associated with retirement.

[0078] like Figure 5 As shown, ROB 540 is coupled to cache 550, which in one embodiment may be a lower level cache (e.g., L1 cache), but the scope of the present invention is not limited in this regard. In addition, execution unit 520 may be directly coupled to cache 550. From cache 550, data communication may occur with higher level caches, system memory, etc. Although in Figure 5The embodiments of the present invention are shown at this high level, but it should be understood that the scope of the present invention is not limited to this. Figure 5 The implementation is about out-of-order machines (e.g. The present invention may be implemented in an in-order processor, a reduced instruction set computing (RISC) processor (e.g., an ARM-based processor), or another type of ISA processor capable of emulating instructions and operations of a different ISA via an emulation engine and associated logic circuitry.

[0079] Although Figure 5 Not shown, but in some embodiments, core 500 may include the following reference Figures 26-30 All or part of the components and / or processes described.

[0080] Now refer to Figure 6 , shows a block diagram of a micro-architecture of a processor core according to another embodiment. Figure 6 In embodiments of the present invention, core 600 may be a low-power core of a different microarchitecture (e.g., a core based on a processor with a relatively limited pipeline depth designed to reduce power consumption). Atom TM As seen, core 600 includes an instruction cache 610 coupled to provide instructions to an instruction decoder 615. Branch predictor 605 may be coupled to instruction cache 610. Note that instruction cache 610 may be further coupled to another level of cache memory (e.g., L2 cache (in Figure 6 In turn, the instruction decoder 615 provides the decoded instruction to the issue queue (IQ) 620 for storage and delivery to a given execution pipeline. A microcode ROM 618 is coupled to the instruction decoder 615.

[0081] The floating-point pipeline 630 includes a floating-point (FP) register file 632, which may include a plurality of architectural registers of a given bit width (e.g., 128, 256, or 512 bits). The pipeline 630 includes a floating-point scheduler 634 for scheduling instructions for execution on one of the pipeline's plurality of execution units. In the illustrated embodiment, these execution units include an ALU 635, a shuffle unit 636, and a floating-point adder 638. In turn, results generated in these execution units may be provided back to buffers and / or registers in the register file 632. Of course, it should be understood that, although illustrated with these few example execution units, in another embodiment, additional or different floating-point execution units may be present.

[0082] An integer pipeline 640 may also be provided. In the illustrated embodiment, the pipeline 640 includes an integer (INT) register file 642, which may include a plurality of architectural registers of a given bit width (e.g., 128 or 256 bits). The pipeline 640 includes an integer execution (IE) scheduler 644 for scheduling instructions for execution on one of the pipeline's multiple execution units. In the illustrated embodiment, these execution units include an ALU 645, a shifter unit 646, and a jump execution unit (JEU) 648. In turn, results generated in these execution units may be provided back to buffers and / or registers in the register file 642. Of course, it should be understood that although illustrated with these few example execution units, in another embodiment, additional or different integer execution units may be present.

[0083] A memory execution (ME) scheduler 650 may schedule memory operations for execution in an address generation unit (AGU) 652, which is also coupled to a TLB 654. As seen, these structures may be coupled to a data cache 660, which may be an L0 and / or L1 data cache, which in turn may be coupled to additional levels in the cache memory hierarchy (including an L2 cache memory).

[0084] To provide support for out-of-order execution, an allocator / renamer 670 may be provided in addition to a reorder buffer 680 configured to reorder instructions executed out-of-order so as to be retired in order. Figure 6 The description of FIGURES is shown with this particular pipeline architecture, but it should be understood that many variations and alternatives are possible.

[0085] Although Figure 6 Not shown, but in some embodiments, core 600 may include the following reference Figures 26-30 All or part of the components and / or processes described.

[0086] Note that in e.g. Figure 5 and Figure 6 In processors with asymmetric cores based on a microarchitecture, workloads can be dynamically swapped between cores for power management reasons, since these cores, while having different pipeline designs and depths, can have the same or related ISAs. This dynamic core swapping can be performed in a manner that is transparent to user applications (and potentially also transparent to the kernel).

[0087] Reference Figure 7 , shows a block diagram of the micro-architecture of a processor core according to yet another embodiment. Figure 7As shown, core 700 can include a multi-stage in-order pipeline for execution at very low power consumption levels. As one such example, core 700 can have a microarchitecture designed based on the ARM Cortex A53 available from ARM Holdings, LTD., Sunnyvale, CA. In an implementation, an 8-stage pipeline configured to execute both 32-bit and 64-bit code can be provided. Core 700 includes a prefetch unit 710 that is configured to prefetch instructions and provide them to a decode unit 715 that can decode instructions (e.g., macroinstructions of a given ISA (e.g., ARMv8 ISA)). Also note that a queue 730 can be coupled to the decode unit 715 to store decoded instructions. The decoded instructions are provided to an issue logic 725 where the decoded instructions can be issued to a given one of a plurality of execution units.

[0088] Further references Figure 7 , issue logic 725 may issue instructions to one of a plurality of execution units. In the embodiment shown, these execution units include an integer unit 735, a multiplication unit 740, a floating point / vector unit 750, a dual issue unit 760, and a load / store unit 770. The results of these different execution units may be provided to a write-back (WB) unit 780. It should be understood that while a single write-back unit is shown for ease of illustration, in some implementations, separate write-back units may be associated with each of the execution units. Furthermore, it should be understood that while the high level representation Figure 7 Each unit and logic shown, but a specific implementation may include more or different structures. It can be implemented in many different terminal products, from mobile devices to server systems, using Figure 7 A processor designed with one or more cores in a pipeline.

[0089] Although Figure 7 Not shown, but in some embodiments, core 700 may include the following reference Figures 26-30 All or part of the components and / or processes described.

[0090] Reference Figure 8 , shows a block diagram of the micro-architecture of a processor core according to yet another embodiment. Figure 8 As shown, core 800 may include a multi-stage, multi-issue, out-of-order pipeline for executing at very high performance levels (which may occur at higher performance levels than Figure 7As one such example, the processor 800 may have a microarchitecture designed according to the ARM Cortex A57. In an implementation, a 15 (or greater) stage pipeline configured to execute both 32-bit and 64-bit code may be provided. In addition, the pipeline may provide 3 (or greater) wide and 3 (or greater) issue operations. The core 800 includes a prefetch unit 810 that is configured to prefetch instructions and provide them to a decoder / renamer / dispatcher unit 815 coupled to a cache 820. The unit 815 may decode instructions (e.g., macroinstructions of the ARMv8 instruction set architecture), rename register references within the instructions, and (ultimately) dispatch the instructions to a selected execution unit. The decoded instructions may be stored in a queue 825. Note that while in Figure 8 A single queue structure is shown in FIG. 1 for ease of illustration, but it will be appreciated that separate queues may be provided for each of a variety of different types of execution units.

[0091] exist Figure 8 Also shown is issue logic 830, from which decoded instructions stored in queue 825 can be issued to selected execution units. Issue logic 830 can also be implemented in certain embodiments where the issue logic 830 is separate for each of multiple different types of execution units to which it is coupled.

[0092] The decoded instructions may be issued to a given one of a plurality of execution units. In the illustrated embodiment, these execution units include one or more integer units 835, multiplication units 840, floating point / vector units 850, branch units 860, and load / store units 870. In an embodiment, the floating point / vector units 850 may be configured to process 128 or 256 bits of SIMD or vector data. Further, the floating point / vector execution units 850 may perform IEEE-754 double precision floating point operations. The results of these different execution units may be provided to a write back unit 880. Note that in some implementations, a separate write back unit may be associated with each execution unit. Furthermore, it should be understood that although presented at a high level, Figure 8 Each unit and logic is shown, but certain implementations may include more or different structures.

[0093] Although Figure 8 Not shown, but in some embodiments, core 800 may include the following reference Figures 26-30 All or part of the components and / or processes described.

[0094] Note that in e.g. Figure 7 and Figure 8In processors with asymmetric cores based on a microarchitecture, workloads can be swapped dynamically for power management reasons because the cores, while having different pipeline designs and depths, can have the same or related ISAs. This dynamic core swapping can be performed in a manner that is transparent to user applications (and potentially also transparent to the kernel).

[0095] It can be used in many different terminal products, from mobile devices to server systems, to achieve the use of Figure 5-Figure 8 Any one or more pipelines of one or more cores of the processor design. Figure 9 , shows a block diagram of a processor according to another embodiment of the present invention. Figure 9 In an embodiment of the present invention, the processor 900 may be a SoC including multiple domains, each of which may be controlled to operate at an independent operating voltage and operating frequency. As a specific illustrative example, the processor 900 may be based on Architecture Core TM In one embodiment, the processor may be a processor (e.g., an i3, i5, i7, or another such processor available from Intel Corporation). However, in other embodiments (e.g., an Apple A7 processor, a Qualcomm Snapdragon processor, or a Texas Instruments OMAP processor), other low-power processors (e.g., a processor available from Advanced Micro Devices, Inc. (AMD) of Sunnyvale, CA, an ARM-based design from ARM Holdings, Ltd. or its licensors, or a MIPS-based design from MIPS Technologies, Inc. of Sunnyvale, CA or its licensors or adopters) may be present instead. Such a SoC may be used in low-power systems (e.g., smartphones, tablet computers, tablet-phone computers, Ultrabooks, etc.) that may include heterogeneous system architectures having processor designs based on heterogeneous system architectures. TM computer or other portable computing device).

[0096] exist Figure 9In the high-level view shown, the processor 900 includes multiple core units 910a-910n. Each core unit may include one or more processor cores, one or more cache memories, and other circuitry. Each core unit 910 can support one or more instruction sets (e.g., the x86 instruction set (newer versions have added some extensions); the MIPS instruction set; the ARM instruction set (with optional additional extensions (e.g., NEON)); or other instruction sets; or a combination thereof). Note that some core units can be heterogeneous resources (e.g., having different designs). In addition, each such core can be coupled to a cache memory (not shown), which in one embodiment can be a shared level 2 (L2) cache memory. Non-volatile storage 930 can be used to store various programs and other data. For example, the storage can be used to store at least a portion of microcode, boot information (e.g., BIOS), other system software, etc.

[0097] Each core unit 910 may also include an interface (e.g., a bus interface unit) for enabling interconnection of additional circuitry to the processor. In an embodiment, each core unit 910 is coupled to a coherence fabric, which may serve as a primary cache coherence on-die interconnect, which in turn is coupled to a memory controller 935. In turn, the memory controller 935 controls communication with memory (e.g., DRAM) (in Figure 9 for ease of illustration (not shown).

[0098] In addition to the core units, there are additional processing engines within the processor, including at least one graphics unit 920, which may include one or more graphics processing units (GPUs) for performing graphics processing and possibly general-purpose operations on the graphics processor (so-called GPGPU operations). In addition, there may be at least one image signal processor 925. The signal processor 925 may be configured to process incoming image data received from one or more capture devices internal to the SoC or external to the chip.

[0099] Other accelerators may also be present. Figure 9 In the illustrated embodiment, a video encoder 950 can perform encoding operations, including encoding and decoding video information, thereby providing hardware acceleration support for high-definition video content, for example. A display controller 955 can also be provided to accelerate display operations, including providing support for internal and external displays of the system. In addition, a security processor 945 can be present to perform security operations (e.g., secure boot operations, various cryptographic operations, etc.).

[0100] Each unit may have its power consumption controlled via a power manager 940 , which may include control logic for performing the various power management techniques described herein.

[0101] In some embodiments, the processor 900 may also include a non-coherent fabric coupled to a coherent fabric to which various peripheral devices may be coupled. One or more interfaces 960a-960d enable communication with one or more off-chip devices. These communications may be via a variety of communication protocols (e.g., PCIe TM ,GPIO,USB,I 2 C, UART, MIPI, SDIO, DDR, SPI, HDMI and other types of communication protocols). Although Figure 9 The embodiments are shown at this high level, but it should be understood that the scope of the present invention is not limited in this regard.

[0102] Although Figure 9 Not shown, but in some embodiments, the processor 900 may include the following reference Figures 26-30 All or part of the components and / or processes described.

[0103] Now refer to Figure 10 , shows a block diagram of a representative SoC. In the embodiment shown, SoC 1000 may be a multi-core SoC configured for low-power operation that is optimized for incorporation into a smartphone or other low-power device (e.g., a tablet or other portable computing device). As an example, SoC 1000 may be implemented using asymmetric or different types of cores (e.g., a combination of high-power cores and / or low-power cores (e.g., out-of-order cores and in-order cores). In different embodiments, these cores may be based on Architecture TM Core design or ARM architecture design. In yet other embodiments, a mix of Intel cores and ARM cores can be implemented in a given SoC.

[0104] exist Figure 10 As can be seen in FIG, SoC 1000 includes a first core domain 1010 having a plurality of first cores 1012a-1012d. In an example, these cores may be low-power cores (e.g., in-order cores). In one embodiment, these first cores may be implemented as ARM Cortex A53 cores. In turn, these cores are coupled to a cache memory 1015 of the core domain 1010. In addition, SoC 1000 includes a second core domain 1020. Figure 10 In the illustration of FIG, the second core domain 1020 has a plurality of second cores 1022a-1022d. In an example, these cores may be cores with higher power consumption than the first core 1012. In an embodiment, the second cores may be out-of-order cores, which may be implemented as ARM Cortex A57 cores. In turn, these cores are coupled to the cache memory 1025 of the core domain 1020. Note that although Figure 10The example shown includes 4 cores in each domain, but it should be understood that in other examples there may be more or fewer cores in a given domain.

[0105] Further references Figure 10 , a graphics domain 1030 is also provided, which may include one or more graphics processing units (GPUs) configured to independently execute graphics workloads, such as provided by one or more cores in core domains 1010 and 1020. As an example, in addition to providing graphics and display rendering operations, GPU domain 1030 may also be used to provide display support for various screen sizes.

[0106] As can be seen, the various domains are coupled to a coherent interconnect 1040, which in embodiments may be a cache coherent interconnect fabric, which in turn is coupled to an integrated memory controller 1050. In some examples, the coherent interconnect 1040 may include shared cache memory (e.g., an L3 cache). In embodiments, the memory controller 1050 may be a direct memory controller to provide multiple channels of communication with off-chip memory (e.g., DRAM (in Figure 10 Multiple channels (not shown for ease of illustration).

[0107] In different examples, the number of core domains may vary. For example, for a low-power SoC suitable for incorporation into a mobile computing device, there may be a limited number of core domains (e.g., Figure 10 ). Furthermore, in these low-power SoCs, the core domain 1020 that includes higher-power cores can have a smaller number of these cores. For example, in one implementation, two cores 1022 can be provided to enable operation at reduced power consumption levels. In addition, the different core domains can also be coupled to an interrupt controller to enable dynamic exchange of workloads between the different domains.

[0108] In yet other embodiments, there may be a greater number of core domains, as well as additional optional IP logic, as the SoC can be scaled to higher performance (and power) levels for incorporation into other computing devices (e.g., desktops, servers, high-performance computing systems, base stations, etc.). As one such example, four core domains may be provided, each with a given number of out-of-order cores. Still further, in addition to optional GPU support (which may take the form of GPGPU, for example), one or more accelerators may be provided to provide hardware support optimized for specific functions (e.g., web serving, network processing, switching, etc.). In addition, there may be input / output interfaces to couple these accelerators to off-chip components.

[0109] Although Figure 10Not shown, but in some embodiments, SoC 1000 may include the following reference Figures 26-30 All or part of the components and / or processes described.

[0110] Now refer to Figure 11 , shows a block diagram of another example SoC. Figure 11 In an embodiment, the SoC 1100 may include various circuits to achieve high performance for multimedia applications, communications, and other functions. Therefore, the SoC 1100 is suitable for incorporation into a variety of portable devices and other devices (e.g., smartphones, tablet computers, smart TVs, etc.). In the example shown, the SoC 1100 includes a central processor unit (CPU) domain 1110. In an embodiment, a plurality of individual processor cores may be present in the CPU domain 1110. As an example, the CPU domain 1110 may be a quad-core processor with four multi-threaded cores. These processors may be homogeneous or heterogeneous processors (e.g., a mix of low-power and high-power processor cores).

[0111] Furthermore, a GPU domain 1120 is provided to perform high-level graphics processing in one or more GPUs to handle graphics and compute APIs. A DSP unit 1130 may provide one or more low-power DSPs for processing low-power multimedia applications (e.g., music playback, audio / video, etc.) in addition to the high-level computations that may occur during the execution of multimedia instructions. Furthermore, a communication unit 1140 may include various components to communicate via various wireless protocols (e.g., cellular communications (including 3G / 4G LTE)), wireless LAN protocols (e.g., Bluetooth TM , IEEE 802.11, etc.) provide connectivity.

[0112] Furthermore, the multimedia processor 1150 can be used to perform the capture and playback of high-definition video and audio content (including processing of user gestures). The sensor unit 1160 can include multiple sensors and / or sensor controllers (for interfacing with various off-chip sensors present in a given platform). The image signal processor 1170 can be provided with one or more separate ISPs to perform image processing on content captured from one or more cameras of the platform (including still cameras and video cameras).

[0113] The display processor 1180 may provide support for connection to a high-definition display of a given pixel density, including the ability to wirelessly transfer content for playback on such a display. Furthermore, the location unit 1190 may include a GPS receiver supporting multiple GPS constellations to provide applications with highly accurate positioning information obtained using such a GPS receiver. It should be understood that although in Figure 11The examples are shown with specific sets of components, but many variations and alternatives are possible.

[0114] Although Figure 11 Not shown, but in some embodiments, SoC 1100 may include the following reference Figures 26-30 All or part of the components and / or processes described.

[0115] Now refer to Figure 12 , shows a block diagram of an example system that can be used with the embodiments. As can be seen, system 1200 can be a smartphone or other wireless communicator. Baseband processor 1205 is configured to perform various signal processing on communication signals to be sent from or received by the system. In turn, baseband processor 1205 is coupled to application processor 1210, which can be the system's main CPU for executing an OS and other system software in addition to user applications (e.g., many well-known social media and multimedia apps). Application processor 1210 can also be configured to perform a variety of other computing operations for the device.

[0116] In turn, the application processor 1210 can be coupled to a user interface / display 1220 (e.g., a touch screen display). Furthermore, the application processor 1210 can be coupled to a storage system, including non-volatile memory (i.e., flash memory 1230) and system memory (i.e., dynamic random access memory (DRAM) 1235). As also seen, the application processor 1210 is also coupled to a capture device 1240 (e.g., one or more image capture devices capable of recording video and / or still images).

[0117] Still refer to Figure 12 A universal integrated circuit card (UICC) 1246, including a subscriber identity module and possibly secure storage and encryption, is also coupled to the application processor 1210. The system 1200 may also include a security processor 1250, which may be coupled to the application processor 1210. A plurality of sensors 1225 may be coupled to the application processor 1210 to enable input of various sensed information (e.g., accelerometer and other environmental information). An audio output device 1295 may provide an interface for outputting sound in the form of, for example, voice communications, played or streamed audio data, etc.

[0118] As further shown, a near field communication (NFC) contactless interface 1260 is provided that communicates in the NFC near field via an NFC antenna 1265. Figure 12 Separate antennas are shown in FIG, but it should be understood that in some implementations, one antenna or a different set of antennas may be provided to enable various wireless functions.

[0119] A power management integrated circuit (PMIC) 1215 is coupled to the application processor 1210 to perform platform-level power management. To this end, the PMIC 1215 can issue power management requests to the application processor 1210 to enter a desired low-power state. Furthermore, based on platform constraints, the PMIC 1215 can also control the power levels of other components of the system 1200.

[0120] To enable sending and receiving communications, various circuits may be coupled between the baseband processor 1205 and the antenna 1290. Specifically, a radio frequency (RF) transceiver 1270 and a wireless local area network (WLAN) transceiver 1275 may be present. Typically, the RF transceiver 1270 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol (e.g., a 3G or 4G wireless communication protocol) (e.g., according to Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Long Term Evolution (LTE), or other protocols). In addition, a GPS sensor 1280 may be present. Other wireless communications may also be provided (e.g., receiving or transmitting radio signals (e.g., AM / FM and other signals)). Additionally, local wireless communications may also be implemented via the WLAN transceiver 1275.

[0121] Although Figure 12 Not shown, but in some embodiments, the system 1200 may include the following reference Figures 26-30 All or part of the components and / or processes described.

[0122] Now refer to Figure 13 , shows a block diagram of another example system that can be used with the embodiments. Figure 13 In the illustration of , system 1300 can be a mobile low-power system (e.g., a tablet computer, a 2:1 tablet, a tablet phone, or other convertible or standalone tablet system). As shown, there is a SoC 1310 that can be configured to operate as an application processor for the device.

[0123] A variety of devices can be coupled to SoC 1310. In the illustrated diagram, the memory subsystem includes flash memory 1340 and DRAM 1345 coupled to SoC 1310. Additionally, a touch panel 1320 is coupled to SoC 1310 to provide display capabilities and user input via touch, including providing a virtual keyboard on the display of touch panel 1320. To provide wired network connectivity, SoC 1310 is coupled to an Ethernet interface 1330. A peripheral hub 1325 is coupled to SoC 1310 to enable interfacing with various peripheral devices, such as those that may be coupled to system 1300 through any of a variety of ports or other connectors.

[0124] In addition to the internal power management circuitry and functionality within SoC 1310, PMIC 1380 is coupled to SoC 1310 to provide platform-based power management, for example, based on whether the system is powered by battery 1390 or AC power via AC adapter 1395. In addition to this source-based power management, PMIC 1380 can also perform platform power management activities based on environmental and usage conditions. Furthermore, PMIC 1380 can communicate control and status information to SoC 1310 to cause various power management actions within SoC 1310.

[0125] Still refer to Figure 13 To provide wireless capabilities, a WLAN unit 1350 is coupled to the SoC 1310 and, in turn, to an antenna 1355. In various implementations, the WLAN unit 1350 may provide communication according to one or more wireless protocols.

[0126] As further shown, a plurality of sensors 1360 may be coupled to the SoC 1310. These sensors may include various accelerometers, environmental sensors, and other sensors (including user gesture sensors). Finally, an audio codec 1365 is coupled to the SoC 1310 to provide an interface to an audio output device 1370. Of course, it should be understood that while Figure 13 The embodiment is shown with this particular implementation, but many variations and alternatives are possible.

[0127] Although Figure 13 Not shown, but in some embodiments, the system 1300 may include the following references Figures 26-30 All or part of the components and / or processes described.

[0128] Now refer to Figure 14 , shows a representative computer system 1400 (eg, notebook, Ultrabook TM or other small form factor systems). In one embodiment, processor 1410 comprises a microprocessor, a multi-core processor, a multi-threaded processor, an ultra-low voltage processor, an embedded processor, or other known processing element. In the illustrated implementation, processor 1410 serves as the main processing unit and hub for communicating with many of the various components of system 1400 and may include the power management circuitry described herein. As one example, processor 1410 is implemented as a SoC.

[0129] In one embodiment, processor 1410 is in communication with system memory 1415. As an illustrative example, system memory 1415 is implemented via multiple memory devices or modules to provide a fixed amount of system memory.

[0130] To provide persistent storage of information (e.g., data, applications, one or more operating systems, etc.), mass storage 1420 may also be coupled to processor 1410. In various embodiments, to enable thinner and lighter system designs and improve system responsiveness, this mass storage may be implemented via an SSD, or may be implemented primarily using a hard disk drive (HDD) with a smaller amount of SSD storage acting as an SSD cache to enable non-volatile storage of context state and other such information during a power loss event, enabling rapid power-up when system activity is reinitiated. Figure 14 Also shown in FIG14 , a flash memory device 1422 may be coupled to the processor 1410, for example, via a serial peripheral interface (SPI). The flash memory device may provide non-volatile storage for system software, including the system's basic input / output software (BIOS) and other firmware.

[0131] Various input / output (I / O) devices may be present within system 1400 . Figure 14 Specifically shown in the embodiment of FIG. 1 is a display 1424, which may be a high-definition LCD or LED panel that further provides a touch screen 1425. In one embodiment, the display 1424 may be coupled to the processor 1410 via a display interconnect, which may be implemented as a high-performance graphics interconnect. The touch screen 1425 may be coupled to the processor 1410 via another interconnect, which may be an I 2 C interconnection. Figure 14 As further shown, in addition to the touch screen 1425, user input by touch may also occur via a touch pad 1430, which may be configured within the housing and may also be coupled to the same I / O as the touch screen 1425. 2 C interconnection.

[0132] For sensory computing and other purposes, there may be various sensors within the system that may be coupled to the processor 1410 in different ways. Certain inertial and environmental sensors may be coupled to the processor 1410, for example, via I 2 The C interconnect is coupled to the processor 1410 through the sensor hub 1440. Figure 14 In the illustrated embodiment, these sensors may include an accelerometer 1441, an ambient light sensor (ALS) 1442, a compass 1443, and a gyroscope 1444. Other environmental sensors may include one or more thermal sensors 1446, which in some embodiments are coupled to processor 1410 via a system management bus (SMBus).

[0133] exist Figure 1414. As can be seen in FIG14, various peripheral devices can be coupled to processor 1410 via a low pin count (LPC) interconnect. In the embodiment shown, various components can be coupled through an embedded controller 1435. These components can include a keyboard 1436 (e.g., coupled via a PS2 interface), a fan 1437, and a thermal sensor 1439. In some embodiments, a touchpad 1430 can also be coupled to EC 1435 via a PS2 interface. In addition, a security processor (e.g., a trusted platform module (TPM) 1438) can also be coupled to processor 1410 via the LPC interconnect.

[0134] System 1400 can communicate with external devices in a variety of ways (including wirelessly). Figure 14 In the illustrated embodiment, various wireless modules are present, each of which may correspond to a radio configured for a specific wireless communication protocol. One method for short-range wireless communication (e.g., near field) may be via NFC unit 1445. In one embodiment, NFC unit 1445 may communicate with processor 1410 via SMBus. Note that via NFC unit 1445, devices in close proximity to each other may communicate.

[0135] As in Figure 14 As further seen in FIG, additional wireless units may include other short-range wireless engines, including WLAN unit 1450 and Bluetooth TM Unit 1452. Using WLAN unit 1450, Wi-Fi can be implemented TM Communication via Bluetooth TM Unit 1452, can generate short-range Bluetooth TM Communication. These units can communicate with the processor 1410 via given links.

[0136] Furthermore, wireless wide area communications, such as those according to cellular protocols or other wireless wide area protocols, may occur via a WWAN unit 1456, which in turn may be coupled to a subscriber identity module (SIM) 1457. Furthermore, to enable the receipt and use of location information, a GPS module 1455 may also be present. Figure 14 In the illustrated embodiment, the WWAN unit 1456 and the integrated capture device (eg, camera module 1454) may communicate via a given link.

[0137] To provide audio input and output, an audio processor may be implemented via a digital signal processor (DSP) 1460, which may be coupled to the processor 1410 via a high definition audio (HDA) link. Similarly, the DSP 1460 may communicate with an integrated coder / decoder (CODEC) and amplifier 1462, which in turn may be coupled to output speakers 1463, which may be implemented within the chassis. Similarly, the amplifier and CODEC 1462 may be coupled to receive audio input from a microphone 1465, which, in one embodiment, may be implemented via a dual array microphone (e.g., a digital microphone array) to provide high quality audio input to enable voice activated control of various operations within the system. Note also that audio output may be provided from the amplifier / CODEC 1462 to a headphone jack 1464. While in Figure 14 The embodiments are shown with these specific components, but it should be understood that the scope of the present invention is not limited thereto.

[0138] Although Figure 14 Not shown, but in some embodiments, the system 1400 may include the following reference Figures 26-30 All or part of the components and / or processes described.

[0139] The embodiments can be implemented by many different system types. Figure 15 , shows a block diagram of a system according to an embodiment of the present invention. Figure 15 As shown, the multiprocessor system 1500 is a point-to-point interconnect system and includes a first processor 1570 and a second processor 1580 coupled via a point-to-point interconnect 1550. Figure 15 As shown, each of processors 1570 and 1580 can be a multi-core processor, including first and second processor cores (i.e., processor cores 1574a and 1574b and processor cores 1584a and 1584b), but there can potentially be more cores in the processor. Each processor can include a PCU or other power management logic to perform processor-based power management as described herein.

[0140] Still refer to Figure 15 , the first processor 1570 further includes a memory controller hub (MCH) 1572 and point-to-point (PP) interfaces 1576 and 1578. Similarly, the second processor 1580 includes an MCH 1582 and PP interfaces 1586 and 1588. Figure 15As shown, MCHs 1572 and 1582 couple the processors to respective memories (i.e., memory 1532 and memory 1534), which may be part of system memory (e.g., DRAM) locally attached to the respective processors. First processor 1570 and second processor 1580 may be coupled to chipset 1590 via PP interconnects 1562 and 1564, respectively. Figure 15 As shown, chipset 1590 includes PP interfaces 1594 and 1598 .

[0141] In addition, the chipset 1590 includes an interface 1592 for coupling the chipset 1590 with the high-performance graphics engine 1538 via the PP interconnect 1539. Furthermore, the chipset 1590 can be coupled to the first bus 1516 via an interface 1596. Figure 15 As shown, various input / output (I / O) devices 1514 may be coupled to first bus 1516, along with a bus bridge 1518 that couples first bus 1516 to a second bus 1520. In one embodiment, various devices may be coupled to second bus 1520, including, for example, a keyboard / mouse 1522, communication devices 1526, and a data storage unit 1528 (e.g., a hard drive or other mass storage device), which may include code 1530. Additionally, an audio I / O 1524 may be coupled to second bus 1520. Embodiments may be incorporated into other types of systems, including mobile devices (e.g., smart cell phones, tablet computers, netbooks, ultrabooks, etc.). TM wait).

[0142] Although Figure 15 Not shown, but in some embodiments, system 1500 may include the following reference Figures 26-30 All or part of the components and / or processes described.

[0143] One or more aspects of at least one embodiment may be implemented by representative code representing and / or defining logic within an integrated circuit (e.g., a processor) stored on a machine-readable medium. For example, a machine-readable medium may include instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to manufacture logic to perform the techniques described herein. These representations (referred to as "IP cores") are reusable units of logic for an integrated circuit that may be stored on a tangible machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be provided to various consumers or manufacturing facilities, which load the hardware model onto a manufacturing machine for manufacturing the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any embodiment described herein.

[0144] Figure 161 is a block diagram illustrating an IP core development system 1600 that can be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 1600 can be used to generate modular, reusable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., a SoC integrated circuit). A design facility 1630 can generate a software simulation 1610 of the IP core design using a high-level programming language (e.g., C / C++). The software simulation 1610 can be used to design, test, and verify the behavior of the IP core. A register transfer level (RTL) design can then be created or synthesized from the simulation model. The RTL design 1615 is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including modeling the associated logic executed using the modeled digital signals. In addition to the RTL design 1615, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Therefore, the specific details of the initial design and simulation can vary.

[0145] The RTL design 1615 or equivalent may be further synthesized by the design facility into a hardware model 1620, which may be a hardware description language (HDL) or some other representation of the physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored using a non-volatile memory 1640 (e.g., a hard disk, flash memory, or any non-volatile storage medium) for transfer to a third party fabrication facility 1665. Alternatively, the IP core design may be sent via a wired connection 1650 or a wireless connection 1660 (e.g., via the Internet). The fabrication facility 1665 may then fabricate an integrated circuit based at least in part on the IP core design. The fabricated integrated circuit may be configured to perform the following operations according to the referenced embodiments of the present invention: Figures 26-30 The described components and / or processes perform operations.

[0146] The following description Figures 17A-25 Describe in detail the exemplary architecture and system to implement the following reference Figures 26-30 In some embodiments, Figures 26-30 One or more hardware components and / or instructions described in the EMBODIMENTS 100 may be simulated as described in detail below, or implemented as software modules.

[0147] The embodiments of the instructions described above can be implemented using the "universal vector friendly instruction format" described in detail below. In other embodiments, instead of utilizing this format, another instruction format is used. However, the following description of write mask registers, various data transformations (swizzles, broadcasts, etc.), addressing, etc., generally applies to the description of the embodiments of the instructions above. In addition, exemplary systems, architectures, and pipelines are described in detail below. The embodiments of the instructions above can be executed on these systems, architectures, and pipelines, but are not limited to those described in detail.

[0148] An instruction set may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, bit positions) and / or other data fields (e.g., masks) that specify the operation to be performed (e.g., opcode) and the operands on which the operation is to be performed. Some instruction formats may be further subdivided by defining instruction templates (or subformats). For example, instruction templates for a given instruction format may be defined to have different subsets of the fields of the instruction format (the included fields are typically in the same order, but at least some have different bit positions because there are fewer included fields), and / or to have different interpretations of given fields. Thus, each instruction of an ISA is expressed using a given instruction format (and using one of the given instruction templates for that instruction format, if defined)) and includes fields for specifying the operation and operands. For example, an exemplary ADD instruction has a specific opcode and instruction format that includes an opcode field for specifying the opcode and an operand field for selecting operands (source1 / destination and source2); and the appearance of the ADD instruction in an instruction stream will have specific content in the operand field for selecting the specific operand. A set of SIMD extensions called Advanced Vector Extensions (AVX) (AVX1 and AVX2) and using the Vector Extensions (VEX) encoding scheme have been released and / or disclosed (e.g., see 64 and IA-32 Architectures Software Developer's Manual, September 2014; and see Advanced Vector Extensions Programming Reference, October 2014).

[0149] Example instruction format

[0150] The embodiments of the instructions described herein may be embodied in different formats. In addition, exemplary systems, architectures, and pipelines are described in detail below. The embodiments of the instructions may be executed on these systems, architectures, and pipelines, but are not limited to those described in detail.

[0151] Generic vector-friendly instruction format

[0152] The vector friendly instruction format is an instruction format suitable for vector instructions (e.g., there are certain fields specific to vector operations). Although embodiments are described in which both vector and scalar operations are supported by the vector friendly instruction format, alternative embodiments only use vector operations of the vector friendly instruction format.

[0153] Figures 17A-17Bis a block diagram illustrating a general vector friendly instruction format and instruction templates thereof according to an embodiment of the present invention. Figure 17A is a block diagram illustrating a general vector friendly instruction format and a class A instruction template thereof according to an embodiment of the present invention; and Figure 17B 17 is a block diagram illustrating a generic vector friendly instruction format and its class B instruction templates according to an embodiment of the present invention. Specifically, class A and class B instruction templates are defined for the generic vector friendly instruction format 1700, both of which include a no memory access 1705 instruction template and a memory access 1720 instruction template. The term "generic" in the context of the vector friendly instruction format refers to an instruction format that is not tied to any particular instruction set.

[0154] While embodiments of the invention will be described in which the vector friendly instruction format supports: 64-byte vector operand lengths (or sizes) with 32-bit (4-byte) or 64-bit (8-byte) data element widths (or sizes) (and therefore, 64-byte vectors of 16 doubleword-sized elements or, alternatively, 8 quadword-sized elements); 64-byte vector operand lengths (or sizes) with 16-bit (2-byte) or 8-bit (1-byte) data element widths (or sizes); vector operand lengths (or sizes) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); vector operand lengths (or sizes) with 32-bit (4-byte), 64-bit (8-byte), or 16-bit (2 ... or 8-bit (1 byte) data element width (or size); and 16-bit vector operand lengths (or sizes) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1 byte) data element width (or size); however, alternative embodiments may support more, fewer, and / or different vector operand sizes (e.g., 256-byte vector operands) with more, fewer, or different data element widths (e.g., 128-bit (16-byte) data element width).

[0155] Figure 17A The class A instruction templates include: 1) within the no memory access 1705 instruction template, the no memory access, full rounding control type operation 1710 instruction template and the no memory access, data transformation type operation 1715 instruction template are shown; and 2) within the memory access 1720 instruction template, the memory access, temporary 1725 instruction template and the memory access, non-temporary 1730 instruction template are shown. Figure 17B The class B instruction templates include: 1) within the no memory access 1705 instruction template, there are shown the no memory access, write mask control, partial rounding control type operation 1712 instruction template and the no memory access, write mask control, vsize type operation 1717 instruction template; and 2) within the memory access 1720 instruction template, there is shown the memory access, write mask control 1727 instruction template.

[0156] The general vector friendly instruction format 1700 includes the following: Figures 17A-17B The following fields are listed in the order shown.

[0157] Format field 1740 - The specific value in this field (the instruction format identifier value) uniquely identifies the vector friendly instruction format, and therefore identifies the occurrence of instructions of the vector friendly instruction format in the instruction stream. Therefore, this field is optional in the sense that it is not required for instruction sets that only have the general vector friendly instruction format.

[0158] Basic operation field 1742 - its content distinguishes different basic operations.

[0159] Register index field 1744 - its contents specify the location of the source and destination operands (whether they are in registers or memory) directly or through address generation. They include a sufficient number of bits to select N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. While in one embodiment, N can be up to three source registers and one destination register, alternative embodiments can support more or fewer source and destination registers (e.g., can support up to two sources, one of which also serves as the destination; can support up to three sources, one of which also serves as the destination; can support up to two sources and one destination).

[0160] Modifier field 1746 - its content distinguishes occurrences of instructions of the generic vector instruction format that specify memory access from occurrences of instructions that do not specify memory access; that is, distinguishes between no memory access 1705 instruction templates and memory access 1720 instruction templates. Memory access operations read and / or write to the memory hierarchy (in some cases, using values ​​in registers to specify the source and / or destination addresses), while no memory access operations do not do so (e.g., the source and destination are registers). While in one embodiment this field also selects between three different ways to perform memory address calculations, alternative embodiments may support more, fewer, or different ways to perform memory address calculations.

[0161] Enhanced operation field 1750 - Its contents distinguish which of a variety of different operations is to be performed in addition to the basic operation. This field is context-specific. In one embodiment of the present invention, this field is divided into a class field 1768, an alpha field 1752, and a beta field 1754. Enhanced operation field 1750 allows a common set of operations to be performed in a single instruction instead of two, three, or four instructions.

[0162] Scale field 1760 - its content allows the contents of the index field to be scaled for use in memory address generation (e.g., address generation using 2 scale × index + base address).

[0163] Displacement field 1762A - its contents are used as part of memory address generation (e.g., address generation uses 2 scale × index + base address + displacement).

[0164] Displacement Factor field 1762B (note that the concatenation of displacement field 1762A directly over displacement factor field 1762B indicates that one or the other is used) - its contents are used as part of the address generation; it specifies the displacement factor to be scaled by the size of the memory access (N) - where N is the number of bytes in the memory access (e.g., address generation uses 2 scale

[00155] The displacement factor field 1762A and the displacement factor field 1762B are optional in the sense that they are not used in the no memory access 1705 instruction template, and / or different embodiments may implement only one or neither of them.

[0165] Data element width field 1764 - its content distinguishes which of multiple data element widths is to be used (in some embodiments, for all instructions; in other embodiments, only for some instructions). This field is optional in the sense that it is not needed if only one data element width is supported and / or multiple data element widths are supported using some aspect of the opcode.

[0166] Writemask field 1770—its contents control, on a per-data-element basis, whether that data-element position in the destination vector operand reflects the results of the base and enhanced operations. Class A instruction templates support merge-writemasking, while class B instruction templates support both merge-writemasking and zero-writemasking. When merged, a vector mask allows any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base and enhanced operations); in another embodiment, the old value of each element in the destination is preserved where the corresponding mask bit has a value of 0. In contrast, a zero-vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base and enhanced operations); in one embodiment, when the corresponding mask bit has a value of 0, the elements of the destination are set to 0. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span of elements being modified, from first to last); however, the modified elements do not need to be contiguous. Thus, writemask field 1770 allows for partial vector operations, including loads, stores, arithmetic, logical, and more. Although embodiments of the present invention are described in which the contents of write mask field 1770 select one of multiple write mask registers containing the write mask to be used (and therefore, the contents of write mask field 1770 indirectly identify the masking to be performed), alternative embodiments instead or additionally allow the contents of write mask field 1770 to directly indicate the masking to be performed.

[0167] Immediate field 1772 - its content allows the specification of an immediate value. This field is optional in the sense that it is not present in implementations that do not support the generic vector friendly format for immediate values, and it is not present in instructions that do not use immediate values.

[0168] Class field 1768 - its contents distinguish between different instruction classes. Figure 17A Figure 17-B, the content of this field selects between class A and class B instructions. Figures 17A-17B In , a rounded square is used to indicate the presence of a specific value in a field (e.g. Figures 17A-17B 1768A and class B 1768B for class field 1768, respectively).

[0169] Instruction template of class A

[0170] In the case of the no memory access 1705 instruction templates of class A, the alpha field 1752 is interpreted as the RS field 1752A, whose contents distinguish which of the different enhanced operation types is to be performed (e.g., for the no memory access, round type operation 1710 and the no memory access, data transformation type operation 1715 instruction templates, round 1752A.1 and data transformation 1752A.2 are specified, respectively), while the beta field 1754 distinguishes which of the specified types of operations is to be performed. In the no memory access 1705 instruction templates, the scale field 1760, the displacement field 1762A, and the displacement factor field 1762B are not present.

[0171] No memory access instruction templates - full rounding type operations

[0172] In the no memory access full round control type operation 1710 instruction template, the beta field 1754 is interpreted as a round control field 1754A, the contents of which provide static rounding. Although in the described embodiment of the present invention, the round control field 1754A includes a suppress all floating point exceptions (SAE) field 1756 and a round operation control field 1758, alternative embodiments may support encoding these two concepts in the same field, or having only one or the other of these concepts / fields (e.g., only the round operation control field 1758).

[0173] SAE field 1756 - its content distinguishes whether exception event reporting is to be disabled; when the content of the SAE field 1756 indicates that suppression is enabled, the given instruction does not report any kind of floating point exception flags and does not cause any floating point exception handler to be called.

[0174] Round operation control field 1758 - its contents distinguish which of a set of rounding operations is to be performed (e.g., round up, round down, round toward zero, and round toward nearest). Thus, round operation control field 1758 allows the rounding mode to be changed on a per-instruction basis. In one embodiment of the invention where the processor includes a control register for specifying the rounding mode, the contents of round operation control field 1750 take precedence over the register value.

[0175] No memory access instruction templates - data transformation type operations

[0176] In the no memory access data transform type operation 1715 instruction template, the beta field 1754 is interpreted as a data transform field 1754B, the contents of which distinguish which of multiple data transforms is to be performed (eg, no data transform, swizzle, broadcast).

[0177] In the case of a memory access 1720 instruction template of class A, the alpha field 1752 is interpreted as an eviction hint field 1752B, the contents of which distinguish which of the eviction hints to use (in Figure 17A 1752B.1 and non-temporary 1752B.2), respectively, are specified for the memory access, temporary 1725 instruction template and the memory access, non-temporary 1730 instruction template, and the beta field 1754 is interpreted as a data manipulation field 1754C, the contents of which distinguish which of a plurality of data manipulation operations (also known as primitives) is to be performed (e.g., no manipulation; broadcast; upconversion of the source; downconversion of the destination). The memory access 1720 instruction template includes a scale field 1760 and optionally a displacement field 1762A or a displacement factor field 1762B.

[0178] Vector memory instructions perform vector loads from memory and vector stores to memory, with support for conversions. Like regular vector instructions, vector memory instructions transfer data to / from memory in an element-by-data-element manner, where the actual elements transferred are dictated by the contents of the vector mask selected as the writemask.

[0179] Memory Access Instruction Templates – Temporary

[0180] Temporary data is data that is likely to be reused quickly enough to benefit from caching. However, this is a hint, and different processors can implement it in different ways, including ignoring the hint completely.

[0181] Memory access instruction templates – non-temporal

[0182] Non-temporal data is data that is unlikely to be reused quickly enough to benefit from being cached in the level 1 cache, and should be evicted first. However, this is a hint, and different processors can implement it in different ways, including ignoring the hint completely.

[0183] Instruction template for class B

[0184] In the case of instruction templates of class B, the alpha field 1752 is interpreted as a write mask control (Z) field 1752C, the contents of which distinguish whether the write mask controlled by the write mask field 1770 should be merge or zero.

[0185] In the case of the no memory access 1705 instruction template of class B, a portion of the beta field 1754 is interpreted as the RL field 1757A, the contents of which distinguish which of the different enhanced operation types is to be performed (e.g., for the no memory access, write mask control, partial rounding control type operation 1712 instruction template and the no memory access, write mask control, VSIZE type operation 1717 instruction template, rounding 1757A.1 and vector length (VSIZE) 1757A.2 are specified, respectively), while the remainder of the beta field 1754 distinguishes which of the specified types of operations is to be performed. In the no memory access 1705 instruction template, the scale field 1760, the displacement field 1762A, and the displacement factor field 1762B are not present.

[0186] In the no memory access, write mask control, partial rounding control type operation 1710 instruction template, the remainder of the beta field 1754 is interpreted as the rounding operation field 1759A, and exception event reporting is disabled (the given instruction does not report any kind of floating-point exception flags and does not cause any floating-point exception handler to occur).

[0187] Round Operation Control Field 1759A - Just as with Round Operation Control Field 1758, its contents distinguish which of a set of rounding operations (e.g., round up, round down, round toward zero, and round toward nearest) is to be performed. Thus, Round Operation Control Field 1759A allows the rounding mode to be changed on a per-instruction basis. In one embodiment of the invention where the processor includes a control register for specifying the rounding mode, the contents of Round Operation Control Field 1750 take precedence over the register value.

[0188] In the no memory access, write mask control, VSIZE type operation 1717 instruction template, the remainder of the beta field 1754 is interpreted as a vector length field 1759B, the contents of which distinguish which of multiple data vector lengths is to be performed (e.g., 128, 256, or 512 bytes).

[0189] In the case of a memory access 1720 instruction template of class B, a portion of the beta field 1754 is interpreted as a broadcast field 1757B, the contents of which distinguish whether a broadcast-type data manipulation operation is to be performed, while the remainder of the beta field 1754 is interpreted as a vector length field 1759B. The memory access 1720 instruction template includes a scale field 1760 and optionally a displacement field 1762A or a displacement factor field 1762B.

[0190] With respect to the generic vector friendly instruction format 1700, a full opcode field 1774 is shown that includes the format field 1740, the basic operation field 1742, and the data element width field 1764. While one embodiment is shown in which the full opcode field 1774 includes all of these fields, in embodiments that do not support all of the fields, the full opcode field 1774 includes fewer than all of these fields. The full opcode field 1774 provides an operation code (opcode).

[0191] The enhanced operation field 1750, the data element width field 1764, and the write mask field 1770 allow these features to be specified on a per-instruction basis in the generic vector friendly instruction format.

[0192] The combination of the write mask field and the data element width field creates a typed instruction because they allow the mask to be applied based on different data element widths.

[0193] The various instruction templates found within classes A and B are beneficial in different situations. In some embodiments of the present invention, different processors or different cores within a processor may support only class A, only class B, or both classes. For example, a high-performance general-purpose out-of-order core intended for general-purpose computing may support only class B, a core intended primarily for graphics and / or scientific (throughput) computing may support only class A, and a core intended for both may support both (of course, a core with some mix of templates and instructions from both classes, but not all templates and instructions from both classes, is within the scope of the present invention). In addition, a single processor may include multiple cores, all of which support the same class, or different cores may support different classes. For example, in a processor with separate graphics cores and general-purpose cores, one of the graphics cores intended primarily for graphics and / or scientific computing may support only class A, while one or more of the general-purpose cores may be a high-performance general-purpose core with out-of-order execution and register renaming intended for general-purpose computing that supports only class B. Another processor without a separate graphics core may include one or more general-purpose in-order or out-of-order cores that support both classes A and B. Of course, in different embodiments of the present invention, features from one class may also be implemented in another class. A program written in a high-level language will be placed (e.g., compiled just in time or statically) into a variety of different executable forms, including: 1) a form having only instructions of the class supported by the target processor for execution; or 2) a form having alternative routines written using different combinations of instructions from all classes and having control flow code that selects the routine to be executed based on the instructions supported by the processor currently executing the code.

[0194] Exemplary dedicated vector friendly instruction format

[0195] Figures 18A-18Cis a block diagram illustrating an exemplary specific vector friendly instruction format according to an embodiment of the present invention. Figure 18A A specific vector friendly instruction format 1800 is shown, which is specific in the sense that it specifies the location, size, interpretation, and order of fields, as well as the values ​​of some of these fields. The specific vector friendly instruction format 1800 can be used to extend the x86 instruction set, and therefore some fields are similar or identical to those used in the existing x86 instruction set and its extensions (e.g., AVX). The format is consistent with the prefix encoding field, real opcode byte field, MOD R / M field, SIB field, displacement field, and immediate field of the existing x86 instruction set with extensions. Figures 18A-18B The fields are mapped to Figures 17A-17B fields.

[0196] It should be understood that although embodiments of the present invention are described with reference to the specific vector friendly instruction format 1800 in the context of the general vector friendly instruction format 1700 for illustrative purposes, the present invention is not limited to the specific vector friendly instruction format 1800, except where required. For example, the general vector friendly instruction format 1700 contemplates a variety of possible sizes for various fields, while the specific vector friendly instruction format 1800 is shown as having fields of specific sizes. By way of specific example, although the data element width field 1764 is shown as a one-bit field in the specific vector friendly instruction format 1800, the present invention is not limited thereto (i.e., the specific vector friendly instruction format 1800 contemplates other sizes for the data element width field 1764).

[0197] The dedicated vector friendly instruction format 1800 includes the following: Figure 18A The following fields are listed in the order shown.

[0198] EVEX prefix (bytes 0-3) 1802 - encoded in four bytes.

[0199] Format field 1740 (EVEX byte 0, bits [7:0]) - The first byte (EVEX byte 0) is the format field 1740, which contains 0x62 (a unique value used to distinguish the vector friendly instruction format in one embodiment of the present invention).

[0200] The second through fourth bytes (EVEX bytes 1-3) include a number of bit fields that provide specific capabilities.

[0201] REX field 1805 (EVEX byte 1, bits [7-5]) - includes the EVEX.R bit field (EVEX byte 1, bits [7]-R), the EVEX.X bit field (EVEX byte 1, bits [6]-X), and the EVEX.B byte 1, bits [5]-B. The EVEX.R, EVEX.X, and EVEX.B bit fields provide the same functionality as the corresponding VEX bit fields and are encoded using 1s complement form, i.e., ZMM0 is encoded as 1111B and ZMM15 is encoded as 0000B. The other fields of the instruction encode the lower three bits of the register index (rrr, xxx, and bbb), as is known in the art, such that Rrrr, Xxxx, and Bbbb can be formed by adding EVEX.R, EVEX.X, and EVEX.B.

[0202] REX' field 1810 - This is the first part of the REX' field 1810 and is the EVEX.R' bit field (EVEX byte 1, bit [4] - R') used to encode the upper 16 or lower 16 of the extended 32-register set. In one embodiment of the present invention, this bit, along with the other bits indicated below, is stored in bit-reversed format to distinguish it from the BOUND instruction (actually, the opcode byte is 62) in the well-known x86 32-bit mode, but does not accept a MOD field value of 11 in the MOD R / M field (described below); alternative embodiments of the present invention do not store this bit and the other bits indicated below in reverse format. A value of 1 is used to encode the lower 16 registers. In other words, R'Rrrr is formed by combining EVEX.R', EVEX.R, and the other RRRs from the other fields.

[0203] Opcode map field 1815 (EVEX byte 1, bits [3:0] – mmmm)—its contents encode the implied leading opcode byte (0F, 0F 38, or 0F 3).

[0204] Data element width field 1764 (EVEX byte 2, bit [7] – W) – denoted by the symbol EVEX.W. EVEX.W is used to define the granularity (size) of the data type (32-bit data element or 64-bit data element).

[0205] EVEX.vvvv 1820 (EVEX byte 2, bits [6:3]-vvvv) - The roles of EVEX.vvvv can include the following: 1) EVEX.vvvv encodes the first source register operand specified in inverted (1s complement) form and is valid for instructions with 2 or more source operands; 2) EVEX.vvvv encodes the destination register operand specified in 1s complement form for certain vector shifts; or 3) EVEX.vvvv does not encode any operand, the field is reserved and should contain 1111b. Therefore, EVEX.vvvv field 1820 encodes the 4 low-order bits of the first source register specifier stored in inverted (1s complement) form. Depending on the instruction, additional different EVEX bit fields are used to extend the specifier size to 32 registers.

[0206] EVEX.U 1768 Class field (EVEX byte 2, bit [2] - U) - If EVEX.U = 0, it indicates class A or EVEX.U0; if EVEX.U = 1, it indicates class B or EVEX.U1.

[0207] Prefix encoding field 1825 (EVEX byte 2, bits [1:0]-pp) - provides additional bits for the base operation field. In addition to providing support for legacy SSE instructions in EVEX prefix format, this also has the benefit of compressing the SIMD prefix (instead of requiring a byte to express the SIMD prefix, the EVEX prefix only requires 2 bits). In one embodiment, to support legacy SSE instructions that use SIMD prefixes (66H, F2H, F3H) in both the legacy format and the EVEX prefix format, these legacy SIMD prefixes are encoded in the SIMD prefix encoding field; and at runtime, they are expanded into the legacy SIMD prefix and then provided to the decoder's PLA (so the PLA can execute both the legacy and EVEX formats of these legacy instructions without modification). Although newer instructions can use the contents of the EVEX prefix encoding field directly as an opcode extension, some embodiments extend it in a similar manner for consistency, but allow these legacy SIMD prefixes to specify different meanings. Alternative embodiments can redesign the PLA to support 2-bit SIMD prefix encodings and thus not require expansion.

[0208] Alpha field 1752 (EVEX byte 3, bit [7] - EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.write mask control, and EVEX.N; also shown by α) - As previously described, this field is context specific.

[0209] beta field 1754 (EVEX byte 3, bits [6:4] - SSS, also known as EVEX.s 2-0 EVEX.r 2-0 , EVEX.rr1, EVEX.LL0, EVEX.LLB; also shown by βββ) - As previously described, this field is context-specific.

[0210] REX' field 1810 - This is the remainder of the REX' field and is the EVEX.V' bit field (EVEX byte 3, bit [3] - V') that can be used to encode the upper 16 or lower 16 of the extended 32-register set. This bit is stored in bit-reversed format. A value of 1 is used to encode the lower 16 registers. In other words, V'VVVV is formed by combining EVEX.V' and EVEX.vvvv.

[0211] Write mask field 1770 (EVEX byte 3, bits [2:0] - kkk) - its contents specify the index of a register in the write mask register, as previously described. In one embodiment of the invention, the special value EVEX.kkk = 000 has special behavior that implies no write mask is used for the particular instruction (this can be implemented in a variety of ways, including using hardware that is hardwired to all registers or bypassing the masking hardware).

[0212] The real operation code field 1830 (byte 4) is also called the operation code byte. A portion of the operation code is specified in this field.

[0213] The MOD R / M field 1840 (byte 5) includes a MOD field 1842, a Reg field 1844, and an R / M field 1846. As previously described, the contents of the MOD field 1842 distinguish between memory access operations and non-memory access operations. The role of the Reg field 1844 can be summarized as follows: encoding a destination register operand or a source register operand, or being treated as an opcode extension and not used to encode any instruction operand. The role of the R / M field 1846 can include the following: encoding an instruction operand that references a memory address, or encoding a destination register operand or a source register operand.

[0214] Scale, Index, Base (SIB) Byte (Byte 6) - As previously described, the contents of the scale field 1850 are used for memory address generation. SIB.xxx 1854 and SIB.bbb 1856 - The contents of these fields have been mentioned previously with respect to register indices Xxxx and Bbbb.

[0215] Displacement field 1762A (bytes 7-10) - When the MOD field 1842 contains 10, bytes 7-10 are the displacement field 1762A, and it works the same as the legacy 32-bit displacement (disp32) and works at byte granularity.

[0216] Displacement Factor Field 1762B (Byte 7) - When the MOD field 1842 contains 01, byte 7 is the displacement factor field 1762B. The location of this field is the same as the location of the legacy x86 instruction set 8-bit displacement (disp8), which works at byte granularity. Because disp8 is sign-extended, it can only address offsets between -128 and 127 bytes; in terms of a 64-byte cache line, disp8 uses 8 bits, which can be set to only four truly useful values: -128, -64, 0, and 64; because a larger range is often needed, disp32 is used; however, disp32 requires 4 bytes. In contrast to disp8 and disp32, the displacement factor field 1762B is a reinterpretation of disp8; when the displacement factor field 1762B is used, the actual displacement is determined by the contents of the displacement factor field multiplied by the size (N) of the memory operand access. This type of displacement is called disp8×N. This reduces the average instruction length (a single byte is used for the displacement, but with a much larger range). This compressed displacement is based on the assumption that the effective displacement is a multiple of the granularity of the memory access, and therefore, there is no need to encode the redundant low-order bits of the address offset. In other words, the displacement factor field 1762B replaces the legacy x86 instruction set 8-bit displacement. Therefore, the displacement factor field 1762B is encoded in the same manner as the x86 instruction set 8-bit displacement (so, the ModRM / SIB encoding rules are unchanged), with the only exception that disp8 is overloaded to disp8×N. In other words, there is no change in the encoding rules or encoding length, only in the hardware's interpretation of the displacement value (which requires scaling the displacement by the size of the memory operand to obtain a byte-by-byte address offset). The immediate field 1772 operates as previously described.

[0217] Full opcode field

[0218] Figure 18B is a block diagram illustrating the fields of a specific vector friendly instruction format 1800 that make up a full opcode field 1774, according to one embodiment of the present invention. Specifically, the full opcode field 1774 includes a format field 1740, a basic operation field 1742, and a data element width (W) field 1764. The basic operation field 1742 includes a prefix encoding field 1825, an opcode map field 1815, and a real opcode field 1830.

[0219] Register index field

[0220] Figure 18C is a block diagram illustrating the fields of the specific vector friendly instruction format 1800 that make up the register index field 1744, according to one embodiment of the present invention. Specifically, the register index field 1744 includes a REX field 1805, a REX' field 1810, a MODR / M.reg field 1844, a MODR / Mr / m field 1846, a VVVV field 1820, a xxx field 1854, and a bbb field 1856.

[0221] Enhanced Action Field

[0222] Figure 18D 1 is a block diagram illustrating the fields of the specific vector friendly instruction format 1800 that make up the enhanced operation field 1750 according to one embodiment of the present invention. When the class (U) field 1768 contains 0, it indicates EVEX.U0 (class A 1768A); when it contains 1, it indicates EVEX.U1 (class B 1768B). When U=0 and the MOD field 1842 contains 11 (indicating a no memory access operation), the alpha field 1752 (EVEX byte 3, bit [7] - EH) is interpreted as the rs field 1752A. When the rs field 1752A contains 1 (round 1752A.1), the beta field 1754 (EVEX byte 3, bits [6:4] - SSS) is interpreted as the round control field 1754A. The round control field 1754A includes a one-bit SAE field 1756 and a two-bit round operation field 1758. When the rs field 1752A contains 0 (data transformation 1752A.2), the beta field 1754 (EVEX byte 3, bits [6:4]-SSS) is interpreted as a three-bit data transformation field 1754B. When U=0 and the MOD field 1842 contains 00, 01, or 10 (indicating a memory access operation), the alpha field 1752 (EVEX byte 3, bits [7]-EH) is interpreted as an eviction hint (EH) field 1752B, and the beta field 1754 (EVEX byte 3, bits [6:4]-SSS) is interpreted as a three-bit data manipulation field 1754C.

[0223] When U=1, the alpha field 1752 (EVEX byte 3, bit [7]–EH) is interpreted as the write mask control (Z) field 1752C. When U=1 and the MOD field 1842 contains 11 (indicating a no memory access operation), a portion of the beta field 1754 (EVEX byte 3, bit [4]–S0) is interpreted as the RL field 1757A; when it contains 1 (rounded 1757A.1), the remainder of the beta field 1754 (EVEX byte 3, bits [6-5]–S0) is interpreted as the RL field 1757A. 2-1) is interpreted as the rounding operation field 1759A, and when the RL field 1757A contains 0 (VSIZE 1757.A2), the remainder of the beta field 1754 (EVEX byte 3, bits [6-5]-S 2-1 ) is interpreted as the vector length field 1759B (EVEX byte 3, bits [6-5] - L1-0). When U=1 and the MOD field 1842 contains 00, 01, or 10 (indicating a memory access operation), the beta field 1754 (EVEX byte 3, bits [6:4] - SSS) is interpreted as the vector length field 1759B (EVEX byte 3, bits [6-5] - L1-0). 1-0 ) and the broadcast field 1757B (EVEX byte 3, bit [4]-B).

[0224] Exemplary Register Architecture

[0225] Figure 19 is a block diagram of a register architecture 1900 according to one embodiment of the present invention. In the illustrated embodiment, there are 32 vector registers 1910 that are 512 bits wide; these registers are referenced as zmm0 through zmm31. The low-order 256 bits of the lower 16 zmm registers are overlapped with registers ymm0-16. The low-order 128 bits of the lower 16 zmm registers (the low-order 128 bits of the ymm registers) are overlapped with registers xmm0-15. The specific vector-friendly instruction format 1800 operates on these overlapping register files as shown in the following table.

[0226]

[0227] In other words, the vector length field 1759B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the previous length; and instruction templates without a vector length field 1759B operate on the maximum vector length. Furthermore, in one embodiment, the class B instruction templates of the dedicated vector friendly instruction format 1800 operate on packed or scalar single / double precision floating point data and packed or scalar integer data. Scalar operations are operations performed on the lowest-order data element position in the zmm / ymm / xmm register; higher-order data element positions are left at the same position as they were before the instruction, or are reset to zero, depending on the embodiment.

[0228] Write mask registers 1915 - In the embodiment shown, there are eight write mask registers (k0 through k7), each 64 bits in size. In an alternative embodiment, write mask registers 1915 are 16 bits in size. As previously mentioned, in one embodiment of the present invention, vector mask register k0 cannot be used as a write mask; when an encoding that would normally indicate k0 is used for a write mask, it selects a hardwired write mask of 0xFFFF, effectively disabling write masking for that instruction.

[0229] General Purpose Registers 1925 - In the embodiment shown, there are sixteen 64-bit general purpose registers that are used to address memory operands along with existing x86 addressing modes. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0230] Scalar floating point stack register file (x87 stack) 1945, with the MMX packed integer flat 4 register file 1950 aliased on it - in the embodiment shown, the x87 stack is an eight-element stack used to perform scalar floating point operations on 32 / 64 / 80-bit floating point data using the x87 instruction set extension; while the MMX registers are used to perform operations on 64-bit packed integer data and to hold operands for some operations performed between MMX and XMM registers.

[0231] Alternative embodiments of the present invention may use wider or narrower registers.In addition, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0232] Exemplary Core Architectures, Processors, and Computer Architectures

[0233] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of these cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a specialized core intended primarily for graphics and / or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU that includes one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor that includes one or more specialized cores intended primarily for graphics and / or scientific (throughput). These different processors result in different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor in the same package as the CPU, but on a separate die; 3) a coprocessor on the same die as the CPU (in which case the coprocessor is sometimes referred to as specialized logic (e.g., integrated graphics and / or scientific (throughput) logic) or a specialized core); and 4) a system on a chip that may include the described CPU (sometimes referred to as an application core or application processor), the above-mentioned coprocessor, and additional functionality on the same die. An exemplary core architecture is described next, followed by a description of exemplary processor and computer architectures.

[0234] Exemplary Core Architecture

[0235] In-order and out-of-order core block diagram

[0236] Figure 20A is a block diagram illustrating an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to an embodiment of the present invention. Figure 20B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to an embodiment of the present invention. Figure 20A-Figure 20B The solid line boxes in show the in-order pipeline and in-order core, while the optional addition of dashed line boxes shows the register renaming, out-of-order issue / execution pipeline and core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0237] exist Figure 20A , the processor pipeline 2000 includes a prefetch stage 2002, a length decoding stage 2004, a decoding stage 2006, an allocation stage 2008, a renaming stage 2010, a scheduling (also called dispatch or emission) stage 2012, a register read / memory read stage 2014, an execution stage 2016, a write back / memory write stage 2018, an exception handling stage 2022, and a commit stage 2024.

[0238] Figure 20BA processor core 2090 is shown, comprising a front end unit 2030 coupled to an execution engine unit 2050, and both coupled to a memory unit 2070. The core 2090 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the core 2090 may be a specialized core (e.g., a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.).

[0239] The front end unit 2030 includes a branch prediction unit 2032, which is coupled to an instruction cache unit 2034, which is coupled to an instruction translation lookaside buffer (TLB) 2036, which is coupled to an instruction prefetch unit 2038, which is coupled to a decode unit 2040. The decode unit 2040 (or decoder) can decode instructions and generate as output one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals that are decoded from, reflect, or derived from the original instruction. The decode unit 2040 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read-only memories (ROMs), and the like. In one embodiment, the core 2090 includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in the decode unit 2040 or within the front end unit 2030). The decode unit 2040 is coupled to the rename / allocator unit 2052 in the execution engine unit 2050 .

[0240] The execution engine unit 2050 includes a rename / allocator unit 2052, which is coupled to a retire unit 2054 and a set of one or more scheduler units 2056. The scheduler units 2056 represent any number of different schedulers, including reservation stations, central instruction windows, and the like. The scheduler units 2056 are coupled to physical register file units 2058. Each physical register file unit 2058 represents one or more physical register files, where different physical register file units store one or more different data types (e.g., scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed)). In one embodiment, the physical register file units 2058 include a vector register unit, a write mask register unit, and a scalar register unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file unit 2058 overlaps with the retire unit 2054 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using a reorder buffer and a retire register file; using a future file, a history buffer, and a retire register file; using a register map and a pool of registers; etc.). The retire unit 2054 and the physical register file unit 2058 are coupled to an execution cluster 2060. The execution cluster 2060 includes a set of one or more execution units 2062 and a set of one or more memory access units 2064. The execution units 2062 can perform various operations (e.g., shifts, additions, subtractions, multiplications) on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit 2056, physical register file unit 2058, and execution cluster 2060 are shown as possibly multiple because some embodiments create separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline, each with its own scheduler unit, physical register file unit, and / or execution cluster—and in the case of a separate memory access pipeline, some embodiments implement only the execution cluster of that pipeline with a memory access unit 2064). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, while the rest are in-order.

[0241] The set of memory access units 2064 is coupled to the memory unit 2070 and includes a data TLB unit 2072, which is coupled to a data cache unit 2074, which is coupled to a level 2 (L2) cache unit 2076. In one exemplary embodiment, the memory access unit 2064 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 2072 in the memory unit 2070. The instruction cache unit 2034 is also coupled to a level 2 (L2) cache unit 2076 in the memory unit 2070. The L2 cache unit 2076 is coupled to one or more other levels of cache and ultimately to main memory.

[0242] By way of example, an exemplary register renaming, out-of-order issue / execution core architecture may implement pipeline 2000 as follows: 1) instruction prefetch 2038 executes prefetch stage 2002 and length decode stage 2004; 2) decode unit 2040 executes decode stage 2006; 3) rename / allocator unit 2052 executes allocate stage 2008 and rename stage 2010; 4) scheduler unit 2056 executes schedule stage 2012; 5) physical register file unit 2058 and storage unit 2070 execute register read / memory read stage 2014; execution cluster 2060 executes execute stage 2016; 6) memory unit 2070 and physical register file unit 2058 execute write back / memory write stage 2018; 7) various units may be involved in exception handling stage 2022; and 8) rollback unit 2054 and physical register file unit 2058 execute commit stage 2024.

[0243] The core 2090 may support one or more instruction sets including the instructions described herein (e.g., the x86 instruction set (newer versions have added extensions); the MIPS instruction set from MIPS Technologies of Sunnyvale, CA; the ARM instruction set from ARM Holdings of Sunnyvale, CA (with optional additional extensions such as NEON)). In one embodiment, the core 2090 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), thereby enabling operations used by many multimedia applications to be performed using packed data.

[0244] It should be understood that a core may support multithreading (executing two or more operations or sets of threads in parallel) and may do so in a variety of ways, including: time-sliced ​​multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that the physical core is simultaneously multithreading), or a combination thereof (e.g., in e.g., Hyperthreading technology with time-sliced ​​prefetching and decoding and subsequent simultaneous multithreading).

[0245] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiment of the processor also includes separate instruction and data cache units 2034 / 2074 and a shared L2 cache unit 2076, alternative embodiments may have a single internal cache (e.g., a level 1 (L1) internal cache or multiple levels of internal cache) for both instructions and data. In some embodiments, the system may include a combination of internal caches and external caches external to the core and / or processor. Alternatively, all caches may be external to the core and / or processor.

[0246] Certain exemplary in-order core architectures

[0247] Figures 21A-21B A block diagram illustrating a more specific exemplary in-order core architecture, which would be one of several logic blocks in a chip (including other cores of the same and / or different types). Depending on the application, the logic block communicates with some fixed-function logic, memory I / O interfaces, and other necessary I / O logic via a high-bandwidth interconnect network (e.g., a ring network).

[0248] Figure 21A 2 is a block diagram of a single processor core and its connection to the on-die interconnect network 2102 and its local subset of the level 2 (L2) cache 2104 according to an embodiment of the present invention. In one embodiment, the instruction decoder 2100 supports the x86 instruction set with the packed data instruction set extension. The L1 cache 2106 allows low-latency access to cache memory for access to the scalar and vector units. Although in one embodiment (to simplify the design), the scalar unit 2108 and the vector unit 2110 use separate register sets (scalar registers 2112 and vector registers 2114, respectively), and data transferred between them is written to memory and then read back from the level 1 (L1) cache 2106, alternative embodiments of the present invention may use different approaches (e.g., using a single register set, or including a communication path that allows data to be transferred between the two register files without writing and reading back).

[0249] The local subset of L2 cache 2104 is part of the global L2 cache, which is divided into separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset of L2 cache 2104. Data read by a processor core is stored in its L2 cache subset 2104 and can be quickly accessed in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 2104 and is cleared from other subsets when necessary. The ring network ensures consistency with respect to shared data. The ring network is bidirectional to allow agents (e.g., processor cores, L2 caches, and other logic blocks) to communicate with each other within the chip. Each ring data path is 1012 bits wide in each direction.

[0250] Figure 21B According to an embodiment of the present invention Figure 21A A magnified view of a portion of a processor core in FIG. Figure 21B Includes the L1 data cache 2106A portion of the L1 cache 2104 and more details about the vector unit 2110 and vector registers 2114. Specifically, the vector unit 2110 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 2128) that executes one or more of integer instructions, single-precision floating-point instructions, and double-precision floating-point instructions. The VPU supports swizzling of register inputs via the swizzle unit 2120, value conversion via the value conversion units 2122A-B, and copying on memory inputs via the copy unit 2124. Write mask register 2126 allows asserted vector writes.

[0251] Figure 22 is a block diagram of a processor 2200 according to an embodiment of the present invention, which may have more than one core, may have an integrated memory controller, and may have integrated graphics. Figure 22 The solid line box in the figure shows a processor 2200 having a single core 2202A, a system agent 2210, a set of one or more bus controller units 2216, while the optional addition of the dashed line box shows an alternative processor 2200 having multiple cores 2202A-N, a set of one or more integrated memory controller units 2214 in the system agent unit 2210, and dedicated logic 2208.

[0252] Thus, different implementations of processor 2200 may include: 1) a CPU having dedicated logic 2208, which is integrated graphics and / or scientific (throughput) logic (which may include one or more cores); and cores 2202A-N, which are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of both); 2) a coprocessor having cores 2202A-N, which are a large number of dedicated cores primarily intended for graphics and / or scientific (throughput); and 3) a coprocessor having cores 2202A-N, which are a large number of general-purpose in-order cores. Thus, processor 2200 may be a general-purpose processor, a coprocessor, or a dedicated processor (e.g., a network or communications processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput multi-integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 2200 may be part of one or more substrates and / or may be implemented on one or more substrates using any of a variety of process technologies (e.g., BiCMOS, CMOS, or NMOS).

[0253] The memory hierarchy architecture includes one or more levels of cache within the core, a set of one or more shared cache units 2206, and external memory (not shown) coupled to the set of integrated memory controller units 2214. The set of shared cache units 2206 may include one or more intermediate level caches (e.g., level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache), a last level cache (LLC), and / or combinations thereof. While in one embodiment, a ring-based interconnect unit 2212 interconnects the integrated graphics logic 2208, the set of shared cache units 2206, and the system agent unit 2210 / integrated memory controller unit 2214, alternative embodiments may use any number of well-known techniques for interconnecting these units. In one embodiment, coherence is maintained between the one or more cache units 2206 and the cores 2202-AN.

[0254] In some embodiments, one or more of the cores 2202A-N may be multithreaded. The system agent unit 2210 includes components that coordinate and operate the cores 2202A-N. The system agent unit 2210 may include, for example, a power control unit (PCU) and a display unit. The PCU may be or include the logic and components required to regulate the power state of the cores 2202A-N and the integrated graphics logic 2208. The display unit is used to drive one or more externally connected displays.

[0255] The cores 2202A-N may be homogeneous or heterogeneous with respect to the architectural instruction set; that is, two or more of the cores 2202A-N may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of the instruction set or a different instruction set.

[0256] Exemplary Computer Architecture

[0257] Figure 23-24 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptop computers, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network appliances, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, various systems or electronic devices that can incorporate the processors and / or other execution logic disclosed herein are generally suitable.

[0258] Now refer to Figure 23 , shows a block diagram of a system 2300 according to one embodiment of the present invention. System 2300 may include one or more processors 2310, 2315 coupled to a controller hub 2320. In one embodiment, controller hub 2320 includes a graphics memory controller hub (GMCH) 2390 and an input / output hub (IOH) 2350 (which may be on separate chips); GMCH 2390 includes a memory controller and a graphics controller, to which memory 2340 and coprocessor 2345 are coupled; and IOH 2350 couples input / output (I / O) devices 2360 to GMCH 2390. Alternatively, one or both of the memory controller and graphics controller are integrated within the processor (as described herein), memory 2340 and coprocessor 2345 are directly coupled to processor 2310, and controller hub 2320 and IOH 2350 are on a single chip.

[0259] exist Figure 23 The optional nature of the additional processor 2315 is indicated by dashed lines in FIG. 22. Each processor 2310, 2315 may include one or more processing cores described herein and may be some version of the processor 2200.

[0260] The memory 2340 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 2320 communicates with the processors 2310, 2315 via a multi-drop bus (e.g., front-side bus (FSB)), a point-to-point interface (e.g., QuickPath Interconnect (QPI)), or similar connection 2395.

[0261] In one embodiment, the coprocessor 2345 is a special purpose processor (eg, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc.) In one embodiment, the controller hub 2320 may include an integrated graphics accelerator.

[0262] There may be a variety of differences between the physical resources 2310, 2315 in terms of a range of quality metrics including architectural characteristics, microarchitectural characteristics, thermal characteristics, power consumption characteristics, etc.

[0263] In one embodiment, the processor 2310 executes instructions that control general-purpose data processing operations. Embedded within the instructions may be coprocessor instructions. The processor 2310 recognizes these coprocessor instructions as types that should be executed by the attached coprocessor 2345. Accordingly, the processor 2310 transmits these coprocessor instructions (or control signals representing coprocessor instructions) to the coprocessor 2345 over a coprocessor bus or other interconnect. The coprocessor 2345 accepts and executes the received coprocessor instructions.

[0264] Now refer to Figure 24 , showing a block diagram of a SoC 2400 according to an embodiment of the present invention. Figure 24 Similar elements in the FIGURE 1 use similar reference numerals. In addition, the dashed boxes are optional features on more advanced SoCs. Figure 24 In the embodiment, the interconnect unit 2402 is coupled to: an application processor 2410, which includes a set of one or more cores 202A-N and a shared cache unit 2206; a system agent unit 2210; a bus controller unit 2216; an integrated memory controller unit 2214; a set of one or more coprocessors 2420, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 2430; a direct memory access (DMA) unit 2432; and a display unit 2440 for coupling to one or more external displays. In one embodiment, the coprocessors 2420 include special-purpose processors (e.g., a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, an embedded processor, etc.).

[0265] The embodiments of the mechanisms disclosed herein may be implemented by hardware, software, firmware, or a combination of these implementation methods. The embodiments of the present invention may be implemented as a computer program or program code executed on a programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0266] Program code can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor (e.g., a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor).

[0267] The program code can be implemented in a high-level procedural or object-oriented programming language to communicate with the processing system. If desired, the program code can also be implemented in assembly or machine language. In fact, the mechanism described herein is not limited to any particular programming language in terms of scope. In any case, the language can be a compiled language or an interpreted language.

[0268] One or more aspects of at least one embodiment may be implemented through representative instructions stored on a machine-readable medium that represent the various logic within a processor, which, when read by a machine, causes the machine to fabricate the logic to perform the techniques described herein. These representations, known as "IP cores," may be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.

[0269] These machine-readable storage media may include, but are not limited to, non-transitory tangible arrangements of articles manufactured or formed by a machine or device, including: storage media such as a hard disk, any other type of disk (including floppy disks, optical disks, compact disk read-only memory (CD-ROM), compact disk rewritable (CD-RW), and magneto-optical disks); semiconductor devices (e.g., read-only memory (ROM), random access memory (RAM) (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM), magnetic cards or optical cards); or any other type of medium suitable for storing electronic instructions.

[0270] Therefore, embodiments of the present invention also include non-transitory, tangible, machine-readable media containing instructions or design data (e.g., hardware description language (HDL)) that define the structures, circuits, devices, processors, and / or system features described herein. These embodiments may also be referred to as program products.

[0271] Simulation (including binary translation, code deformation, etc.)

[0272] In some cases, an instruction converter can be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter can translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), deform, emulate, or convert instructions to one or more other instructions to be processed by the core. The instruction converter can be implemented in software, hardware, firmware, or a combination thereof. The instruction converter can be on the processor, off the processor, or partially on the processor and partially off the processor.

[0273] Figure 25 1 is a block diagram illustrating the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set according to an embodiment of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter, but alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 25 It is shown that a program written in a high-level language 2502 can be compiled using an x86 compiler 2504 to generate x86 binary code 2506 that can be natively executed by a processor having at least one x86 instruction set core 2516. A processor having at least one x86 instruction set core 2516 represents any processor that is capable of performing substantially the same functions as an Intel processor having at least one x86 instruction set core by compatibly executing or processing (1) a large portion of the instruction set of an Intel x86 instruction set core; or (2) an object code version of an application or other software targeted to run on an Intel processor having at least one x86 instruction set core, so as to achieve substantially the same results as an Intel processor having at least one x86 instruction set core. The x86 compiler 2504 represents a compiler that is operable to generate x86 binary code 2506 (e.g., object code) that can be executed on a processor having at least one x86 instruction set core 2516 with or without additional link processing. Similarly, Figure 25The diagram shows that a program written in a high-level language 2502 can be compiled using an alternative instruction set compiler 2508 to generate alternative instruction set binary code 2510 that can be natively executed by a processor that does not have at least one x86 instruction set core 2514 (e.g., a processor having a core that executes the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and / or the ARM instruction set of ARM Holdings of Sunnyvale, CA). An instruction converter 2512 is used to convert the x86 binary code 2506 into code that can be natively executed by a processor that does not have an x86 instruction set core 2514. This converted code is unlikely to be identical to the alternative instruction set binary code 2510 because an instruction converter capable of performing this operation is difficult to manufacture; however, the converted code will perform common operations and be composed of instructions from the alternative instruction set. Thus, the instruction converter 2512 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code 2506 through simulation, emulation, or any other process.

[0274] Utilization metrics for processing engines

[0275] Now refer to Figure 26 , shows a block diagram of a system 2600 according to one or more embodiments. In some embodiments, system 2600 can be all or part of an electronic device or component. For example, system 2600 can be a cellular phone, a computer, a server, a network device, a system on a chip (SoC), a controller, a wireless transceiver, a power supply unit, etc. In addition, in some embodiments, system 2600 can be part of a group of related or interconnected devices (e.g., a data center, a computing cluster, etc.).

[0276] like Figure 26 As shown, system 2600 may include a processor 2610 operatively coupled to system memory 2605 and a power supply 2650. Figure 26 26. Although not shown, system 2600 may include other components. In one or more embodiments, system memory 2605 may be implemented by any type of computer memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile memory (NVM), a combination of DRAM and NVM, etc.). Power supply 2650 may provide power to processor 2610.

[0277] In one or more embodiments, processor 2610 may be a hardware processing device (e.g., a central processing unit (CPU), a system on a chip (SoC), etc.). As shown, processor 2610 may include any number of processing engines 2620A-2620N (also generally referred to as processing engines 2620) and a power control unit 2630. Each processing engine 2620 may execute one or more execution threads 2640A-2640N (also generally referred to as execution threads 2640).

[0278] In one or more embodiments, power control unit 2630 may be a hardware unit of processor 2610 to control the power state of processing engine 2620. For example, power control unit 2630 may control operating frequency, voltage level, and the like.

[0279] As shown, power control unit 2630 may include and / or maintain processing engine (PE) data 2632. In some embodiments, PE data 2632 may include power state information (e.g., operating frequency) and / or utilization metrics (e.g., percentage or number of active clock cycles, percentage or number of active time units, whether a particular component was used during a time period, whether a particular pattern of memory access was used, etc.) for each processing engine 2620. Power control unit 2630 may perform periodic collection and / or calculations to update PE data 2632 for each processing engine 2620.

[0280] In some embodiments, the power control unit 2630 may include transfer logic 2634 for managing the power state of the processing engine 2620 with thread transfer. For example, the transfer logic 2634 may use the PE data 2632 of the first processing engine 2620 to generate or update the PE data 2632 of the second processing engine 2620. Figures 27A-30 Describe various aspects of transfer logic 2634.

[0281] In some embodiments, the power control unit 2630 can calculate a utilization metric of the second processing engine based on the second processing engine's instructions to one or more first instructions in combination with the utilization metric of the first processing engine, wherein the utilization metric of the first processing engine is based on the first processing engine's instructions to one or more second instructions, and wherein the one or more first instructions and the one or more second instructions correspond to one or more threads of a single application.

[0282] Reference Figures 27A-27B , shows an illustration of an example thread transfer operation according to one or more embodiments. Specifically, Figures 27A-27B Two time periods during data transfer between producer-consumer execution threads on two processing engines are shown respectively. Note that Figures 27A-27BThe components shown may generally correspond to those described above with reference to Figure 26 Similar components described.

[0283] Now refer to Figure 27A , assume that during a first time period, first PE 2710 executes first thread 2715, and second PE 2720 executes second thread 2725. Further assume that first thread 2715 is a producer thread that is active while generating data for second thread 2725, and therefore second thread 2725 may be inactive while waiting to receive data generated by first thread 2715. Therefore, PCU 2730 may access information 2702 from first PE 2710 to update first PE data 2740. In some embodiments, first PE data 2740 may include utilization metrics, power state information, and the like. However, because second thread 2725 is currently inactive, PCU 2730 may not have any utilization data for second PE 2720 (or may have utilization data with a value of zero).

[0284] Now refer to Figure 27B , assuming that at a later time period, the first thread 2715 has completed its execution and thus becomes inactive after passing the generated data 2704 to the second thread 2725. Additionally, the second thread 2725 may become active to process the received data 2704. In some embodiments, the PCU 2730 may use the first PE data 2740 (associated with the first PE 2710) to generate the second PE data 2745 (associated with the second PE 2720). For example, the PCU 2730 may create the second PE data 2745 as a copy of the first PE data 2740.

[0285] In some examples, the second PE 2720 may already be active (e.g., executing a third thread) prior to receiving the data 2704. In these examples, during the first time period, the PCU 2730 may already include the second PE data 2745 having a utilization value greater than zero. Therefore, the PCU 2730 may sum the utilization value from the first PE data 2740 (reflecting the utilization associated with executing the first thread 2715) with the existing utilization value in the second PE data 2745. Further, if the sum exceeds a maximum utilization value (e.g., 100 percent utilization), the sum may be limited to the maximum utilization value.

[0286] In some embodiments, after generating the second PE data 2745, the PCU 2730 can use the second PE data 2745 to manage the power state of the second PE 2720. For example, the PCU 2730 can set the operating frequency of the second PE 2720 based on the second PE data 2745 (e.g., utilization metrics and frequency data). Thus, the operating frequency of the second PE 2720 can be set to reflect the processing load of the first PE 2710 when generating the data 2704, rather than zero or low processing load of the second PE 2720 while waiting for the data 2704. In this way, the performance loss associated with data transfer between producer threads and consumer threads can be reduced.

[0287] Now refer to Figures 28A-28B , shows a diagram of an example thread transfer operation according to one or more embodiments. Specifically, Figures 28A-28B Two time periods during thread migration between two processing engines are shown respectively. Note that Figures 28A-28B The components shown may generally correspond to those described above with reference to Figure 26 and Figures 27A-27B Similar components described.

[0288] Reference Figure 28A , assuming that in a first time period, the first PE 2810 executes the first thread 2815 and the second PE 2820 is in an inactive power state. Therefore, the PCU 2830 can access the information 2802 from the first PE 2810 to update the first PE data 2840.

[0289] Now refer to Figure 28B At a later time period, the first thread 2815 migrates (2804) to the second PE 2820. In some embodiments, the PCU 2830 may copy (2806) the first PE data 2840 to generate the second PE data 2845. Furthermore, after generating the second PE data 2845, the PCU 2830 may use the second PE data 2845 to manage the power state of the second PE 2820. Thus, the power state of the second PE 2820 may be immediately set to reflect the processing load of the first PE 2810 when executing the first thread 2815. Thus, the performance loss associated with thread migration may be reduced.

[0290] Now refer to Figure 29A-29B , shows a diagram of an example thread-level register 2910 according to one or more embodiments. Specifically, Figure 29A Thread-level registers 2910 are shown, including a branch source field 2902 , a branch type field 2904 , and any number of other fields 2906 .

[0291] In one or more embodiments, any number of thread-level registers 2910 may be included in a processor (e.g., Figure 26 processor 2610) or a PE (e.g., Figure 26 2640A). In some embodiments, thread-level registers 2910 may be associated with or assigned to the destination thread of a thread transfer (i.e., the consumer thread that receives the data or thread that is migrated to the new PE). For example, each PE may include a thread-level register 2910 for each destination thread of the PE. In other embodiments, each thread may be associated with a corresponding thread-level register 2910 even if the thread is not associated with the thread transfer. For example, processor 2610 may include a thread-level register 2910 for each thread executed by processor 2610.

[0292] In some embodiments, transfer source field 2902 may identify the source of a thread transfer associated with a destination thread. For example, transfer source field 2902 may identify the source thread of the thread transfer (i.e., the producer thread that generates the data or threads to be transferred). In another example, transfer source field 2902 may identify the PE of the source thread that performs the thread transfer. In yet another example, if the thread associated with thread-level register 2910 is not part of the thread transfer, transfer source field 2902 may be empty or may store a zero value.

[0293] In one or more embodiments, transfer type field 2904 may identify the type of thread transfer associated with the destination thread. For example, transfer type field 2904 may include a value indicating whether the thread transfer involves a producer-consumer data transfer, thread migration, or other dependencies between threads. Additionally, if the thread associated with thread-level register 2910 is not part of the thread transfer, transfer type field 2904 may be empty or may store a zero value.

[0294] like Figure 29A As shown, in the first time period, the operating system 2905 may fill in the values ​​of the transfer source field 2902 and the transfer type field 2904. For example, the operating system 2905 may store the identifier of the source PE of the thread transfer in the transfer source field 2902.

[0295] Now refer to Figure 29BDuring the second time period, PCU 2920 may read the values ​​of transfer source field 2902 and transfer type field 2904. Using these values, PCU 2920 may determine whether the thread associated with thread-level register 2910 will be the destination thread of the thread transfer, and if so, determine the type of thread transfer. In some embodiments, PCU 2920 may generate utilization metrics data for the PE executing the destination thread. Furthermore, when the thread transfer is complete, PCU 2920 may use the generated utilization metrics data to control the power state of the PE executing the destination thread.

[0296] In some embodiments, in response to determining that the thread transfer is complete, the transfer source field 2902 and the transfer type field 2904 may be cleared or reset. For example, in some embodiments, the operating system 2905 may set the transfer source field 2902 to zero, blank, or other value indicating that the thread associated with the thread-level register 2910 is not the destination thread of the thread transfer.

[0297] Now refer to Figure 30 , shows a flow chart of method 3000 according to one or more embodiments. In various embodiments, method 3000 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions running on a processing device), or a combination thereof. In some implementations, the method 3000 may be performed using Figure 26-29B One or more components shown (e.g., transfer logic 2634, PCU 2730, etc.) perform method 3000. In a firmware or software embodiment, method 3000 may be implemented by computer-executed instructions stored in a non-transitory machine-readable medium (e.g., an optical storage device, a semiconductor storage device, or a magnetic storage device). The machine-readable medium may store data that, if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform the method. For purposes of illustration, reference may be made below to an example embodiment according to one or more embodiments. Figure 26-29B The actions involved in method 3000 are described. However, the scope of the various embodiments discussed herein is not limited in this regard.

[0298] Block 3010 may include monitoring, by a power control unit of a processor, a first utilization metric of a first processing engine of the processor. Figure 27A, the PCU 2730 may generate and / or update the first PE data 2740 to include utilization data about the first PE 2710. In some embodiments, the utilization data may reflect the level of usage or activity of the first PE 2710 (e.g., the percentage of active clock cycles, the percentage or number of active time units, whether a particular component was used during a time period, whether a particular pattern of memory ranges or addresses was accessed, etc.).

[0299] Block 3020 may include detecting, by the power control unit, a thread transfer from the first processing engine to the second processing engine. Figure 29B , the PCU 2920 can access the transfer source field 2902 of the thread-level register 2910 and can therefore determine that the thread associated with the thread-level register 2910 is the destination thread of the thread transfer. In addition, in some embodiments, the PCU 2920 can access the transfer type field 2904 to determine the type of thread transfer (e.g., producer-consumer data transfer, thread migration, etc.).

[0300] Block 3030 may include generating, by the power control unit, a second utilization metric for the second processing engine using the first utilization metric for the first processing engine. Figure 27B , PCU 2730 may use first PE data 2740 (associated with first PE 2710 ) to generate second PE data 2745 (associated with second PE 2720 ). In some examples, PCU 2730 may copy first PE data 2740 to generate second PE data 2745 .

[0301] Block 3040 may include controlling, by the power control unit, the power state of the second processing engine using the generated second utilization metric. Figure 27B , PCU 2730 can use second PE data 2745 to manage the power state of second PE 2720. In some examples, PCU 2730 can set the operating frequency of second PE 2720 based on second PE data 2745 (e.g., utilization and frequency data). After block 3040, method 3000 is complete.

[0302] The following clauses and / or examples pertain to further embodiments.

[0303] In Example 1, a processor for generating a utilization metric includes: a plurality of processing engines; and a power control unit. The power control unit is configured to: monitor a first utilization metric of a first processing engine; detect a thread transfer from the first processing engine to a second processing engine; and generate a second utilization metric of the second processing engine using the first utilization metric of the first processing engine.

[0304] In Example 2, the subject matter of Example 1 can optionally include the power control unit being configured to control a power state of the second processing engine using the generated second utilization metric.

[0305] In Example 3, the subject matter of Examples 1-2 can optionally include that the detected thread transfer includes a handover of data from a first thread executing on the first processing engine to a second thread executing on the second processing engine.

[0306] In Example 4, the subject matter of Examples 1-3 may optionally include a first thread-specific register associated with the second thread, the first thread-specific register being used to store an identifier of the first thread.

[0307] In Example 5, the subject matter of Examples 1-4 can optionally include that the detected thread transfer comprises a migration of a first thread from the first processing engine to the second processing engine.

[0308] In Example 6, the subject matter of Examples 1-5 can optionally include the second utilization metric being a copy of the first utilization metric.

[0309] In Example 7, the subject matter of Examples 1-6 can optionally include the power control unit being configured to generate the second utilization metric using a combination of a past utilization metric of the second processing engine and the first utilization metric.

[0310] In Example 8, the subject matter of Examples 1-7 may optionally include a plurality of thread-specific registers, each thread-specific register including a transfer source field and a transfer type field.

[0311] In Example 9, a method for generating a utilization metric includes: monitoring, by a power control unit of a processor, a first utilization metric of a first processing engine of the processor; detecting, by the power control unit, a thread transfer from the first processing engine to a second processing engine; and generating, by the power control unit, a second utilization metric of the second processing engine using the first utilization metric of the first processing engine.

[0312] In Example 10, the subject matter of Example 9 can optionally include controlling a power state of the second processing engine using the generated second utilization metric.

[0313] In Example 11, the subject matter of Examples 9-10 can optionally include that the detected thread transfer comprises one of a data handover between threads and a migration of a single thread.

[0314] In Example 12, the subject matter of Examples 9-11 can optionally include generating the second utilization metric as a copy of the first utilization metric.

[0315] In Example 13, the subject matter of Examples 9-12 can optionally include generating the second utilization metric using a combination of past utilization metrics of the second processing engine and the first utilization metric.

[0316] In Example 14, the subject matter of Examples 9-13 may optionally include detecting a thread transfer comprising reading, by the power control unit, a transfer source field of a thread-level register associated with a destination thread of the thread transfer.

[0317] In Example 15, the subject matter of Examples 9-14 can optionally include populating the transfer source field by an operating system before reading the transfer source field.

[0318] In Example 16, a computing device for generating utilization metrics includes: one or more processors; and a memory having a plurality of instructions stored therein, which, when executed by the one or more processors, cause the computing device to perform the method of any one of Examples 9-15.

[0319] In Example 17, at least one machine-readable medium may have data stored thereon that, if used by at least one machine, causes the at least one machine to perform the method of any of Examples 9-15.

[0320] In Example 18, an electronic device for generating utilization metrics includes: a module for performing the method of any of Examples 9-15.

[0321] In Example 19, a system for generating a utilization metric includes: a processor; and a system memory coupled to the processor, wherein the processor includes a first processing engine, a second processing engine, and a power control unit, the power control unit configured to calculate a utilization metric of the second processing engine based on execution of one or more first instructions by the second processing engine in combination with a utilization metric of the first processing engine, wherein the utilization metric of the first processing engine is based on execution of one or more second instructions by the first processing engine, the one or more first instructions and the one or more second instructions corresponding to one or more threads of a single application.

[0322] In Example 20, the subject matter of Example 19 may optionally include the one or more first instructions corresponding to a producer thread, and the one or more second instructions corresponding to a consumer thread, wherein the producer thread provides data to the consumer thread.

[0323] In Example 21, the subject matter of Examples 19-20 may optionally include the one or more first instructions and the one or more second instructions corresponding to a single thread that is migrated from the first processing engine to the second first processing engine.

[0324] In Example 22, the subject matter of Examples 19-21 can optionally include the power control unit being operable to control a power state of the second processing engine using a utilization metric of the second processing engine.

[0325] In Example 23, the subject matter of Examples 19-22 may optionally include a plurality of thread-specific registers, each thread-specific register including a transfer source field and a transfer type field.

[0326] In Example 24, an apparatus for generating a utilization metric includes: a module for monitoring a first utilization metric of a first processing engine of a processor; a module for detecting a thread transfer from the first processing engine to a second processing engine; and a module for generating a second utilization metric of the second processing engine using the first utilization metric of the first processing engine.

[0327] In Example 25, the subject matter of Example 24 can optionally include means for controlling a power state of the second processing engine using the generated second utilization metric.

[0328] In Example 26, the subject matter of Examples 24-25 can optionally include the detected thread transfer comprising one of a data handover between threads and a migration of a single thread.

[0329] In Example 27, the subject matter of Examples 24-26 can optionally include means for generating the second utilization metric as a copy of the first utilization metric.

[0330] In Example 28, the subject matter of Examples 24-27 can optionally include means for generating the second utilization metric using a combination of the past utilization metric of the second processing engine and the first utilization metric.

[0331] In Example 29, the subject matter of Examples 24-28 may optionally include the means for detecting a thread transfer comprising means for reading a transfer source field of a thread-level register associated with a destination thread of the thread transfer.

[0332] In Example 30, the subject matter of Examples 24-29 can optionally include means for populating the transfer source field by an operating system before reading the transfer source field.

[0333] According to some embodiments, examples of using utilization metrics for power management in a processor are provided. Figures 26-30 As discussed, some embodiments may include a power control unit configured to maintain a utilization metric for a first processing engine of a processor. The power control unit may detect a thread transfer from the first processing engine to a second processing engine and may use the utilization metric for the first processing engine to generate a utilization metric for the second processing engine. The power control unit may use the generated utilization metric to control a power state of the second processing engine. Thus, in some embodiments, the second processing engine may operate in a power state that more accurately reflects the activity associated with the thread transfer, and the execution performance of the thread transfer may be improved as a result.

[0334] Note that although Figures 26-30 Various example implementations are shown, but other variations are possible. For example, it is contemplated that Figure 1-Figure 25 One or more embodiments are implemented in the described example devices and systems.

[0335] Notice, Figure 1-Figure 30 The examples shown are provided for illustrative purposes and are not intended to limit any embodiment. Specifically, although embodiments may be shown in simplified form for clarity, embodiments may include any number and / or arrangement of processors, cores, and / or additional components (e.g., buses, storage media, connectors, power components, buffers, interfaces, etc.). For example, it is contemplated that some embodiments may include any number of components in addition to those shown, and that different arrangements of the components shown may be present in certain implementations. Furthermore, it is contemplated that Figure 1-Figure 30 Details in the examples shown may be used anywhere in one or more embodiments.

[0336] It should be understood that various combinations of the above examples are possible. Embodiments may be used in many different types of systems. For example, in one embodiment, a communication device may be configured to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to communication devices, but other embodiments may involve other types of apparatuses for processing instructions, or one or more machine-readable media containing instructions, which, in response to being executed on a computing device, cause the device to perform one or more methods and techniques described herein.

[0337] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrases "one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. Furthermore, particular features, structures, or characteristics may be implemented in other suitable forms besides the specific embodiment shown, and all such forms may be encompassed by the claims of this application.

[0338] While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of the present invention.

Claims

1. A processor for generating a utilization metric, comprising: Multiple processing engines; and Power control unit for: monitoring a first utilization metric of a first processing engine; detecting a thread transfer from the first processing engine to a second processing engine; as well as In response to detecting a thread transfer from the first processing engine to the second processing engine, a second utilization metric for managing only the second processing engine is generated using the first utilization metric of at least the first processing engine.

2. The processor according to claim 1, wherein the power control unit is configured to: The generated second utilization metric is used to control a power state of the second processing engine.

3. The processor of claim 1, wherein: The detected thread transfer includes a handover of data from a first thread executing on the first processing engine to a second thread executing on the second processing engine.

4. The processor of claim 3, further comprising: A first thread-specific register is associated with the second thread, the first thread-specific register being configured to store an identifier of the first thread.

5. The processor of claim 1, wherein: The detected thread transfer includes a migration of a first thread from the first processing engine to the second processing engine.

6. The processor of claim 1, wherein: The second utilization metric is a copy of the first utilization metric.

7. The processor according to claim 1, wherein the power control unit is configured to: The second utilization metric is generated using a combination of the past utilization metric of the second processing engine and the first utilization metric.

8. The processor of claim 1 , further comprising: A plurality of thread-specific registers, each thread-specific register including a branch source field and a branch type field.

9. A method for generating a utilization metric, comprising: monitoring, by a power control unit of a processor, a first utilization metric for a first processing engine of the processor; detecting, by the power control unit, a thread transfer from the first processing engine to a second processing engine; as well as In response to detecting a thread transfer from the first processing engine to the second processing engine, the power control unit uses the first utilization metric of at least the first processing engine to generate a second utilization metric for managing only the second processing engine.

10. The method of claim 9, further comprising: The generated second utilization metric is used to control a power state of the second processing engine.

11. The method of claim 9, wherein: The detected thread transfer includes one of data handover between threads and migration of a single thread.

12. The method of claim 9, further comprising: The second utilization metric is generated as a copy of the first utilization metric.

13. The method of claim 9, further comprising: The second utilization metric is generated using a combination of the past utilization metric of the second processing engine and the first utilization metric.

14. The method of claim 9, wherein: Detecting thread transfers includes: A transfer source field of a thread-level register associated with a destination thread of a thread transfer is read by the power control unit.

15. The method of claim 14, further comprising: Before reading the transfer source field: The transfer source field is populated by the operating system.

16. A computing device for generating a utilization metric, comprising: one or more processors; and A memory having a plurality of instructions stored therein, which, when executed by the one or more processors, cause the computing device to perform the method of any one of claims 9 to 15.

17. At least one machine-readable medium having stored thereon data which, if used by at least one machine, causes the at least one machine to perform the method of any one of claims 9 to 15.

18. An electronic device for generating utilization metrics, comprising means for performing the method of any one of claims 9-15.

19. A system for generating a utilization metric, comprising: a processor comprising a first processing engine, a second processing engine, and a power control unit, the power control unit configured to: calculate a utilization metric of the second processing engine based on execution of one or more first instructions by the second processing engine in combination with a utilization metric of the first processing engine, wherein the utilization metric of the first processing engine is based on execution of one or more second instructions by the first processing engine, the one or more first instructions and the one or more second instructions corresponding to one or more threads of a single application, the power control unit using the utilization metric of the second processing engine to control only the second processing engine; and A system memory is coupled to the processor.

20. The system of claim 19, wherein: The one or more first instructions correspond to a producer thread and the one or more second instructions correspond to a consumer thread, wherein the producer thread provides data to the consumer thread.

21. The system of claim 19, wherein: The one or more first instructions and the one or more second instructions correspond to a single thread that is migrated from the first processing engine to the second processing engine.

22. The system of claim 19, wherein the power control unit is configured to: The utilization metric of the second processing engine is used to control a power state of the second processing engine.

23. The system of claim 19, further comprising: A plurality of thread-specific registers, each thread-specific register including a branch source field and a branch type field.

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