Organic light emitting display device

Abstract

An organic light-emitting display device is provided. The organic light-emitting display device includes a substrate, a first semiconductor element, a second semiconductor element, a protective electrode, and a light-emitting structure. The protective electrode is disposed between a second active layer and a second source electrode and between the active layer and a second drain electrode, and has an opening that exposes a portion of the second active layer. The light-emitting structure is disposed on the first semiconductor element and the second semiconductor element.

Description

Technical Field

[0001] Example embodiments generally relate to an organic light emitting display device and a method of manufacturing an organic light emitting display device. More specifically, embodiments of the inventive concept relate to an organic light emitting display device including a silicon-based semiconductor element and a metal oxide-based semiconductor element and a method of manufacturing an organic light emitting display device including a silicon-based semiconductor element and a metal oxide-based semiconductor element. Background Art

[0002] Flat panel display ("FPD") devices are widely used as display devices of electronic devices because they are lightweight and thin compared to cathode ray tube ("CRT") display devices. Typical examples of FPD devices are liquid crystal display ("LCD") devices and organic light emitting display ("OLED") devices.

[0003] Recently, it has become possible to develop an OLED device that includes a silicon-based semiconductor element and a metal oxide-based semiconductor element simultaneously (or in parallel). In the process for forming the silicon-based semiconductor element and the metal oxide-based semiconductor element, a heat treatment process may be performed after forming the contact hole of the silicon-based semiconductor element. When the heat treatment process is performed, a portion of the silicon semiconductor layer included in the silicon-based semiconductor element may be exposed to the outside through the contact hole. The exposed surface of the silicon semiconductor layer may react with the oxygen ions present in the chamber so that an oxide may be formed on the exposed surface. In order to remove the oxide, a buffered oxide etchant ("BOE") process may be performed. When the BOE process is performed, the metal oxide-based semiconductor layer included in the metal oxide-based semiconductor element may be damaged by the etchant used in the BOE process. Therefore, defects of the metal oxide-based semiconductor element may occur. Summary of the invention

[0004] Some example embodiments provide an organic light emitting display (OLED) device including a silicon-based semiconductor element and a metal oxide-based semiconductor element.

[0005] Some example embodiments provide a method of manufacturing an OLED device including a silicon-based semiconductor element and a metal oxide-based semiconductor element.

[0006] According to some example embodiments, an OLED device includes a substrate, a first semiconductor element, a second semiconductor element, a protective electrode, and a light emitting structure. The substrate has a first region and a second region adjacent to the first region. The first semiconductor element includes a first active layer disposed on the substrate and in the first region, a first gate electrode disposed on the first active layer, and a first source electrode and a first drain electrode disposed on the first gate electrode. The second semiconductor element includes a second gate electrode disposed on the substrate and in the second region, a second active layer disposed on the second gate electrode, and a second source electrode and a second drain electrode disposed on the second active layer. The protective electrode is disposed between the second active layer and the second source electrode and the second active layer and the second drain electrode, and has an opening exposing a portion of the second active layer, and the light emitting structure is disposed on the first semiconductor element and the second semiconductor element.

[0007] In example embodiments, the second active layer may be positioned to overlap the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode.

[0008] In example embodiments, the second active layer may be disposed under the protection electrode to overlap a portion of the protection electrode.

[0009] In example embodiments, the protection electrode may contact lower surfaces of the first source electrode and the second drain electrode and be disposed in a space disposed between the first source electrode and the second drain electrode. The protection electrode may electrically connect the first source electrode and the second drain electrode.

[0010] In example embodiments, the second active layer may not be disposed in a space disposed between the first source electrode and the first drain electrode but may be disposed in a space disposed between the first source electrode and the second drain electrode and in a space disposed between the second source electrode and the second drain electrode.

[0011] In example embodiments, the protection electrode may not be disposed in both a space disposed between the first source electrode and the first drain electrode and a space disposed between the second source electrode and the second drain electrode, and the space disposed between the second source electrode and the second drain electrode corresponds to the opening of the protection electrode.

[0012] In example embodiments, the first semiconductor element may have a top gate structure and may include a silicon-based semiconductor. The second semiconductor element may have a bottom gate structure and may include a metal oxide-based semiconductor.

[0013] In example embodiments, the first active layer of the first semiconductor element may include amorphous silicon or polycrystalline silicon.

[0014] In example embodiments, the OLED device may further include a gate electrode pattern disposed on the first gate electrode, and the gate electrode pattern and the second gate electrode may be located on the same layer.

[0015] In an example embodiment, the OLED device may further include a gate insulating layer covering the first active layer in the first region on the substrate, a first insulating interlayer covering the first gate electrode in the first region on the gate insulating layer, a second insulating interlayer covering the second gate electrode in the second region on the first insulating interlayer, and a protective insulating layer covering the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode on the second insulating interlayer. The protective insulating layer may have an opening exposing a portion of the first drain electrode.

[0016] In example embodiments, the protection insulating layer may contact an upper surface of the second active layer and a sidewall of the protection electrode in a space disposed between the second source electrode and the second drain electrode.

[0017] In example embodiments, the protection insulating layer may contact an upper surface of the second insulating interlayer, a sidewall of the second active layer, and a sidewall of the protection electrode in a space disposed between the first source electrode and the first drain electrode.

[0018] In example embodiments, the second insulating interlayer may contact a lower surface of the second active layer, and the second insulating interlayer and the protective insulating layer may include silicon oxide.

[0019] In example embodiments, the light emitting structure may include a lower electrode disposed on the first semiconductor element and the second semiconductor element, a light emitting layer disposed on the lower electrode, and an upper electrode disposed on the light emitting layer.

[0020] In an example embodiment, the OLED device may further include a planarization layer disposed between the protective insulating layer and the lower electrode. The planarization layer may include an organic material, and the planarization layer may have a contact hole exposing the upper surface of the first drain electrode exposed through the opening of the protective insulating layer. The lower electrode may be connected to the first drain electrode through the contact hole of the planarization layer.

[0021] According to some example embodiments, a method for manufacturing an OLED device is provided as follows. A substrate having a first region and a second region adjacent to the first region is provided. A first active layer having a source region and a drain region, a first gate electrode, and a gate insulating layer disposed between the first active layer and the first gate electrode are formed on the substrate and in the first region. A gate electrode pattern is formed on the substrate and in the first region, and a second gate electrode is formed on the substrate and in the second region. An insulating interlayer is formed on the second gate electrode and the gate electrode pattern. An initial second active layer is formed on the insulating interlayer. An initial protective electrode layer is formed on the initial second active layer. A first contact hole and a second contact hole are formed to expose each of the source region and the drain region of the first active layer by removing the initial protective electrode layer, the initial second active layer, and the first and second portions of the insulating interlayer. An initial electrode layer is formed on the initial protective electrode layer. A first source electrode and a first drain electrode in the first region, a second active layer, a protective electrode, and a second source electrode and a second drain electrode in the second region are formed on the insulating interlayer by selectively etching the initial electrode layer, the initial protective electrode layer, and the initial second active layer.

[0022] In example embodiments, when the preliminary second active layer, the preliminary protecting electrode layer, and the preliminary electrode layer are selectively etched, a portion of the preliminary protecting electrode layer may be removed in the second region, and an upper surface of the preliminary second active layer may be exposed.

[0023] In example embodiments, the method may further include performing a heat treatment process on the initial second active layer, the first contact hole and the second contact hole, and the first active layer after forming the first contact hole and the second contact hole, and after the heat treatment process, performing a buffered oxide etchant ("BOE") process to remove the oxide layer of the first contact hole and the second contact hole.

[0024] In example embodiments, when the BOE process is performed, the preliminary second active layer may be protected by the preliminary protective electrode layer.

[0025] In example embodiments, the method may further include forming a protective insulating layer covering the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode on the insulating interlayer, and the protective insulating layer may be in direct contact with an upper surface of the second active layer and side walls of the protective electrode in the second region.

[0026] According to the example embodiment, the OLED device includes the protection electrode, and the OLED device can protect the second active layer from the etchant used in the BOE process. Therefore, the OLED device can prevent defects of the second semiconductor element.

[0027] In addition, because the SiO xThe second insulating interlayer and the protective insulating layer are in direct contact with the second active layer, so the interface characteristics of the second active layer can be relatively improved. Therefore, the OLED device according to the example embodiment can include a second semiconductor element with increased reliability.

[0028] In the method of manufacturing an OLED device according to an example embodiment, when the heat treatment process is performed on the first active layer and the initial second active layer, the driving range of the first semiconductor element corresponding to the driving transistor can be relatively widened, and since the distribution of the threshold voltage of the second semiconductor element corresponding to the switching transistor is reduced, a relatively accurate second semiconductor element can be obtained. In addition, since the heat treatment process is performed on the first active layer and the initial second active layer at the same time, the manufacturing cost of the OLED device can be relatively reduced.

[0029] In addition, since the initial protective electrode layer completely covers the initial second active layer, the initial protective electrode layer can protect the initial second active layer from the etchant used in the BOE process. Therefore, after forming the initial second active layer, the BOE process can be performed without damaging the initial second active layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Example embodiments may be understood in more detail through the following description in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a cross-sectional view showing an organic light emitting display (OLED) device according to an example embodiment;

[0032] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 is a cross-sectional view illustrating a method of manufacturing an OLED device according to an example embodiment;

[0033] Fig.11 is a cross-sectional view showing an OLED device according to an example embodiment; and

[0034] Fig.12 is a cross-sectional view showing an OLED device according to example embodiments. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments of the inventive concept will be explained in detail with reference to the accompanying drawings.

[0036] Figure 1 is a cross-sectional view illustrating an organic light emitting display (OLED) device according to example embodiments.

[0037] Reference Figure 1 , the OLED device 100 may include a substrate 110, a first semiconductor element 250, a second semiconductor element 255, a gate electrode pattern 180, a gate insulating layer 150, a first insulating interlayer 190, a second insulating interlayer 300, a protective electrode 195, a protective insulating layer 400, a planarization layer 270, a light emitting structure 200, a pixel defining layer 310, etc. Here, the first semiconductor element 250 may include a first active layer 130, a first gate electrode 170, a first source electrode 210, and a first drain electrode 230, and the second semiconductor element 255 may include a second active layer 135, a second gate electrode 175, a second source electrode 215, and a second drain electrode 235. In addition, the light emitting structure 200 may include a lower electrode 290, a light emitting layer 330, and an upper electrode 340.

[0038] When the OLED device 100 includes the protection electrode 195 , the OLED device 100 may prevent the second active layer 135 from being damaged by an etchant used in a buffered oxide etchant (“BOE”) process.

[0039] A substrate 110 including a transparent or opaque material may be provided. For example, the substrate 110 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluoride-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, etc. Alternatively, the substrate 110 may include a flexible transparent material such as a flexible transparent resin substrate (e.g., a polyimide substrate). In this case, the polyimide substrate may include a first polyimide layer, a barrier film layer, a second polyimide layer, etc. For example, the polyimide substrate may have a structure in which a first polyimide layer, a barrier film layer, and a second polyimide layer are stacked on a rigid glass substrate. Since the polyimide substrate is relatively thin and flexible, the polyimide substrate may be formed on a rigid glass substrate to help support the formation of an upper structure (e.g., a first semiconductor element 250, a second semiconductor element 255, a light emitting structure 200, etc.). When manufacturing the OLED device 100, after an insulating layer (e.g., a buffer layer) is provided on the second polyimide layer of the polyimide substrate, an upper structure may be formed on the insulating layer. After forming the upper structure on the buffer layer, the rigid glass substrate on which the polyimide substrate is formed can be removed. Because the polyimide substrate is relatively thin and flexible, it may be difficult to directly form the upper structure on the polyimide substrate. Therefore, the upper structure is formed on the polyimide substrate and the rigid glass substrate, and then after removing the rigid glass substrate, the polyimide substrate can be used as the substrate 110.

[0040] In example embodiments, the substrate 110 may have a first region 10 and a second region 20, and the first region 10 may be located adjacent to the second region 20. For example, the first region 10 may be a region where a driving transistor is disposed, and the second region 20 may be a region where a switching transistor is disposed.

[0041] A buffer layer (not shown) may be disposed on the substrate 110. The buffer layer may be disposed on the entire substrate 110. The buffer layer may prevent metal atoms and / or impurities from diffusing from the substrate 110 into the first semiconductor element 250, the second semiconductor element 255, and the light emitting structure 200. In addition, the buffer layer may control the heat transfer rate in the crystallization process for forming the active layer, thereby obtaining a substantially uniform active layer. In addition, when the surface of the substrate 110 is relatively uneven, the buffer layer may improve the surface flatness of the substrate 110. Depending on the type of the substrate 110, at least two buffer layers may be disposed on the substrate 110, or no buffer layer may be disposed. For example, the buffer layer may include an organic material or an inorganic material.

[0042] The first active layer 130 may be disposed on the substrate 110 and in the first region 10. For example, the first active layer 130 may include a metal oxide semiconductor, amorphous silicon, polycrystalline silicon, an organic semiconductor, etc. In example embodiments, the first active layer 130 may include a silicon-based semiconductor, and may include amorphous silicon or polycrystalline silicon. In addition, the first active layer 130 may include a source region, a drain region, and a channel region between the source region and the drain region. For example, the first contact hole 212 may expose the source region, and the second contact hole 232 may expose the drain region.

[0043] The gate insulating layer 150 may be disposed on the substrate 110 and the first active layer 130 and in the first region 10 and the second region 20. The gate insulating layer 150 may cover the first active layer 130 in the first region 10 on the substrate 110, and may be disposed on the entire substrate 110. For example, the gate insulating layer 150 may cover the first active layer 130 on the substrate 110, and may be disposed to a substantially uniform thickness along a contour of the first active layer 130. Alternatively, the gate insulating layer 150 may fully cover the first active layer 130 on the substrate 110, and may have a substantially flat upper surface without a step around the first active layer 130. The gate insulating layer 150 may include a silicon compound, a metal oxide, or the like. For example, the gate insulating layer 150 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiO x C y ), Silicon Carbonitride (SiC x N y), aluminum oxide (AlO x ), aluminum nitride (AlN x ), tantalum oxide (TaO x ), hafnium oxide (HfO x ), zirconium oxide (ZrO x ), titanium oxide (TiO x ) etc. Alternatively, the gate insulating layer 150 may have a multilayer structure including a plurality of insulating layers. For example, the insulating layers may have different thicknesses from each other or include different materials from each other.

[0044] The first gate electrode 170 may be disposed on the gate insulating layer 150 and in the first region 10. The first gate electrode 170 may be disposed on a portion of the gate insulating layer 150 under which the first active layer 130 is located. In other words, the first gate electrode 170 may be positioned to overlap the channel region of the first active layer 130. The first gate electrode 170 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in a suitable combination thereof. Alternatively, the first gate electrode 170 may have a multilayer structure including a plurality of layers.

[0045] The first insulating interlayer 190 may be disposed on the gate insulating layer 150 and the first gate electrode 170 and in the first region 10 and the second region 20. The first insulating interlayer 190 may cover the first gate electrode 170 in the first region 10 on the gate insulating layer 150, and may be disposed on the entire gate insulating layer 150. For example, the first insulating interlayer 190 may cover the first gate electrode 170 on the gate insulating layer 150, and may be disposed to a substantially uniform thickness along the contour of the first gate electrode 170. Alternatively, the first insulating interlayer 190 may fully cover the first gate electrode 170 on the gate insulating layer 150, and may have a substantially flat upper surface, and may not have a step around the first gate electrode 170. The first insulating interlayer 190 may include a silicon compound, a metal oxide, and the like. Alternatively, the first insulating interlayer 190 may have a multilayer structure including a plurality of insulating layers. For example, the insulating layers may have different thicknesses from each other or include different materials from each other.

[0046] The gate electrode pattern 180 may be disposed on the first insulating interlayer 190 and in the first region 10. The gate electrode pattern 180 may be disposed on a portion of the first insulating interlayer 190 under which the first gate electrode 170 is positioned. The gate electrode pattern 180 may be used as a wiring. For example, the gate electrode pattern 180 may be a data signal wiring for providing a data signal, a gate signal wiring for providing a gate signal, an initialization signal wiring for providing an initialization signal, a light emitting signal wiring for providing a light emitting signal, a power supply wiring for providing a power supply voltage, etc. The gate electrode pattern 180 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in a suitable combination thereof. Alternatively, the gate electrode pattern 180 may have a multilayer structure including a plurality of layers. In some example embodiments, the gate electrode pattern 180 may be used as an electrode. In this case, wiring may also be provided on the gate electrode pattern 180, and the wiring may be connected to the gate electrode pattern 180 via a contact hole.

[0047] The second gate electrode 175 may be disposed on the first insulating interlayer 190 and in the second region 20. In example embodiments, the second gate electrode 175 and the gate electrode pattern 180 may be located on the same layer and may be formed simultaneously (or in parallel) using the same material. The second gate electrode 175 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in appropriate combinations thereof. Alternatively, the second gate electrode 175 may have a multilayer structure including a plurality of layers.

[0048] The second insulating interlayer 300 may be disposed on the first insulating interlayer 190, the second gate electrode 175, and the gate electrode pattern 180. The second insulating interlayer 300 may cover the gate electrode pattern 180 on the first insulating interlayer 190 and in the first region 10 and cover the second gate electrode 175 on the first insulating interlayer 190 and in the second region 20, and may be disposed on the entire first insulating interlayer 190. For example, the second insulating interlayer 300 may cover the gate electrode pattern 180 and the second gate electrode 175 on the first insulating interlayer 190, and may be disposed to a substantially uniform thickness along the contours of the gate electrode pattern 180 and the second gate electrode 175. Alternatively, the second insulating interlayer 300 may fully cover the gate electrode pattern 180 and the second gate electrode 175 on the first insulating interlayer 190, and may have a substantially flat upper surface without steps surrounding the gate electrode pattern 180 and the second gate electrode 175. The second insulating interlayer 300 may include a silicon compound, a metal oxide, etc. Alternatively, the second insulating interlayer 300 may have a multilayer structure including a plurality of insulating layers. For example, the insulating layers may have different thicknesses or include different materials from each other.

[0049] In example embodiments, the second insulating interlayer 300 may be in direct contact with the second active layer 135 to ensure the characteristics or reliability of the second semiconductor element 255. In other words, the upper surface of the second insulating interlayer 300 may be in direct contact with the lower surface of the second active layer 135. For example, when the second active layer 135 including a metal oxide semiconductor is in direct contact with the lower surface of the second active layer 135 including SiO x When the second active layer 135 is in direct contact with the second insulating interlayer 300 , the interface characteristics of the second active layer 135 may be relatively improved.

[0050] The second active layer 135 may be disposed on the second insulating interlayer 300 and in the second region 20. The second active layer 135 may be disposed on a portion of the second insulating interlayer 300 under which the second gate electrode 175 is positioned. In addition, the second active layer 135 may extend along a first direction D1 on the second insulating interlayer 300, which is a direction from the second region 20 to the first region 10. In example embodiments, the second active layer 135 is disposed under the protective electrode 195 to overlap with a portion of the protective electrode 195. In example embodiments, the second active layer 135 may be positioned to overlap with the protective electrode 195, the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235, and may not be located on the first contact hole 212 and the second contact hole 232. In addition, the second active layer 135 may be disposed in a space between the second source electrode 215 and the second drain electrode 235, and may not be disposed in a space between the first source electrode 210 and the first drain electrode 230. In addition, the second active layer 135 may be disposed in a space between the second drain electrode 235 and the first source electrode 210. The second active layer 135 may include a metal oxide semiconductor. In other words, the second active layer 135 may include a metal oxide semiconductor layer including a two-component compound (AB x ), ternary compounds (AB x C y ), four-component compound (AB x C y D z ) and the like. These compounds contain indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), and the like. For example, the second active layer 135 may include zinc oxide (ZnO x ), gallium oxide (GaO x ), titanium oxide (TiO x ), tin oxide (SnO x ), indium oxide (InO x), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc tin oxide (ZTO), zinc zirconium oxide (ZnZr x O y ), indium gallium-zinc oxide (IGZO), indium zinc oxide-tin (IZTO), indium gallium-hafnium oxide (IGHO), tin oxide-aluminum-zinc (TAZO), indium gallium-tin oxide (IGTO), etc.

[0051] The protection electrode 195 may be disposed on the second active layer 135 except for the region overlapping the channel region of the first semiconductor element 250 and the second semiconductor element 255. The protection electrode 195 may be disposed on the second active layer 135 and in the second region 20. The protection electrode 195 may be disposed between the second active layer 135 and the second source electrode 215 and the second drain electrode 235. In addition, the protection electrode 195 may have a first opening exposing the upper surface of the second active layer 135 in the second region 20 and a second opening exposing the upper surface of the second insulating interlayer 300 in the first region 10. In addition, the protection electrode 195 may extend in the first direction D1 on the second active layer 135. In example embodiments, the protection electrode 195 may be positioned to overlap the second active layer 135, the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235, and may not be located on the first contact hole 212 and the second contact hole 232. In addition, the protective electrode 195 may not be disposed in the space between the second source electrode 215 and the second drain electrode 235, and may not be disposed in the space between the first source electrode 210 and the first drain electrode 230. Here, the space between the second source electrode 215 and the second drain electrode 235 may correspond to the first opening, and the space between the first source electrode 210 and the first drain electrode 230 may correspond to the second opening. In addition, the protective electrode 195 may be disposed in the space between the second drain electrode 235 and the first source electrode 210. For example, the protective electrode 195 may contact the lower surface of the first source electrode 210 and the lower surface of the second drain electrode 235, and may electrically connect the first source electrode 210 and the second drain electrode 235.

[0052] The protective electrode 195 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the protective electrode 195 may include gold (Au), silver (Ag), aluminum (Al), tungsten (W), copper (Cu), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum alloy, aluminum nitride (AlN), etc. x), silver alloy, tungsten nitride (WN x ), copper alloys, molybdenum alloys, titanium nitride (TiN x ), chromium nitride (CrN x ), Tantalum Nitride (TaN x ), strontium ruthenium oxide (SRO), zinc oxide (ZnO x )、Indium Tin Oxide (ITO), Tin Oxide (SnO x ), indium oxide (InO x ), gallium oxide (GaO x ), indium zinc oxide (IZO), etc. These materials may be used alone or in appropriate combination thereof. Alternatively, the protective electrode 195 may have a multi-layer structure including a plurality of layers.

[0053] For example, in the manufacturing process of the OLED device 100, the protection electrode 195 may include a material not etched by a buffered oxide etchant (BOE) to protect the second active layer 135 from the effects caused by the buffered oxide etchant. In example embodiments, the protection electrode 195 may include Mo or Cu.

[0054] The first source electrode 210 and the first drain electrode 230 may be disposed on the protective electrode 195 and in the first region 10. The first source electrode 210 may contact the source region of the first active layer 130 via a first contact hole 212 formed by removing the first portion of the second active layer 135, the protective electrode 195, the second insulating interlayer 300, the first insulating interlayer 190, and the gate insulating layer 150. The first drain electrode 230 may contact the drain region of the first active layer 130 via a second contact hole 232 formed by removing the second active layer 135, the protective electrode 195, the second insulating interlayer 300, the first insulating interlayer 190, and the gate insulating layer 150. Each of the first source electrode 210 and the first drain electrode 230 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These materials may be used alone or in appropriate combinations thereof. Alternatively, each of the first source electrode 210 and the first drain electrode 230 may have a multilayer structure including a plurality of layers.

[0055] Therefore, the first semiconductor element 250 including the first active layer 130, the first gate electrode 170, the first source electrode 210 and the first drain electrode 230 may be disposed on the substrate 110. Here, the first semiconductor element 250 may be used as a driving transistor having a silicon-based semiconductor. In addition, the first semiconductor element 250 may be used as a transistor having a top gate structure.

[0056] The second source electrode 215 and the second drain electrode 235 may be disposed on the second insulating interlayer 300 and in the second region 20. The second source electrode 215 may overlap with the first lateral portion of the second gate electrode 175 and may be disposed on the protective electrode 195. The second drain electrode 235 may overlap with the second lateral portion of the second gate electrode 175 and may be disposed on the protective electrode 195. Here, the first lateral portion may be opposite to the second lateral portion. In other words, the second source electrode 215 and the second drain electrode 235 may be disposed on the protective electrode 195 to overlap with two lateral portions of the second gate electrode 175, and may expose a portion of the upper surface of the second active layer 135 (or may not be disposed in a portion of the upper surface of the second active layer 135). Each of the second source electrode 215 and the second drain electrode 235 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in appropriate combinations thereof. In example embodiments, each of the first source electrode 210 and the first drain electrode 230 and the second source electrode 215 and the second drain electrode 235 may be located on the same layer, and each of the first source electrode 210 and the first drain electrode 230 and the second source electrode 215 and the second drain electrode 235 may be simultaneously formed using the same material. Alternatively, each of the second source electrode 215 and the second drain electrode 235 may have a multilayer structure including a plurality of layers.

[0057] Therefore, a second semiconductor element 255 including a second active layer 135, a second gate electrode 175, a second source electrode 215, and a second drain electrode 235 may be disposed on the substrate 110. Here, the second semiconductor element 255 may be used as a switching transistor including an oxide-based semiconductor. In addition, the second semiconductor element 255 may be used as a transistor having a bottom gate structure.

[0058] In example embodiments, the OLED device 100 includes two transistors, for example, the first semiconductor element 250 and the second semiconductor element 255, but is not limited thereto. For example, the OLED device 100 may include at least three transistors and at least one capacitor.

[0059] The protective insulating layer 400 may be disposed on the second insulating interlayer 300, the first source electrode 210 and the first drain electrode 230, the second source electrode 215 and the second drain electrode 235. The protective insulating layer 400 may cover the first source electrode 210 and the first drain electrode 230 in the first region 10 and the second source electrode 215 and the second drain electrode 235 in the second region 20 on the second insulating interlayer 300, and may be disposed on the entire second insulating interlayer 300. For example, the protective insulating layer 400 may cover the first source electrode 210 and the first drain electrode 230 and the second source electrode 215 and the second drain electrode 235 on the second insulating interlayer 300, and may be disposed to a substantially uniform thickness along the contours of the first source electrode 210 and the first drain electrode 230 and the second source electrode 215 and the second drain electrode 235. Alternatively, the protective insulating layer 400 may fully cover the first source electrode 210 and the first drain electrode 230 and the second source electrode 215 and the second drain electrode 235 on the second insulating interlayer 300, and may have a substantially flat upper surface without a step surrounding the first source electrode 210 and the first drain electrode 230 and the second source electrode 215 and the second drain electrode 235. In example embodiments, the protective insulating layer 400 may have an opening 402 exposing a portion of the upper surface of the first drain electrode 230 in the first region 10. The lower electrode 290 may contact the first drain electrode 230 through the opening 402 and the contact hole of the planarization layer 270. The protective insulating layer 400 may include a silicon compound, a metal oxide, or the like. In example embodiments, the protective insulating layer 400 may include SiO x In addition, the protective insulating layer 400 may directly contact the upper surface of the second active layer 135 and the sidewall of the protective electrode 195 in the space provided between the second source electrode 215 and the second drain electrode 235 (eg, the first opening of the protective electrode 195). x The protective insulating layer 400 is in direct contact with the second active layer 135, so the interface characteristics of the second active layer 135 can be relatively improved. In addition, the protective insulating layer 400 provided in the space provided between the first source electrode 210 and the first drain electrode 230 (for example, the second opening of the protective electrode 195) can be in direct contact with the upper surface of the second insulating interlayer 300, the sidewall of the second active layer 135, and the sidewall of the protective electrode 195. Optionally, the protective insulating layer 400 may have a multilayer structure including a plurality of insulating layers. For example, the insulating layers may have different thicknesses from each other or include different materials from each other.

[0060] The planarization layer 270 may be disposed on the protective insulating layer 400. The planarization layer 270 may be disposed on the entire protective insulating layer 400. For example, the planarization layer 270 may have a thickness sufficient to fully cover the protective insulating layer 400. In this case, the planarization layer 270 may have a substantially flat upper surface. When the upper surface of the substrate 110 is not flat enough, a planarization process may be further performed on the planarization layer 270 to achieve a flat upper surface. A portion of the upper surface of the first drain electrode 230 may be exposed via a contact hole formed by removing a portion of the planarization layer 270. The planarization layer 270 may include an organic material or an inorganic material. In example embodiments, the planarization layer 270 may include an organic material such as polyimide, epoxy resin, acrylic resin, polyester fiber, photoresist, polyacrylic resin, polyimide resin, polyamide resin, siloxane resin, etc. For example, since the protective insulating layer 400 includes an inorganic material and the planarization layer 270 includes an organic material, the protective insulating layer 400 may not be removed in an etching process for forming a contact hole of the planarization layer 270. Therefore, in order to expose a portion of the upper surface of the first drain electrode 230, the contact hole of the planarization layer 270 may be formed after the opening 402 of the protective insulating layer 400 is formed.

[0061] The lower electrode 290 may be disposed on the planarization layer 270. The lower electrode 290 may be in direct contact with the first drain electrode 230 via a contact hole formed in the planarization layer 270, and may be electrically connected to the first semiconductor element 250. The lower electrode 290 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in a suitable combination thereof. Alternatively, the lower electrode 290 may have a multilayer structure including a plurality of layers.

[0062] The pixel defining layer 310 may be disposed on a portion of the lower electrode 290 and a portion of the planarization layer 270. The pixel defining layer 310 may cover the entire edge of the lower electrode 290 including two lateral portions of the lower electrode 290, and may expose a portion of the upper surface of the lower electrode 290. The pixel defining layer 310 may include an organic material or an inorganic material. In example embodiments, the pixel defining layer 310 may include an organic material.

[0063] The light-emitting layer 330 may be disposed on the lower electrode 290 exposed by the pixel defining layer 310. The light-emitting layer 330 may be formed using at least one of the light-emitting materials capable of generating light of different colors (e.g., red light, blue light, green light, etc.) according to the sub-pixel. Alternatively, the light-emitting layer 330 may generally generate white light by stacking a plurality of light-emitting materials capable of generating light of different colors such as red light, green light, blue light, etc. In this case, a color filter may be disposed on the light-emitting layer 330, for example, overlapping the light-emitting layer 330 and disposed on the lower surface of the encapsulation substrate (not shown). The color filter may include at least one color filter selected from a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may include a photosensitive resin, a color photoresist, and the like.

[0064] The upper electrode 340 may be disposed on the pixel defining layer 310 and the light emitting layer 330. The upper electrode 340 may cover the light emitting layer 330 and the pixel defining layer 310, and may be completely disposed on the light emitting layer 330 and the pixel defining layer 310. The upper electrode 340 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in a suitable combination thereof. Alternatively, the upper electrode 340 may have a multilayer structure including a plurality of layers.

[0065] Therefore, the light emitting structure 200 including the lower electrode 290 , the light emitting layer 330 , and the upper electrode 340 may be disposed on the planarization layer 270 .

[0066] An encapsulation substrate (not shown) may be disposed on the upper electrode 340. The encapsulation substrate and the substrate 110 may include substantially the same material. For example, the encapsulation substrate may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluoride-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, and the like. In some example embodiments, the encapsulation substrate may include a transparent inorganic material or a flexible plastic. For example, the encapsulation substrate may include a flexible transparent resin substrate. In this case, in order to increase the flexibility of the OLED device 100, the encapsulation substrate may have a stacking structure in which at least one inorganic layer and at least one organic layer are alternately stacked. The stacking structure may include a first inorganic layer, an organic layer, and a second inorganic layer. For example, a first inorganic layer having flexibility may be disposed along the contour of the upper electrode 340, and an organic layer having flexibility may be disposed on the first inorganic layer. A second inorganic layer having flexibility may be disposed on the organic layer. That is, the stacking structure may correspond to a thin film encapsulation structure in direct contact with the upper electrode 340. Therefore, an OLED device 100 may be provided.

[0067] Since SiO xThe second insulating interlayer 300 and the protective insulating layer 400 are in direct contact with the second active layer 135, so the interface characteristics of the second active layer 135 may be relatively improved. Therefore, the OLED device 100 according to example embodiments may include the second semiconductor element 255 having improved reliability.

[0068] In addition, since the OLED device 100 according to the example embodiment includes the protection electrode 195 , the OLED device 100 can protect the second active layer 135 from damage caused by an etchant used in the BOE process. Therefore, the OLED device 100 can prevent defects of the second semiconductor element 255 .

[0069] Figures 2 to 10 is a cross-sectional view illustrating a method of manufacturing an OLED device according to example embodiments.

[0070] Reference Figure 2 , a substrate 110 including a transparent or opaque insulating material may be provided. For example, the substrate 110 may be formed using a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluoride-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, or the like. Alternatively, the substrate 110 may be formed using a flexible transparent material such as a flexible transparent resin substrate (e.g., a polyimide substrate). In example embodiments, the substrate 110 may have a first region 10 and a second region 20, and the first region 10 may be positioned adjacent to the second region 20.

[0071] A buffer layer (not shown) may be formed on the substrate 110. The buffer layer may be formed on the entire substrate 110. The buffer layer may prevent metal atoms and / or impurities from diffusing from the substrate 110 into the first semiconductor element 250, the second semiconductor element 255, and the light emitting structure 200. In addition, the buffer layer may control the heat transfer rate in the crystallization process for forming the active layer, thereby obtaining a substantially uniform active layer. In addition, when the surface of the substrate 110 is relatively uneven, the buffer layer may improve the surface flatness of the substrate 110. Depending on the type of the substrate 110, at least two buffer layers may be provided on the substrate 110, or no buffer layer may be formed. For example, an organic material or an inorganic material may be used to form the buffer layer.

[0072] The first active layer 130 may be formed on the substrate 110 and in the first region 10. For example, the first active layer 130 may be formed using a metal oxide semiconductor, amorphous silicon, polycrystalline silicon, an organic semiconductor, etc. In example embodiments, the first active layer 130 may include a silicon-based semiconductor, and may include amorphous silicon or polycrystalline silicon. In addition, the first active layer 130 may include a source region, a drain region, and a channel region located between the source region and the drain region.

[0073] A gate insulating layer 150 may be formed on the substrate 110 and the first active layer 130 and in the first region 10 and the second region 20. The gate insulating layer 150 may cover the first active layer 130 in the first region 10 on the substrate 110, and may be formed on the entire substrate 110. For example, the gate insulating layer 150 may cover the first active layer 130 on the substrate 110, and may be formed to a substantially uniform thickness along a contour of the first active layer 130. Alternatively, the gate insulating layer 150 may fully cover the first active layer 130 on the substrate 110, and may have a substantially flat upper surface without a step around the first active layer 130. The gate insulating layer 150 may be formed using a silicon compound, a metal oxide, or the like. For example, the gate insulating layer 150 may include SiO x 、SiN x 、SiO x N y 、SiO x C y 、SiC x N y 、AlO x 、AlN x 、TaO x , HfO x 、ZrO x 、TiO x Etc. Alternatively, the gate insulating layer 150 may have a multi-layer structure including a plurality of insulating layers. For example, the insulating layers may have different thicknesses from each other or include different materials from each other.

[0074] A first gate electrode 170 may be formed on the gate insulating layer 150 and in the first region 10. The first gate electrode 170 may be formed on a portion of the gate insulating layer 150 under which the first active layer 130 is positioned. In other words, the first gate electrode 170 may be positioned to overlap with the channel region of the first active layer 130. The first gate electrode 170 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in a suitable combination thereof. Alternatively, the first gate electrode 170 may have a multilayer structure including a plurality of layers. After the first gate electrode 170 is formed, a source region and a drain region may be formed by doping the source region and the drain region that are not overlapped with the first gate electrode 170 with impurities.

[0075] Reference Figure 3, a first insulating interlayer 190 may be formed on the gate insulating layer 150 and the first gate electrode 170 and in the first region 10 and the second region 20. The first insulating interlayer 190 may cover the first gate electrode 170 in the first region 10 on the gate insulating layer 150, and may be formed on the entire gate insulating layer 150. For example, the first insulating interlayer 190 may cover the first gate electrode 170 on the gate insulating layer 150, and may be formed to a substantially uniform thickness along the contour of the first gate electrode 170. Alternatively, the first insulating interlayer 190 may fully cover the first gate electrode 170 on the gate insulating layer 150, and may have a substantially flat upper surface, and may not have a step around the first gate electrode 170. The first insulating interlayer 190 may be formed using a silicon compound, a metal oxide, or the like. Optionally, the first insulating interlayer 190 may have a multilayer structure including a plurality of insulating layers. For example, the insulating layers may have different thicknesses from each other or include different materials from each other.

[0076] A gate electrode pattern 180 may be formed on the first insulating interlayer 190 and in the first region 10. The gate electrode pattern 180 may be formed on a portion of the first insulating interlayer 190 under which the first gate electrode 170 is positioned. The gate electrode pattern 180 may be used as wiring. For example, the gate electrode pattern 180 may be a data signal wiring for providing a data signal, a gate signal wiring for providing a gate signal, an initialization signal wiring for providing an initialization signal, a light emitting signal wiring for providing a light emitting signal, a power supply wiring for providing a power supply voltage, etc. The gate electrode pattern 180 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0077] The second gate electrode 175 may be formed on the first insulating interlayer 190 and in the second region 20. In example embodiments, the second gate electrode 175 and the gate electrode pattern 180 may be located on the same layer and may be formed simultaneously using the same material. For example, after an initial gate electrode layer is formed on the entire first insulating interlayer 190, the second gate electrode 175 and the gate electrode pattern 180 may be formed simultaneously by selectively removing the initial gate electrode layer. The second gate electrode 175 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like.

[0078] The second insulating interlayer 300 may be formed on the first insulating interlayer 190, the second gate electrode 175, and the gate electrode pattern 180. The second insulating interlayer 300 may cover the gate electrode pattern 180 on the first insulating interlayer 190 and in the first region 10 and cover the second gate electrode 175 on the first insulating interlayer 190 and in the second region 20, and may be formed on the entire first insulating interlayer 190. For example, the second insulating interlayer 300 may cover the gate electrode pattern 180 and the second gate electrode 175 on the first insulating interlayer 190, and may be formed to a substantially uniform thickness along the contours of the gate electrode pattern 180 and the second gate electrode 175. Alternatively, the second insulating interlayer 300 may fully cover the gate electrode pattern 180 and the second gate electrode 175 on the first insulating interlayer 190, and may have a substantially flat upper surface without steps around the gate electrode pattern 180 and the second gate electrode 175. The second insulating interlayer 300 may be formed using silicon compounds, metal oxides, and the like. Alternatively, the second insulating interlayer 300 may have a multi-layer structure including a plurality of insulating layers. For example, the insulating layers may have different thicknesses from each other or include different materials from each other.

[0079] Reference Figure 4 , the initial second active layer 1135 may be formed on the entire second insulating interlayer 300 and in the first region 10 and the second region 20. For example, the initial second active layer 1135 may be formed to a substantially uniform thickness along the contour of the second insulating interlayer 300. The initial second active layer 1135 may be formed using a metal oxide semiconductor. In other words, the initial second active layer 1135 may include a metal oxide semiconductor layer including AB x , AB x C y , AB x C y D z At least one of the compounds described above. These compounds include In, Zn, Ga, Sn, Ti, Al, Hf, Zr, Mg, etc. For example, the initial second active layer 1135 may include ZnO x 、GaO x 、TiO x SnO x 、InO x ,IGO,IZO,ITO,GZO,ZMO,ZTO,ZnZr x O y , at least one of IGZO, IZTO, IGHO, TAZO, IGTO, etc.

[0080] The initial protective electrode layer 1195 may be formed on the entire initial second active layer 1135 and in the first region 10 and the second region 20. For example, the initial protective electrode layer 1195 may be formed to a substantially uniform thickness along the contour of the initial second active layer 1135. The initial protective electrode layer 1195 may be formed using a conductive layer such as a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the initial protective electrode layer 1195 may include Au, Ag, Al, W, Cu, Pt, Ni, Ti, Pd, Mg, Ca, Li, Cr, Ta, Mo, Sc, Nd, Ir, an alloy of aluminum, AlN x , silver alloy, WN x , copper alloy, molybdenum alloy, TiN x CrN x 、TaN x 、SRO、ZnO x 、ITO、SnO x 、InO x 、GaO x , IZO, etc. These materials may be used alone or in appropriate combinations thereof. Optionally, the initial protective electrode layer 1195 may have a multilayer structure including a plurality of layers. In example embodiments, the initial protective electrode layer 1195 may include a material that is not etched by an etchant used in a BOE process (to be described below) to protect the initial second active layer 1135 from the effects caused by the etchant used in the BOE process. For example, the initial protective electrode layer 1195 may include Mo or Cu.

[0081] Reference Figure 5 , the first contact hole 212 may be formed by removing the first portion of the initial second active layer 1135, the initial protective electrode layer 1195, the second insulating interlayer 300, the first insulating interlayer 190, and the gate insulating layer 150 in the first region 10. The first contact hole 212 may expose the source region of the first active layer 130. In addition, the second contact hole 232 may be formed by removing the second portion of the initial second active layer 1135, the initial protective electrode layer 1195, the second insulating interlayer 300, the first insulating interlayer 190, and the gate insulating layer 150 in the first region 10. The second contact hole 232 may expose the drain region of the first active layer 130. The first and second portions of the initial second active layer 1135, the initial protective electrode layer 1195, the second insulating interlayer 300, the first insulating interlayer 190, and the gate insulating layer 150 may be removed by an oxygen plasma treatment process.

[0082] Reference Figure 6, the heat treatment process may be performed on the entire substrate 110. In example embodiments, when the heat treatment process is performed on the first active layer 130, a driving range (to be described below) of the first semiconductor element 250 corresponding to the driving transistor may be relatively widened. In addition, when the heat treatment process is performed on the initial second active layer 1135, since the distribution of the threshold voltage of the second semiconductor element 255 corresponding to the switching transistor (to be described below) is reduced, a relatively accurate second semiconductor element 255 may be obtained. When the heat treatment process is performed on the first active layer 130 and the initial second active layer 1135 at the same time, the manufacturing cost of the OLED device may be relatively reduced.

[0083] In the heat treatment process, an oxide layer (or oxides) may be formed in the source region and the drain region of the first active layer 130. For example, because the heat treatment process is performed in an atmosphere in which oxygen ions exist in the chamber, the upper surface of the first active layer 130 exposed to the outside through the first contact hole 212 and the second contact hole 232 may react with the oxygen ions, and thus, an oxide layer may be formed on the surface of the exposed first active layer 130.

[0084] After the heat treatment process, an etching process using BOE (BOE process) may be performed to remove the oxide layer formed on the first active layer 130. During the BOE process, since the initial protective electrode layer 1195 completely covers the initial second active layer 1135, the initial protective electrode layer 1195 may protect the initial second active layer 1135 from damage caused by an etchant used in the BOE process. Therefore, the BOE process may be performed without damaging the initial second active layer 1135.

[0085] Reference Figure 7 , the initial electrode layer 1210 may be formed on the entire initial protective electrode layer 1195 and in the first region 10 and the second region 20. For example, the initial electrode layer 1210 may be formed to a substantially uniform thickness along the contour of the initial protective electrode layer 1195. The initial electrode layer 1210 may be formed using metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, and the like. These materials may be used alone or in appropriate combinations thereof. Alternatively, the initial electrode layer 1210 may have a multilayer structure including a plurality of layers. After the initial electrode layer 1210 is formed, a selective etching process may be performed using a halftone mask.

[0086] Reference Figure 8By selectively etching the initial second active layer 1135, the initial protective electrode layer 1195 and the initial electrode layer 1210, a first source electrode 210 and a first drain electrode 230 can be formed on the second insulating interlayer 300 and in the first region 10, and a second active layer 135, a protective electrode 195, a second source electrode 215 and a second drain electrode 235 can be formed on the second insulating interlayer 300 and in the second region 20.

[0087] For example, by using a selective etching process through a half-tone mask, the second active layer 135 may be formed in a space disposed between the second source electrode 215 and the second drain electrode 235, but may not be formed in a space disposed between the first source electrode 210 and the first drain electrode 230. In other words, the initial electrode layer 1210 and the initial protective electrode layer 1195 disposed between the second source electrode 215 and the second drain electrode 235 may be removed, and thus the second active layer 135 disposed between the second source electrode 215 and the second drain electrode 235 may be exposed. The second active layer 135 may be removed in a space disposed between the first drain electrode 230 and the first source electrode 210. In addition, the protective electrode 195 disposed between the second source electrode 215 and the second drain electrode 235 may be removed, and the protective electrode 195 disposed between the first source electrode 210 and the first drain electrode 230 may be removed. In other words, the first opening of the protection electrode 195 may be formed by removing the initial protection electrode layer 1195 and the initial electrode layer 1210 disposed in the space between the second source electrode 215 and the second drain electrode 235 in the second region 20, and the second opening may be formed by removing the initial second active layer 1135, the initial protection electrode layer 1195, and the initial electrode layer 1210 disposed in the space between the first source electrode 210 and the first drain electrode 230 in the first region 10. The protection electrode 195 may not be removed in the space disposed between the second drain electrode 235 and the first source electrode 210. In addition, the second insulating interlayer 300 disposed between the first source electrode 210 and the first drain electrode 230 may be exposed, and the second insulating interlayer 300 disposed between the second drain electrode 235 and the first source electrode 210 may be covered by the second active layer 135 and the protection electrode 195. In other words, by removing the preliminary electrode layer 1210 disposed between the second drain electrode 235 and the first source electrode 210 , the second insulating interlayer 300 may be covered by the second active layer 135 and the protection electrode 195 .

[0088] Thus, a first semiconductor element 250 including a first active layer 130 , a first gate electrode 170 , a first source electrode 210 , and a first drain electrode 230 may be formed, and a second semiconductor element 255 including a second active layer 135 , a second gate electrode 175 , a second source electrode 215 , and a second drain electrode 235 may be formed.

[0089] Reference Fig. 9 , a protective insulating layer 400 may be formed on the second insulating interlayer 300, the first source electrode 210 and the first drain electrode 230, and the second source electrode 215 and the second drain electrode 235. The protective insulating layer 400 may cover the first source electrode 210 and the first drain electrode 230 in the first region 10 and the second source electrode 215 and the second drain electrode 235 in the second region 20 on the second insulating interlayer 300, and may be formed on the entire second insulating interlayer 300. For example, the protective insulating layer 400 may cover the first source electrode 210 and the first drain electrode 230 and the second source electrode 215 and the second drain electrode 235 on the second insulating interlayer 300, and may be formed to a substantially uniform thickness along the contours of the first source electrode 210 and the first drain electrode 230 and the second source electrode 215 and the second drain electrode 235. Alternatively, the protective insulating layer 400 may fully cover the first source electrode 210 and the first drain electrode 230 and the second source electrode 215 and the second drain electrode 235 on the second insulating interlayer 300, and may have a substantially flat upper surface without a step around the first source electrode 210 and the first drain electrode 230 and the second source electrode 215 and the second drain electrode 235. The protective insulating layer 400 may be formed using a silicon compound, a metal oxide, or the like. In example embodiments, the protective insulating layer 400 may include SiO x . In addition, the protective insulating layer 400 may be in direct contact with the upper surface of the second active layer 135 and the sidewall of the protective electrode 195 in the space (e.g., the first opening of the protective electrode 195) disposed between the second source electrode 215 and the second drain electrode 235. In addition, the protective insulating layer 400 disposed in the space (e.g., the second opening of the protective electrode 195) between the first source electrode 210 and the first drain electrode 230 may be in direct contact with the upper surface of the second insulating interlayer 300, the sidewall of the second active layer 135, and the sidewall of the protective electrode 195. Optionally, the protective insulating layer 400 may have a multilayer structure including a plurality of insulating layers. For example, the insulating layers may have different thicknesses from each other or include different materials from each other.

[0090] Reference Fig.10, an opening 402 exposing a portion of the upper surface of the first drain electrode 230 may be formed in the first region 10. A planarization layer 270 may be formed on the protective insulating layer 400. The planarization layer 270 may be formed on the entire protective insulating layer 400. For example, the planarization layer 270 may be formed to a thickness sufficient to cover the protective insulating layer 400. In this case, the planarization layer 270 may have a substantially flat upper surface. If the surface of the planarization layer 270 is not flat, a planarization process may be further performed on the planarization layer 270 to achieve a flat upper surface of the planarization layer 270. A portion of the upper surface of the first drain electrode 230 may be exposed via a contact hole formed by removing a portion of the planarization layer 270. The planarization layer 270 may be formed of an organic material such as polyimide, epoxy resin, acrylic resin, polyester fiber, photoresist, polyacrylic resin, polyimide resin, polyamide resin, siloxane resin, etc. For example, since the protective insulating layer 400 includes an inorganic material and the planarization layer 270 includes an organic material, the protective insulating layer 400 may not be removed in an etching process for forming a contact hole of the planarization layer 270. Therefore, in order to expose a portion of the upper surface of the first drain electrode 230, the contact hole of the planarization layer 270 may be formed after forming the opening 402 of the protective insulating layer 400.

[0091] A lower electrode 290 may be formed on the planarization layer 270. The lower electrode 290 may be in direct contact with the first drain electrode 230 via a contact hole in the planarization layer 270. The lower electrode 290 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in a suitable combination thereof. Alternatively, the lower electrode 290 may have a multilayer structure including a plurality of layers.

[0092] A pixel defining layer 310 may be formed on a portion of the lower electrode 290 and a portion of the planarization layer 270. The pixel defining layer 310 may cover the entire edge of the lower electrode 290 including two lateral portions of the lower electrode 290, and may expose a portion of the upper surface of the lower electrode 290. The pixel defining layer 310 may be formed using an organic material.

[0093] Reference Figure 1, a light emitting layer 330 may be formed on the lower electrode 290 exposed by the pixel defining layer 310. The light emitting layer 330 may be formed using at least one of the light emitting materials capable of generating light of different colors (e.g., red light, blue light, green light, etc.) according to the sub-pixel. Alternatively, the light emitting layer 330 may generally generate white light by stacking a plurality of light emitting materials capable of generating light of different colors such as red light, green light, blue light, etc. In this case, a color filter may be formed on the light emitting layer 330, for example, so that the color filter is overlapped with the light emitting layer 330 on the lower surface of the encapsulation substrate (not shown). The color filter may include at least one selected from a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may be formed using a photosensitive resin, a color photoresist, and the like.

[0094] The upper electrode 340 may be formed on the pixel defining layer 310 and the light emitting layer 330. The upper electrode 340 may cover the light emitting layer 330 and the pixel defining layer 310, and may be completely formed on the light emitting layer 330 and the pixel defining layer 310. The upper electrode 340 may be formed using metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These materials may be used alone or in appropriate combinations thereof. Alternatively, the upper electrode 340 may have a multilayer structure including a plurality of layers.

[0095] Thus, the light emitting structure 200 including the lower electrode 290 , the light emitting layer 330 , and the upper electrode 340 may be formed.

[0096] An encapsulation substrate (not shown) may be formed on the upper electrode 340. The encapsulation substrate and the substrate 110 may include substantially the same material. For example, the encapsulation substrate may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluoride-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, and the like. In some example embodiments, the encapsulation substrate may include a transparent inorganic material or a flexible plastic. For example, the encapsulation substrate may include a flexible transparent resin substrate. In this case, in order to increase the flexibility of the OLED device, the encapsulation substrate may have a stacking structure in which at least one inorganic layer and at least one organic layer are alternately stacked. The stacking structure may include a first inorganic layer, an organic layer, and a second inorganic layer. For example, a first inorganic layer having flexibility may be formed along the contour of the upper electrode 340, and an organic layer having flexibility may be formed on the first inorganic layer. A second inorganic layer having flexibility may be formed on the organic layer. That is, the stacking structure may correspond to a thin film encapsulation structure in direct contact with the upper electrode 340.

[0097] Therefore, it is possible to produce Figure 1 The OLED device 100 shown in FIG.

[0098] In the method of manufacturing the OLED device 100 according to the example embodiment, when the heat treatment process is performed on the first active layer 130 and the initial second active layer 1135, the driving range of the first semiconductor element 250 corresponding to the driving transistor can be relatively widened, and because the distribution of the threshold voltage of the second semiconductor element 255 corresponding to the switching transistor is reduced, a relatively accurate second semiconductor element 255 can be obtained. In addition, since the heat treatment process is performed on the first active layer 130 and the initial second active layer 1135 at the same time, the manufacturing cost of the OLED device 100 can be relatively reduced.

[0099] In addition, since the initial protective electrode layer 1195 completely covers the initial second active layer 1135, the initial protective electrode layer 1195 can protect the initial second active layer 1135 from damage caused by the etchant used in the BOE process. Therefore, after the initial second active layer 1135 is formed, the BOE process can be performed without damaging the initial second active layer 1135.

[0100] Fig.11 5 is a cross-sectional view showing an OLED device according to an example embodiment. In addition to the connection electrode 510, Fig.11 The OLED display device 500 shown in FIG. 1 may have the same Figure 1 The configuration of the OLED display device 100 described above is substantially the same or similar. Fig.11 In, with reference Figure 1 Detailed descriptions of elements that are substantially the same or similar to the described elements may not be repeated.

[0101] Reference Fig.11 The OLED device 500 may include a substrate 110, a first semiconductor element 250, a second semiconductor element 255, a gate electrode pattern 180, a gate insulating layer 150, a first insulating interlayer 190, a second insulating interlayer 300, a protective electrode 195, a protective insulating layer 400, a planarization layer 270, a light emitting structure 200, a pixel defining layer 310, and the like.

[0102] In example embodiments, the connection electrode 510 may correspond to a source electrode of the first semiconductor element 250 and a drain electrode of the second semiconductor element 255. In other words, the source electrode of the first semiconductor element 250 and the drain electrode of the second semiconductor element 255 may be integrally formed.

[0103] Fig.12 6 is a cross-sectional view showing an OLED device according to an example embodiment. In addition to the second active layer 635 and the protective electrode 695, Fig.12 The OLED display device 600 shown in FIG. 1 may have the same Figure 1The configuration of the OLED display device 100 described above is substantially the same or similar. Fig.12 In, with reference Figure 1 Detailed descriptions of elements that are substantially the same or similar to the described elements may not be repeated.

[0104] Reference Fig.12 , the OLED device 600 may include a substrate 110, a first semiconductor element 250, a second semiconductor element 255, a gate electrode pattern 180, a gate insulating layer 150, a first insulating interlayer 190, a second insulating interlayer 300, a protective electrode 695, a protective insulating layer 400, a planarization layer 270, a light emitting structure 200, a pixel defining layer 310, etc. Here, the first semiconductor element 250 may include a first active layer 130, a first gate electrode 170, a first source electrode 210, and a first drain electrode 230, and the second semiconductor element 255 may include a second active layer 635, a second gate electrode 175, a second source electrode 215, and a second drain electrode 235. In addition, the light emitting structure 200 may include a lower electrode 290, a light emitting layer 330, and an upper electrode 340.

[0105] The second active layer 635 may be disposed to overlap the protection electrode 695, the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235, and may not be disposed in the first contact hole 212 and the second contact hole 232. In addition, the second active layer 635 may be disposed in a space disposed between the second source electrode 215 and the second drain electrode 235, and may not be disposed between the first source electrode 210 and the first drain electrode 230. In addition, the second active layer 635 may not be disposed in a space between the second drain electrode 235 and the first source electrode 210.

[0106] The protection electrode 695 may be disposed to overlap the second active layer 635, the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235, and may not be disposed in the first contact hole 212 and the second contact hole 232. In addition, the protection electrode 695 may not be disposed in the space between the second source electrode 215 and the second drain electrode 235, and may not be disposed in the space between the first source electrode 210 and the first drain electrode 230. The protection electrode 695 may not be disposed in the space between the second drain electrode 235 and the first source electrode 210. In other words, the protection electrode 695 may have a first opening exposing the upper surface of the second active layer 635 in the second region 20, a second opening exposing the upper surface of the second insulating interlayer 300 in the first region 10, and a third opening exposing the upper surface of the second insulating interlayer 300 in the boundary between the first region 10 and the second region 20. That is, since the second active layer 635 and the protection electrode 695 may not be disposed in the space between the second drain electrode 235 and the first source electrode 210, the first semiconductor element 250 may be separated from the second semiconductor element 255. Therefore, the first semiconductor element 250 and the second semiconductor element 255 may be driven independently of each other.

[0107] The inventive concept can be applied to various display devices including OLED devices. For example, the inventive concept can be applied to vehicle display devices, ship display devices, aircraft display devices, portable communication devices, display devices for display or for information transmission, medical display devices, etc.

[0108] The foregoing is illustrative of example embodiments and should not be construed as limiting the example embodiments. Although a few example embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications can be made in the example embodiments without substantially departing from the novel teachings and features of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Therefore, it should be understood that the foregoing is illustrative of various example embodiments and should not be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the claims.

Claims

1. An organic light-emitting display device, comprising: a substrate having a first region and a second region adjacent to the first region; A first semiconductor element, comprising: a first active layer disposed on the substrate and in the first region; a first gate electrode disposed on the first active layer; and a first source electrode and a first drain electrode disposed on the first gate electrode; A second semiconductor element, comprising: a second gate electrode disposed on the substrate and in the second region; a second active layer disposed on the second gate electrode; and a second source electrode and a second drain electrode disposed on the second active layer; a protection electrode disposed between the second active layer and the second source electrode and between the second active layer and the second drain electrode, the protection electrode having an opening exposing a portion of the second active layer; and a light emitting structure, disposed on the first semiconductor element and the second semiconductor element, wherein the protection electrode contacts a lower surface of the first source electrode and a lower surface of the second drain electrode and is disposed in a space disposed between the first source electrode and the second drain electrode, and The protection electrode electrically connects the first source electrode and the second drain electrode.

2. The organic light emitting display device according to claim 1, wherein: The second active layer is positioned to overlap the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode.

3. The organic light emitting display device according to claim 1, wherein: The second active layer is disposed under the protection electrode to overlap a portion of the protection electrode.

4. The organic light emitting display device according to claim 1, wherein: The second active layer is not disposed in a space disposed between the first source electrode and the first drain electrode, but is disposed in the space disposed between the first source electrode and the second drain electrode and in a space disposed between the second source electrode and the second drain electrode.

5. The organic light emitting display device according to claim 1, wherein: The protection electrode is not provided in both a space provided between the first source electrode and the first drain electrode and a space provided between the second source electrode and the second drain electrode, Wherein, a space disposed between the second source electrode and the second drain electrode corresponds to the opening of the protection electrode.

6. The organic light emitting display device according to claim 1, wherein: The first semiconductor element has a top gate structure and includes a silicon-based semiconductor, and Wherein, the second semiconductor element has a bottom gate structure and includes a metal oxide-based semiconductor.

7. The organic light emitting display device according to claim 6, wherein: The first active layer of the first semiconductor element includes amorphous silicon or polycrystalline silicon.

8. The organic light emitting display device according to claim 1, further comprising: a gate electrode pattern, disposed on the first gate electrode, Wherein, the gate electrode pattern and the second gate electrode are located on the same layer.

9. The organic light emitting display device according to claim 1, further comprising: a gate insulating layer, covering the first active layer in the first region on the substrate; a first insulating intermediate layer, covering the first gate electrode in the first region on the gate insulating layer; a second insulating interlayer, covering the second gate electrode in the second region on the first insulating interlayer; as well as A protective insulating layer covers the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode on the second insulating interlayer and has an opening exposing a portion of the first drain electrode.

10. The organic light emitting display device according to claim 9, wherein: The protective insulating layer contacts an upper surface of the second active layer and a sidewall of the protective electrode in a space provided between the second source electrode and the second drain electrode.

11. The organic light emitting display device according to claim 9, wherein: The protective insulating layer contacts an upper surface of the second insulating interlayer, a sidewall of the second active layer, and a sidewall of the protective electrode in a space provided between the first source electrode and the first drain electrode.

12. The organic light emitting display device according to claim 9, wherein: The second insulating interlayer contacts a lower surface of the second active layer, and the second insulating interlayer and the protective insulating layer include silicon oxide.

13. The organic light emitting display device according to claim 12, wherein: The light emitting structure comprises: A lower electrode, disposed on the first semiconductor element and the second semiconductor element; a light-emitting layer, disposed on the lower electrode; and The upper electrode is arranged on the light-emitting layer.

14. The organic light emitting display device according to claim 13, further comprising: a planarization layer, disposed between the protective insulating layer and the lower electrode, the planarization layer comprising an organic material, The planarization layer has a contact hole exposing an upper surface of the first drain electrode exposed through the opening of the protective insulating layer, and the lower electrode is connected to the first drain electrode through the contact hole of the planarization layer.

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