Semiconductor packages with embedded interconnects

Abstract

A semiconductor package may include a semiconductor package first side, an embedded bridge interconnect, a first through-hole, and a second through-hole. The bridge interconnect may include a first side having a conductive pad and a second side. A distance between the first side of the bridge interconnect and the first side of the semiconductor package may be smaller than a distance between the second side of the bridge interconnect and the first side of the semiconductor package. The first and second through-holes may each include a first end that is narrower than a second end. The first side of the semiconductor package may be closer to the first end of the first through-hole than to the second end of the first through-hole, and closer to the second end of the second through-hole than to the first end of the second through-hole. The first side of the semiconductor package may be configured to be electrically coupled to a die.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor packaging, and more particularly, to a semiconductor package with an embedded bridge interconnect. Background Art

[0002] An integrated circuit device may include electrical contacts that may be used to couple the device to another component. However, if substrate coplanarity is not achieved, it may be difficult to form a desired electrical connection between the device and the other component. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] In the accompanying drawings, which are not necessarily drawn to scale, like numbers may describe similar components in different views. Like numbers with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not by way of limitation.

[0004] Figure 1 Illustrated are side cross-sectional views of integrated circuit assemblies according to various embodiments.

[0005] Figure 2-19 Illustrated are side cross-sectional views of an integrated circuit assembly following various operations in its fabrication according to various embodiments.

[0006] Figure 20A and Figure 20B Illustrated is a side cross-sectional view of a semiconductor package including an electrolytic connector according to various embodiments.

[0007] Figure 21 Illustrated is a side cross-sectional view of an active bridge interconnect according to various embodiments.

[0008] Figure 22A and Figure 22B Illustrated are side cross-sectional views of a semiconductor package before and after planarizing a distorted surface according to various embodiments.

[0009] Figure 23 is a flow chart of a method for fabricating an integrated circuit assembly according to various embodiments.

[0010] Figure 24 is a block diagram of an example computing device that may include one or more of any of the semiconductor packages disclosed herein. DETAILED DESCRIPTION

[0011] As die placement tolerances tighten, thermocompression bonding is becoming more common, which introduces new challenges with respect to substrate flatness. Typically, a thermocompression bonding head places the die on the substrates to be bonded together, attaching the substrates to a pedestal by pulling an applied vacuum on the backside of the substrates. While the vacuum pulls the substrates flat on the "bottom" side, "top" substrate coplanarity is inherent to substrate thickness variations. Coplanarity of the "top" substrate beneath the vacuum pedestal is critical to the success of the thermocompression bonding process. However, due to inherent substrate manufacturing variations associated with the organic lamination process, meeting substrate coplanarity requirements can be quite challenging.

[0012] Conventionally, methods for reducing substrate thickness variation focus on optimizing copper metal density, copper plating, and the buildup lamination process. However, these conventional methods cannot completely solve the coplanarity problem because there will always be some inherent variation on the "top" and "bottom" sides of the substrate, resulting from the copper plating process, the buildup material lamination process, solder resist material variations, core variations, and pattern plating material variations. For flip-chip structures, it may be almost impossible to provide a line-end substrate with little or no variation (i.e., good top coplanarity) as may be required in certain applications. In addition, conventional methods may significantly reduce substrate design flexibility and potentially increase substrate manufacturing costs for specialized copper and buildup lamination processes.

[0013] Various embodiments disclosed herein include methods for the manufacture of semiconductor packages and integrated circuit assemblies that use coreless processing techniques to produce components with very good top coplanarity (e.g., with very little or almost zero variation). This top coplanarity can enable the use of thermocompression bonding during die attach, even at extremely fine feature spacing (e.g., sub-100 micron bump pitch).

[0014] In some embodiments, the semiconductor packages disclosed herein can use the surface of the first buildup layer laminated onto a strippable sacrificial core as a "C4" or flip-chip connection side. An interconnect (e.g., a silicon bridge interconnect) can be embedded in a cavity (e.g., formed by a laser or photolithography process after the formation of the first or second metal layers), and the cavity can be filled with a buildup resin or other material between the interconnect and the cavity. By using the surface of the first buildup layer as the C4 side, the C4 side will be as flat as the surface profile of the strippable sacrificial core. The flat C4 surface enables the formation of fine microvias on subsequent buildups, which may be necessary for the fine bump pitch (e.g., a bump pitch of less than 55 microns) used in embedded interconnect devices.

[0015] Once the package is detached from the sacrificial core, it is at risk of deformation (e.g., due to residual stresses caused by thermal expansion coefficient mismatch and shrinkage imbalances during the build-up curing and copper aging processes). Planarizing the device (using, for example, mechanical and / or vacuum forces, as described below) can prevent warping / deformation of the "top" surface, or alternatively, re-planarize the "top" surface after warping / deformation. Presenting a substantially coplanar surface to the die to which the semiconductor package is to be attached can improve the connection between the semiconductor package and the die during the thermocompression bonding process.

[0016] Additionally, some embodiments can include constructing a first through-hole from a first side of the semiconductor package and constructing a second through-hole from a second side of the semiconductor package. Furthermore, at least some of the described embodiments provide significant design and substrate manufacturing flexibility. In at least one embodiment, infringement can be detected by taking a cross-section of a coreless device with embedded components, which cross-section can show, for example, a first set of through-holes inverted relative to a second set of through-holes. In at least one embodiment, the cross-section can show the narrower side of the first set of through-holes facing the "top" of the device and the narrower side of the second set of through-holes facing the "bottom" of the device.

[0017] Figure 1 A side cross-sectional view of an integrated circuit assembly 100 according to various embodiments is illustrated. The integrated circuit assembly 100 may include a semiconductor package 102 and a die 104. In at least one embodiment, the integrated circuit assembly 100 may include a plurality of dies 104 coupled to the semiconductor package 102. The semiconductor package 102 may include embedded interconnects 106 (e.g., bridge interconnects, active die, or passive die). In the illustrated embodiment, the semiconductor package 102 includes two embedded bridge interconnects 106, but in other embodiments, the semiconductor package 102 may include any number of embedded interconnects 106.

[0018] The semiconductor package 102 may include a semiconductor package first side 108 and a semiconductor package second side 110 opposite the semiconductor package first side 108. The semiconductor package 102 may include first through-vias 112. Each first through-via 112 may include a first end 114 that is narrower than a second end 116 of the first through-via 112. In some embodiments, a distance between the first end 114 (the narrower end) of the first through-via 112 and the semiconductor package first side 108 may be smaller than a distance between the second end 116 (the wider end) of the first through-via 112 and the semiconductor package first side 108. For example, in the illustrated embodiment, the narrower end (the first end 114) of the first through-via 112 faces "upward," while the wider end (the second end 116) of the first through-via 112 faces "downward."

[0019] The semiconductor package 102 may further include second through-vias 118. Each second through-via 118 may include a first end 120 that is narrower than a second end 122 of the second through-via 118. In some embodiments, the distance between the second end 122 (the wider end) of the second through-via 118 and the semiconductor package first side 108 may be smaller than the distance between the first end 120 (the narrower end) of the second through-via 118 and the semiconductor package first side 108. For example, in the illustrated embodiment, the wider end (the second end 122) of the second through-via 118 faces "up," while the narrower end (the first end 120) of the second through-via 118 faces "down." In some embodiments, the first through-via 112 and the second through-via 114 may include copper.

[0020] Integrated circuit assembly 100 may further include an electrolytic connector 124 that electrically couples semiconductor package 102 to die 104. In the illustrated embodiment, electrolytic connector 124 includes copper pillars 126 and solder bumps 128. In at least one embodiment, die 104 is electrically coupled to embedded bridge interconnect 106 via second vias 118 and the electrolytic connector. In at least one embodiment, at least a portion of semiconductor package first side 108 has a profile that is complementary to a surface profile of the sacrificial core.

[0021] Figure 2-19 Illustrated are side cross-sectional views of semiconductor packages, such as semiconductor package 102 , and integrated circuit assemblies, such as integrated circuit assembly 100 , following various operations in the fabrication of the assemblies, in accordance with various embodiments. Figure 2An assembly 200 is illustrated, which may include a sacrificial core 202 and a metal plating 204 formed on the sacrificial core 202. The sacrificial core 202 may include a body material 206 disposed between foils 208. In some embodiments, the foils 208 may include an inner foil layer 210, an outer foil layer 212, and an adhesive layer 214 disposed between the inner and outer foil layers 210, 212. In at least one embodiment, the inner and outer foil layers 210, 212 may include copper foil. The adhesive layer 214 may temporarily bond the inner foil layer 210 to the outer foil layer 212. In at least one embodiment, the adhesive layer 214 may act as a release layer, allowing the inner and outer foil layers 210, 212 to be "peeled" apart. When the outer foil layer 212 is peeled away from the inner foil layer 210, the sacrificial core 202 may be released or "sacrificed." In at least one embodiment, the sacrificial core 202 may include a peelable sacrificial core 202. In the illustrated embodiment, assembly 200 includes two foils 208 disposed on opposite sides of a bulk material 206. While the illustrated embodiment is described with respect to a sacrificial core 202, in some embodiments, other components may be used in place of sacrificial core 202, such as a reusable carrier (e.g., stainless steel with a mechanical release layer) or a glass carrier (e.g., with a laser or mechanical release layer). In at least one embodiment of a laser release scheme, the buildup may be deposited on only one side of the panel. In at least one embodiment, an electroless copper layer or a sputtered Ti, Cr, or Ni and Cu seed layer may be deposited, followed by electrolytic plating using the deposited seed layer to form a thicker copper layer.

[0022] In at least one embodiment, the metal plating 204 may be formed on the outer foil layer 212. In at least one embodiment, the metal plating 204 may be formed on the surface 240 of the sacrificial core 202. The metal plating 204 may include a first layer 216 and a second layer 218, wherein the first layer 216 is formed on the second layer 218. In at least one embodiment, the first layer may include copper. In at least one embodiment, the second layer 218 may include nickel. In some embodiments, the metal plating 204 may include a third layer 220, wherein the second layer 218 is formed on the third layer 220, and the first layer 216 is formed on the second layer 218. In at least one embodiment, the third layer 220 may include copper. In some embodiments, the metal plating 204 may include a fourth layer 222, wherein the fourth layer 222 is formed on the third layer 220, the second layer 218 is formed on the fourth layer 222, and the first layer 216 is formed on the second layer 218. In at least one embodiment, the third layer 220 may include copper, and the fourth layer 222 may include gold. In the illustrated embodiment, the metallization 204 formed on each outer foil layer 212 is formed as a mirror image so that two identical semiconductor packages can be manufactured on the same sacrificial core 202. For ease of illustration, not all instances of the various structures will be labeled, but representative features will be labeled to indicate the same features.

[0023] Figure 3 The assembly 300 is shown after providing a build-up material 302 deposited on a first side 304 and a second side 306 of the assembly 300. In at least one embodiment, the build-up material 302 can be deposited directly on the sacrificial core 202. In some embodiments, the build-up material 302 includes a first build-up layer. In some embodiments, the build-up material 302 covers the metal plating 204.

[0024] Figure 4 The assembly 400 is shown after forming a first set 402 of first through-holes 112 by building up the material 302. The first through-holes 112 may include a first end 114 that is narrower than a second end 116. In at least one embodiment, one or more of the first through-holes 112 may be formed on the metallization 204. In at least one embodiment, one or more of the first through-holes 112 of the first set 402 include micro-vias. The assembly 400 may be formed from the assembly 300 using, for example, micro-via fabrication techniques, dry film resist techniques, patterned plating techniques, combinations thereof, and the like.

[0025] Figure 5Assembly 500 is illustrated after providing additional buildup material 302 and forming a second set 502 of first vias 112 from the additional buildup material 302. First vias 112 may include a first end 114 that is narrower than a second end 116. In at least one embodiment, one or more of second set 502 of first vias 112 may be formed on first set 402 of first vias. In some embodiments, first end 114 (the narrower end) of second set 502 of first vias 112 is coupled to second end 116 (the wider end) of first set 402 of first vias 112. In at least one embodiment, one or more of first vias 112 of second set 502 comprise microvias. Assembly 500 may be formed from assembly 400 using, for example, microvia fabrication techniques, dry film resist techniques, patterned plating techniques, combinations thereof, or the like.

[0026] Figure 6 The assembly 600 is illustrated subsequent to providing additional build-up material 302 over the second set 502 of first through-holes 112 . Figure 7 The assembly 700 is illustrated after forming a cavity 702 in the buildup material 302. In at least one embodiment, the cavity 702 is formed down to the outer foil level 212 of the foil 208 of the sacrificial core 202. While the illustrated embodiment includes first and second sets 402, 502 of first through-holes 112, other embodiments may include a different number of sets of first through-holes 112 and a different number of layers of the buildup material 302. The cavity 702 may be formed by laser post-processing all of the buildup layers by laser ablation (e.g., Figure 7 ) or a photolithography process using photo-imaging dielectric materials. In at least one embodiment, a cavity 702 can be created at each layer. In at least one embodiment, the cavity 702 can be created using a ga dry etching process with the aid of a mask.

[0027] Figure 8 Pictured Figure 7 A replacement assembly 800 for assembly 700 is provided. Figure 8 The assembly 800 is illustrated subsequent to providing an additional layer of build-up material 302 over the second set 502 of first through-vias 112 and forming cavities 802 through the build-up material and between the various first through-vias 112 .

[0028] Figure 9The assembly 900 formed from the assembly 700 is illustrated following the placement of a bridge (or passive or active die) interconnect 902 in the cavity 702. In some embodiments, the bridge interconnect 106 can include one or more conductive pads 904 on a die backside film 906 disposed at a bridge interconnect first side 908 of the bridge interconnect 106. The bridge interconnect first side 908 can contact the outer foil layer 212 of the foil 208. The bridge interconnect can include a bridge interconnect second side 910 opposite the bridge interconnect first side 908. While the illustrated embodiment includes four bridge interconnects 902, other embodiments can include any number of bridge interconnects 902.

[0029] Figure 10 Assembly 1000 is illustrated after providing additional buildup material 302 to embed bridge interconnect 106, forming a third set 1002 of first vias 112, and providing additional buildup material 302 over third set 1102 of first vias 112. Each via 112 of third set 1002 of first vias 112 may include a first end 114 that is narrower than a second end 116. In at least one embodiment, first ends 114 (the narrower ends) of first vias 112 of third set 1002 are connected to second ends 116 (the wider ends) of first vias 114 of second set 502. Assembly 1000 may also include conductive structures 1004 formed on buildup material 302 over bridge interconnect second side 910. Assembly 1000 may be formed from assembly 900 using, for example, microvia fabrication techniques, dry film resist techniques, patterned plating techniques, combinations thereof, and the like.

[0030] Figure 11 The assembly 1100 is illustrated after providing additional buildup material 302 over the conductive structure 1004 and forming a fourth set 1102 of first vias 112. Each first via 112 of the fourth set 1102 may include a first end 114 and a second end 116. One or more vias of the fourth set 1102 of first vias 112 may be connected at their first end 114 (the narrower end) to the second end 116 (the wider end) of a via in the third set 1002 of first vias 112. One or more vias of the fourth set 1102 of first vias 112 may be connected at their first end 114 (the narrower end) to the conductive structure 1004. In at least one embodiment, the assembly 900 may include a via 112 extending between the embedded interconnect 910 and the conductive structure 1004.

[0031] Figure 12 The diagram shows the direction Figure 11The assembly 1200 is shown after providing the patterned solder resist 1202 to the assembly 1100, and after providing the planarization device 1204 on the patterned solder resist 1202. In some embodiments, the planarization device 1204 can be a temporary carrier. In at least one embodiment, the planarization device 1204 can be a strippable sacrificial core. In at least one embodiment, the planarization device 1204 can be a glass carrier. In some embodiments, the planarization device 1204 can be provided to prevent panel handling from being challenging for a continuous process after depaneling. In at least one embodiment, the planarization device 1204 can prevent warping or deformation of the substrate due to residual stress accumulated in the substrate due to thermal expansion coefficient mismatch and shrinkage imbalance between the buildup layer and the copper layer during the build curing and copper aging process.

[0032] Figure 13 The assembly 1300 is shown after the body material 206 of the sacrificial core 202 has been "peeled" or otherwise removed from the assembly 1200. In at least one embodiment, the assembly 1300 can be formed from the assembly 1200 using a depaneling technique. In at least one embodiment, the depaneling process results in two assemblies, each of which is built on the outer foil layer 212 in a mirror-image formation. For ease of illustration, the remaining figures will only illustrate one of the resulting assemblies, but each manufacturing operation can be performed on each of the two assemblies in parallel, serially, or in any desired order. In at least one embodiment, the planarization device 1204 maintains the shape of the assembly 1300, preventing warping or deformation that would otherwise occur.

[0033] Figure 14 The diagram shows the succession Figure 13 Assembly 1300 after etching away outer foil layer 212. Second layer 218 of metallization 204 may also be removed. Fourth layer 222 of metallization 204 ( Figure 2 ) can also be removed. In at least one embodiment, the second layer 218 can act as an etch stop. For example, if the outer foil layer comprises copper and the second layer 218 comprises nickel, the copper etch process will remove all of the copper and stop at the nickel. If desired, in some embodiments, a subsequent nickel etch process can be used to remove the second layer 218. In at least one embodiment, the die backside film 906 can prevent the conductive pad 904 from being etched during the etch process.

[0034] Figure 15Assembly 1500 is illustrated following removal of die backside film 906 from bridge interconnect 902, and following removal (e.g., using grinding or plasma etching) of buildup material 302 between first set 402 of first vias 112, such that buildup material 302 is flush with first set 402 of first vias. In at least one embodiment, conductive pad 904 may now be exposed at bridge interconnect first side 908.

[0035] Figure 16 Assembly 1600 is illustrated after being flipped over so that buildup can begin on bridge interconnect first side 908, and after second buildup material 1602 is provided over bridge interconnect first side 908. In the flipped configuration of the illustrated embodiment, planarization device 1204 appears on the "bottom," followed by patterned solder resist 1202, fourth set 1102 of first vias, third set 1002 of first vias, second set 502 of first vias, and finally first set 402 of first vias 112, with the second buildup material on the "top." In at least one embodiment, second buildup material 1602 can comprise the same material as previous buildup material 302. In at least one embodiment, second buildup material 1602 and buildup material 302 can comprise different materials. In at least one embodiment, second buildup material 1602 can comprise a buildup laminate layer.

[0036] Figure 17 The assembly 1700 is illustrated following formation of the first set 1702 of second through-holes 118 by the second build-up material 1602, and Figure 18 Assembly 1800 is illustrated after filling first set 1702 of second vias 118 and forming patterned plating 1802. In some embodiments, each second via 118 includes a first end 120 that is narrower than a second end 122. In some embodiments, first end 120 of second via 118 can contact conductive pad 904 at bridge interconnect first side 908. In some embodiments, first end 120 of second via 118 can contact metal plating 204. In at least one embodiment, patterned plating 1802 can connect two of first set 1702 of second vias 118 together.

[0037] Figure 19 The assembly 1900 is shown after providing additional build-up material 1902 over the first set 1702 of second through-holes 118 and pattern plating 1802. In at least one embodiment, the additional build-up material 1902 comprises solder lamination. In some embodiments, the additional build-up material can be the same as the previous build-up material 302.

[0038] Figure 20A and Figure 20B Each of the diagrams illustrates the semiconductor package 102 after forming and filling a second set 2002 of second through-vias 118 in the additional build-up material 1902. Each of the second through-vias 118 of the second set may include a first end 120 that is narrower than a second end 122. In at least one embodiment, the first ends 120 (the narrower ends) of the second through-vias 112 of the second set 2002 may contact the second ends 122 (the wider ends) of the second through-vias 112 of the first set 1702. The semiconductor package 102 may include a semiconductor package first side 108 and a semiconductor package second side 110 opposite the semiconductor package first side 108. Figure 20A and Figure 20B In the illustrated embodiment, semiconductor package first side 108 appears as a “top” side, and semiconductor package second side 110 appears as a “bottom” side.

[0039] The embedded bridge interconnect 106 may be positioned within the semiconductor package 102 such that a distance between the bridge interconnect first side 908 and the semiconductor package first side 108 is less than a distance between the bridge interconnect second side 910 and the semiconductor package first side 108. Each first through-via 112 may be positioned within the semiconductor package 102 such that a distance between a first end 114 of the first through-via 112 and the semiconductor package first side 108 is less than a distance between a second end 114 of the first through-via 112 and the semiconductor package first side 108. Each second through-via 118 may be positioned within the semiconductor package 102 such that a distance between a second end 122 of the second through-via 118 and the semiconductor package first side 108 is less than a distance between a first end 120 of the second through-via 118 and the semiconductor package first side 108. For example, in Figure 20A and Figure 20B In the illustrated embodiment, first side 114 (the narrower side) of first through-hole 112 faces toward semiconductor package first side 108 ("top"), while first side 120 (the narrower side) of second through-hole 118 faces toward semiconductor package second side 110 ("bottom"). In at least one embodiment, second through-hole 118 can allow for increased design flexibility.

[0040] The semiconductor package 102 may further include one or more electrolytic connectors 124 disposed at the semiconductor package first side 108. In some embodiments, the electrolytic connectors 124 may include copper pillars 126. The copper pillars 126 may be bonded to the die 104 via solder bumps 128. In at least one embodiment, the electrolytic connectors 124 may include copper pillars 126 and solder bumps 128. In some embodiments, the electrolytic connectors 124 may include solder bumps 2010 disposed directly on the second through-holes 118. In at least one embodiment, the electrolytic connectors 124 may include electroplated solder. After the semiconductor package 102 has been electrically coupled to the die 104, the planarization device 1204 may be removed (e.g., stripped off or otherwise removed) to allow the planarization device 1204 to be removed. Figure 20A and Figure 20B The semiconductor package 102 is converted to Figure 1 The integrated circuit assembly 100 is shown.

[0041] Figure 21 The diagram shows Figure 10 Assembly 2100 is shown at a similar stage in the manufacturing process to assembly 1000, where assembly 2100 is shown after embedding bridge interconnect 106. However, in the illustrated embodiment, in addition to one or more conductive pads 904 formed on bridge interconnect first side 908, bridge interconnect 106 may include one or more conductive pads 2102 formed on bridge interconnect second side 910. Bridge interconnect 106 may further include third vias 2104 to electrically couple conductive pads 904 on bridge interconnect first side 908 to conductive pads 2102 on bridge interconnect second side 910. In some embodiments, third vias 2104 may include through-silicon vias (TSVs). In at least one embodiment, TSVs 2104 may allow bridge interconnect 106 to include an active bridge interconnect. In at least one embodiment, TSVs 2104 may allow bridge connection 902 to receive power from semiconductor package first side 108 by electrically coupling a power source to electrolytic connector 124. In at least one embodiment, die 104 may include a power source. In some embodiments, through silicon vias allow for increased design flexibility.

[0042] Figure 22A and Figure 22BThe side cross-sectional views of a semiconductor package 2202 are shown before and after planarizing a distorted surface 2200 of the semiconductor package 2202. The semiconductor package 2202 may have components 2206 disposed thereon. In at least one embodiment, the components 2206 may include electrolytic connectors, contacts, pads, combinations thereof, etc. In some embodiments, the components 2206 may have been formed on the surface 2200 such that a surface 2208 of each component 2206 is planar when the surface 2200 is planar, but the distortion of the semiconductor package 2202 may cause the component surfaces 2208 to be out of plane. Figure 22B Surface 2200 is shown after it has been "planarized" using planarization device 2210. In at least one embodiment, planarization device 2210 is deployed preemptively to prevent surface 2200 from being flattened. Figure 22A In at least one embodiment, the planarization device 2210 may include a temporary carrier. In some embodiments, the planarization device 2210 may include a sacrificial core or a glass carrier. In at least one embodiment, the planarization device 2210 may include a vacuum fixture. In at least one embodiment, the planarization device 2210 may include a plurality of planarization device components 2212. In various embodiments, the plurality of planarization device components may be positionable in different locations relative to the semiconductor package 2202.

[0043] In at least one embodiment, the planarization device may include a vacuum clamp 2210 comprising a plurality of vacuum clamp components 2212. In at least one embodiment, a first vacuum clamp component 2212 may be attached to a semiconductor package first side 2220 to pull the surface 2200 flat, and then a second clamp component 2212 may be attached to a semiconductor package second side 2222 to hold the semiconductor package 2202 in a flat position. Before attaching a die to the semiconductor package first side 2220, the first vacuum clamp component 2212 may be removed from the semiconductor package first side 2220, while the second vacuum clamp component 2212 holds the semiconductor package 2202 flat from the semiconductor package second side 2222. In at least one embodiment, the vacuum clamp 2210 may be used preemptively to prevent deformation or distortion of the semiconductor package 2202.

[0044] Figure 23 is a method for manufacturing an integrated circuit assembly (e.g., Figure 1 Flowchart of method 2300 of integrated circuit assembly 100). Figure 1-2 2. Characterization method 2300.

[0045] At block 2302, a buildup material 302 may be provided on the sacrificial core 202. In at least one embodiment, the buildup material 302 may be formed on the surface 240 of the sacrificial core 202 (eg, the surface 240 of the outer foil layer 212).

[0046] At block 2304, a cavity 802 may be formed in the buildup material 302. In at least one embodiment, the cavity 802 may be sized and shaped to accommodate the bridge interconnect 106. The cavity 802 may be formed using any of a variety of methods, such as laser, photolithography, wet etching, dry etching, combinations thereof, and the like. In at least one embodiment, the cavity 802 may be formed in the buildup material 302 down to the surface 240 of the sacrificial core 202.

[0047] At block 2306, the bridge interconnect 106 may be disposed in the cavity 802. In some embodiments, the bridge interconnect 106 may be passive, having one or more conductive pads 904 at a bridge interconnect first side 908. In at least one embodiment, the bridge interconnect 106 may be active, having conductive pads 904 at the bridge interconnect first side 908, conductive pads 2102 at a bridge interconnect second side 2102, and through silicon vias 2104 connecting the first set of conductive pads 904 to the second set of conductive pads 2102.

[0048] At block 2308, the bridge interconnect 106 may be embedded within the assembly 1000. In at least one embodiment, additional build-up material 302 may be deposited over the bridge interconnect 106 to embed the bridge interconnect 106 within the build-up material 302 formed at the surface 240 of the sacrificial core 202. In at least one embodiment, the distance between the bridge interconnect first side 908 and the surface 240 may be less than the distance between the bridge interconnect second side 910 and the surface 240.

[0049] At block 2310, first vias 112 may be formed. In at least one embodiment, one or more layers of buildup material 302 and first vias 112 may be formed prior to forming cavity 802, such that cavity 802 may be formed between first vias 112. For example, prior to forming cavity 802, first set 402 of first vias 112 may be formed in a first buildup material layer, and second set 502 of first vias 112 may be formed in a second buildup material layer. In other embodiments, more or fewer sets of first vias 112 may be formed prior to forming cavity 802. After forming cavity 802 and embedding bridge interconnect 106, more sets of first vias 112 may be formed in the buildup material. In at least one embodiment, third set 1002 and fourth set 1102 of first vias 112 may be formed after embedding bridge interconnect 106. In at least one embodiment, first vias 112 may have first ends 114 that are narrower than second ends 116 of first vias 112. In some embodiments, the first end 114 of the first through-via 112 is closer to the surface 240 of the sacrificial core 202 than the second end 116 of the first through-via 112 is to the surface 240 of the sacrificial core 202. In some embodiments, the distance between the first end 114 of the first through-via 112 and the semiconductor package first side 108 is less than the distance between the second end 116 of the first through-via 112 and the semiconductor package first side 108. In at least one embodiment, the first end 114 of the first through-via can contact the second end 116 of the first through-via 112.

[0050] At block 2312, planarization devices 1204, 2210 may be attached to semiconductor package 102 to maintain a flat surface on semiconductor package first side 108. In at least one embodiment, planarization devices 1204, 2210 may include a temporary carrier 1204 attached to a side of semiconductor package 102 opposite sacrificial core 202. In at least one embodiment, temporary carrier 1204 may be attached to semiconductor package second side 110. In some embodiments, the planarization device may help prevent deformation of semiconductor package 102. In at least one embodiment, the planarization device may be a second sacrificial core or a glass carrier.

[0051] At block 2314, the sacrificial core 202 can be removed, peeled apart, or sacrificed. In at least one embodiment, the foil 208 is separated such that the outer foil layer 212 is pulled away from the inner foil layer 210 at the adhesive layer 214. In some embodiments, the manufacturing steps can be performed on either side of the sacrificial core 202 such that removal of the sacrificial core results in two separate assembled devices. In at least one embodiment, the two separate assembled devices can be identical. For ease of description, we will only describe the following steps of method 2300 with respect to one of the assembled devices, although it should be understood that any and all of method 2300 can also be performed on the second assembled device.

[0052] At block 2316, additional build-up material 1602 may be provided at the bridge interconnect first side 908, and at block 2318, one or more second vias 118 may be formed through the additional build-up material 1602. In at least one embodiment, a first set 1702 of second vias 118 may be formed. In some embodiments, the second vias 118 may have first ends 120 that are narrower than second ends 122 of the second vias 118. In some embodiments, the first ends 114 of the first vias 112 and the first ends 120 of the second vias 118 face in opposite directions. In some embodiments, multiple layers of additional build-up material 1602, 1902 and the sets 1702, 2002 of second vias 118 may be formed at the first side 108 of the semiconductor package 102. In at least one embodiment, a patterned plating layer 1802 may be formed between some of the second vias 118. In at least one embodiment, the first ends 120 of the second vias 118 may contact the conductive pad 904. In at least one embodiment, first end 120 of second via 118 may contact metal plating 204. In at least one embodiment, first end 120 of second via 118 may contact second end 122 of second via 118. In some embodiments, first via 112 and second via 118 may form inverse shapes of each other.

[0053] At block 2320, an electrolytic connector 124 may be disposed at the semiconductor package first side 108 and electrically coupled to the second through-hole 118. In some embodiments, the electrolytic connector 124 may be connected to the second side 122 of the second through-hole 118. In at least one embodiment, the electrolytic connector 124 may be a solder bump 2010. In some embodiments, the electrolytic connector may be a copper pillar 126. In at least one embodiment, the copper pillar 126 may include a solder bump 128.

[0054] At block 2322, die 104 can be attached to semiconductor package 102 at electrolytic connector 124. In at least one embodiment, solder reflow can be used to electrically couple die 104 to semiconductor package 102. At block 2324, planarizing devices 1204, 2210 can be removed from semiconductor package second side 110, as the attachment to die 104 will keep semiconductor package 102 flat. In some embodiments, the result of method 2300 is a coreless embedded bridge interconnect semiconductor package 102 electrically coupled to die 104. In at least one embodiment, the result of method 2300 is an integrated circuit assembly 100. In some embodiments, due to the use of sacrificial core 202, planarizing devices 1204, 2210, combinations thereof, etc., semiconductor package first side 108 can achieve the coplanarity necessary to ensure successful coupling to die 104. In some embodiments, at least one feature 2212 of planarization device 2210 may be removed before die 104 is attached to semiconductor package 102 .

[0055] Figure 24 A system level diagram is shown according to at least one embodiment. For example, Figure 24 Depicted herein include references to Figure 1-23 Examples of electronic devices (eg, systems) in which integrated circuit assemblies are described. Figure 24 2400 is included to illustrate examples of higher-level device applications of the present invention. In one embodiment, system 2400 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet device, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular phone, a mobile computing device, a smartphone, an Internet appliance, or any other type of computing device. In some embodiments, system 2400 is a system-on-a-chip (SOC) system.

[0056] In one embodiment, processor 2410 has one or more processing cores 2412 and 2412N, where 2412N represents the Nth processor core within processor 2410, where N is a positive integer. In one embodiment, system 2400 includes multiple processors, including processors 2410 and 2405, wherein processor 2405 has logic similar to or identical to that of processor 2410. In some embodiments, processing core 2412 includes, but is not limited to, prefetch logic for fetching instructions, decode logic for decoding instructions, and execution logic for executing instructions. In some embodiments, processor 2410 has a cache memory 2416 for caching instructions and / or data for system 2400. Cache memory 2416 may be organized into a hierarchical structure including one or more levels of cache memory.

[0057] In some embodiments, processor 2410 includes a memory controller 2414 operable to perform functions enabling processor 2410 to access and communicate with memory 2430, including volatile memory 2432 and / or non-volatile memory 2434. In some embodiments, processor 2410 is coupled to memory 2430 and chipset 2420. Processor 2410 may also be coupled to wireless antenna 2490 for communication with any device configured to transmit and / or receive wireless signals. In one embodiment, wireless antenna interface 2490 operates in accordance with, but is not limited to, IEEE 2402.11 and its related families, Home Plug AV (HPAV), Ultra-Wideband (UWB), Bluetooth, WiMax, or any other form of wireless communication protocol.

[0058] In some embodiments, the volatile memory 2432 includes, but is not limited to, synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM), and / or any other type of random access memory device. The non-volatile memory 2434 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0059] Memory 2430 stores information and instructions to be executed by processor 2410. In one embodiment, memory 2430 may also store temporary variables or other intermediate information while processor 2410 is executing instructions. In the illustrated embodiment, chipset 2420 is connected to processor 2410 via point-to-point (PtP or PP) interfaces 2417 and 2422. Chipset 2420 enables processor 2410 to connect to other elements in system 2400. In some embodiments of the present invention, interfaces 2417 and 2422 are based on processors such as Intel. In other embodiments, a different interconnect may be used.

[0060] In some embodiments, the chipset 2420 is operable to communicate with the processors 2410 , 2405N, the display device 2440 , and other devices 2472 , 2476 , 2474 , 2460 , 2462 , 2464 , 2466 , 2477 , etc. The chipset 2420 may also be coupled to a wireless antenna 2490 to communicate with any device configured to transmit and / or receive wireless signals.

[0061] Chipset 2420 is connected to display device 2440 via interface 2426. Display 2440 may be, for example, a liquid crystal display (LCD), a plasma display, a cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the present invention, processor 2410 and chipset 2420 are combined into a single SOC. Furthermore, chipset 2420 is connected to one or more buses 2450 and 2455, which interconnect various components 2474, 2460, 2462, 2464, and 2466. Buses 2450 and 2455 may be interconnected via bus bridge 2472. In one embodiment, chipset 2420 is coupled to non-volatile memory 2460, mass storage device(s) 2462, keyboard / mouse 2464, and network interface 2466 via interfaces 2424 and / or 2404, smart TV 2476, consumer electronics 2477, and the like.

[0062] In one embodiment, mass storage device 2462 includes, but is not limited to, a solid-state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 2466 is implemented using any type of well-known network interface standard, including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a peripheral component interconnect (PCI) express interface, a wireless interface, and / or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, IEEE 2402.11 and its related families, Home Plug AV (HPAV), Ultra-Wideband (UWB), Bluetooth, WiMax, or any other form of wireless communication protocol.

[0063] Although Figure 24 The modules shown in FIG24 are depicted as separate blocks within system 2400, but the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 2416 is depicted as a separate block within processor 2410, cache memory 2416 (or selected aspects of 2416) may be incorporated into processor core 2412.

[0064] Example

[0065] The following examples relate to further embodiments.

[0066] Example 1 is a semiconductor package comprising: a first side of the semiconductor package; a second side of the semiconductor package opposite to the first side of the semiconductor package; an interconnect embedded in a first build-up material; a first through-hole extending through the first build-up material, the first through-hole including a first end narrower than a second end of the first through-hole, wherein a distance between the first end of the first through-hole and the first side of the semiconductor package is less than a distance between the second end of the first through-hole and the first side of the semiconductor package; and a second through-hole extending through a second build-up material, the second through-hole including a first end narrower than the second end of the second through-hole, wherein a distance between the second end of the second through-hole and the first side of the semiconductor package is less than a distance between the first end of the second through-hole and the first side of the semiconductor package.

[0067] In Example 2, the subject matter of Example 1 can optionally include wherein the first buildup material and the second buildup material comprise the same material.

[0068] In Example 3, the subject matter of any one or more of Examples 1-2 may optionally include, wherein the interconnect comprises: a first side of the interconnect having a first conductive pad; and a second side of the interconnect opposite the first side of the interconnect; wherein a distance between the first side of the interconnect and the first side of the semiconductor package is less than a distance between the second side of the interconnect and the first side of the semiconductor package; and wherein the second through-hole extends from the first conductive pad toward the first side of the semiconductor package.

[0069] In Example 4, the subject matter of any one or more of Examples 1-3 may optionally include an electrolytic connector disposed at the semiconductor package first side and electrically coupled to the second through-via.

[0070] In Example 5, the subject matter of Example 4 can optionally include wherein the electrolytic connector comprises a solder bump.

[0071] In Example 6, the subject matter of Example 5 can optionally include, wherein the electrolytic connector further comprises: a solder plating disposed at the second side of the second through-hole, wherein the solder plating is configured to form a solder bump in response to reflow.

[0072] In Example 7, the subject matter of any one or more of Examples 5-6 can optionally include, wherein the electrolytic connector further comprises: a copper pillar disposed at the second side of the second through-hole, wherein the solder bump is disposed on the copper pillar.

[0073] In Example 8, the subject matter of any one or more of Examples 1-7 may optionally include a sacrificial core disposed between the semiconductor package and the second semiconductor package.

[0074] In Example 9, the subject matter of Example 8 can optionally include wherein at least a first portion of the first side of the semiconductor package has a profile that is complementary to a surface profile of the sacrificial core.

[0075] In Example 10, the subject matter of any one or more of Examples 1-9 can optionally include, wherein the semiconductor package first side is configured to be electrically coupled to one or more dies.

[0076] In Example 11, the subject matter of any one or more of Examples 1-10 can optionally include, wherein the interconnect includes a plurality of first conductive pads positioned at a first side of the interconnect.

[0077] In Example 12, the subject matter of any one or more of Examples 1-11 can optionally include, wherein the semiconductor package includes a plurality of first through-vias.

[0078] In Example 13, the subject matter of any one or more of Examples 1-12 can optionally include, wherein the semiconductor package includes a plurality of second through-vias.

[0079] In Example 14, the subject matter of any one or more of Examples 1-13 can optionally include, wherein the interconnect comprises a silicon bridge.

[0080] In Example 15, the subject matter of any one or more of Examples 1-14 may optionally include a first conductive pad positioned at the first side of the interconnect; and a second conductive pad positioned at the second side of the interconnect.

[0081] In Example 16, the subject matter of Example 15 can optionally include a third via extending from the second conductive pad through the interconnect to the first conductive pad.

[0082] In Example 17, the subject matter of Example 16 can optionally include, wherein the third via comprises a through silicon via.

[0083] In Example 18, the subject matter of any one or more of Examples 1-17 can optionally include wherein at least a first portion of the first side of the semiconductor package has a profile that is complementary to a surface profile of the sacrificial core.

[0084] In Example 19, the subject matter of any one or more of Examples 1-18 optionally includes a copper pattern plating electrically coupled to the second via.

[0085] Example 20 is an integrated circuit assembly comprising: a first die; and a semiconductor package, the semiconductor package comprising: a first side of the semiconductor package; a second side of the semiconductor package opposite to the first side of the semiconductor package; a bridge interconnect embedded in a first build-up material, the bridge interconnect comprising a first side of the bridge interconnect having a first conductive pad and a second side of the bridge interconnect opposite to the first side of the bridge interconnect, wherein a distance between the first side of the bridge interconnect and the first side of the semiconductor package is less than a distance between the second side of the bridge interconnect and the first side of the semiconductor package; a first through-hole extending through the first build-up material, the first through-hole comprising a first end narrower than a second end of the first through-hole, wherein a distance between the first end of the first through-hole and the first side of the semiconductor package is less than a distance between the second end of the first through-hole and the first side of the semiconductor package; and a second through-hole extending through the second build-up material, the second through-hole comprising a first end narrower than the second end of the second through-hole, wherein the first end of the second through-hole is positioned at a conductive pad face at the conductive pad opposite to the first side of the bridge interconnect; wherein the first die is electrically coupled to the bridge interconnect via the second through-hole.

[0086] In Example 21, the subject matter of Example 20 optionally includes an electrolytic connector formed at the second end of the second through-via, wherein the first die is electrically coupled to the bridge interconnect at the electrolytic connector.

[0087] In Example 22, the subject matter of Example 21 can optionally include, wherein the electrolytic connector is selected from the group consisting of a solder bump and a copper pillar bump.

[0088] In Example 23, the subject matter of any one or more of Examples 20-22 may optionally include a second conductive pad positioned at the second side of the bridge interconnect; and a third via extending from the first conductive pad through the bridge interconnect to the second conductive pad.

[0089] In Example 24, the subject matter of Example 23 can optionally include, wherein the semiconductor package includes an active bridge interconnect.

[0090] In Example 25, the subject matter of any one or more of Examples 23-24 may optionally include a second die electrically coupled to the second side of the semiconductor package.

[0091] In Example 26, the subject matter of any one or more of Examples 23-25 may optionally include a power supply configured to provide power via the semiconductor package first side bridge interconnect.

[0092] Example 27 is a method for manufacturing a semiconductor package, comprising: providing an interconnect embedded in a buildup material formed on a surface of a sacrificial core, the interconnect comprising a first side of the interconnect having a conductive pad and a second side of the interconnect opposite to the first side of the interconnect, such that a distance between the first side of the interconnect and the surface is less than a distance between the second side of the interconnect and the surface; forming a first through-hole in the buildup material, wherein the first through-hole has a first end narrower than the second end of the first through-hole, and the first end is closer to the surface than the second end; removing the sacrificial core to expose the first side of the interconnect; providing additional buildup material at the first side of the interconnect; and forming a second through-hole in the buildup material arranged at the first side of the interconnect, wherein the second through-hole has a first end narrower than the second end, wherein the first end of the first through-hole and the first end of the second through-hole face opposite directions.

[0093] In Example 28, the subject matter of Example 27 optionally includes, wherein providing the interconnect embedded within the buildup material formed on the surface of the sacrificial core further comprises: providing the buildup material on the surface of the sacrificial core; forming a cavity in the buildup material down to the surface of the sacrificial core; arranging the interconnect in the cavity; and providing additional buildup material to embed the interconnect.

[0094] In Example 29, the subject matter of any one or more of Examples 27-28 optionally includes forming a patterned plating electrically coupled to the second via.

[0095] In Example 30, the subject matter of any one or more of Examples 27-29 optionally includes providing a temporary carrier on a side of the semiconductor package opposite the sacrificial core prior to removal of the sacrificial core.

[0096] In Example 31, the subject matter of any one or more of Examples 28-30 optionally includes removing the temporary carrier after electrically coupling the die to the interconnect first side via the second via.

[0097] In Example 32, the subject matter of any one or more of Examples 27-31 optionally includes, wherein forming the first through hole and the second through hole further includes: forming the first through hole such that a distance between a first end of the first through hole and a first side of the semiconductor is less than a distance between a second side of the first through hole and a first side of the semiconductor package; and forming the second through hole such that a distance between a first side of the second through hole and a first side of the semiconductor package is greater than a distance between a second side of the second through hole and the first side of the semiconductor package.

[0098] In Example 33, the subject matter of Example 32 can optionally include, wherein a distance between the interconnect first side and the semiconductor package first side is less than a distance between the interconnect second side and the semiconductor package first side.

[0099] Example 34 is a method of manufacturing an integrated circuit assembly, comprising: providing a semiconductor package, the semiconductor package comprising: a semiconductor package first side; a semiconductor package second side; a bridge interconnect embedded in a build-up material, the bridge interconnect comprising a bridge interconnect first side comprising a conductive pad and a bridge interconnect second side opposite the bridge interconnect first side, wherein a distance between the bridge interconnect first side and a first side of the semiconductor package is less than a distance between the bridge interconnect second side and the first side of the semiconductor package; a first through-hole extending through a portion of the build-up material, the first through-hole comprising a first end narrower than a second end of the first through-hole, wherein the first end of the first through-hole is adjacent to the semiconductor package; a planarizing device to attach a planarizing device to the semiconductor package to maintain the first side of the semiconductor package planar; providing additional build-up material at the first side of the bridge interconnect; forming a second through-hole extending through the additional build-up material, the second through-hole including a first end narrower than the second end of the second through-hole, wherein the distance between the second end of the second through-hole and the first side of the semiconductor package is less than the distance between the first end of the second through-hole and the first side of the semiconductor package; and attaching the die to the first side of the semiconductor package while the planarizing device maintains the first side of the semiconductor package planar.

[0100] In Example 35, the subject matter of Example 34 can optionally include, wherein attaching the planarization device to the semiconductor package includes attaching a temporary carrier to the semiconductor package second side before forming the second through-via.

[0101] In Example 36, the subject matter of Example 35 can optionally include, wherein the temporary carrier is selected from the group consisting of a sacrificial core and a glass carrier.

[0102] In Example 37, the subject matter of any one or more of Examples 34-36 can optionally include, wherein attaching the planarization device to the semiconductor package includes attaching a vacuum chuck to the semiconductor package.

[0103] In Example 38, the subject matter of Example 37 optionally includes, wherein attaching the planarization device to the semiconductor package comprises: attaching a first vacuum clamp assembly to the first side of the semiconductor package; attaching a second vacuum clamp assembly to the second side of the semiconductor package; and removing the first vacuum clamp assembly from the first side of the semiconductor package before attaching the die to the first side of the semiconductor package.

[0104] In Example 39, the subject matter of any one or more of Examples 34-38 may optionally include, wherein attaching the die to the semiconductor package first side includes performing a thermocompression bonding process.

[0105] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The accompanying drawings illustrate specific embodiments that can be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, examples that include the elements shown or described are also contemplated. Furthermore, examples using any combination or permutation of the elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein are also contemplated.

[0106] The publications, patents, and patent documents mentioned in this document are incorporated herein by reference in their entirety, as if individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) supplements that of this document; for irreconcilable inconsistencies, the usage in this document controls.

[0107] In this document, the terms "a" or "an" are used to include one or more than one, as is common in patent documents, independent of any other instance or usage of "at least one" or "one or more." In this document, unless otherwise indicated, the term "or" is used to refer to a non-exclusive "or" such that "A or B" includes "A but not B," "B but not A," and "A and B." In the appended claims, the terms "including" and "in which" are used as the plain English equivalents of the respective terms "comprising" and "wherein." Furthermore, in the claims that follow, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles, or processes that include elements in addition to those listed after such terms in the claim are still considered to fall within the scope of the claim. Furthermore, in the claims that follow, the terms "first," "second," and "third," etc., are used merely as labels and are not intended to imply a numerical order of their objects.

[0108] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with other examples. Other embodiments may be used, such as would be used by one of ordinary skill in the art upon reviewing the above description. The Abstract is intended to allow the reader to quickly ascertain the nature of the technical disclosure and is submitted with the understanding that the Abstract will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the above Detailed Description, various features may be grouped together to simplify the disclosure. However, the claims may not recite the features disclosed herein, as embodiments may include a subset of the features described. Furthermore, embodiments may include fewer features than those disclosed in a specific example. Therefore, the following claims are hereby incorporated into the Detailed Description, with the claims standing on their own as separate embodiments. The scope of the embodiments disclosed herein is to be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A semiconductor package, comprising: a semiconductor package first side, wherein at least a first portion of the semiconductor package first side has a profile that is complementary to a surface profile of the sacrificial core; a second side of the semiconductor package opposite the first side of the semiconductor package; interconnects embedded in the first buildup material; a first through-hole extending through the first build-up material, the first through-hole including a first end that is narrower than a second end of the first through-hole, wherein a distance between the first end of the first through-hole and a first side of the semiconductor package is less than a distance between the second end of the first through-hole and the first side of the semiconductor package, wherein the first through-hole is formed before removing the sacrificial core; and A second through-hole extends through the second build-up material, the second through-hole including a first end narrower than a second end of the second through-hole, wherein a distance between the second end of the second through-hole and the first side of the semiconductor package is less than a distance between the first end of the second through-hole and the first side of the semiconductor package, wherein the second through-hole is formed after removing the sacrificial core. 2 . The semiconductor package according to claim 1 , wherein the first build-up material and the second build-up material comprise the same material.

3. The semiconductor package according to claim 1 , wherein the interconnection comprises: an interconnect first side having a first conductive pad; and a second side of the interconnect opposite the first side of the interconnect; wherein a distance between the first side of the interconnect and the first side of the semiconductor package is less than a distance between the second side of the interconnect and the first side of the semiconductor package; The second through hole extends from the first conductive pad toward the first side of the semiconductor package.

4. The semiconductor package according to claim 1 , further comprising: An electrolytic connector is disposed at the first side of the semiconductor package and electrically coupled to the second through-hole. The semiconductor package of claim 4 , wherein the electrolytic connector comprises a solder bump.

6. The semiconductor package according to claim 5, wherein the electrolytic connector further comprises: A solder plating layer is disposed at the second side of the second through-hole, wherein the solder plating layer is configured to form a solder bump in response to reflow.

7. The semiconductor package according to claim 5, wherein the electrolytic connector further comprises: A copper pillar is disposed at a second side of the second through-hole, wherein the solder bump is disposed on the copper pillar. 8 . The semiconductor package of claim 1 , wherein the first side of the semiconductor package is configured to be electrically coupled to one or more dies.

9. The semiconductor package according to claim 1, further comprising: a first conductive pad positioned at a first side of the interconnect; and A second conductive pad is positioned at the second side of the interconnect.

10. The semiconductor package according to claim 9, further comprising: A third via extends from the second conductive pad through the interconnect to the first conductive pad. The semiconductor package according to claim 10 , wherein the third through-via comprises a through-silicon via.

12. The semiconductor package according to claim 1, further comprising: A copper pattern plating is provided in electrical communication with the second through hole.

13. An integrated circuit assembly comprising: a first tube core; and A semiconductor package, comprising: a semiconductor package first side, wherein at least a first portion of the semiconductor package first side has a profile that is complementary to a surface profile of the sacrificial core; a second side of the semiconductor package opposite the first side of the semiconductor package; a bridge interconnect embedded in the first build-up material, the bridge interconnect comprising a bridge interconnect first side having a first conductive pad and a bridge interconnect second side opposite the bridge interconnect first side, wherein a distance between the bridge interconnect first side and the first side of the semiconductor package is smaller than a distance between the bridge interconnect second side and the first side of the semiconductor package; a first through-hole extending through the first build-up material, the first through-hole including a first end that is narrower than a second end of the first through-hole, wherein a distance between the first end of the first through-hole and a first side of the semiconductor package is less than a distance between the second end of the first through-hole and the first side of the semiconductor package, wherein the first through-hole is formed before removing the sacrificial core; and a second via extending through the second build-up material, the second via including a first end narrower than a second end of the second via, wherein the first end of the second via is positioned at a side of the conductive pad opposite the first side of the bridge interconnect, wherein the second via is formed after removing the sacrificial core; Wherein the first die is electrically coupled to the bridge interconnect via a second via.

14. The integrated circuit assembly of claim 13, further comprising: An electrolytic connector is formed at the second end of the second through-hole, wherein the first die is electrically coupled to the bridge interconnect at the electrolytic connector.

15. The integrated circuit assembly of claim 14, wherein the electrolytic connector is selected from the group consisting of a solder bump and a copper pillar bump.

16. The integrated circuit assembly of claim 13, further comprising: a second conductive pad positioned at a second side of the bridge interconnect; and A third via extends from the first conductive pad through the bridge interconnect to the second conductive pad.

17. The integrated circuit assembly of claim 16, wherein the semiconductor package includes an active bridge interconnect.

18. The integrated circuit assembly of claim 16, further comprising: A second die is electrically coupled to the second side of the semiconductor package.

19. A method for manufacturing a semiconductor package, comprising: providing an interconnect embedded in a buildup material formed on a surface of a sacrificial core, the interconnect comprising a first side of the interconnect having a conductive pad and a second side of the interconnect opposite the first side of the interconnect such that a distance between the first side of the interconnect and the surface is less than a distance between the second side of the interconnect and the surface; forming a first through-hole in the buildup material, wherein the first through-hole has a first end that is narrower than a second end of the first through-hole, and the first end is closer to the surface than the second end; providing a temporary carrier on a side of the semiconductor package opposite the sacrificial core prior to removal of the sacrificial core; removing the sacrificial core to expose the interconnect first side; providing additional buildup material at the interconnect first side; as well as A second via is formed in the buildup material disposed at the first side of the interconnect, wherein the second via has a first end narrower than a second end, wherein the first end of the first via and the first end of the second via face in opposite directions.

20. The method of claim 19, wherein providing interconnects embedded within a buildup material formed on a surface of the sacrificial core further comprises: providing a buildup material on a surface of the sacrificial core; forming a cavity in the buildup material down to the surface of the sacrificial core; arranging the interconnect in the cavity; as well as Additional build-up material is provided to embed the interconnects.

21. The method of claim 19, wherein forming the first through-hole and the second through-hole further comprises: forming the first through hole so that a distance between a first end of the first through hole and the first side of the semiconductor package is smaller than a distance between a second side of the first through hole and the first side of the semiconductor package; as well as The second through hole is formed such that a distance between a first side of the second through hole and the first side of the semiconductor package is greater than a distance between a second side of the second through hole and the first side of the semiconductor package.

22. A method of manufacturing an integrated circuit assembly, comprising: A semiconductor package is provided, comprising: a first side of a semiconductor package; a second side of the semiconductor package; a bridge interconnect embedded in the build-up material, the bridge interconnect comprising a bridge interconnect first side including the conductive pad and a bridge interconnect second side opposite the bridge interconnect first side, wherein a distance between the bridge interconnect first side and a first side of the semiconductor package is less than a distance between the bridge interconnect second side and the first side of the semiconductor package; a first through-hole extending through a portion of the build-up material, the first through-hole including a first end that is narrower than a second end of the first through-hole, wherein a distance between the first end of the first through-hole and a first side of the semiconductor package is less than a distance between the second end of the first through-hole and the first side of the semiconductor package; Before forming the second through hole, attaching a planarizing device to the semiconductor package to keep the first side of the semiconductor package planar, wherein attaching the planarizing device to the semiconductor package comprises: attaching a temporary carrier to the second side of the semiconductor package; providing additional buildup material at the bridge interconnect first side; forming a second through-hole extending through the additional build-up material, the second through-hole including a first end narrower than a second end of the second through-hole, wherein a distance between the second end of the second through-hole and the first side of the semiconductor package is less than a distance between the first end of the second through-hole and the first side of the semiconductor package; and A die is attached to the first side of the semiconductor package while the planarizing device maintains the first side of the semiconductor package planar.

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