First boot with one memory channel

Abstract

An embodiment of a semiconductor packaging device may include techniques to identify a partial set of populated memory channels from a complete set of populated memory channels of a multi-channel memory system, and to complete a first boot of an operating system using only the identified partial set of memory channels of the multi-channel memory system. Other embodiments are disclosed and claimed.

Description

Technical Field

[0001] Embodiments generally relate to memory systems. More specifically, embodiments relate to a first boot with one memory channel. Background Art

[0002] In some memory systems, training is performed shortly after powering on the system. The training may include setting up and calibration to get various input / output (I / O) interfaces ready to receive commands. For example, higher double data rate (DDR) speeds may require the dynamic random access memory (DRAM) channels to be tuned to achieve improved or optimal signal quality and DDR bus timing. This tuning is performed by the basic input / output system (BIOS) during boot and may be referred to as DDR training. Brief Description of the Drawings

[0003] By reading the following description and the appended claims, and by referring to the following drawings, various advantages of the embodiments will become apparent to those of ordinary skill in the art, in which:

[0004] Figure 1 is a block diagram of an example of an electronic processing system according to an embodiment;

[0005] Figure 2 is a block diagram of an example of a semiconductor package device according to an embodiment;

[0006] Figures 3A to 3B is a flowchart of an example of a method for booting an operating system according to an embodiment;

[0007] Figures 4 to 6 is an illustrative block diagram of an example of a multi-channel memory system according to an embodiment;

[0008] Figure 7 is a flowchart of another example of a method for booting an operating system according to an embodiment;

[0009] Figure 8A and 8B is a block diagram of an example of a memory trainer device according to an embodiment;

[0010] Figure 9 is a block diagram of an example of a processor according to an embodiment; and

[0011] Figure 10 is a block diagram of an example of a system according to an embodiment. Detailed Description

[0012] Now turning to Figure 1, an embodiment of the electronic processing system 10 may include a processor 11, a multi-channel memory system 12 communicatively coupled to the processor 11, and a logic 13 communicatively coupled to the processor 11. The logic 13 identifies a partial set of the populated memory channels from a complete set of the populated memory channels of the multi-channel memory system 12, and completes a first boot of the operating system using only the identified partial set of the memory channels of the multi-channel memory system 12. For example, the multi-channel memory system may include N memory channels C1 to C N , where N is greater than 1. One or more of the memory channels C1 to C N may be populated with one or more memory devices or components. In some embodiments, the logic 13 may be configured to identify one memory channel (e.g., a single memory channel populated with one or more memory devices) for the partial set of the populated memory channels. For example, the logic 13 may be configured to identify the first populated memory channel of the multi-channel memory system 12 as the one memory channel. In another example, the logic 13 may be configured to identify the first populated memory channel of the multi-channel memory system 12 having fewer memory components than a threshold as the one memory channel. In another example, the logic 13 may be configured to identify the least populated memory channel of the multi-channel memory system as the one memory channel. In some embodiments, the logic 13 may also be configured to bring other populated memory channels of the complete set of the populated memory channels online after the first boot is completed.

[0013] Embodiments of each of the above processor 11, multi-channel memory system 12, logic 13, and other system components may be implemented in hardware, software, or any suitable combination thereof. For example, a hardware implementation may include configurable logic, such as a programmable logic array (PLA), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or fixed function logic hardware using circuit technologies such as application specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS), or transistor-transistor logic (TTL) technology, or any combination of these.

[0014] Alternatively or additionally, all or some parts of these components may be implemented in one or more modules as a set of logical instructions stored in a machine or computer-readable storage medium for execution by a processor or computing device, such as a random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc. For example, computer program code for performing the operations of the components may be written in any combination of one or more operating system (OS)-applicable / suitable programming languages, including object-oriented programming languages such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc., and also including traditional procedural programming languages such as the "C" programming language or similar programming languages. For example, the multi-channel memory system 12, persistent storage medium, or other system memory may store a set of instructions that, when executed by the processor 11, cause the system 10 to implement one or more components, features, or aspects of the system 10 (e.g., logic 13, identifying a partial set of populated memory channels from the complete set of populated memory channels of the multi-channel memory system 12 and completing a first boot of the operating system using only the identified partial set of memory channels of the multi-channel memory system 12, etc.).

[0015] Now turning to Figure 2 , an embodiment of the semiconductor packaging device 20 may include a substrate 21 and logic 22 coupled to the substrate 21, where the logic 22 is at least partially implemented in one or more of configurable logic and fixed-function hardware logic. The logic 22 coupled to the substrate 21 may be configured to identify a partial set of populated memory channels from the complete set of populated memory channels of a multi-channel memory system and complete a first boot of the operating system using only the identified partial set of memory channels of the multi-channel memory system. In some embodiments, the logic 22 may be configured to identify one memory channel (e.g., a single memory channel populated with one or more memory devices) for the partial set of populated memory channels. For example, the logic 22 may be configured to identify the first populated memory channel of the multi-channel memory system as the one memory channel. In another example, the logic 22 may be configured to identify the first populated memory channel of the multi-channel memory system having fewer memory components than a threshold as the one memory channel. In another example, the logic 22 may be configured to identify the least populated memory channel of the multi-channel memory system as the one memory channel. In some embodiments, the logic 22 may also be configured to bring other populated memory channels of the complete set of populated memory channels online after the first boot is completed.

[0016] Embodiments of logic 22 and other components of apparatus 20 may be implemented in hardware, software, or any combination thereof, including at least partial implementation in hardware. For example, a hardware implementation may include configurable logic such as a PLA, FPGA, CPLD, or fixed function logic hardware using circuit technologies such as ASIC, CMOS, or TTL technology, or any combination of these. Additionally, some portions of these components may be implemented in one or more modules as a set of logic instructions stored in a machine or computer-readable storage medium for execution by a processor or computing device, such as RAM, ROM, PROM, firmware, flash memory, and the like. For example, computer program code for performing the operations of the components may be written in any combination of one or more OS-applicable / suitable programming languages, including object-oriented programming languages such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc., and also including traditional procedural programming languages such as the "C" programming language or similar programming languages.

[0017] Now turning to Figures 3A to 3B , embodiments of method 30 for booting an operating system may include, at block 31, identifying a partial set of populated memory channels from a complete set of populated memory channels of a multi-channel memory system, and at block 32, completing a first boot of the operating system using only the identified partial set of memory channels of the multi-channel memory system. Some embodiments of method 30 may include, at block 33, identifying one memory channel for the partial set of populated memory channels. For example, method 30 may include, at block 34, identifying a first populated memory channel of the multi-channel memory system as the one memory channel. In another example, method 30 may include, at block 35, identifying a first populated memory channel of the multi-channel memory system having fewer memory components than a threshold as the one memory channel. In another example, method 30 may include, at block 36, identifying the least populated memory channel of the multi-channel memory system as the one memory channel. Some embodiments of method 30 may further include, at block 37, bringing other populated memory channels of the complete set of populated memory channels online after the first boot is completed.

[0018] Embodiments of method 30 may be implemented in a system, apparatus, computer, device, etc. (such as those described herein). More specifically, a hardware implementation of method 30 may include configurable logic, such as a PLA, FPGA, CPLD, or may be implemented in fixed-function logic hardware using circuit technologies such as ASIC, CMOS, or TTL technology, or any combination thereof. Alternatively or additionally, method 30 may be implemented in one or more modules as a set of logical instructions stored on a machine or computer-readable storage medium for execution by a processor or computing device, the machine or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc. For example, computer program code for performing the operations of the components may be written in any combination of one or more OS-applicable / suitable programming languages, including object-oriented programming languages such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc., and also including traditional procedural programming languages such as the "C" programming language or similar programming languages.

[0019] For example, method 30 may be implemented on a computer-readable medium as described below in connection with Examples 19 through 24. Embodiments or some portions of method 30 may be implemented in firmware, an application (e.g., via an application programming interface (API)), or driver software running on an operating system (OS).

[0020] Some embodiments may advantageously provide techniques to make the first boot of the basic input / output system (BIOS) faster and / or to make the boot time consistent. Some embodiments may provide a load-reduced boot and / or a consistent load boot. A technical problem with many electronic systems is the time between turning on the system and the system appearing responsive to the user. In some electronic systems, this time may be referred to as the boot time. After power-on, the BIOS may control the boot process and eventually transfer control to the OS when the boot is complete (e.g., at which point the system may appear responsive to the user). During the first boot (e.g., turning on from a powered-off or fully shut-down state), the BIOS may perform dual-inline-memory-module (DIMM) timing training to deliver a stable memory access environment to the OS. In some other systems, this training time highly depends on the number of DIMMs populated on the platform and may take a relatively long time (e.g., the memory training time may take about 1.5 minutes on some 24-DIMM platforms with a released BIOS version and even longer for a debug BIOS version). Advantageously, some embodiments may provide techniques to reduce the boot time and / or reduce or eliminate any dependence on the number of DIMMs populated on the platform.

[0021] Now turning to Figure 4 , an embodiment of a multi-channel memory system 40 may include one or more sockets (e.g., socket 0, socket 1, etc.). Each socket may include a plurality of memory channels. For example, socket 0 may include memory channels 0 to 5, socket 1 may include memory channels 0 to 5, and so on. Each socket may also include a plurality of memory controllers coupled to the respective memory channels. For example, socket 0 may include integrated memory controllers (iMCs) 0 and 1, where iMC 0 is configured to control memory channels 0 to 2 and iMC 1 is configured to control memory channels 3 to 5. Similarly, socket 1 may include corresponding iMCs 0 and 1, where iMC 0 is configured to control memory channels 0 to 2 and iMC 1 is configured to control memory channels 3 to 5, and so on. Each memory channel may include a plurality of slots to mount memory devices or components, such as DIMMs. For example, each of memory channels 0 to 5 of each socket may include two slots (e.g., in Figure 4(labeled “1” and “2” in the figure). Thus, embodiments that utilize the platform of the multi-channel memory system 40 can support two sockets, two iMCs per socket, three channels per iMC, and two memory slots per channel. Other embodiments can support more or fewer sockets, IMCs, memory channels, memory slots, and so on. For illustrative purposes, the shaded pattern of a memory slot represents a DIMM device installed in the memory slot, while the white box can represent an empty memory slot (e.g., no DIMM device is installed).

[0022] In some other systems, the BIOS first boot can train the memory timings of each socket in parallel. For example, in a two-socket system, the overall training time can be approximately half as long as training each socket sequentially. However, other systems can train all the memory channels within a socket serially during the first boot. Other systems can also implement the memory online BIOS feature entirely in the system management mode (SMM). For these other systems, both the BIOS first boot and the memory going online can take a long time and result in a poor user experience because the system appears unresponsive to the user during these periods. For example, when a new DIMM is added to the platform (e.g., similar to memory hot plug), other systems can run in the SMM mode after the OS boot, which may seem to the user that the OS is stuck and not running smoothly until the memory goes online. Advantageously, some embodiments can provide techniques to boot the OS while training a reduced number of DIMMs and train the remaining DIMMs in the BIOS normal mode, which allows the OS to remain responsive until the DIMMs are ready to go online.

[0023] In some embodiments, the BIOS can look for the memory channels populated with the fewest number of DIMMs, train only the DIMMs on the identified channels, and leave the remaining DIMMs untrained until the BIOS boot is complete and after entering the OS. Then the OS driver can call the BIOS-specific runtime services in a multi-threaded mode to train the remaining DIMMs in parallel. After all the DIMMs are trained, the system can enter the SMM mode to create a new memory map and bring the DIMMs online during or after the OS boot. Advantageously, some embodiments can significantly reduce the BIOS boot time. For Figure 4In an example platform with a full memory configuration (e.g., each memory slot is filled with a DIMM device), the BIOS boot time will be approximately one-sixth (1 / 6) of the time compared to some other systems. In some embodiments, the BIOS boot time can be less than approximately one-twelfth (1 / 12) of the time if there is only one DIMM on one channel and the remaining channels are fully filled with DIMMs. Another advantage is that the BIOS boot time can be more consistent because regardless of how many sockets the platform supports, only one memory channel needs to be trained during the BIOS phase. In some embodiments, announcements and / or messages on the BIOS screen can be advantageously provided with a fixed display time to provide a consistent user experience.

[0024] Now turning to Figure 5 , an illustrative example of memory training during the BIOS phase of the multi-channel memory system 40 can identify memory channel 1 of socket 0 as including the fewest number of DIMMs that can be populated in the two-socket memory channel of the platform. For example, minimum and / or maximum thresholds can be set to help the BIOS identify the appropriate memory channel to select for training during the BIOS phase. In a two-socket system, any channel that is filled with only one DIMM can be selected as corresponding to the fewest possible number of DIMMs in any channel (e.g., requiring the least amount of training time accordingly). Since memory channel 1 of socket 0 is the first memory channel found to be filled with only one DIMM, this memory channel can be trained during the BIOS phase. For example, the platform central processor unit (CPU) and / or memory controller can communicate with the DIMM device via the system management (SM) bus. The DIMM can include a serial presence detect (SPD) chip, which the CPU can read via the SM bus. The BIOS can include firmware or commands that direct the CPU to scan each memory channel, and the BIOS can identify therefrom the first channel that indicates the channel is filled with the fewest number of DIMM devices (e.g., one DIMM in the Figure 4 example). Some embodiments can identify more information about the DIMM device and select the first boot memory channel based on the memory capacity of the populated DIMM(s) and / or other characteristics of the populated DIMM(s).

[0025] Now turning to Figure 6 , an illustrative example of memory training during the OS phase of the multi-channel memory system 40 can include the remaining DIMMs. In some other systems, the memory training time can correspond to the maximum time of any socket trained in parallel (e.g., for Figure 4Example system, training time of the nine (9) DIMMs populated in socket 0). In some embodiments, the BIOS may advantageously seek out the memory channel populated with the smallest number of DIMMs. For Figure 4 Example system, only socket 0 channel 1 (e.g., one (1) DIMM) is trained during the BIOS phase. The BIOS may report only the trained BIOS size to the OS, and the remaining DIMMs may be trained during the OS phase.

[0026] Now turning to Figure 7 , an embodiment of a method 70 for booting an operating system may include initiating a BIOS first boot at block 71 and selecting a DIMM training path at block 72. For example, method 70 may determine from the BIOS settings whether the load mitigation mode is enabled. If enabled, method 70 may scan the channels and return the channel number of the channel populated with the smallest number of DIMMs. Alternatively, method 70 may compare the number of populated DIMMs with a threshold and return the first channel number that satisfies the comparison (e.g., number of populated DIMMs = 1; number of populated DIMMs > 0 and < 4; etc.). Alternatively, method 70 may simply return the channel number of the first channel populated with any DIMM. Depending on the platform configuration, any of several suitable criteria may be used to identify a suitable memory channel or a partial set of memory channels for training during the BIOS phase. In some embodiments, the number and / or selection / identification criteria of the memory channels may be configurable. If the load mitigation mode is not enabled, method 70 may abort and the first boot may train all DIMMs.

[0027] If a particular channel (e.g., or a set of channels) is identified to be trained during the BIOS phase (e.g., the channel containing the smallest number of DIMMs), method 70 may then perform DIMM training on that (one or more) particular channel at block 73. Method 70 may then create a memory map and boot the OS at block 74. The memory map created at this time may be based on the (one or more) DIMMs on that particular channel. Method 70 may then move to the OS phase at block 75 and the OS driver may call the BIOS memory training service. For example, the BIOS may provide an entry for the OS to execute specific memory training BIOS code. For example, the BIOS may provide runtime services, or may reserve space for a private service and translate it into a virtual address for OS calls. In some embodiments, the chipset driver may trigger the BIOS memory training service. In some embodiments, the call to the BIOS memory training service may be similar to a later-added hot-pluggable memory and may be initiated by a simulated hot-plug event. Allowing the OS driver to call the BIOS memory training entry permits execution in the OS multi-threaded mode. Advantageously, memory training may be performed on different CPU cores to train different channels in parallel. In some embodiments, the memory training function may be integrated into the chipset driver.

[0028] Method 70 may then perform the memory training service at block 76. This may be done in the BIOS normal mode (e.g., non-SMM). The training service may unlock the required resources, including but not limited to the memory training hardware engine, CSR, etc., and perform memory training on the remaining channels or DIMMs. Since the OS is unaware of the untrained channels or DIMMs, some embodiments advantageously ensure that there are no conflicts in hardware access when the OS and BIOS are running in parallel. The memory service may lock the resources after the memory training is completed and trigger a system management interrupt (SMI) to create a new memory map. Advantageously, since the remaining memory training is done in the BIOS normal mode rather than the SMM mode, the training may be performed in the multi-threaded mode with reduced or minimal time delay and impact on the user experience. Some embodiments may utilize this technique to provide an in-line BIOS memory feature outside of the first boot process to advantageously make the memory come online more smoothly when new DIMMs are added to the platform (e.g., starting from the OS driver call at block 75).

[0029] The SMI interrupt can enable a method to create a new memory map in block 77 in SMM mode. Running in SMM mode can avoid hardware resource access conflicts during memory map reconstruction. Method 70 can also perform Advanced Configuration and Power Interface (ACPI) table updates for the new memory map reported to the OS. Advantageously, the amount of time spent in SMM mode can be much less because memory training has been completed and can have little or no impact on the user experience. Method 70 can then leave the SMM mode in block 78 and all memory bring-up can be completed.

[0030] Figure 8A illustrates a memory trainer device 132(132a - 132b) that can implement one or more aspects of method 30( Figures 3A to 3B ) and / or method 70( Figure 7 ). The memory trainer device 132, which can include logic instructions, configurable logic, fixed function hardware logic, can easily replace the system 10( Figure 1 ) discussed previously. The memory channel selector 132a of the memory trainer device 132 can identify a partial set of populated memory channels from the complete set of populated memory channels of a multi-channel memory system, and the BIOS can complete the first boot of the operating system using only the identified partial set of memory channels of the multi-channel memory system. In some embodiments, the memory channel selector 132a can be configured to identify one memory channel (e.g., a single memory channel populated with one or more memory devices) for the partial set of populated memory channels. For example, the memory channel selector 132a can identify the first populated memory channel of a multi-channel memory system as the one memory channel. In another example, the memory channel selector 132a can identify the first populated memory channel of a multi-channel memory system having fewer memory components than a threshold as the one memory channel. In another example, the memory channel selector 132a can identify the least populated memory channel of a multi-channel memory system as the one memory channel. In some embodiments, the memory channel trainer 132b can train and bring up the other populated memory channels of the complete set of populated memory channels after the first boot is completed.

[0031] Now turning to Figure 8B , a memory trainer device 134(134a, 134b) is illustrated, where logic 134b (e.g., transistor arrays and other integrated circuit / IC components) is coupled to a substrate 134a (e.g., silicon, sapphire, gallium arsenide). The logic 134b can generally implement method 30( Figures 3A to 3B ) and / or method 70( Figure 7) aspects. Thus, logic 134b can identify a partial set of the populated memory channels from the complete set of populated memory channels of the multi-channel memory system and complete the first boot of the operating system using only the identified partial set of the memory channels of the multi-channel memory system. In some embodiments, logic 134b can identify one memory channel (e.g., a single memory channel populated with one or more memory devices) for the partial set of populated memory channels. For example, logic 134b can identify the first populated memory channel of the multi-channel memory system as the one memory channel. In another example, logic 134b can identify the first populated memory channel of the multi-channel memory system having fewer memory components than a threshold as the one memory channel. In another example, logic 134b can identify the least populated memory channel of the multi-channel memory system as the one memory channel. In some embodiments, logic 134b can also bring other populated memory channels of the complete set of populated memory channels online after the first boot is completed. In one example, device 134 is a semiconductor die, chip, and / or package.

[0032] Figure 9 Processor core 200 is illustrated according to one embodiment. Processor core 200 can be a core for any type of processor, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, or other device that executes code. Although only one processor core 200 is illustrated in Figure 9 , the processing element can alternatively include more than one Figure 9 processor core 200 as shown in. Processor core 200 can be a single-threaded core, or for at least one embodiment, processor core 200 can be multi-threaded in that it can include more than one hardware thread context (or "logical processor") for each core.

[0033] Figure 9 Memory 270 coupled to processor core 200 is also illustrated. Memory 270 can be any one of various memories (including various levels of the memory hierarchy) known to those skilled in the art or otherwise available. Memory 270 can include one or more code 213 instructions to be executed by processor core 200, where code 213 can implement method 30 ( Figures 3A to 3B ) and / or method 70 ( Figure 7) aspects. The processor core 200 follows a program sequence of instructions indicated by the code 213. Each instruction can enter the front-end portion 210 and be processed by one or more decoders 220. The decoder 220 can generate micro-operations such as fixed-width micro-operations in a predetermined format as its output, or can generate other instructions, micro-instructions, or control signals that reflect the original code instructions. The illustrated front-end portion 210 also includes register renaming logic 225 and scheduling logic 230, which generally allocate resources and queue operations corresponding to the translated instructions for execution.

[0034] The processor core 200 is shown as including execution logic 250 having a set of execution units 255-1 to 255-N. Some embodiments may include several execution units dedicated to a particular function or set of functions. Other embodiments may include only one execution unit or one execution unit that can perform a particular function. The illustrated execution logic 250 performs the operations specified by the code instructions.

[0035] After the operations specified by the code instructions are completed, the back-end logic 260 retires the instructions of the code 213. In one embodiment, the processor core 200 allows out-of-order execution of instructions but requires in-order retirement of instructions. The retirement logic 265 can take various forms known to those skilled in the art (e.g., a reorder buffer or the like). Thus, the processor core 200 is transformed during the execution of the code 213, at least in terms of the output generated by the decoder, the hardware registers and tables utilized by the register renaming logic 225, and any registers (not shown) modified by the execution logic 250.

[0036] Although not shown in Figure 9 , the processing element may include other elements on the chip having the processor core 200. For example, the processing element may include memory control logic together with the processor core 200. The processing element may include I / O control logic and / or may include I / O control logic integrated with the memory control logic. The processing element may also include one or more caches.

[0037] Now referring to Figure 10 , a block diagram of a system 1000 according to an embodiment is shown. Figure 10 Shown in

[0038] is a multi-processor system 1000, which includes a first processing element 1070 and a second processing element 1080. Although two processing elements 1070 and 1080 are shown, it should be understood that embodiments of the system 1000 may also include only one such processing element. Figure 10Any or all of the interconnections shown may be implemented as a multi-drop bus rather than a point-to-point interconnection.

[0039] As Figure 10 shown, each of processing elements 1070 and 1080 may be a multi-core processor, including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b). Such cores 1074a, 1074b, 1084a, 1084b may be configured to execute instruction code in a manner similar to that described above in connection with Figure 9 the foregoing.

[0040] Each processing element 1070, 1080 may include at least one shared cache 1896a, 1896b (e.g., static random access memory / SRAM). The shared caches 1896a, 1896b may store data (e.g., objects, instructions) utilized by one or more components of the processor (e.g., cores 1074a, 1074b and 1084a, 1084b respectively). For example, the shared caches 1896a, 1896b may store data in local cache memories 1032, 1034 for more rapid access by components of the processor. In one or more embodiments, the shared caches 1896a, 1896b may include one or more intermediate-level caches, such as a level 2 (L2), level 3 (L3), level 4 (L4) or other level cache, last level cache (LLC), and / or combinations thereof.

[0041] Although shown as only having two processing elements 1070, 1080, it is to be understood that the scope of the embodiments is not limited thereto. In other embodiments, one or more additional processing elements may be present in a given processor. Alternatively, one or more of the processing elements 1070, 1080 may be elements other than a processor, such as an accelerator or a field programmable gate array. For example, the (one or more) additional processing elements may include the (one or more) additional processors that are the same as the first processor 1070, the (one or more) additional processors that are heterogeneous or asymmetric to the first processor 1070, accelerators (e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processing element. Between the processing elements 1070, 1080, there may be a variety of differences in terms of the range of value metrics including architecture characteristics, microarchitecture characteristics, thermal characteristics, power consumption characteristics, and so on. These differences may actually manifest themselves as asymmetry and heterogeneity between the processing elements 1070, 1080. For at least one embodiment, the various processing elements 1070, 1080 may be present in the same die package.

[0042] The first processing element 1070 may further include memory controller logic (MC) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, the second processing element 1080 may include MC 1082 and P-P interfaces 1086 and 1088. As Figure 10 shown, MCs 1072 and 1082 couple the processors to respective memories, namely memories 1032 and 1034, which may be part of the main memories locally attached to the respective processors. Although MCs 1072 and 1082 are shown integrated into the processing elements 1070, 1080, for alternative embodiments, the MC logic may be discrete logic external to the processing elements 1070, 1080 rather than integrated therein.

[0043] The first processing element 1070 and the second processing element 1080 may be coupled to the I / O subsystem 1090 via P-P interconnections 1076, 1086, respectively. As Figure 10 shown, the I / O subsystem 1090 includes a TEE 1097 (e.g., a security controller) and P-P interfaces 1094 and 1098. In addition, the I / O subsystem 1090 includes an interface 1092 to couple the I / O subsystem 1090 to the high-performance graphics engine 1038. In one embodiment, a bus 1049 may be used to couple the graphics engine 1038 to the I / O subsystem 1090. Alternatively, point-to-point interconnections may couple these components.

[0044] Furthermore, the I / O subsystem 1090 may be coupled to the first bus 1016 via an interface 1096. In one embodiment, the first bus 1016 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a rapid PCI bus or another third-generation I / O interconnect bus, although the scope of the embodiments is not limited thereto.

[0045] As Figure 10As shown, various I / O devices 1014 (e.g., cameras, sensors) can be coupled to a first bus 1016, and a bus bridge 1018 that can couple the first bus 1016 to a second bus 1020. In one embodiment, the second bus 1020 can be a low pin count (LPC) bus. Various devices can be coupled to the second bus 1020, such as including a keyboard / mouse 1012, one or more network controllers / communication devices 1026 (which can in turn communicate with a computer network), and a data storage unit 1019, such as a disk drive or other mass storage device, which can include code 1030 in one embodiment. The code 1030 can include instructions for performing embodiments of one or more of the methods described above. Thus, the illustrated code 1030 can implement one or more aspects of the methods 30 ( Figures 3A to 3B ) and / or method 70 ( Figure 7 ), and can be similar to the code 213 ( Figure 9 ) that has been discussed. Additionally, audio I / O 1024 can be coupled to the second bus 1020.

[0046] Note that other embodiments are envisioned. For example, instead of Figure 10 a point-to-point architecture, the system can implement a multi-drop bus or another such communication topology.

[0047] Additional Notes and Examples:

[0048] Example 1 can include an electronic processing system, including: a processor, a multi-channel memory system communicatively coupled to the processor, and logic communicatively coupled to the processor for: identifying a partial set of populated memory channels from a complete set of populated memory channels of the multi-channel memory system, and completing a first boot of an operating system using only the identified partial set of memory channels of the multi-channel memory system.

[0049] Example 2 can include the system as described in Example 1, wherein the logic is further for: identifying one memory channel for the partial set of populated memory channels.

[0050] Example 3 can include the system as described in Example 2, wherein the logic is further for: identifying a first populated memory channel of the multi-channel memory system as the one memory channel.

[0051] Example 4 can include the system as described in Example 2, wherein the logic is further for: identifying a first populated memory channel of the multi-channel memory system that has fewer memory components than a threshold as the one memory channel.

[0052] Example 5 may include the system as described in Example 2, wherein the logic is further configured to: identify the least populated memory channel of the multi-channel memory system as the one memory channel.

[0053] Example 6 may include the system as described in any one of Examples 1 to 5, wherein the logic is further configured to: after the first startup is completed, bring online other populated memory channels of the complete set of populated memory channels.

[0054] Example 7 may include a semiconductor packaging device, comprising: a substrate, and logic coupled to the substrate, wherein the logic is at least partially implemented in one or more of configurable logic and fixed-function hardware logic, and the logic coupled to the substrate is configured to: identify a partial set of populated memory channels from the complete set of populated memory channels of a multi-channel memory system, and complete a first startup of an operating system using only the identified partial set of memory channels of the multi-channel memory system.

[0055] Example 8 may include the device as described in Example 7, wherein the logic is further configured to: identify one memory channel for the partial set of populated memory channels.

[0056] Example 9 may include the device as described in Example 8, wherein the logic is further configured to: identify the first populated memory channel of the multi-channel memory system as the one memory channel.

[0057] Example 10 may include the device as described in Example 8, wherein the logic is further configured to: identify the first populated memory channel of the multi-channel memory system having fewer memory components than a threshold as the one memory channel.

[0058] Example 11 may include the device as described in Example 8, wherein the logic is further configured to: identify the least populated memory channel of the multi-channel memory system as the one memory channel.

[0059] Example 12 may include the device as described in any one of Examples 7 to 11, wherein the logic is further configured to: after the first startup is completed, bring online other populated memory channels of the complete set of populated memory channels.

[0060] Example 13 may include a method for starting an operating system, comprising: identifying a partial set of populated memory channels from the complete set of populated memory channels of a multi-channel memory system, and completing a first startup of the operating system using only the identified partial set of memory channels of the multi-channel memory system.

[0061] Example 14 may include the method as described in Example 13, further comprising: identifying a memory channel for a partial set of the populated memory channels.

[0062] Example 15 may include the method as described in Example 14, further comprising: identifying a first populated memory channel of the multi-channel memory system as the one memory channel.

[0063] Example 16 may include the method as described in Example 14, further comprising: identifying a first populated memory channel of the multi-channel memory system that has fewer memory components than a threshold as the one memory channel.

[0064] Example 17 may include the method as described in Example 14, further comprising: identifying the least populated memory channel of the multi-channel memory system as the one memory channel.

[0065] Example 18 may include the method as described in any one of Examples 13 to 17, further comprising: after the first boot is completed, bringing online other populated memory channels of the complete set of the populated memory channels.

[0066] Example 19 may include at least one computer-readable medium including a set of instructions that, when executed by a computing device, cause the computing device to: identify a partial set of populated memory channels from a complete set of populated memory channels of a multi-channel memory system, and complete a first boot of an operating system using only the identified partial set of memory channels of the multi-channel memory system.

[0067] Example 20 may include the at least one computer-readable medium as described in Example 19, including another set of instructions that, when executed by the computing device, cause the computing device to: identify a memory channel for the partial set of the populated memory channels.

[0068] Example 21 may include the at least one computer-readable medium as described in Example 20, including another set of instructions that, when executed by the computing device, cause the computing device to: identify a first populated memory channel of the multi-channel memory system as the one memory channel.

[0069] Example 22 may include the at least one computer-readable medium as described in Example 20, including another set of instructions that, when executed by the computing device, cause the computing device to: identify a first populated memory channel of the multi-channel memory system that has fewer memory components than a threshold as the one memory channel.

[0070] Example 23 may include at least one computer-readable medium as described in Example 20, including another set of instructions that, when executed by the computing device, cause the computing device to: identify the least-populated memory channel of the multi-channel memory system as the one memory channel.

[0071] Example 24 may include at least one computer-readable medium as described in any one of Examples 19 to 23, including another set of instructions that, when executed by the computing device, cause the computing device to: after the first startup is completed, bring online the other populated memory channels of the complete set of populated memory channels.

[0072] Example 25 may include a startup device including means for: identifying a partial set of populated memory channels from the complete set of populated memory channels of a multi-channel memory system and completing a first startup of an operating system using only the identified partial set of memory channels of the multi-channel memory system.

[0073] Example 26 may include the device as described in Example 25, further including: means for identifying one memory channel for the partial set of populated memory channels.

[0074] Example 27 may include the device as described in Example 26, further including: means for identifying the first populated memory channel of the multi-channel memory system as the one memory channel.

[0075] Example 28 may include the device as described in Example 26, further including: means for identifying the first populated memory channel of the multi-channel memory system having fewer memory components than a threshold as the one memory channel.

[0076] Example 29 may include the device as described in Example 26, further including: means for identifying the least-populated memory channel of the multi-channel memory system as the one memory channel.

[0077] Example 30 may include the device as described in any one of Examples 25 to 29, further including: means for bringing online the other populated memory channels of the complete set of populated memory channels after the first startup is completed.

[0078] The embodiments are applicable to use with all types of semiconductor integrated circuit (“IC”) chips. Examples of such IC chips include, but are not limited to, processors, controllers, chip set components, programmable logic arrays (PLAs), memory chips, network chips, systems on chip (SoCs), SSD / NAND controller ASICs, and the like. Additionally, in some of the figures, signal conductors are represented by lines. Some may be different to indicate more constituent signal paths, some have numerical annotations to indicate the number of constituent signal paths, and / or some have arrows at one or more ends to indicate the primary information flow direction. However, this should not be construed in a limiting manner. Rather, such added details may be used in connection with one or more exemplary embodiments to facilitate easier understanding of the circuitry. Any represented signal line, whether or not having additional information, may actually include one or more signals that may travel in multiple directions and may be implemented using any suitable type of signal scheme (e.g., digital or analog lines implemented using differential pairs, fiber optic lines, and / or single-ended lines).

[0079] Example sizes / models / values / ranges may be given, although the embodiments are not limited thereto. As manufacturing technologies (e.g., lithography) mature over time, it is expected that devices of smaller sizes can be manufactured. Additionally, for simplicity of illustration and discussion, and in order not to obscure certain aspects of the embodiments, well-known power / ground connections to the IC chips and other components may or may not be shown in the figures. Further, the arrangements may be shown in block diagram form to avoid obscuring the embodiments and also in view of the fact that the specific details regarding the implementation of such block diagram arrangements are highly dependent on the platform within which the embodiments are implemented, i.e., such specific details should be entirely within the purview of those of ordinary skill in the art. In cases where specific details (e.g., circuits) are set forth to describe example embodiments, it should be apparent to those of ordinary skill in the art that the embodiments can be implemented without these specific details or with variations of these specific details. Thus, the specification should be considered illustrative rather than restrictive.

[0080] The term “coupled” may be used herein to refer to any type of relationship between the components involved, whether direct or indirect, and may apply to electrical, mechanical, liquid, optical, electromagnetic, electromechanical, or other connections. Additionally, unless otherwise indicated, the terms “first,” “second,” etc. may be used herein only to facilitate discussion and do not carry a particular temporal or precedence meaning.

[0081] As used in this application and in the claims, a list of items joined by the term "one or more of" can mean any combination of the listed terms. For example, both the phrases "one or more of A, B, and C" and "one or more of A, B, or C" can mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0082] Those skilled in the art will appreciate from the foregoing description that the broad techniques of the embodiments can be implemented in many forms. Thus, while the embodiments have been described in connection with their specific examples, the true scope of the embodiments should not be so limited, since other modifications will become apparent to those skilled in the art upon study of the drawings, the specification, and the appended claims.

Claims

1. An electronic processing system, comprising: A processor; A multi-channel memory system communicatively coupled to the processor; And Logic communicatively coupled to the processor, the logic being configured to: Identify a partial set of populated memory channels from a complete set of populated memory channels of the multi-channel memory system, Complete a first boot of an operating system only using the identified partial set of memory channels of the multi-channel memory system, and After the first boot is completed, bring online other populated memory channels of the complete set of populated memory channels, Wherein completing the first boot of the operating system only using the identified partial set of memory channels includes: performing memory training operations during the first boot only based on the identified partial set of memory channels, and Wherein bringing online other populated memory channels of the complete set of populated memory channels includes: performing memory training operations based on the other populated memory channels.

2. The system according to claim 1, wherein the logic is further configured to: Identify one memory channel for the partial set of populated memory channels.

3. The system according to claim 2, wherein the logic is further configured to: Identify a first populated memory channel of the multi-channel memory system as the one memory channel.

4. The system according to claim 2, wherein the logic is further configured to: Identify a first populated memory channel of the multi-channel memory system that has fewer memory components than a threshold as the one memory channel.

5. The system according to claim 2, wherein the logic is further configured to: Identify the least populated memory channel of the multi-channel memory system as the one memory channel.

6. A semiconductor package device, comprising: A substrate; And Logic coupled to the substrate, wherein the logic is at least partially implemented in one or more of configurable logic and fixed function hardware logic, and the logic coupled to the substrate is configured to: Identify a partial set of populated memory channels from a complete set of populated memory channels of a multi-channel memory system, Complete a first boot of an operating system only using the identified partial set of memory channels of the multi-channel memory system, and After the first boot is completed, bring online other populated memory channels of the complete set of populated memory channels, Wherein completing the first boot of the operating system only using the identified partial set of memory channels includes: performing memory training operations during the first boot only based on the identified partial set of memory channels, and Wherein bringing online other populated memory channels of the complete set of populated memory channels includes: performing memory training operations based on the other populated memory channels.

7. The device according to claim 6, wherein the logic is further configured to: Identify one memory channel for the partial set of populated memory channels.

8. The device according to claim 7, wherein the logic is further configured to: Identify a first populated memory channel of the multi-channel memory system as the one memory channel.

9. The apparatus according to claim 7, wherein the logic is further configured to: Identify, as the one memory channel, a first populated memory channel of the multi-channel memory system that has fewer memory components than a threshold.

10. The apparatus according to claim 7, wherein the logic is further configured to: Identify, as the one memory channel, the least populated memory channel of the multi-channel memory system.

11. A method for booting an operating system, comprising: Identifying a partial set of populated memory channels from a complete set of populated memory channels of a multi-channel memory system; Completing a first boot of the operating system using only the identified partial set of memory channels of the multi-channel memory system; And After the first boot is completed, bringing other populated memory channels of the complete set of populated memory channels online, wherein completing the first boot of the operating system using only the identified partial set of memory channels includes: performing memory training operations during the first boot based only on the identified partial set of memory channels, and wherein bringing other populated memory channels of the complete set of populated memory channels online includes: performing memory training operations based on the other populated memory channels.

12. The method according to claim 11, further comprising: Identifying one memory channel for the partial set of populated memory channels.

13. The method according to claim 12, further comprising: Identifying a first populated memory channel of the multi-channel memory system as the one memory channel.

14. The method according to claim 12, further comprising: Identifying, as the one memory channel, a first populated memory channel of the multi-channel memory system that has fewer memory components than a threshold.

15. The method according to claim 12, further comprising: Identifying, as the one memory channel, the least populated memory channel of the multi-channel memory system.

16. A booting device, comprising: Means for identifying a partial set of populated memory channels from a complete set of populated memory channels of a multi-channel memory system; Means for completing a first boot of an operating system using only the identified partial set of memory channels of the multi-channel memory system; And Means for bringing other populated memory channels of the complete set of populated memory channels online after the first boot is completed, wherein the means for completing the first boot of the operating system using only the identified partial set of memory channels includes: means for performing memory training operations during the first boot based only on the identified partial set of memory channels, and wherein the means for bringing other populated memory channels of the complete set of populated memory channels online includes: means for performing memory training operations based on the other populated memory channels.

17. The apparatus according to claim 16, further comprising: Means for identifying one memory channel for the partial set of populated memory channels.

18. The apparatus according to claim 17, further comprising: Apparatus for identifying a first populated memory channel of the multi-channel memory system as the one memory channel.

19. The apparatus of claim 17, further comprising: Apparatus for identifying a first populated memory channel of the multi-channel memory system having fewer memory components than a threshold as the one memory channel.

20. The apparatus of claim 17, further comprising: Apparatus for identifying the least populated memory channel of the multi-channel memory system as the one memory channel.

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