Memory Test Control of Stacked DDR Memory

Abstract

Disclosed are methods and apparatus for implementing a memory controller such as a bus integrated memory controller (BIMC), the memory controller comprising a memory built-in self-test (MBIST) controller or logic. The MBIST controller is configured to test at least one memory device, such as a stacked low power double data rate (LPDDR) memory in a system on chip or a similar configuration that makes it difficult to test the memory device externally. The MBIST controller can be implemented in a standard memory controller and comprises memory conversion logic, the memory conversion logic being configured to convert a signal for testing at least one memory device into a signal in a format that can be used by at least one memory device, wherein the conversion logic is used to implement a memory representation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Provisional Patent Application No. 201741033496 filed in the Indian Patent Office on September 21, 2017 and Non-Provisional Patent Application No. 15 / 887,695 filed in the United States Patent and Trademark Office on February 2, 2018, the entire contents of which are incorporated herein by reference in their entirety as if fully set forth below and for all applicable purposes. Technical Field

[0003] The present invention relates to a memory test control for a double data rate (DDR) memory, and more particularly to a memory test control for a stacked DDR dynamic random access memory (DRAM) in a system on chip (SoC).

[0004] Run memory tests on the memory. Background Art

[0005] Specifically, in SoC and similar structures, DDR memories (such as low-power DDR memories (e.g., LPDDR4)) are stacked within the SoC. Many DDR memory manufacturers provide memory devices to be tested according to specific tests that are usually provided by the manufacturer. In the case of stacked memories, manufacturers also recommend that these memories be tested according to complete memory tests. However, in this case of a stacked SoC, it is impossible to quickly test the DDR memory devices using known interfaces, which makes it difficult to test according to the recommended tests, and if a system failure occurs, it is difficult to distinguish the cause of the system failure. Therefore, a method and apparatus that meets the test requirements includes using a built-in test controller that is compatible with the Joint Electron Device Engineering Council (JEDEC) standard and supports a specific DDR interface (such as a low-power DDR 4 (LPDDR4) interface) to ensure the integrity of the stacked DDR memory. Summary of the invention

[0006] Various features, apparatus, and methods described herein provide a programmable built-in self-test (BIST) in a memory controller.

[0007] According to one aspect, an apparatus is disclosed that can be implemented, for example, in a mobile station or as a mobile station. The apparatus includes a memory controller (MC) that includes a memory built-in self-test (MBIST) configured to test at least one memory device. The MBIST includes memory conversion logic that is configured to convert a signal for testing at least one memory device into a signal in a format of at least one memory device.

[0008] According to another aspect, a method for testing a memory device is disclosed. The method comprises: initiating an MBIST operation in a memory controller (MC), initiating the MBIST operation comprises: enabling MBIST logic to communicate with the memory device. The method further comprises: utilizing memory conversion logic to convert one or more commands and data from the MBIST logic for testing the memory device into signals in a format compatible with the memory device.

[0009] In another aspect, a device is disclosed, which includes a memory that receives one or more instructions for testing a memory. The instruction includes a command for initiating an MBIST operation in a memory controller (MC), wherein initiating the MBIST operation includes: causing MBIST logic to communicate with a memory device; and a command for converting one or more commands and data from the MBIST logic for testing the memory device into a signal in a format compatible with the memory device using a memory conversion logic.

[0010] According to another aspect, a non-transitory computer-readable medium storing computer executable code is disclosed. The medium includes code for causing a computer to perform the following operations: implement a memory built-in self-test (MBIST) function in a memory controller (MC), the MBIST function being configured to test at least one memory device. Further, the medium includes code for converting a signal for testing at least one memory device using the MBIST function into a signal in a format used by at least one memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011]

[0013] Various features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which like reference characters identify corresponding elements.

[0012] Figure 1 An example of a memory package and a memory controller (MC), such as a bus integrated memory controller (BIMC), within a system-on-chip architecture is illustrated.

[0013] Figure 2 An exemplary block diagram of a MC (eg, a BIMC) including memory built-in self-test (MBIST) logic coupled between a bus and a memory device is illustrated.

[0014] Figure 3 The diagram shows Figure 2 An exemplary block diagram of the MBIST logic MC is shown.

[0015] Figure 4 Pictured Figure 3An exemplary block diagram of MBIST logic is shown.

[0016] Figure 5 Pictured Figure 4 An exemplary block diagram of at least a memory representation portion of the MBIST core logic is shown.

[0017] Figure 6 The diagram shows that Figure 4 and Figure 5 An exemplary conversion module utilized within a memory representation within the MBIST logic.

[0018] Figure 7 A timing diagram of command data (eg, CA / CS / CKE signals) within the MBIST logic and at the input of the memory is illustrated, where the timing frequency of the MBIST is a fraction of the memory operating frequency.

[0019] Figure 8 A timing diagram of DQ data within the MBIST logic and at the input of the memory is illustrated, where the timing frequency of the MBIST logic is a fraction of the memory operating frequency.

[0020] Fig. 9 and Fig.10 Phase control including phase shifting according to an aspect of the present disclosure is illustrated.

[0021] Fig.11 A flow chart of an exemplary method for implementing and / or operating MBIST logic in a MC is illustrated.

[0022] Fig.12 A flow chart of another exemplary method for implementing and / or operating MBIST logic in a MC is illustrated.

[0023] Fig.13 A conceptual diagram illustrating an example of a hardware implementation for an exemplary user equipment (UE) or mobile station in which the present MC may be implemented is illustrated. DETAILED DESCRIPTION

[0024] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, it should be understood by those of ordinary skill in the art that various aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams so as not to obscure various aspects in unnecessary detail. In other examples, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure various aspects of the present disclosure.

[0025] Ideally, a memory built-in self-test controller or logic (e.g., MBIST) should support all the various custom operations required to support custom testing and other algorithms that different memory vendors may request. DDR memory devices used with system-on-chip (SoC) devices and especially LPDDR4 memory devices (such as DDR stacked with SoC) generally have requirements imposed by memory vendors, which require extensive external memory testing. Although DDR is tested independently by memory vendors, when stacking DDR, there is a situation where there is no interface that can quickly test the DDR memory configured in this way. Thus, the currently disclosed method and apparatus provide for testing stacked DDR memory using MBIST, which can fully support various test algorithms provided by different memory vendors. Additionally, the currently disclosed method and apparatus provide MBIST, which can be integrated in existing BIMC designs with minimal interface changes. The present method and apparatus also provide a MBIST design, which can provide a set of custom operations and custom algorithms for various types of DDR memories (including LPDDR4 memories) by using at least one conversion finite state machine (FSM) or similar logic.

[0026] In addition, the present method and apparatus also provide dual command / address (CA) bus and data bus support, which implements BIMC support with a ratio of 1:2 (i.e., 1:2 operating mode), so that the memory test controller (e.g., the interface of the memory test controller) can operate at half the frequency of the DDR memory. Extending with the 1:2 mode, the present method and apparatus also provide phase control support for the 1:2 mode. That is, programmable logic or mechanism for phase swapping can be provided to implement a memory cycle shift for both the CA bus and the data bus. Further still, the presently disclosed method and apparatus provide different data mask (DM) sequence support, wherein different group write enables and swap mechanisms are used to implement different DM sequences that may be required by custom algorithms.

[0027] For contextualization, Figure 1 An example of a package structure including a SoC system is illustrated, the SoC structure having, for example, a stacked memory device with a memory controller having MBIST logic for testing the memory device and running self-diagnostic tests to check the operation and / or functionality of the package. Specifically, Figure 1The package 100 is illustrated as including a substrate 101, a memory controller 102 (e.g., on an application processor die), a first memory die 104, and a second memory die 106. In one aspect, the memory controller 102 can be located on top of the substrate 101. The memory controller 102 can include MBIST logic 112 and memory controller logic 110. It should be noted that although Figure 1 MBIST logic within the memory controller 102 is illustrated, but MBIST may alternatively be a test provided by a host via a communication link or coupling, which is in turn performed by a memory device or die. The first memory die 104 may be located at the top of the memory controller 102, and the second memory die 106 may be located at the top of the first memory die 104. Further, in another alternative, the first memory die 104 and the second memory die 106 may also be located on the side of the memory controller 102 using a specific packaging configuration. In some implementations, at least one of the memories 104, 106 is a double data rate synchronous dynamic random access memory (DDR SDRAM). In other implementations, (multiple) memories 104, 106 are memories configured as LPDDR4 memory devices.

[0028] The memory controller 102 is configured to control access, writing, reading, etc. to the first memory die 104 and the second memory die 106. In some implementations, the control is performed by the memory controller logic 110. The MBIST control or logic 112 is configured to test at least one or more memory dies, such as the first memory die 104 and the second memory die 106.

[0029] As explained in more detail later, the MBIST controller or logic 112 can be defined by one or more circuits in the memory controller 102. Likewise, the memory controller logic 110 can be defined by one or more circuits in the memory controller 102. Although only two memory dies are shown, the package 100 may include more than two memory dies. In addition, the location of the die can be located at different locations. For example, in some implementations, the memory controller 102 can be located between the first memory die 104 and the second memory die 106. In some implementations, the memory controller 102 can also be located on top of the second memory die 106. In some implementations, the die in the package 100 can be electrically and communicatively coupled to each other by, for example, communication coupling (e.g., chip-to-chip link) such as through silicon vias (TSVs), wire bonding, and / or some solder bumps.

[0030] It should be pointed out that Figure 1The structure can be implemented in a mobile device such as a mobile station (MS), a user equipment (UE), a cellular phone, or any other mobile communication device. Furthermore, the memory controller 102 can be a host, a processor (e.g., an application processor), or a part of a processing circuit of a mobile station.

[0031] Figure 2 An exemplary block diagram of a memory controller such as memory controller 102 is illustrated. As can be seen, memory controller 102, which may be a memory controller (MC) or, in some aspects, a bus interface memory controller (BIMC), includes MBIST logic 112 and memory controller logic 110. Further, as Figure 2 As shown, the BIMC 102 is communicatively coupled to a communication coupling or system bus 202 that is configured for communicating with a host or alternatively other portions of a host via a bus interface 204. The memory controller 102 is also communicatively coupled to at least one memory 104 via a memory interface 206. The memory controller 102 controls read operations and write operations of the memory 104. In one aspect, it should be noted that the memory controller 102 can be part of a host device that is writing and reading data to the memory 104.

[0032] The memory test logic or MBIST logic 112 may also be coupled between the bus interface 204 and the memory interface 206. In order for the MBIST logic 112 to perform test operations on the memory(s) 104, 106, the MBIST logic 112 communicates with the memory controller logic 110 and sends instructions on behalf of the memory controller logic 110. Therefore, a switch interface 208 configured to selectively provide a communication coupling between the MBIST logic 112 and the memory interface 206 may be utilized. According to some embodiments, the interface 208 may be under the control of the MBIST logic 112, but the selection is not limited thereto and may alternatively be implemented by some external signal from a processor in a device or SoC employing the memory controller 102. Further, as illustrated, the switch interface 208 may be separate from the memory interface 206, or as shown in the figure, the switch interface 208 may be separate from the memory interface 206. Figure 3 As shown in the example of , it is incorporated into the memory interface 206. Further, it should be noted that the switch interface 208 can be a multiplexer.

[0033] The memory controller logic 110 may perform control operations on the memories 104, 106 through the memory interface 206. For example, the memory controller logic 110 may perform read operations and write operations on the memory 202. These read operations and write operations may specify locations of the memories 104, 106 where data is written and / or read.

[0034] MBIST logic 112 can be tested by memory interface 206 to memory 104,106.As discussed in more detail later, MBIST logic 112 can perform multiple test operations (for example, using different test algorithms and / or scans).These test operations or scans can be selectable and / or programmable.In some implementations, MBIST logic 112 can be programmable (for example, the type of test that MBIST logic can perform is programmed) by interface (for example, joint test action group (JTAG) interface).And, in some implementations, MBIST logic 112 can be a circuit separated from the circuit of the memory controller logic of the memory controller.

[0035] Figure 3 A more detailed block diagram of an exemplary implementation of the memory controller 102 utilizing the MBIST logic 112 is illustrated. It should be noted that the memory controller logic 110 has been omitted from this figure for the sake of clarity.

[0036] MBIST logic 112 is located between bus interface 204 and memory interface 206 in BIMC 102. Multiple signals can be directly driven between bus interface 204 and memory interface 206. During testing, some of these signals are intercepted and driven by using MBIST logic 112 for testing memory 104, 106. According to one aspect, currently disclosed MBIST logic 112 provides a built-in memory test controller design, which supports the extensive algorithm test required for DDR memory, especially LPDDR4 or LPDDR5 stacked memory (or similar memory device). In one example, MBIST 112 can be configured as an LPDDR4 or LPDDR5 memory test controller integrated in the BIMC design (that is, the present disclosure does not necessarily only relate to the modification of LPDDR4 or LPDDR5 memory BIMC, but for example, can be used for any memory BIMC architecture (such as, LPDDR2 BIMC architecture) in several memory BIMC architectures.

[0037] like Figure 3As shown, MBIST logic 112 can have MBIST core logic 302.This core logic 302 can also comprise conversion finite state machine (FSM) or similar structure or function, for conversion command and instruction to be able to be connected (for example, PHY interface 304, DDR input / output 306) and memory itself (for example, 104) interface with memory interface 206 and various memory.MBIST core logic 302 is also configured to have the self-defined operation set and the self-defined algorithm for the specific memory (such as LPDDR4 memory) to be tested.This logic also comprises conversion state machine, and this conversion state machine converts MBIST signal into the compatible command for the memory to be tested.Conversion state machine realizes memory representation creation, so that this instrument thinks that this memory is local memory, just like pseudo memory.Conversion state machine also has the task of generating required I / O 306 and DDR PHY 304 signals accurately read and write required from memory.

[0038] The memory interface 206 also includes a first-in-first-out (FIFO) buffer 308, which receives the DDR data read back from the PHY / memory (304 / 104). The FIFO 308 allows the BIST logic 302 to interface with the PHY / memory without having to handle the synchronization of the DDR data. On the other hand, it should be noted that the DDR memory operates at a frequency (e.g., a DDR memory interface frequency) higher than the typical frequency used to operate the BIMC controller 102. However, the memory interface needs to operate at a frequency corresponding to the DDR operating frequency (e.g., the DDR memory interface frequency) to interface with the memory appropriately. For example, the DDR operating frequency may refer to the maximum DDR memory interface frequency specified by the specification, such as LPDDR4 or LPDDR5. Therefore, the present disclosure also provides an interface 206 that allows MBIST 112 and MBIST logic 302 to operate at the same frequency as the frequency of BIMC102, which is about half of the DDR frequency (i.e., a ratio of 1:2). In other embodiments, the frequency ratio may be larger or smaller, depending on the specific memory being tested. In one example, the present disclosure allows testing of DDR memory at a maximum DDR memory interface frequency.

[0039] MBIST 112 is also configured to receive BIST or MBIST enable signal 310 to make or trigger the system to enter memory test mode and generate override signal 312, to switch memory interface 206 between MBIST signal and functional interface signal via switch 208 during normal operation, and this functional interface signal is transmitted between bus interface 204 and memory interface 206. In some aspects, MBIST enable signal 310 can be received from logic within BIMC 102, from logic or processing outside BIMC 102. Alternatively, in some embodiments, MBIST enable signal 310 can also be generated in MBIST logic 112 itself, rather than received from external logic or processor. The override signal 312 may be configured to be generated by the MBIST logic 302 and used to select which input of the switch or multiplexer 208 is output to the PHY / DDR I / O / memory device, i.e., the input from the MBIST logic 112 during standard memory control by the BIMC 102 or the normal functional interface signal from the bus interface 204 (or other logic used in memory control operations).

[0040] Although the switching or multiplexing between the functional signals and the memory BIST signals is within the memory interface 102 (i.e., using the switch or multiplexer 208), due to the requirements of the specific memory and memory interface 206 and the JEDEC specification, other switching or multiplexing as represented by the multiplexer 314 can be utilized at the output of the MBIST core logic and FSM (and especially the memory representation discussed later). The MBIST logic 112 is also configured to receive external instructions and data via a JTAG interface 316.

[0041] Figure 4 Pictured Figure 2 and Figure 3 More detailed block diagram of the MBIST logic 112 shown.First, it should be noted that various logic blocks or logic components illustrated in this article can be hard-coded and fixed.Yet, in other examples, logic blocks or logic components can be configured or realized by a memory configuration tool, and are then connected with the memory configuration tool.

[0042] Can be obtained from Figure 4In the embodiment of the present invention, MBIST logic 112 (more specifically, according to specific example, core logic 302) can include MBIST controller logic 402, which is timed under the frequency of BIMC clock. MBIST controller logic 402 controls the operation of MBIST logic 112 by MBIST memory interface logic 404, and this MBIST memory interface logic 404 is particularly engaged with memory representation transformation logic or FSM 406 interfaces. Because memory device 104,106 is outside the chip, so create memory representation so that memory device looks to be the local memory of MBIST logic 112, thereby serve as the type of proxy memory or pseudo memory. On the one hand, it should be noted that the memory representation model can comprise specification, and this specification notifies the specific MBIST logic to be inserted or configured to the MBIST logic configuration tool.

[0043] In one aspect, can automatically generate and connect MBIST core logic in MBIST logic 112 by memory configuration tool.MBIST core logic can be considered to be made up of MBIST controller logic 402, MBIST memory interface logic 404 and test access port (TAP) 408.TAP 408 is coupled with JTAG interface 316 communication, and this JTAG interface 316 can be configured as the LVTAP that is positioned at chip or SoC top layer, and is configured to communicate with each TAP module in the system.Further, can perform selection or multiplexing between function signal and MBIST signal in memory interface.

[0044] Figure 5 Pictured Figure 3 and Figure 4 500 of at least a portion of the memory representation or memory representation logic 406 or FSM 302 shown. As noted above, the reason for utilizing the memory representation is that the memory device does not exist in the area parsed by the MBIST logic 112, so the memory representation logic is used to trick the logic into identifying the memory representation as a local memory and performing the normal automatic insertion of the MBIST logic 112. Additionally, the MBIST logic 112 has the flexibility to create signals with different purposes, but it cannot accurately create a signal set that matches the functionality and timing expected by the memory interface 206. Thus, Figure 5 The memory representation shown provides the MBIST logic 112 with functionality to convert and adapt signals between the MBIST logic 112 and the memory interface 206 .

[0045] like Figure 5As shown, multiplexer 502 allows selection of a function signal 504 or an MBIST conversion signal of various command and data signals 506 input to and converted by conversion block 508 based on an MBIST enable signal (e.g., 310). Conversion block 508 provides the ability to convert MBIST signals into signals compatible with memory interface 206 to test memory devices 104, 106. Conversion block 508 may also convert based on inputs to bank sorting block or logic 510, which is operable based on input address 512 and bank select and sorting signals 514.

[0046] The memory representation logic portion 500 may also include pass-through signals 516, 518 for signals that are not affected by or related to the MBIST logic 112. It should also be noted that the various signals illustrated as input to and output from the memory representation logic portion 500 are exemplary only, and the present disclosure is not intended to be limited in this regard.

[0047] Figure 6 The diagram shows the Figure 5 500. The memory representation of the exemplary conversion module or encoder 600 in 500. Conversion module 600 is configured to obtain the signal between MBIST components and logic and memory interface 206, and adjust the timing of these signals, so that communication can be made between MBIST logic 112 and memory interface 206. As an example, any MBIST request or signal (such as address, activation, read enable, write enable, BIST user bit, user IR bit, preload, etc.) from MBIST logic 112 is converted to corresponding request in the format that memory interface 206 can interpret. Conversion FSM and conversion module 600 also perform the task of generating required I / O and DDR PHY signals that are accurately read and written from memory devices 104,106. According to another aspect, conversion FSM can include programmable data (DQ) and strobe (DQS) delay, to meet memory device timing (that is, DQ and DQS timing relationship).

[0048] Figure 7The sequential diagram of the command data (for example, CA / CS / CKE signal) at the input of MBIST logic output and memory (or memory interface) is illustrated, wherein the sequential frequency of the MBIST logic and signal for testing memory is a part for memory operation frequency.As illustrated, the clock 702 for the operation of MBIST logic 112 operates under specific frequency or clock cycle length.As can be seen, in the whole cycle of clock 702, generate command data 704 or 706 for the first phase and the second phase (P0, P1).But, as discussed above, the frequency of the clock 702 of MBIST operation is lower than the operating frequency of DDR memory device, and in some aspects, equals memory controller (MC) or BIMC clock.

[0049] After the MBIST signal of the MBIST logic 112 is converted to be compatible with the memory interface (and memory device), the DDR operating frequency is higher than the BIMC clock. In this example, the operating frequency of the clock of the DDR memory device or clock 708 is approximately twice the BIMC clock frequency of the clock signal 702. Because the MBIST logic 112 or a portion thereof (including the interface) operates at approximately half the frequency of the DDR memory (e.g., the DDR memory interface) and the CA operation is performed at a single data rate (SDR) at the DDR memory, the MBIST logic needs to provide twice the data in each MBIST logic clock cycle. Therefore, the command data of the phases P0 and P1 generated in the cycle of the MBIST clock 702 are now transmitted in two cycles of the clock 708 of the DDR memory operation. Thus, the command data 710 of the first phase P0 is transmitted in the first cycle of the clock 708, and the command data 712 of the second phase P1 is transmitted in the next second cycle of the clock 708. Thus, in Figure 7 In the example of , the present method and apparatus provide approximately 1:2 frequency support. It should be noted that the present disclosure is not limited to only 1:2 frequency support, and other ratios may be considered within the scope of the present disclosure.

[0050] Figure 8 The timing diagram of DQ / DQS data within the MBIST logic and at the input of the memory is shown, where the timing frequency of the MBIST is a fraction of the memory operating frequency. Figure 7 For example, if the MBIST logic (e.g., the interface of the MBIST logic) operates at a frequency that is approximately half the frequency of the DDR memory device and data operations are performed at a double data rate (DDR) at the DDR memory, the MBIST logic needs to provide four words of data at each cycle of the MBIST clock 802. As illustrated, the four words of data are illustrated by data 804 or 806, and are data for both the phase 0 mode and the phase 1 mode (P0 and P1).

[0051] However, at the memory input, two data words are transferred during each cycle of the DDR clock 808. Thus, as shown by 810 and 812, DQ of phase P0 is transferred during the first cycle, and as can be seen by data 814 and 816, DQ of phase P1 is transferred during the second subsequent cycle.

[0052] It should also be noted that the strobe DQS consists of a write-enabled signal and can be transmitted on the DDR bus along with the write data. Depending on some configurations, the conversion FSM may take into account the timing of DQ and DQS.

[0053] Because of the features of the approximately 1:2 BIMC / DDR ratio discussed above, another aspect of the present disclosure is to provide phase control support to support phase control of the CA / DQ / IE (input enable) / OE (output enable) bus.

[0054] Since BIMC operates at about half the frequency of DDR, it is necessary to support issuing commands and data at either P0 or P1 phase. Thus, the present disclosure provides a phase support module in the MBIST logic (e.g., see Figure 4 Phase control logic or module 412 in 4 is used as an example) to shift the data / command / IE / OE, etc. by, for example, about half of the period of the BIMC clock (or a full period of the DDR DRAM clock). Fig. 9 As can be seen in FIG, when commands and data are issued on phase P0, no shifting is required. However, when the issuance of commands or data begins during phase 1, the phase 0 (P0) data is first switched for transmission, and the phase 1 (P1) is delayed or shifted by half a cycle in a single state pipeline, for example, to be transmitted during the next phase mode (e.g., P0), as shown in FIG. Fig.10 shown.

[0055] According to another aspect of the present disclosure, a mask control function and / or logic is provided (e.g., see Figure 4 In some embodiments, the exemplary logic 414 of DM bus is used to support several data mask (DM) sequence options (for example, DM sequence 0101-0101, 0011-0011, 0110-0110 or 0101-1010) for the different MBIST algorithms that can be performed. In a specific example, the MBIST native support of odd array write enable and even array write enable command has been modified to support several different data mask algorithms. According to an embodiment, the mask control feature is realized by the intelligent exchange of DM bus (being integrated into the BIMC system simultaneously). According to another aspect, mask control can be configured to be user selectable.

[0056] According to another aspect of the previous disclosure, the present disclosure provides programmable delay control for one or more signals (see, for example, Figure 4 ), rather than relying on hard-coded delays for each operation set for each operating frequency. In one aspect, programmable delay control can be provided for one or more of the following signals: write delay; read (rd_traffic, etc.) delay; read enable (Read_enable) delay; IE / OE programmable delay with phase control; programmable data polarity delay; inhibit data (Inhibit_data) comparison, or expect data (Expect_data) command selection, and strobe delay, to name a few examples. It should be noted that the hard-coded delays in previously known systems produce a large operation set area. The current programmable delay control provides a reduction in the operation set area of ​​approximately 30%. Further, it should be noted that the programmable delay control provides the ability to support several different delays (including JEDEC delays).

[0057] Fig.11 An exemplary method 1100 for implementing and operating MBIST in a BIMC is illustrated. As illustrated, the method 1100 includes: as shown in block 1102, initiating an MBIST operation in the BIMC. The initiation process of block 1102 may include: placing or generating MBIST logic (e.g., Figure 3 302 in ) and connect MBIST logic or make MBIST logic communicate with memory device or memory interface (for example, 104 and 206). As an example, the process of block 1102 can be implemented by BIMC 102 and other controllers or logic for issuing BIST enable signal 310.

[0058] The method 1100 also includes, as indicated at block 1104, using memory conversion logic (eg, 410, 500, 600) to convert one or more commands and data from the MBIST logic into signals formatted to be compatible with the DDR memory / memory interface when testing the memory device.

[0059] Further, method 1100 can also include MBIST logic, and MBIST logic is configured to operate under the frequency of MC or BIMC, wherein the frequency of MC operation is less than the operating frequency of at least memory device, and in one aspect, MBIST logic (for example, 112 or its component logic) is configured to receive the signal for testing under the frequency less than the operating frequency of memory device.In particular aspects, the operating frequency of BIMC and MBIST logic is approximately half the operating frequency of at least one memory device.When the operating frequency of BIMC and MBIST is half the frequency of memory device, MBIST logic is also configured to provide the data of the data at the output of the MBIST of approximately twice normal output to at least one memory device in each BIMC clock cycle.The data outputted by MBIST logic can include one or more of the following: CA signaling, CKE signaling, CS / signaling, DQ signaling or DQS signaling.

[0060] According to another aspect, MBIST logic can be configured to be incorporated in traditional BIMC, thereby avoids the demand to self-defined BIMC.As previously mentioned, this can be realized by using software tool, and this software tool can configure internal BIMC logic / circuit to configure MBIST logic or be used for MBIST logic.According to another aspect, disclosed conversion also is performed by memory conversion logic or memory representation, and this memory conversion logic or memory representation comprise the use of finite state machine (FSM), and this finite state machine comprises the conversion logic that is configured to convert command and data into the format compatible with memory device and the memory interface that is coupled between MBIST logic and memory device.

[0061] In another aspect, MBIST logic can also include phase control support logic, this phase control support logic is configured to issue at least one in command or data on any phase mode in first phase mode or second phase mode, this phase control support logic comprises switching mechanism, this switching mechanism is configured to half the approximately BIMC clock cycle of data bus and CA bus shift. In another aspect, MBIST logic also includes data mask control logic, this data mask control logic is configured to be used to depend on the programmable selection to data mask (DM) sequence of the specific algorithm of the type configuration for at least one memory device.Data mask control logic can also be configured to use group write enable function and switching mechanism to realize the required different DM sequences of self-defined algorithm.

[0062] In another aspect, the MBIST logic can also include a programmable delay control logic, which is configured to provide delay control for one or more signals in the MBIST.It should be noted that one or more signals include one or more of the following: write signal, read signal, read enable (Read_enable) signal, IE / OE programmable delay signal with phase control, programmable data polarity delay signal, prohibition data (Inhibit_data) comparison signal, data command selection signal and gating delay signal.In another aspect, the MBIST logic can also include a memory representation logic, which is configured to simulate local memory device to the MBIST logic.

[0063] Fig.12 The flowchart of another exemplary method 1200 for realizing MBIST in BIMC is illustrated. In method 1200, first process 1202 comprises: first in traditional BIMC (such as utilizing memory configuration tool or software / firmware) configure MBIST to realize MBIST logic, this MBIST logic comprises logic such as one or more in MBIST controller 402, MBIST interface logic 404 and memory representation 406 and the interface (such as being coupled to the TAP 408 of JTAG interface 316) for external instruction. Further, MBIST configuration can comprise the configuration of FSM and conversion logic 410 in memory representation 406.

[0064] After MBIST is configured in frame 1202, method 1200 also comprises: as shown in frame 1204, initiate MBIST operation, initiate this MBIST operation and comprise: MBIST is switched to be coupled to memory interface by communication.This process in frame 1204 can comprise: under the control of BIST enable signal 310, use multiplexer 208 in multiplexer 314 and memory interface 206 to carry out BIST and enable.

[0065] Still further, the method 1200 includes converting one or more commands / data from the MBIST logic into signals in a format recognized by the memory device for testing the memory device and for implementing a memory representation including both a write operation and a read operation.

[0066] Fig.131304 is a conceptual diagram illustrating an example of a hardware implementation for an exemplary user equipment (UE) 1300 or mobile station employing a processing system 1314. According to various aspects of the present disclosure, an element or any portion of an element or any combination of elements may be implemented by a processing system 1314 including one or more processors 1304. The processing system 1314 may be an architecture including a bus interface 1308, a bus 1302, a memory 1305 (e.g., one or more stacked LPDDR4 memories), a processor 1304, and a computer-readable medium 1306. Further, the UE 1300 may include a user interface 1312 and a transceiver 1310.

[0067] In some aspects of the present disclosure, processor 1304 may include MBIST (and BIMC) control circuit 1340, which is configured for various functions related to testing memory 1305. For example, circuit 1340 may be configured to implement the above-mentioned Figures 2 to 12 One or more of the functions or circuits / logics described. Further, one or more of the processing system 1314, the processor 1304 and / or the MBIST control circuit 1340 and their equivalents may constitute a device for setting, configuring, establishing or determining an MBIST control for testing a DDR memory.

[0068] In some other aspects of the present disclosure, the processor 1304 may include MBIST configuration logic or circuit 1342, which is configured to be used for various functions related to configuring MBIST. For example, the circuit 1340 may be configured to implement the above Figures 2 to 12 One or more of the functions or circuits / logics described. Further, one or more of the processing system 1314, the processor 1304 and / or the MBIST configuration logic 1342 and their equivalents may constitute a device for setting, configuring, establishing or determining an MBIST control for testing a DDR memory.

[0069] One or more processors 1304 in the processing system 1314 can execute software. Software should be broadly interpreted as meaning instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, processes, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language or other forms. The software can reside on a computer-readable medium 1306. The computer-readable medium 1306 can be a non-transitory computer-readable medium. Non-transitory computer-readable media include, for example, magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips), optical disks (e.g., compact disks (CDs) or digital versatile disks (DVDs)), smart cards, flash memory devices (e.g., cards, sticks, or key drives), random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), registers, removable disks, and any other suitable medium for storing software and / or instructions that can be accessed and read by a computer. For example, computer readable media may also include carrier waves, transmission lines, and any other suitable media for transmitting software and / or instructions that can be accessed and read by a computer. Computer readable media 1306 may reside in processing system 1314, outside processing system 1314, or distributed in multiple entities including processing system 1314. Computer readable media 1306 may be embodied in a computer program product. By way of example, a computer program product may include a computer readable medium in a packaging material. Those skilled in the art will recognize how to best implement the described functions given throughout this disclosure based on specific applications and the overall design constraints imposed on the entire system.

[0070] In one or more examples, the computer-readable storage medium 1306 may include software or code 1352 configured for various functions including, for example, setting, configuring, establishing, or determining an MBIST test for a DDR memory (such as a stacked LPDDR4 memory). For example, the software or code 1352 may be configured to implement the above description of Figures 2 to 12 One or more of the described functions, including for example Fig.11 Frame 1104 in the FIG.

[0071] Medium 1306 can also include software or code 1354, and software or code 1354 is configured to be used for various functions, and these functions include for example setting, configuration or setting up MBIST controller.For example, software or code 1354 can be configured to realize above about Figures 2 to 12 One or more of the described functions, including for example Fig.12 Frame 1202 in the FIG.

[0072] In other aspects, the apparatus that can be implemented in UE 1300 may include a memory (e.g., 1305), which receives one or more instructions for testing the memory, wherein the instruction includes a command for initiating an MBIST operation in a memory controller (MC), and initiating the MBIST operation includes: enabling MBIST logic to communicate with a memory device. Further, the instruction may include a command for converting one or more commands and data from the MBIST logic for testing the memory device into a signal whose format is compatible with the memory device using a memory conversion logic.

[0073] In view of the foregoing, it should be appreciated by those skilled in the art that the currently disclosed method and apparatus provide a memory test controller design that implements and supports extensive algorithm testing of stacked memory and LPDDR4 memory in a specific example, wherein the memory test controller can be added to an existing design with minimal modifications. Further, since the conversion FSM and MBIST are used for the memory decoder as discussed above, MBIST can be used to support DDR compatible operations. Further still, split LPDDR4 commands can be easily supported (e.g., activate-1-activate-2, Write-1-cas-2, etc.). Additionally, in the case of LPDDR4, specific operations (such as data bus inversion (DBI) features) or vendor-specific test modes and operations (such as die-id reading) can be easily supported by the present method and apparatus.

[0074] Moreover, those skilled in the art will appreciate that calibration-related LPDDR4 operations (eg, DQ calibration, DQ latching, MPC calibration, etc.) may be supported. In addition, byte-specific MRR reading is enabled.

[0075] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Fig.11 and / or Fig.12 One or more of the components, steps, features and / or functions illustrated in the drawings may be rearranged and / or combined into a single component, step, feature or function, or embodied as several components, steps or functions. Additional elements, components, steps and / or functions may also be added without departing from the present invention.

[0076] One or more of the components, steps, features and / or functions shown in the accompanying drawings may be rearranged and / or combined into a single component, step, feature or function, or embodied as several components, steps or functions. Additional elements, components, steps and / or functions may also be added without departing from the novel features disclosed herein. The devices, equipment and / or components shown in the figures may be configured to perform one or more of the methods, features or steps described in the figures. The novel algorithms described herein may also be effectively implemented in software and / or embedded in hardware.

[0077] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, then objects A and C may still be considered coupled to each other even if they are not in direct physical contact with each other.

[0078] In addition, it should be noted that the embodiments can be described as a process, which is depicted as a flow chart, a flow diagram, a structure diagram or a block diagram. Although the flow chart can describe the operation as a sequential process, many operations in the operation can be performed in parallel or simultaneously. In addition, the order of operations can be rearranged. When its operation is completed, the process terminates. A process can correspond to a method, a function, a process, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination corresponds to the function returning to the calling function or the main function.

[0079] In addition, the storage medium can represent one or more devices for storing data, including read-only memory (ROM), random access memory (RAM), disk storage medium, optical storage medium, flash memory device, and / or other machine-readable media for storing information. The term "computer-readable medium", "machine-readable medium" or "machine-readable storage medium" includes but is not limited to portable or fixed memory devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying (multiple) instructions and / or data. Further, in various aspects of the present disclosure, a non-transient computer-readable medium for storing computer executable code can be provided. This code can be configured to enable a computer: implement a memory built-in self-test (MBIST) function or an equivalent logic function configured to test at least one memory device in a memory controller (MC). Further, the code can enable a computer to use the MBIST function to convert a signal for testing at least one memory device into a signal of a format used by at least one memory device.

[0080] Further, the embodiment can be implemented by hardware, software, firmware, middleware, microcode or any combination thereof. When implemented with software, firmware, middleware or microcode, the program code or code segment for performing the necessary tasks can be stored in a machine-readable medium such as a storage medium or (multiple) other storage devices. The processor can perform the necessary tasks. The code segment can represent any combination of a process, function, subroutine, program, routine, subroutine, module, software package, class or instruction, data structure or program statement. By transmitting and / or receiving information, data, independent variables, parameters or memory contents, the code segment can be coupled to another code segment or hardware circuit. Information, independent variables, parameters, data, etc. can be transmitted, forwarded or transmitted via any suitable means, and these suitable means include memory sharing, message passing, token passing, network transmission, etc.

[0081] The various illustrative logical blocks, modules, circuits (e.g., processing circuits), elements, and / or components described in conjunction with the examples disclosed herein may be implemented or executed by a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing components, for example, a combination of a DSP and a microprocessor, several microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration.

[0082] The method or algorithm described in conjunction with the examples disclosed herein may be embodied in hardware, in a software module that can be executed by a processor, or in a combination of the two in the form of a processing unit, programming instructions or other directions, and may be contained in a single device or distributed in multiple devices. The software module may reside in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. A storage medium may be coupled to a processor so that the processor can read information from the storage medium and can write information to the storage medium. Alternatively, the storage medium may be integrated with the processor.

[0083] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps are generally described above in terms of their functions. Whether such functions are implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system.

[0084] Without departing from the present invention, the various features of the present invention described herein can be implemented in different systems. It should be noted that the foregoing aspects of the present disclosure are merely examples and should not be interpreted as limiting the present invention. The description of the various aspects of the present disclosure is intended to be illustrative, rather than limiting the scope of the claims. Thus, this teaching can be easily applied to other types of devices, and many alternatives, modifications and variations are apparent to those skilled in the art.

Claims

1. A device comprising: A memory controller MC, wherein the memory controller MC comprises: A memory built-in self-test MBIST controller is configured to test at least one memory device, wherein the MBIST controller comprises: a memory representation logic comprising a memory conversion logic configured to convert a signal for testing the at least one memory device into a converted signal having a format used by the at least one memory device, and wherein the memory representation logic is further configured to provide a memory representation that simulates a local memory in the MBIST controller, Wherein the MBIST controller is further configured to: receive the signal for testing at a frequency less than an operating frequency of the at least one memory device. 2 . The apparatus according to claim 1 , wherein a frequency of the signal used for testing is half of the operating frequency of the at least one memory device or a memory interface of the at least one memory device.

3. device according to claim 2, wherein said MBIST controller is configured to: in each MC clock cycle, provide twice the data output of the data input to said at least one memory device at the output of said MBIST controller.

4. device according to claim 3, wherein the described data exported by described mbist controller comprise one or more in the following: command address CA signaling, clock enable CKE signaling, chip select CS signaling, data DQ signaling or data strobe DQS signaling.

5. device according to claim 1, wherein said memory conversion logic comprises finite state machine FSM, said finite state machine FSM comprises the conversion logic that is configured to command and data are converted to the format compatible with said at least one memory device and memory interface, and said memory interface is coupled between said mbist controller and said at least one memory device.

6. device according to claim 1, described MBIST controller also comprises: Phase control support logic is configured to issue at least one of a command or data in either a first phase mode or a second phase mode, the phase control support logic including a switching mechanism configured to shift both the data bus and the CA bus by half of the MC clock cycle.

7. device according to claim 1, described MBIST controller also comprises: A data mask control logic is configured for programmable selection of a data mask DM sequence dependent on a specific algorithm configured for a type of the at least one memory device. 8 . The apparatus of claim 7 , wherein the data mask control logic is further configured to use a group write enable and a swap mechanism to implement different DM sequences required by a custom algorithm.

9. device according to claim 1, described MBIST controller also comprises: Programmable delay control logic is configured to provide delay control for one or more signals in the MBIST controller.

10. The device according to claim 9, wherein the one or more signals include one or more of the following: a write signal, a read signal, a read enable signal, an input enable IE / output enable OE programmable delay signal with phase control, a programmable data polarity delay signal, a data comparison disable signal, a data command selection signal, and a selection delay signal.

11. The device according to claim 1, wherein the device further comprises: A host computer including the MC.

12. The device according to claim 11, comprising: at least one memory; A communicative coupling is provided, wherein the communicative coupling is configured to communicate the signal from the at least one memory device for testing the at least one memory device.

13. The apparatus according to claim 12, further comprising: One of a mobile phone and a mobile communication device comprises the host, the communicative coupling, and the at least one memory.

14. A method for testing a memory device, comprising: Initiating a memory built-in self-test MBIST operation in the memory controller MC, initiating the MBIST operation comprises: enabling MBIST logic to communicate with at least one memory device, the MBIST logic comprising memory representation logic, the memory representation logic comprising memory conversion logic; and Utilizing the memory conversion logic, converting one or more commands and data from the MBIST logic for testing the at least one memory device into converted signals, the converted signals having a format compatible with the at least one memory device, and utilizing the memory representation logic to provide a memory representation that simulates a local memory in the MBIST logic, The MBIST logic is further configured to operate at a frequency of the MC, wherein the frequency at which the MC operates is less than an operating frequency of the at least one memory device or a memory interface of the at least one memory device.

15. The method of claim 14, wherein the frequency of operation of the MC and the MBIST logic is half the operating frequency of the at least one memory device.

16. The method of claim 15, wherein the MBIST logic is configured to provide a data output at the output of the MBIST logic that is twice the data input to the at least one memory device during each MC clock cycle.

17. The method of claim 16, wherein the data output by the MBIST logic comprises one or more of: CA signaling, CKE signaling, CS signaling, DQ signaling, or DQS signaling.

18. The method of claim 14, wherein the MBIST logic is configured to be incorporated into a conventional bus integrated memory controller (BIMC).

19. method according to claim 14, wherein said conversion utilizes memory conversion logic to perform, and said memory conversion logic comprises a finite state machine FSM, and said finite state machine FSM comprises a conversion logic configured to convert command and data into a format compatible with said at least one memory device and a memory interface, and said memory interface is coupled between said MBIST logic and said at least one memory device.

20. according to the method of claim 14, described MBIST logic also comprises: Phase control support logic is configured to issue at least one of a command or data in either a first phase mode or a second phase mode, the phase control support logic including a switching mechanism configured to shift both the data bus and the CA bus by half of the MC clock cycle.

21. according to the method of claim 14, described MBIST logic also comprises: A data mask control logic is configured for programmable selection of a data mask DM sequence dependent on a specific algorithm configured for a type of the at least one memory device.

22. according to the method of claim 14, described MBIST logic also comprises: The programmable delay control logic is configured to provide delay control for one or more signals in the MBIST logic.

23. An apparatus comprising: A memory, receiving one or more instructions for testing the memory, the instructions comprising: A command for initiating a memory built-in self-test MBIST operation in a memory controller MC, wherein initiating the MBIST operation comprises: enabling MBIST logic to communicate with the memory; Utilize memory conversion logic to convert one or more commands and data from the MBIST logic for testing the memory into commands of converted signals, the converted signals having a format compatible with the memory; and instructions for providing, using memory representation logic, a memory representation that emulates a local memory in said MBIST logic, Wherein the MBIST operation is further configured to: receive the signal for testing at a frequency less than an operating frequency of the memory.

24. A non-transitory computer readable medium storing computer executable code, comprising code for causing a computer to perform the following operations: Implementing a memory built-in self-test MBIST function in the memory controller MC, wherein the memory built-in self-test MBIST function is configured to test at least one memory device; Using the MBIST function, converting a signal used to test the at least one memory device into a converted signal having a format used by the at least one memory device; as well as providing a representation of a local memory in emulating said MBIST function using a memory representation function, said memory representation function being part of said MBIST function, The non-transitory computer-readable medium also includes code for causing a computer to receive the signal for testing at a frequency less than an operating frequency of the at least one memory device.

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