FPGA-based FIFO interface multi-channel DMA controller

Abstract

The application discloses a FIFO interface multi-channel DMA controller based on FPGA, which comprises an input data distribution module, an input data cache module, an output data distribution module, an output data cache module, a DMA scheduling module, a DDR output module and a DDR interface module; is used for caching multi-channel high-speed data of multiple data sources in a memory, does not occupy on-chip RAM resources of the FPGA, realizes parallel, independent and efficient storage and storage of multi-channel data, a data interaction interface is a standard FIFO interface, a user does not need to care about complex DDR3 / 4 (Double Data Rate) interface timing and multi-channel data scheduling, programming is realized by using a hardware description language, parameterization configuration is adopted, other FPGA platforms are compatible, the application can be called in FPGA design as an IP, a development cycle is shortened, and development efficiency is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of DMA control, and particularly relates to a FIFO interface multi-channel DMA controller based on FPGA. BACKGROUND

[0002] In a modern computer system or an embedded system, a DMA controller provides a method for allowing a peripheral device to access system memory without CPU intervention. When the peripheral device needs to transmit a data block, the CPU configures address information, data size, interrupt mode, etc. for the DMA controller, and then the peripheral device and the DMA controller complete data transmission, and finally generate an interrupt to notify the CPU of the completion of transmission. The emergence of the DMA controller greatly improves the working efficiency of the CPU, so that the CPU can focus on scheduling, calculation and other operations, and is freed from time-consuming data migration.

[0003] In some specific scenarios in the industrial and defense fields, a system integrates a network, multiple high-definition cameras, multiple optical fibers and other interfaces, has multiple working modes for dynamic switching, generates a large amount of multi-channel high-speed data that needs to be cached or stored in real time, and the general DMA controller has problems such as the need for CPU cooperation for initialization and interrupt response during work, low efficiency for multi-channel access, complex configuration process, occupation of more resources, poor portability and the like. The FIFO interface multi-channel DMA controller based on FPGA can effectively solve these problems, cache multi-channel high-speed data of multiple data sources in memory without occupying on-chip RAM (Random Access Memory) resources of the FPGA, realize parallel, independent and efficient storage and storage of multi-channel data, the data interaction interface is a standard FIFO interface, pure logic programming is realized, parameterized configuration is adopted, other FPGA platforms are compatible, and the FIFO interface multi-channel DMA controller based on FPGA can be called as an IP (Intellectual Property). SUMMARY

[0004] In order to overcome the deficiencies of the prior art, the application provides a FIFO interface multi-channel DMA controller based on FPGA, which comprises an input data distribution module, an input data caching module, an output data distribution module, an output data caching module, a DMA scheduling module, a DDR output module and a DDR interface module; is used for caching multi-channel high-speed data of multiple data sources in memory without occupying on-chip RAM resources of the FPGA, realizing parallel, independent and efficient storage and storage of multi-channel data, and taking a standard FIFO interface as a data interaction interface. Users do not need to care about complex DDR3 / 4 (Double Data Rate) interface timing and multi-channel data scheduling, pure hardware description language programming is adopted, parameterized configuration is adopted, other FPGA platforms are compatible, the FIFO interface multi-channel DMA controller based on FPGA can be called as an IP in FPGA design, the development cycle is shortened, and the development efficiency is improved.

[0005] The technical scheme adopted by the present application to solve its technical problems is as follows:

[0006] A FIFO interface multi-channel DMA controller based on FPGA, comprising a data distribution module and a DMA control module; the data distribution module comprises an input data distribution module, an input data cache module, an output data distribution module and an output data cache module; the DMA control module comprises a DMA scheduling module, a DDR output module and a DDR interface module; the FIFO interface multi-channel DMA controller based on FPGA comprises m input data sources, n input data channels and p output data channels;

[0007] The input data distribution module is used for selecting and distributing the input data, and outputs p-channel data to the input data cache module;

[0008] The input data cache module is a p-asynchronous FIFO module, which is used for clock domain conversion, data bit width conversion and caching of the p-channel data output by the input data distribution module, so as to be read out by the DMA control module for next processing;

[0009] The output data cache module is a p-asynchronous FIFO module, which is used for clock domain conversion, data bit width conversion and caching of the data output by the DDR output module, so as to be read out by the output data distribution module for next processing;

[0010] The output data distribution module is used for selecting and distributing the p-channel data output by the output data cache module; according to different working modes, the p-channel data or output is processed subsequently, or the p-output channel data is distributed into n channels and then output at a designated interface;

[0011] The DMA scheduling module is used for polling writing or reading out data in the memory of the p channel; the FIFO data amount in the input data buffer module is monitored in real time, and when the pre-set read-write burst operation block size B is reached, the DMA write operation is started, the corresponding FIFO data is continuously written into the memory area, and other channels are continuously polled; meanwhile, the data amount written into different memory areas is monitored in real time, and when the pre-set read burst operation block size S is reached, the read operation of the corresponding memory area is started, the data amount continuously read by each read burst operation is B, other memory areas are continuously polled, and B size data amount is continuously read in the current area; a pair of logical read-write addresses is defined for each memory area, the start address and the end address are set, when the read-write address reaches the end address, the start address is jumped to, a ring buffer area is formed, the data amount written and read in the memory is represented by a counter value, the current written or readable data amount in the memory area is represented by the difference value of the counter, and the read-write operation is not directly judged by the read-write address, the read-write operation is logically independent and does not affect each other; when the write rate is greater than the read rate, the read-write monitoring threshold is set, the readable burst block size number in the memory area is monitored in real time, when the read-write monitoring threshold is exceeded, the input data distribution module is fed back to no longer write more data into the input data buffer module, and when the read-write monitoring threshold is less than the read-write monitoring threshold, the write buffer operation is started; when the read rate is greater than the write rate, the read operation is started when the data amount written in the memory area is greater than or equal to the read burst block size, and the written data is valid when the condition is not met, only the write pointer is updated.

[0012] The DDR output module is used for distributing the data output by the DDR interface module; the DDR output module comprises two synchronous FIFOs which are respectively used for reading operation command buffering and reading data buffering, a signal with a marked memory area is written into the command buffer after one reading operation, the data output by the DDR is written into the reading data buffer, when the command buffer is not empty, a signal is read out, the data of a specified size is read out from the data buffer and output to the corresponding data channel of the output data distribution module, the next signal is read out from the command buffer, and the cycle is repeated; the reading operation and the reading data are synchronized;

[0013] The DDR interface module is used for realizing the DDR interface timing; the DDR interface module signal comprises a control signal, a command signal, an address signal and a data signal; when the control signals app_rdy and app_en are pulled high at the same time, the address signal app_addr and the command signal app_cmd are given, when the control signals app_wdf_rdy and app_wdr_wren are pulled high at the same time, the data signal app_wdf_data is given, and one writing operation is completed; when the control signals app_rdy and app_en are pulled high at the same time, the command signal app_cmd is given, when app_rd_data_valid is valid, the data appears on the reading data bus, and one reading operation is completed.

[0014] Preferably, the m, n, p are positive integers not more than 16.

[0015] The beneficial effects of the present application are as follows:

[0016] (1) The present application encapsulates the memory into multiple independent virtual channels, and after simple parameterized configuration, it can realize the high-speed and independent caching of multi-channel data in different areas of the memory in multiple working modes.

[0017] (2) The present application encapsulates the interface into a standard FIFO interface, and the user does not need to care about the complex DDR interface timing, and can be called as an IP, which is convenient for integration and use in the system.

[0018] (3) The present application is designed based on a hardware description language, and does not need CPU cooperation during work, runs on FPGA, occupies less resources, and has high running efficiency.

[0019] (4) The present application adopts modular design, is suitable for different manufacturers and different models of FPGA, and has strong flexibility and portability. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is the overall block diagram of the multi-channel DMA controller of the present application.

[0021] Figure 2 is the memory read-write address control schematic diagram of the present application.

[0022] Figure 3 is the multi-channel DMA controller state machine jump schematic diagram of the present application.

[0023] Figure 4 is the resource occupation diagram of the multi-channel DMA controller of the present application.

[0024] Figure 5 is the read-write rate test diagram of the multi-channel DMA controller of the present application.

[0025] Figure 6 is the application example block diagram of the multi-channel DMA controller of the present application.

[0026] Figure 7 is the test example diagram of the multi-channel DMA controller of the present application. DETAILED DESCRIPTION

[0027] The present application will be further described below in combination with the drawings and examples.

[0028] The FIFO interface multi-channel DMA controller based on FPGA comprises a data distribution module and a DMA control module; the data distribution module comprises an input data distribution module, an input data cache module, an output data distribution module and an output data cache module; the DMA control module comprises a DMA scheduling module, a DDR output module and a DDR interface module; the FIFO interface multi-channel DMA controller based on FPGA comprises m input data sources, n input data channels and p output data channels; m, n and p are positive integers not greater than 16;

[0029] The input data distribution module is used for selecting and distributing input data; in different working modes, input data sources are different, input data channels are different, and required output data channels are also different; the input data distribution module distributes input data under different combinations of M input data sources, N input data channels and P output data channels, and outputs p-channel data to the input data cache module;

[0030] The input data cache module is a p asynchronous FIFO module, which is used for clock domain conversion, data bit width conversion and caching of p-channel data output by the input data distribution module, so as to read out the data by the DMA control module for next processing;

[0031] The output data cache module is a p asynchronous FIFO module, which is used for clock domain conversion, data bit width conversion and caching of data output by the DDR output module, so as to read out the data by the output data distribution module for next processing;

[0032] The output data distribution module is used for selecting and distributing p-channel data output by the output data cache module; according to different working modes, P-channel data or output is processed subsequently, or p-output-channel data is distributed as n channels and then output at a specified interface;

[0033] The DMA scheduling module is used for polling writing or reading in the memory for the data of the p channel; the FIFO data amount in the input data buffer module is monitored in real time, and when the pre-set read-write burst operation block size B is reached, the DMA write operation is started, the corresponding FIFO data is continuously written into the memory area, and other channels are continuously polled; meanwhile, the data amount written into different memory areas is monitored in real time, and when the pre-set read burst operation block size S is reached, the read operation of the corresponding memory area is started, the data amount continuously read by each read burst operation is B, other memory areas are continuously polled, and B size data amount is continuously read in the current area; a pair of logical read-write addresses is defined for each memory area, the start address and the end address are set, when the read-write address reaches the end address, the start address is jumped to, a ring buffer area is formed, the data amount written and read in the memory is represented by a counter value, the current written or readable data amount in the memory area is represented by the difference value of the counter, and is not directly judged by the read-write address, so that the data amount calculation error caused by the address boundary jump is avoided, the read-write operation is independently operated in logic, and does not affect each other; the DMA scheduling module is limited by the use scene, and the read-write rate may not match: when the write rate is greater than the read rate, the write address pointer reaches the read address pointer after traversing the memory area once, so that the data in the memory area is not read out in time and is covered, the read-write monitoring threshold is set, the readable burst block size number in the memory area is monitored in real time, when the read-write monitoring threshold is exceeded, the input data distribution module is fed back to no longer write more data into the input data buffer module, and when the read-write monitoring threshold is less than the read-write monitoring threshold, the write buffer operation is started; when the read rate is greater than the write rate, the read pointer catches up with or exceeds the write pointer, so that the invalid data in the memory area is read out, the read operation is started when the data amount written in the memory area is greater than or equal to the read burst block size, and the condition is not met, only the write pointer is updated, and the read data is effective.

[0034] The DDR output module is used for distributing the data output by the DDR interface module; due to the physical characteristics of the DDR device, after the read command is given, a period of time is delayed, and then the effective data appears on the bus, the DMA control module is high-speed polled for read-write operation according to the set condition, and the read operation is out of synchronization with the read data; the DDR output module includes two synchronous FIFOs, which are respectively used for reading operation command buffer and reading data buffer, after one read operation, the signal with the marked memory area is written into the command buffer, the data output by the DDR is written into the reading data buffer, when the command buffer is not empty, a signal is read out, then the specified size data is read out from the data buffer and output to the corresponding data channel of the output data distribution module, and then the next signal is read out from the command buffer, and the cycle is repeated; the read operation is synchronized with the read data.

[0035] The DDR interface module is used for realizing DDR interface timing; the DDR interface module signal comprises: control signal, command signal, address signal and data signal; when the control signals app_rdy and app_en are pulled up simultaneously, the address signal app_addr and the command signal app_cmd are given, when the control signals app_wdf_rdy and app_wdr_wren are pulled up simultaneously, the data signal app_wdf_data is given, and once write operation is completed; when the control signals app_rdy and app_en are pulled up simultaneously, the command signal app_cmd is given, when app_rd_data_valid is valid, data appears on the read data bus, and once read operation is completed. Specific embodiments:

[0037] Figure 1 The figure shows the overall block diagram of the multi-channel DMA controller of the application, the data of multiple data sources is outputted to a certain data source data after being selected by the input data distribution module according to the current working mode, and is sequentially punched into the corresponding FIFO of the input data cache module in clock beats for caching, each FIFO corresponds to a logical area in the memory; the DMA control module polls the data amount in each FIFO, when the burst size set by the pre-parameters is reached, the data is continuously taken out and written into the corresponding memory area; at the same time, the data amount written in each memory area is monitored in real time, when the read burst size set by the pre-parameters is reached, the burst read operation is started, the burst size set by the pre-parameters is continuously read, the read data is written into the corresponding FIFO cache of the output data cache module after being selected by the output data distribution module according to the current working mode, and then subsequent processing is carried out, and the multiple channels read and write alternately.

[0038] Figure 2The memory read-write address control schematic diagram is shown, first, according to the parameter setting data channel number P, the memory space is divided into P logical regions, each logical region defines a read-write address pointer; The core is to maintain the read-write pointer, to meet the condition that the data amount in the FIFO in the input data buffer module is greater than or equal to the read-write burst block size, to start the write operation of the corresponding channel, the data in the memory region is enough for a read burst block size, to start the read operation of the corresponding channel, each read operation is in units of read-write block size, in addition, three cases must be considered, one is that the write rate is greater than the read rate, the write address pointer jumps to the read address pointer after one round, causing the data in the memory region to be overwritten without being read out in time, the application sets a threshold, which monitors the number of readable burst blocks in the memory region in real time, when the threshold is exceeded, the input data distribution module no longer writes more data to the input data buffer module, when the threshold is less than the threshold, the input data distribution module writes operation is started again; Two is that the read rate is greater than the write rate, the read address pointer catches up with or exceeds the write address pointer, causing invalid data in the memory region to be read out, the application sets a read burst operation block size, which monitors the amount of data written in the memory region in real time, and starts the read operation when the amount of data is greater than or equal to the read burst operation block size, if the condition is not met, only the write address pointer is updated, to ensure that the read data is valid; Three is the read-write address boundary processing, the memory is divided into P logical regions, the read-write address is added to the region boundary and jumps to the initial address, forming a circular cache region, the amount of data written and read in the memory is represented by a counter value, not directly generated by the read-write address, to avoid calculation error of the amount of written data when the address boundary jumps.

[0039] Figure 3 The multi-channel DMA controller state machine jump schematic diagram is shown, the control state machine jumps between multiple states according to the design to complete the read-write of multi-channel data and corresponding memory region. According to the parameter setting data channel number p, there are 2p+2 states. An idle IDLE state is used to determine whether the write operation condition is met, a waiting WAIT state is used to determine whether the read operation condition is met, p write states and p read states are respectively corresponding to the read-write operation of p channel data. Assuming that 4 channels are set, the state machine jump conditions are shown in the following table:

[0040] Table 1 state machine jump condition table

[0041]

[0042]

[0043]

[0044] Figure 4It is a multi-channel DMA controller resource occupation figure, and the application is designed by using a hardware description language, synthesized, laid out and wired by using EDA (Electronic Design Automation) software, and generated into a programmable file, and then downloaded by using JTAG (Joint Test Action Group) to run on an FPGA chip. Figure 4 It indicates resource occupation on a Xilinx Kintex7 325T FFG900 platform.

[0045] Figure 5 It is a multi-channel DMA controller read-write rate test figure, and data d is written and read out in t time, so that the actual rate of the controller is The theoretical rate of the memory is k = 400 MHz * 2 * 64 bit = 50 B / s = 6.25 B / s; and the efficiency of the controller is s ÷ k = 48%.

[0046] Figure 6 It is a multi-channel DMA controller application example block diagram, and the specific steps are as follows:

[0047] 1) Set the working mode and parameters, set the data source M = 2, which is from a network and an optical fiber respectively; the input data channel number N = 1, and the output data channel number P = 4, which correspond to four memory areas and four solid state disks respectively; the back-end storage system is composed of four SSDs to form a RAID0 array. There are four working modes, which are network import, network export, optical fiber import and optical fiber export respectively; and the network import is taken as an application example for description;

[0048] 2) Data distribution, after the working mode is selected, the corresponding data source is selected through the input data distribution module, and the data received by the network is written into the corresponding four FIFOs of the input data cache module in a round-robin manner under the control of the input data distribution module; and the data distribution rule also determines the data distribution rule when the network is exported;

[0049] 3) Four-channel data DMA writes into a memory area, when the data amount in the four FIFOs of the input data cache module reaches the burst write size (4 KB) of the DMA, the state machine starts the burst write memory operation, and the data is written into the corresponding memory area in a 4 KB block size in a round-robin manner;

[0050] 4) Four-channel data DMA reads from a memory area, when the data amount written in the memory area reaches the burst read size (256 KB) and the back-end read FIFO is not full, the state machine starts the burst read memory operation, and the data is read from the corresponding memory area in a 4 KB block size in a round-robin manner;

[0051] 5) Reading data channel marking and distribution: Memory read operations suffer from timing discrepancies between commands and data. That is, after a read command is given, data may appear on the memory bus several clock cycles later. When read operations occur discontinuously across multiple memory regions, the correspondence between the read data and the channel is lost. This invention designs a command cache and a data cache. Read commands are marked and written to the command cache, while data is directly sent to the data cache. Then, based on the markings retrieved from the command cache, the corresponding data is retrieved and written to the read FIFO, thus re-establishing the correspondence between data and the channel.

[0052] 6) 4-channel data writing to SSD: Data is read from memory and written to the read FIFO while data is retrieved from the read FIFO and written to the SSD. The 4 channels are in parallel. When the read FIFO is almost full, a feedback signal is generated to indicate that the corresponding memory area should pause read burst operations.

[0053] 7) The DMA controller is reset, and all levels of cache, logic modules and state machines are reset, returning to the initial state, and one network import is completed.

[0054] Figure 7 This is a test example diagram of a multi-channel DMA controller. The test software was used to complete functions such as setting the working mode and parameters, issuing start and stop commands, sending and receiving network data, etc. In fiber optic import mode, four SSDs formed a RAID 0 array. According to the test results, the speed reached 1.49GB / s, basically reaching the maximum value of SSDs.

Claims

1. An FPGA-based FIFO interface multi-lane DMA controller, characterized in that, The application relates to a multi-channel DMA controller based on a FIFO interface of FPGA, which comprises a data distribution module and a DMA control module; the data distribution module comprises an input data distribution module, an input data cache module, an output data distribution module and an output data cache module; the DMA control module comprises a DMA scheduling module, a DDR output module and a DDR interface module; the multi-channel DMA controller based on the FIFO interface of FPGA comprises m input data sources, n input data channels and p output data channels; The input data distribution module is used for selecting and distributing input data and outputting p-channel data to the input data cache module; The input data cache module is a p-asynchronous FIFO module, which is used for clock domain conversion, data bit width conversion and caching of the p-channel data output by the input data distribution module, so as to provide the DMA control module with the next step of processing; The output data cache module is a p-asynchronous FIFO module, which is used for clock domain conversion, data bit width conversion and caching of the data output by the DDR output module, so as to provide the output data distribution module with the next step of processing; The output data distribution module is used for selecting and distributing p-channel data output by the output data cache module; according to different working modes, the p-channel data or output is subjected to subsequent processing, or the p-output channel data is distributed into n channels and then output at a designated interface; The DMA scheduling module is used for polling writing or reading of the p-channel data in the memory; the FIFO data amount in the input data cache module is monitored in real time, and when the read-write burst operation block size B reaches a preset value, the DMA write operation is started, the corresponding FIFO data is continuously written into a memory area, and then other channels are continuously polled; meanwhile, the data amount written into different memory areas is monitored in real time, and when the read burst operation block size S reaches a preset value, the read operation of the corresponding memory area is started, the data amount continuously read by each read burst operation is B, other memory areas are continuously polled, and then the data amount of B size is continuously read in the current area; a pair of logical read-write addresses is defined for each memory area, the start address and the end address are set, when the read-write address reaches the end address, the start address is jumped to, a ring-shaped cache area is formed, the data amount written into and read out of the memory is represented by a counter value, the current data amount written or readable in the memory area is represented by the difference value of the counter, and the read-write operation is not directly judged by the read-write address, the read-write operation is logically independent and does not affect each other; when the write rate is greater than the read rate, a read-write monitoring threshold is set, the readable burst block size number in the memory area is monitored in real time, when the readable burst block size number exceeds the read-write monitoring threshold, the input data distribution module is fed back to stop writing more data into the input data cache module, and when the readable burst block size number is smaller than the read-write monitoring threshold, the write cache operation is started; when the read rate is greater than the write rate, the read operation is started when the data amount written into the memory area is greater than or equal to the read burst block size, and only the write pointer is updated when the condition is not met, so that the read data is valid. The DDR output module is used for distributing the data output by the DDR interface module; the DDR output module contains two synchronous FIFOs respectively used for reading operation command cache and reading data cache, a signal with a marked memory area is written into the command cache after a reading operation, the data output by the DDR is written into the reading data cache, when the command cache is not empty, a signal is read out, then the data of a specified size is read out from the data cache and output to the corresponding data channel of the output data distribution module, then the next signal is read out from the command cache, and the cycle is repeated; the reading operation and the reading data are synchronized; The DDR interface module is used for realizing the DDR interface timing; the DDR interface module signal contains: a control signal, a command signal, an address signal and a data signal; when the control signals app_rdy and app_en are pulled up at the same time, the address signal app_addr and the command signal app_cmd are given out, when the control signals app_wdf_rdy and app_wdr_wren are pulled up at the same time, the data signal app_wdf_data is given out, and a writing operation is completed; when the control signals app_rdy and app_en are pulled up at the same time, the command signal app_cmd is given out, when app_rd_data_valid is valid, the data appears on the reading data bus, and a reading operation is completed.

2. The FIFO interface multi-lane DMA controller based on FPGA according to claim 1, wherein, The m, n and p are positive integers not greater than 16.

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