A Three-Color PIN Photodiode Array for Visible Light Communication and Its Preparation Method

Abstract

The present invention discloses a three-color PIN photodiode array for visible light communication and a preparation method thereof. The three-color PIN photodiode array for visible light communication includes a chip and a 3×3 red, green, and blue three-color PIN photodiode array integrated on an SiO2 layer in the chip. The red, green, and blue three-color PIN photodiode array is arranged in the y-axis direction in sequence as a green photodiode, a red photodiode, and a blue photodiode, and in the x-axis direction as a monochromatic photodiode. The three-color PIN photodiode array for visible light communication according to the present invention integrates photodiodes of three colors on the same chip. At the same time, the thicknesses of the three-color PIN photodiodes are consistent and very thin. The structure of the present invention enhances the integration degree of the device, reduces the device volume, and improves the response bandwidth and quantum efficiency of the device.

Description

Technical Field

[0001] The present invention relates to the field of optical communication devices, and more specifically, to a three-color PIN photodiode array for visible light communication and a preparation method thereof. Background Art

[0002] Visible light communication (VLC) can take into account both lighting and communication at the same time, effectively improving the energy utilization efficiency and meeting the energy-saving and green requirements of future communication systems. Since the VLC spectrum resource is rich, it can effectively alleviate the problem of the shortage of wireless communication spectrum resources. And the performance of the receiving link of VLC is one of the main parameters for evaluating the quality of a VLC system. Since the sensitivity spectral range of silicon is between 380 nm and 1100 nm, the visible light detectors of VLC systems are mainly silicon-based photodiodes (PDs). At present, the common silicon-based visible light detectors on the market have a peak at about 600 nm. The absorption coefficients of silicon for blue light and red light differ greatly. Therefore, the thicknesses of red light detectors and blue light detectors also differ greatly, and the quantum efficiency of blue light is very low, generally not exceeding 80%. Therefore, it is necessary to seek a photodiode with high integration, high bandwidth, and high quantum efficiency. Summary of the Invention

[0003] The present invention aims to overcome at least one of the above-mentioned deficiencies of the prior art, and provides a three-color PIN photodiode array for visible light communication. The three-color PIN photodiode array for visible light communication integrates photodiodes of three colors on the same chip, and at the same time, the thicknesses of the three-color PIN photodiodes are consistent and very thin. The structure of the present invention enhances the integration of the device, reduces the overall volume of the device; improves the response bandwidth and quantum efficiency of the device; the PIN photodiode with a micro-nano optical structure in the transverse direction can effectively increase the incident light illumination area, and therefore further improves the quantum efficiency of the device from another aspect.

[0004] Another object of the present invention is to provide a preparation method of the three-color PIN photodiode array for visible light communication.

[0005] The technical solution adopted by the present invention is:

[0006] A three-color PIN photodiode array for visible light communication includes a chip and a 3×3 red, green, and blue three-color PIN photodiode array integrated on the SiO2 layer in the chip. The red, green, and blue three-color PIN photodiode array is arranged in the y-axis direction in sequence according to the green photodiode, the red photodiode, and the blue photodiode, and the transverse direction in the x-axis direction is a monochromatic photodiode.

[0007] In the present invention, three green light photodiodes, three red light photodiodes, and three blue light photodiodes are sequentially arranged in the y-axis direction on the same chip to obtain a 3×3 red, green, and blue three-color PIN photodiode array. This three-color PIN photodiode array integrates photodiodes of three colors on the same chip, enhancing the device integration. The PIN photodiode with a micro-nano optical structure in the lateral direction can effectively improve the quantum efficiency of the device, and the ultra-thin three-color photodiode can effectively improve the bandwidth of the device.

[0008] Preferably, the monochromatic photodiode includes a substrate silicon layer, an SiO2 layer located on the substrate silicon layer, a top silicon layer located on the SiO2 layer, p-type Si, i-type Si, and n-type Si located in the top silicon layer, an air hole array located in the i-type Si, and electrodes located on the p-type Si and n-type Si. The p-type Si is Si heavily doped with B, the n-type Si is Si heavily doped with P, and the i-type Si is an intrinsic region lightly doped with P.

[0009] In the present invention, a uniformly distributed two-dimensional hole array is designed in the intrinsic layer i-type Si. The refractive index change of the air on the surface of the photodiode, the two-dimensional hole array in the intrinsic layer, and the SiO2 thin film constitutes a structure similar to the refractive index of an optical fiber, greatly increasing the absorption rates of red, green, and blue three-color lights integrated on the same chip, thereby improving the absorption rates of the photodiode for red, green, and blue three-color lights.

[0010] Preferably, the width of the p-type Si is 0.1 μm - 5 μm, and the length is the same as the width of the i-type Si.

[0011] Preferably, the width of the i-type Si is 1 μm - 50 μm, and the length is the same as the width of the i-type Si.

[0012] Preferably, the width of the n-type Si is 0.1 μm - 5 μm, and the length is the same as the width of the i-type Si.

[0013] Preferably, the i-type Si is located between the p-type Si and the n-type Si.

[0014] Preferably, the period P of the air hole array is 350 nm - 600 nm, and the filling rate f (the filling rate is the percentage of the area of the air holes in the silicon area within a single period, f = πd 2 / 4p 2 , where d is the diameter of the air hole) is 40% - 70%.

[0015] Preferably, an isolation region is provided between the green light photodiode and the red light photodiode, and between the red light photodiode and the blue light photodiode. The width of the isolation region is 5 μm - 50 μm, and the depth of the isolation region is the same as the thickness of the top silicon layer.

[0016] Preferably, the chip is a SOI chip.

[0017] Preferably, the method for preparing the three-color PIN photodiode array for visible light communication includes the following steps:

[0018] (1) Select an SOI chip with a top silicon thickness of 0.1 - 2 μm, and sequentially place the SOI chip into piranha solution, ethanol, acetone, ethanol, and deionized water for ultrasonic cleaning;

[0019] (2) Spin-coat a protective layer on the surface of the SOI chip, then perform pre-baking treatment on a hot plate, and then use a lithography machine for lithography. Remove the excess protective layer in the developer, and finally perform hard-baking treatment on the hot plate to prepare a mask layer with p-Si;

[0020] (3) Use ion implantation to form a B-heavily doped p ++ layer as the p-type ohmic contact layer, with a doping concentration of 10 15 -10 19 cm -3 , and remove the mask layer;

[0021] (4) Repeat the operation process of step (2) to fabricate the n ++ layer mask layer, and then use ion implantation to form a P-heavily doped n ++ layer as the n-type ohmic contact layer, with a doping concentration of 10 15 -10 19 cm -3 , and then remove the mask layer;

[0022] (5) Repeat the operation process of step (2) to fabricate the mask layer for the isolation region between the three color pixel units; then use wet etching or dry etching to fabricate the isolation region between the pixel units, and remove the mask layer;

[0023] (6) Repeat the operation process of step (2) to fabricate the mask layer for the electrode, and then deposit 10 - 30 nm / 90 - 110 nm thick Pt / Al by electron beam evaporation, then strip the excess metal in an acetone solution, and finally perform annealing treatment in an N2 environment;

[0024] (7) Repeat the operation process of step (2) to fabricate the mask layer for the i-type Si, and then use ion implantation to form a P-lightly doped n - layer as the intrinsic region, with a doping concentration of 10 12 -10 16 cm -3, then remove the mask layer; fabricate the mask layer of the air hole array again, and use reactive ion etching or deep reactive ion etching methods to fabricate the micro-nano optical structures in the intrinsic layers of the three-color photodiodes respectively. The air holes are arranged in a cubic lattice pattern, and then remove the mask layer; the differences among the three-color photodiodes lie in the different periods and filling ratios of the micro-nano optical structures in the intrinsic layer. Among them, the period and filling ratio of the green photodiode are 450nm - 500nm and 50% - 60% respectively, those of the red photodiode are 500nm - 600nm and 40% - 50% respectively, and those of the blue photodiode are 350nm - 450nm and 60% - 70% respectively.

[0025] Preferably, the thickness of the Pt / Al is 20nm / 100nm.

[0026] Compared with the prior art, the beneficial effects of the present invention are as follows: in the present invention, the green photodiode, red photodiode, and blue photodiode are sequentially arranged in the y-axis direction on the same chip, and a 3×3 red, green, and blue three-color PIN photodiode array is obtained. This three-color PIN photodiode array integrates the three-color photodiodes on the same chip, enhancing the device integration. The lateral PIN photodiode can effectively increase the incident light illumination area; a uniformly distributed two-dimensional hole array is designed in the intrinsic layer, greatly increasing the absorption rates of the red, green, and blue three-color lights integrated on the same chip; the present invention controls the thickness of the PIN photodiode within a very small range, thereby reducing the junction capacitance of the device and improving the response bandwidth of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of the overall structure of the three-color PIN photodiode array for visible light communication in the embodiment.

[0028] Figure 2 Cross-sectional view of the monochromatic photodiode in the embodiment.

[0029] Figure 3 Schematic diagram of the device structure obtained in step (1) in the embodiment.

[0030] Figure 4 Schematic diagram of the device structure obtained in step (2) in the embodiment.

[0031] Figure 5 Schematic diagram of the device structure obtained in step (3) in the embodiment.

[0032] Figure 6 Schematic diagram of the device structure obtained in step (4) in the embodiment.

[0033] Figure 7 Top view of the device structure obtained in step (5) in the embodiment.

[0034] Figure 8 It is a schematic diagram of the device structure obtained in step (6) of the embodiment.

[0035] Figure 9 It is a schematic diagram of the device structure obtained in step (7) of the embodiment.

[0036] Description of the drawings: 10, green photodiode; 20, red photodiode; 30, blue photodiode; 1, top silicon layer; 2, SiO2 layer; 3, substrate silicon layer; 4, p-type Si; 5, n-type Si; 6, air hole array; 7, i-type Si; 8, electrode. Detailed implementation manners

[0037] The drawings of this application are only for illustrative purposes and should not be construed as a limitation to this application. To better illustrate the following embodiments, some components in the drawings will be omitted, enlarged or reduced, which do not represent the dimensions of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0038] Embodiment

[0039] As Figure 1 shown, a three-color PIN photodiode array for visible light communication includes a chip and a 3×3 red, green, and blue three-color PIN photodiode array integrated on the chip. The red, green, and blue three-color PIN photodiode arrays are arranged in the y-axis direction in sequence as the green photodiode 10, the red photodiode 20, and the blue photodiode 30, and the x-axis direction is a monochromatic photodiode. As Figure 2 shown, the monochromatic photodiode includes a substrate silicon layer 3, an SiO2 layer 2 located on the substrate silicon layer 3, a top silicon layer 1 located on the SiO2 layer, a p-type Si 4, an i-type silicon 7, and an n-type Si 5 located in the top silicon layer 1, an air hole array 6 located in the i-type Si 7, and an electrode 8 located on the p-type Si 4 and the n-type Si 5. The i-type Si 7 is located between the p-type Si 4 and the n-type Si 5. More specifically, in this embodiment, the period of the air hole array is 350 nm - 600 nm, and the filling rate is 40% - 70%.

[0040] Furthermore, in this embodiment, the width of the p-type Si is 0.1 μm - 5 μm, and the length is the same as the width of the i-type Si; the width of the i-type Si is 1 μm - 50 μm, and the length is the same as the width of the i-type Si; the width of the n-type Si is 0.1 μm - 5 μm, and the length is the same as the width of the i-type Si.

[0041] The preparation process of the three-color PIN photodiode array for visible light communication described in this embodiment is as follows:

[0042] (1) Select an SOI chip with a top silicon thickness of 0.1 - 2 μm, and sequentially place the SOI chip into piranha solution, ethanol, acetone, ethanol, and deionized water for ultrasonic cleaning, as Figure 3 shown;

[0043] (2) Spin - coat a protective layer on the surface of the SOI chip, then perform pre - baking on a hot plate, and then use a lithography machine for lithography. Remove the excess protective layer in the developer, and finally perform hard - baking on a hot plate to prepare a mask layer with p - Si, as Figure 4 shown;

[0044] (3) Use ion implantation to form a B - heavily doped p ++ layer as the p - type ohmic contact layer, with a doping concentration of 10 15 - 10 19 cm -3 , and remove the mask layer, as Figure 5 shown;

[0045] (4) Repeat the operation process of step (2) to fabricate the n ++ layer mask layer, and then use ion implantation to form a P - heavily doped n ++ layer as the n - type ohmic contact layer, with a doping concentration of 10 15 - 10 19 cm -3 , and then remove the mask layer, as Figure 6 shown;

[0046] (5) Repeat the operation process of step (2) to fabricate the mask layer for the isolation region between the three - color pixel units; then use wet etching or dry etching to fabricate the isolation region between the pixel units, and remove the mask layer, as Figure 7 shown;

[0047] (6) Repeat the operation process of step (2) to fabricate the mask layer for the electrode, then deposit 20 nm / 100 nm thick Pt / Al by electron beam evaporation, then strip the excess metal in an acetone solution, and finally perform annealing treatment in an N2 environment, as Figure 8 shown;

[0048] (7) Repeat the operation process of step (2) to fabricate the mask layer for i - type Si, and then use ion implantation to form a P - lightly doped n - layer as the intrinsic region, with a doping concentration of 10 12 - 10 16 cm -3, and then remove the mask layer; fabricate the mask layer of the air hole array again, and use reactive ion etching or deep reactive ion etching methods to fabricate the micro-nano optical structures in the intrinsic layers of the three-color photodiodes respectively. The period p of the air hole array is 350 nm - 600 nm, the filling rate f is 40% - 70%, and the air holes are arranged in a cubic lattice pattern. Then remove the mask layer, as Figure 9 shown. The differences among the three-color photodiodes lie in the different periods and filling rates of the micro-nano optical structures in the intrinsic layers. The period and filling rate of the green photodiode are 450 nm - 500 nm and 50% - 60% respectively, those of the red photodiode are 500 nm - 600 nm and 40% - 50% respectively, and those of the blue photodiode are 350 nm - 450 nm and 60% - 70% respectively.

[0049] In the visible light communication three-color PIN photodiode array prepared in this embodiment, the top silicon in the SOI is designed as a lateral PIN photodiode, so that the incident light completely irradiates on the surface of the intrinsic layer, increasing the incident area and improving the quantum efficiency of the device; at the same time, a two-dimensional hole array with uniform distribution is designed in the intrinsic layer, greatly increasing the absorption rates of the red, green, and blue light integrated on the same chip; and the thickness of the PIN photodiode is controlled within a very small range, thereby reducing the junction capacitance of the device and improving the response speed and bandwidth of the device.

[0050] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the technical solutions of the present invention, rather than limitations on the specific implementation manners of the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the claims of the present invention shall be included within the protection scope of the claims of the present invention.

Claims

1. A three-color PIN photodiode array for visible light communication, characterized in that, It includes a chip and a 3×3 red, green, and blue PIN photodiode array integrated on the SiO2 layer in the chip. The red, green, and blue PIN photodiode array is arranged in the y-axis direction in sequence as a green photodiode, a red photodiode, and a blue photodiode, and in the x-axis direction as a monochromatic photodiode; The monochromatic photodiode includes a substrate silicon layer, a SiO2 layer located on the substrate silicon layer, a top silicon layer located on the SiO2 layer, p-type Si, i-type Si, and n-type Si located in the top silicon layer, an air hole array located in the i-type Si, and electrodes located on the p-type Si and n-type Si; An isolation region is provided between the green photodiode and the red photodiode, and between the red photodiode and the blue photodiode. The width of the isolation region is 5μm - 50μm, and the depth of the isolation region is the same as the thickness of the top silicon layer; The chip is a SOI chip.

2. The three-color PIN photodiode array for visible light communication according to claim 1, characterized in that, The width of the p-type Si is 0.1μm - 5μm, and the length is the same as the width of the i-type Si.

3. The three-color PIN photodiode array for visible light communication according to claim 1, wherein, The width of the i-type Si is 1μm - 50μm, and the length is the same as the width of the i-type Si.

4. The three-color PIN photodiode array for visible light communication according to claim 1, wherein, The width of the n-type Si is 0.1μm - 5μm, and the length is the same as the width of the i-type Si.

5. The three-color PIN photodiode array for visible light communication according to claim 1, wherein The period of the air hole array is 350nm - 600nm, and the filling rate is 40% - 70%.

6. The method for preparing a three-color PIN photodiode array for visible light communication according to any one of claims 1 to 5, characterized in that, It includes the following steps: (1) Select a SOI chip with a top silicon layer thickness of 0.1 - 2μm, and sequentially place the SOI chip into piranha solution, ethanol, acetone, ethanol, and deionized water for ultrasonic cleaning; (2) Spin-coat a protective layer on the surface of the SOI chip, then perform pre-baking treatment on a hot plate, then use a photolithography machine for photolithography, remove the excess protective layer in a developer, and finally perform hard-baking treatment on a hot plate to prepare a mask layer with p-Si; (3) Form a heavily boron-doped p ++ layer as the p-type ohmic contact layer with a doping concentration of 10 15 -10 19 cm -3 , and remove the mask layer; (4) Repeat the operation process of step (2) to fabricate n ++ layer mask layer, and then use the ion implantation method to form a P - heavily doped n ++ layer as the n - type ohmic contact layer, with a doping concentration of 10 15 -10 19 cm -3 , and then remove the mask layer; (5) Repeat the operation process of step (2) to fabricate a mask layer for the isolation region between the three-color pixel units; then use wet etching or dry etching methods to fabricate the isolation region between the pixel units and remove the mask layer; (6) Repeat the operation process of step (2) to fabricate a mask layer for the electrodes, then deposit Pt / Al with a thickness of 10 - 30nm / 90 - 110nm by electron beam evaporation, then strip the excess metal in an acetone solution, and finally perform annealing treatment in an N2 environment; (7) Repeat the operation process of step (2) to fabricate the mask layer of type-I Si, and then form a P lightly doped n - layer as the intrinsic region with a doping concentration of 10 12 -10 16 cm -3 , and then remove the mask layer; fabricate the mask layer of the air hole array again, and use reactive ion etching or deep reactive ion etching methods to fabricate the micro-nano optical structures in the intrinsic layers of the three-color photodiodes respectively. The air holes are arranged in a cubic lattice pattern, and then remove the mask layer; the differences among the three-color photodiodes lie in the period and filling rate of the micro-nano optical structures in the intrinsic layer. Among them, the period and filling rate of the green photodiode are 450 nm - 500 nm and 50% - 60% respectively, the period and filling rate of the red photodiode are 500 nm - 600 nm and 40% - 50% respectively, and the blue photodiode is 350 nm - 450 nm and 60% - 70% respectively.

7. The method for preparing a three-color PIN photodiode array for visible light communication according to claim 6, characterized in that, The thickness of the Pt / Al is 20nm / 100nm.

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