Semiconductor package structure, semiconductor wafer level package and semiconductor manufacturing process

Abstract

A semiconductor package structure includes a semiconductor die, at least one wiring structure, a package, and a plurality of conductive elements. The semiconductor die has an active surface. The at least one wiring structure is electrically connected to the active surface of the semiconductor die. The package surrounds the semiconductor die. The package is formed of a package material, and a Young's modulus of the package is between 0.001 GPa and 1 GPa. The conductive elements are embedded in the package and electrically connected to the at least one wiring structure.

Description

Technical Field

[0001] This disclosure relates to a semiconductor packaging structure, semiconductor wafer-level packaging, and semiconductor manufacturing process, and more specifically, to a semiconductor packaging structure including a flexible package, semiconductor wafer-level packaging, and semiconductor manufacturing process. Background Technology

[0002] The trend in electronic products is towards lighter, thinner, shorter, and smaller designs. Semiconductor package structures are designed to meet these requirements. However, warpage can occur in thin semiconductor package structures. Warped semiconductor package structures cannot be attached to the substrate, interposer, or printed circuit board during the reflow process. Therefore, there is a risk of peeling. Summary of the Invention

[0003] In some embodiments, according to one aspect, the semiconductor package structure includes a semiconductor die, at least one wiring structure, an encapsulant, and a plurality of conductive elements. The semiconductor die has an active surface. The at least one wiring structure is electrically connected to the active surface of the semiconductor die. The encapsulant surrounds the semiconductor die. The encapsulant is formed of an encapsulation material, and the Young's modulus of the encapsulant is between 0.001 GPa and 1 GPa. The conductive elements are embedded in the encapsulant and electrically connected to the at least one wiring structure.

[0004] In some embodiments, according to another aspect, a semiconductor wafer-level package includes at least one semiconductor die, at least one wiring layer, a package body, and a plurality of conductive elements. The semiconductor die has an active surface. At least one wiring structure is electrically connected to the active surface of the semiconductor die. The package body surrounds at least one semiconductor die. The package body is formed of a packaging material, and the Young's modulus of the package body is between 0.001 GPa and 1 GPa. The conductive elements are embedded in the package body and electrically connected to at least one wiring layer.

[0005] In some embodiments, according to another aspect, the semiconductor manufacturing process includes: (a) providing a carrier; (b) forming a wiring layer on the carrier; (c) mounting at least one semiconductor die on the wiring layer; and (d) forming a package and a plurality of conductive elements, wherein the package surrounds at least one semiconductor die, the conductive elements are embedded in the package and electrically connected to the wiring layer, wherein the package is formed of a packaging material and the Young's modulus of the package is between 0.001 GPa and 1 GPa. Attached Figure Description

[0006] Some aspects of the embodiments disclosed herein are related to the appendix. Figure 1The best way to understand this text is by reading the following detailed description. Note that the structures may not be drawn to scale, and their dimensions may be increased or decreased for clarity of explanation.

[0007] Figure 1 Cross-sectional views illustrating examples of semiconductor package structures according to some embodiments of this disclosure.

[0008] Figure 2 Cross-sectional views illustrating examples of semiconductor package structures according to some embodiments of this disclosure.

[0009] Figure 3 Cross-sectional views illustrating examples of semiconductor package structures according to some embodiments of this disclosure.

[0010] Figure 4 Cross-sectional views illustrating examples of semiconductor package structures according to some embodiments of this disclosure.

[0011] Figure 5 A cross-sectional view illustrating an example of a semiconductor package structure and substrate assembly according to some embodiments of this disclosure.

[0012] Figure 6 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0013] Figure 7 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0014] Figure 8 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0015] Figure 9 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0016] Figure 10 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0017] Figure 11 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0018] Figure 12 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0019] Figure 13 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0020] Figure 14 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0021] Figure 15 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0022] Figure 16 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0023] Figure 17 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0024] Figure 18 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0025] Figure 19 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0026] Figure 20 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0027] Figure 21 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0028] Figure 22 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0029] Figure 23 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0030] Figure 24 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0031] Figure 25 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0032] Figure 26 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure.

[0033] Figure 27 This describes one or more stages of an example of a semiconductor manufacturing process according to some embodiments of this disclosure. Detailed Implementation

[0034] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. The embodiments disclosed herein will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0035] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features may be formed or disposed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0036] In the semiconductor industry, fan-out products typically have a thickness of less than 200 μm. For example, for a 15mm x 15mm semiconductor package, the thickness can be controlled to less than 200 μm. Simulations show that the warpage amount of a semiconductor package is approximately 745 μm at 25°C and approximately -282 μm at 260°C. Warped semiconductor packages do not meet standard requirements for total warpage, such as + / - 80 μm. Highly warped semiconductor packages cannot easily attach to the substrate, insert, or printed circuit board during reflow processes, thus posing a risk of peeling.

[0037] To at least address the aforementioned problems, the embodiments disclosed herein provide encapsulation materials to form the package, rather than commonly used molding compounds. Furthermore, the Young's modulus of the package in this disclosure is between 0.001 GPa and 1 GPa. Due to the low Young's modulus, the package is flexible. Therefore, the semiconductor package structure disclosed herein can be bent to attach to a substrate, insert, or printed circuit board during reflow processes. This solves the warpage problem. The semiconductor package structure disclosed herein can meet conventional requirements for total warpage, such as + / - 80 μm.

[0038] Figure 1This illustration shows a cross-sectional view of an example of a semiconductor package structure 1 according to some embodiments of the present disclosure. The semiconductor package structure 1 includes a semiconductor die 11, at least one wiring structure 12, a package body 13, and a plurality of conductive elements 14. The semiconductor die 11 has an active surface 111 and a plurality of conductive pillars 113 disposed adjacent to the active surface 111. At least one wiring structure 12 is electrically connected to the active surface 111 of the semiconductor die 11. In some embodiments, the conductive pillars 113 of the semiconductor die 11 are disposed on and electrically connected to the at least one wiring structure 12. Therefore, the active surface 111 faces the wiring structure 12.

[0039] In some embodiments, the wiring structure 12 may include a first redistribution layer 121, a first dielectric layer 122, a second redistribution layer 123, and a second dielectric layer 124. The first dielectric layer 122 covers the first redistribution layer 121, and the second dielectric layer 124 covers the second redistribution layer 123. The first redistribution layer 121 may include a seed layer and a conductive layer. The seed layer may be made of, for example, titanium or copper. In some embodiments, the seed layer may include a titanium layer and a copper layer. The conductive layer may be made of, for example, a conductive metal, such as copper; or another metal or a combination of metals. However, in some embodiments, the seed layer may be omitted. The first redistribution layer 121 may include at least one conductive via 125 disposed in a via of the first dielectric layer 122, and at least one conductive pad. In some embodiments, the first redistribution layer 121 may further include at least one trace.

[0040] In some embodiments, the first dielectric layer 122 may be made of an insulating or dielectric material, such as polypropylene (PP). It should be noted that the first dielectric layer 122 may comprise or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) including a photoinitiator. The first dielectric layer 122 defines at least one through-hole extending through the first dielectric layer 122.

[0041] In some embodiments, the second re-layer 123 is electrically connected to the first re-layer 121 via a conductive via 125. The second re-layer 123 may include a seed layer and a conductive layer. The seed layer may be made of, for example, titanium or copper. In some embodiments, the seed layer may include a titanium layer and a copper layer. The conductive layer may be made of, for example, a conductive metal, such as copper; or another metal or combination of metals. However, in some embodiments, the seed layer may be omitted. The second re-layer 123 may include at least one conductive via 126 disposed in a through-hole of the second dielectric layer 124, and at least one conductive pad. In some embodiments, the second re-layer 121 may further include at least one trace.

[0042] In some embodiments, the second dielectric layer 124 may be made of an insulating or dielectric material, such as polypropylene (PP). It should be noted that the second dielectric layer 124 may include or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) including a photoinitiator. The second dielectric layer 124 defines at least one through-hole extending through the second dielectric layer 124.

[0043] Package 13 surrounds or covers at least a portion of semiconductor die 11. Package 13 is formed of a packaging material, and the Young's modulus of the package is between 0.001 GPa and 1 GPa. In some embodiments, the packaging material includes polymers such as epoxy resin, rubber, silicone rubber, silicone mold compound, or polyimide. The above-mentioned packaging materials can be used to form package 13 instead of commonly used molding compounds. Due to its low Young's modulus, the package 13 disclosed herein is flexible. Therefore, the semiconductor package structure 1 disclosed herein can be flexible to attach to a substrate, insert, or printed circuit board during reflow processes. Thus, warpage problems can be solved. The semiconductor package structure 1 disclosed herein can meet conventional requirements for total warpage.

[0044] In some embodiments, the encapsulation material may be a silicone molding compound, and the Young's modulus of the package 13 formed from the silicone molding compound is approximately 0.35 GPa. The semiconductor package structure 1 disclosed herein can be measured by a flexibility test, such as a three-point test. A force of 1 Newton (NT) is applied to the center of the top portion of the semiconductor package structure 1, supporting both ends of the bottom portion. The flexibility of the semiconductor package structure 1 is the deformation amount. That is, the flexibility of the semiconductor package structure 1 is the displacement value of a point at the center portion of the semiconductor package structure after applying a 1NT force. If the flexibility of the semiconductor package structure 1 is large, it means that the semiconductor package structure 1 is soft enough to bend and attach to a substrate, insert, or printed circuit board during a reflow process. After the flexibility test, the flexibility of the semiconductor package structure 1 with the silicone molding compound is approximately 1543 μm.

[0045] In some embodiments, the encapsulation material may be silicone rubber, and the Young's modulus of the encapsulation body 13 formed of silicone rubber is approximately 0.001 GPa. After flexibility testing, the flexibility of the semiconductor encapsulation structure 1 according to the above embodiment is approximately 1773 μm. That is, the semiconductor encapsulation structure 1 with silicone rubber having a Young's modulus of 0.001 GPa is softer than the semiconductor encapsulation structure 1 with silicone molding material having a Young's modulus of 0.35 GPa.

[0046] In some embodiments, the flexibility of the semiconductor package structure 1 is greater than about 1000 μm. By simulating the relationship between Young's modulus and flexibility, when the Young's modulus of the package 13 is less than about 1 GPa, the flexibility of the semiconductor package structure 1 can be greater than about 1000 μm.

[0047] In some embodiments, the thickness of the semiconductor package structure 1 is less than about 200 μm, and the flexibility of the semiconductor package structure 1 is greater than about 1000 μm. That is, for a thin semiconductor package structure 1, the flexibility of the semiconductor package structure 1 can be large enough to overcome the warping problem during the reflow process.

[0048] In some embodiments, the encapsulation material may include a silicon filler. The content of the silicon filler in the encapsulation material may be from about 1% to about 30% by weight. When the content of the silicon filler in the encapsulation material is very low, the encapsulation material is soft. Furthermore, it can prevent porosity problems and incomplete filling problems during the molding process. In other embodiments, the encapsulation material may not include a silicon filler.

[0049] In some embodiments, the package 13 defines a recessed portion 131 disposed on the periphery of the semiconductor package structure 1. That is, the periphery of the package 13 may not have a uniform height.

[0050] A conductive element 14 is embedded in a package 13 and electrically connected to at least one wiring structure 12 via a conductive via 126. The conductive element 14 may surround a semiconductor die 11, and the height of the conductive element 14 may exceed the thickness of the semiconductor die 11. A portion of the conductive element 14 is exposed from the package 13 for electrical connection to external components. That is, a portion of the conductive element 14 may protrude from a recess 131 in the package 13. In some embodiments, the conductive element 14 may be a solder ball. The material of the conductive element 14 may be a conductive metal, such as tin; or another metal or a combination of metals. In some embodiments, the semiconductor package structure 1 further includes a plurality of solder connectors 15. The solder connectors 15 are electrically connected to the bottom of at least one wiring structure 12. The material of the solder connectors 15 may be a conductive metal, such as tin; or another metal or a combination of metals.

[0051] Figure 2 A cross-sectional view illustrating an example of a semiconductor package structure 1a according to some embodiments of the present disclosure. Figure 2 The semiconductor packaging structure 1a shown in the image is similar to... Figure 1The semiconductor package structure 1 shown is described below. In some embodiments, the conductive element 14a may be a metal pillar. A portion of the conductive element 14a is exposed from the package 13 to be electrically connected to an external component. The material of the conductive element 14a may be: a conductive metal, such as copper; or another metal or a combination of metals.

[0052] Figure 3 A cross-sectional view illustrating an example of a semiconductor package structure 1b according to some embodiments of this disclosure. Figure 3 The semiconductor packaging structure 1b shown in the image is similar to Figure 2 The semiconductor package structure 1a shown in the figure has the following differences. In some embodiments, the top surface of the conductive element 14b and the top surface of the semiconductor die 11 may be coplanar with the top surface of the package 13, and the top surfaces of the conductive element 14b and the semiconductor die 11 are exposed from the package 13. Figure 3 Encapsulation body 13 may not be defined Figure 2 The recessed portion 131. The semiconductor package structure 1b further includes a plurality of first solder connectors 15b and a plurality of second solder connectors 16. The first solder connectors 15b are electrically connected to the bottom of at least one wiring structure 12. The second solder connectors 16 are electrically connected to the top surface of the conductive element 14b. The second solder connectors 16 can be used for electrical connection to external components.

[0053] Figure 4 This illustration shows a cross-sectional view of an example of a semiconductor package structure 1c according to some embodiments of the present disclosure. In some embodiments, the semiconductor package structure 1c includes a first wiring structure 12c and a second wiring structure 12d. The first wiring structure 12c is disposed adjacent to the back surface 112 of the semiconductor die 11, and the second wiring structure 12d is disposed adjacent to the active surface 111 of the semiconductor die 11. The back surface 112 of the semiconductor die 11 is adhered to the top surface of the first wiring structure 12c by an adhesive layer 114. The first wiring structure 12c is electrically connected to the bottom surface of a conductive element 14c. The second wiring structure 12d is electrically connected to the top surface of the conductive element 14c and the active surface 111 of the semiconductor die 11. The semiconductor package structure 1c further includes a plurality of solder connectors 15c. The solder connectors 15c are electrically connected to the second wiring structure 12d. The material of the solder connectors 15c may be: a conductive metal, such as tin; or another metal or a combination of metals.

[0054] Figure 5 This is a cross-sectional view illustrating an example of an assembly of a semiconductor package structure 1 and a substrate 17 according to some embodiments of the present disclosure. In some embodiments, the semiconductor package structure 1 is attached to the substrate 17. The substrate 17 may be a base plate, an insert, or a printed circuit board. The substrate 17 is electrically connected to a solder connector 15.

[0055] Figures 6 to 12 This describes semiconductor manufacturing processes according to some embodiments of the present disclosure. In some embodiments, the semiconductor manufacturing process is used to manufacture semiconductor package structures, such as... Figure 1 and 5 The semiconductor packaging structure shown in the image 1.

[0056] refer to Figure 6 A carrier 61 is provided, on which a wiring layer 62 is formed or disposed. In some embodiments, a release layer 63 is disposed between the carrier 61 and the wiring layer 62. In some embodiments, the wiring layer 62 may include a first redistribution layer 621, a first dielectric layer 622, a second redistribution layer 623, and a second dielectric layer 624. The first dielectric layer 622 covers the first redistribution layer 621, and the second dielectric layer 624 covers the second redistribution layer 623. The first redistribution layer 621 may include a seed layer and a conductive layer. The seed layer may be made of, for example, titanium or copper. In some embodiments, the seed layer may include a titanium layer and a copper layer. The conductive layer may be made of, for example, a conductive metal, such as copper; or another metal or combination of metals. However, in some embodiments, the seed layer may be omitted. The first redistribution layer 621 may include at least one conductive via 625 disposed in a through-hole of the first dielectric layer 622, and at least one conductive pad. In some embodiments, the first redistribution layer 621 may further include at least one trace.

[0057] In some embodiments, the first dielectric layer 622 may be made of an insulating or dielectric material, such as polypropylene (PP). It should be noted that the first dielectric layer 622 may include or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) including a photoinitiator. The first dielectric layer 622 defines at least one through-hole extending through the first dielectric layer 622.

[0058] In some embodiments, the second re-layer 623 is electrically connected to the first re-layer 621 via a conductive via 625. The second re-layer 623 may include a seed layer and a conductive layer. The seed layer may be made of, for example, titanium or copper. In some embodiments, the seed layer may include a titanium layer and a copper layer. The conductive layer may be made of, for example, a conductive metal, such as copper; or another metal or combination of metals. However, in some embodiments, the seed layer may be omitted. The second re-layer 623 may include at least one conductive via 626 disposed in a through-hole of the second dielectric layer 624, and at least one conductive pad. In some embodiments, the second re-layer 621 may further include at least one trace.

[0059] In some embodiments, the second dielectric layer 624 may be made of an insulating or dielectric material, such as polypropylene (PP). It should be noted that the second dielectric layer 624 may include or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) including a photoinitiator. The second dielectric layer 624 defines at least one through-hole extending through the second dielectric layer 624.

[0060] See Figure 7 At least one semiconductor die 11 is mounted on a wiring layer 62. The semiconductor die 11 has an active surface 111 and a plurality of conductive pillars 113 disposed adjacent to the active surface 111. The wiring layer 62 is electrically connected to the active surface 111 of the semiconductor die 11. In some embodiments, the conductive pillars 113 of the semiconductor die 11 are disposed on and electrically connected to at least one wiring layer 62. Therefore, the active surface 111 faces the wiring layer 62.

[0061] refer to Figure 8 The conductive element 14 is formed on and electrically connected to the wiring layer 62. In some embodiments, the conductive element 14 may be a solder ball. The material of the conductive element 14 may be a conductive metal, such as tin; or another metal or combination of metals.

[0062] refer to Figure 9 An encapsulation 13 is formed to surround or cover at least one semiconductor die 11 and a conductive element 14. The encapsulation 13 is formed of an encapsulation material, and the Young's modulus of the encapsulation 13 is between 0.001 GPa and 1 GPa. In some embodiments, the encapsulation material includes liquid polymers such as epoxy resin, rubber, silicone rubber, silicone molding raw materials, or polyimide. In some embodiments, the encapsulation material may include silicon fillers. The content of silicon fillers in the encapsulation material may be from about 1% to about 30% by weight. The above-described encapsulation materials can be used to form the encapsulation 13 instead of commonly used molding raw materials. The encapsulation material can be formed by coating, dispensing, or molding. After a curing process, the encapsulation material is cured to become the encapsulation 13. Due to its low Young's modulus, the encapsulation 13 disclosed herein is soft. Therefore, the semiconductor encapsulation structure 1 ( Figure 1 The semiconductor package structure 1 disclosed herein can be bent to attach to a substrate, insert, or printed circuit board during reflow processes. Therefore, warpage issues are resolved. Figure 1 It can meet the conventional requirements for total warpage.

[0063] In some embodiments, the package 13 may define a recessed portion 131 disposed in the region between two adjacent semiconductor dies 11.

[0064] See Figure 10The carrier 61 and release layer 63 are removed. Subsequently, a plurality of solder connectors 15 are formed to be electrically connected to at least one wiring layer 62. The material of the solder connectors 15 can be: a conductive metal, such as tin; or another metal or combination of metals. Thus, a semiconductor wafer-level package 2 is formed. The semiconductor wafer-level package 2 includes at least one semiconductor die 11, at least one wiring layer 62, a package body 13, and a plurality of conductive elements 14. The semiconductor die 11 has an active surface 111. At least one wiring structure 62 is electrically connected to the active surface 111 of the semiconductor die 11. The package body 13 surrounds at least one semiconductor die 11. The package body 13 is formed of a packaging material, and the Young's modulus of the package body 13 is between 0.001 GPa and 1 GPa. The conductive elements 14 are embedded in the package body 13 and are electrically connected to at least one wiring layer.

[0065] refer to Figure 11 Monomerization process is performed to cut semiconductor wafer-level packages 2 to form such Figure 1 Each of the semiconductor package structures 1 shown.

[0066] refer to Figure 12 A semiconductor package structure 1 is attached to a substrate 17. The substrate 17 can be an insert or a printed circuit board. The substrate 17 is electrically connected to solder connectors 15. During the reflow process, the side solder connectors 151 and 152 melt to extend, and the solder connectors 151 and 152 can exert a pulling force on the semiconductor package structure 1 and the substrate 17. Furthermore, the center solder connectors 153 and 154 melt to press, and the solder connectors 153 and 154 can exert a pushing force on the semiconductor package structure 1 and the substrate 17. Therefore, if the semiconductor package structure 1 is sufficiently flexible, the solder connectors 151 and 152 can easily pull the semiconductor package structure 1 and the substrate 17, and the solder connectors 153 and 154 can easily push the semiconductor package structure 1 and the substrate 17. Because the pulling and pushing forces of the solder connectors 15 can create force coupling, the semiconductor package structure 1 and the substrate 17 can be bent to attach to each other, as shown in the image. Figure 5 As shown in the diagram. Therefore, the total warpage of the semiconductor package structure 1 relative to the substrate 17 can be reduced. The semiconductor package structure disclosed herein can meet conventional requirements for total warpage, such as + / - 80 μm.

[0067] Figures 13 to 15 This describes semiconductor manufacturing processes according to some embodiments of the present disclosure. In some embodiments, the semiconductor manufacturing process is used to manufacture semiconductor package structures, such as... Figure 2 The semiconductor packaging structure 1a shown in the diagram illustrates the initial stage of the process and... Figures 6 to 7 The stages described herein are the same or similar. Figure 13 Depicting Figure 7The stage following the stage described in the text.

[0068] like Figure 13 As shown, a package 13 is formed to surround at least one semiconductor die 11, and then a plurality of through-holes 132 are formed to extend through the package 13. In some embodiments, a laser is used to drill the through-holes 132. That is, the through-holes 132 can be formed by laser drilling.

[0069] Package 13 is formed of encapsulating material, and the Young's modulus of package 13 is between 0.001 GPa and 1 GPa. In some embodiments, the encapsulating material includes liquid polymers such as epoxy resin, rubber, silicone rubber, silicone molding raw materials, or polyimide. In some embodiments, the encapsulating material may include silicon fillers. The content of silicon fillers in the encapsulating material may be from about 1% to about 30% by weight. The above-described encapsulating material can be used to form package 13 instead of commonly used molding raw materials. The encapsulating material can be formed by coating, application, or molding. After a curing process, the encapsulating material is cured to become package 13. Due to its low Young's modulus, the package 13 disclosed herein is soft. Therefore, the semiconductor package structure 1a (disclosed) Figure 2 The semiconductor package structure 1a disclosed herein can be bent to attach to a substrate, insert, or printed circuit board during reflow processes. Therefore, the warpage problem is solved. Figure 2 It can meet the conventional requirements for total warpage.

[0070] See Figure 14 The conductive element 14a is formed in the through-hole 132 by, for example, plating. In some embodiments, the conductive element 14a may be a metal pillar. A portion of the conductive element 14a is exposed from the package 13 for electrical connection to an external component. The material of the conductive element 14a may be: a conductive metal, such as copper; or another metal or a combination of metals.

[0071] See Figure 15 The carrier 61 and release layer 63 are removed. Subsequently, a plurality of solder connectors 15 are formed to be electrically connected to at least one wiring layer 62. The material of the solder connectors 15 may be: a conductive metal, such as tin; or another metal or combination of metals. Thus, a semiconductor wafer-level package 2a is formed. The semiconductor wafer-level package 2a includes at least one semiconductor die 11, at least one wiring layer 62, a package body 13, and a plurality of conductive elements 14a. The semiconductor die 11 has an active surface 111. At least one wiring structure 62 is electrically connected to the active surface 111 of the semiconductor die 11. The package body 13 surrounds at least one semiconductor die 11. The package body 13 is formed of a packaging material, and the Young's modulus of the package body 13 is between 0.001 GPa and 1 GPa. The conductive elements 14a are embedded in the package body 13 and are electrically connected to at least one wiring layer 62.

[0072] refer to Figure 16 Monomerization process is performed to cut semiconductor wafer-level packages 2a to form such Figure 2 Each of the semiconductor package structures 1a shown.

[0073] Figures 17 to 21 This describes semiconductor manufacturing processes according to some embodiments of the present disclosure. In some embodiments, the semiconductor manufacturing process is used to manufacture semiconductor package structures, such as... Figure 3 The semiconductor package structure 1b shown in the diagram illustrates the initial stage of the process and... Figures 6 to 7 The stages described herein are the same or similar. Figure 17 Depicting Figure 7 The stage following the stage described in the text.

[0074] See Figure 17 Conductive element 14b is formed on wiring layer 62 and electrically connected to wiring layer 62 by, for example, plating. In some embodiments, conductive element 14b may be a metal pillar. The material of conductive element 14b may be: a conductive metal, such as copper; or another metal or combination of metals.

[0075] refer to Figure 18 A package 13 is formed to surround at least one semiconductor die 11 and a conductive element 14b. The package 13 is formed of a package material, and the Young's modulus of the package 13 is between 0.001 GPa and 1 GPa. In some embodiments, the package material includes a liquid polymer, such as epoxy resin, rubber, silicone rubber, silicone molding compound, or polyimide. In some embodiments, the package material may include a silicon filler. The content of the silicon filler in the package material may be from about 1% to about 30% by weight. The above-described package material can be used to form the package 13 instead of commonly used molding compounds. The package material can be formed by coating, application, or molding. After a curing process, the package material is cured to become the package 13. Due to its low Young's modulus, the package 13 disclosed herein is soft. Therefore, the semiconductor package structure disclosed herein can be flexible to attach to a substrate, insert, or printed circuit board during a reflow process. Thus, warpage problems can be solved. The semiconductor package structure disclosed herein can meet conventional requirements for total warpage. In some embodiments, the package 13 covers at least one semiconductor die 11 and a conductive element 14b.

[0076] refer to Figure 19 In order to expose portions of conductive element 14b and semiconductor die 11, package 13 is ground by a grinding tool 71.

[0077] refer to Figure 20Multiple second solder connectors 16 are mounted on the conductive element 14b, and the second solder connectors 16 are electrically connected to the conductive element 14b. The second solder connectors 16 can be used to electrically connect to external components.

[0078] See Figure 21 The carrier 61 and release layer 63 are removed. Subsequently, a plurality of first solder connectors 15b are formed to be electrically connected to at least one wiring layer 62. The material of the first solder connectors 15b may be: a conductive metal, such as tin; or another metal or combination of metals. Thus, a semiconductor wafer-level package 2b is formed. The semiconductor wafer-level package 2b includes at least one semiconductor die 11, at least one wiring layer 62, a package body 13, and a plurality of conductive elements 14b. The semiconductor die 11 has an active surface 111. At least one wiring structure 62 is electrically connected to the active surface 111 of the semiconductor die 11. The package body 13 surrounds at least one semiconductor die 11. The package body 13 is formed of a packaging material, and the Young's modulus of the package body 13 is between 0.001 GPa and 1 GPa. The conductive elements 14b are embedded in the package body 13 and are electrically connected to at least one wiring layer 62.

[0079] refer to Figure 22 Monomerization processes are performed to cut semiconductor wafer-level packages 2b to form such Figure 3 Each of the semiconductor package structures 1b shown.

[0080] Figures 23 to 27 This describes semiconductor manufacturing processes according to some embodiments of the present disclosure. In some embodiments, the semiconductor manufacturing process is used to manufacture semiconductor package structures, such as... Figure 4 The semiconductor packaging structure 1c shown in the image illustrates the initial stage of the process and... Figure 6 The stages described herein are the same or similar. Figure 23 Depicting Figure 6 The stage following the stage described in the text.

[0081] refer to Figure 23 At least one semiconductor die 11 is adhered to the first wiring layer 62a via an adhesive layer 114. The semiconductor die 11 has an active surface 111 and a rear surface 112. In some embodiments, the rear surface 112 of the semiconductor die 11 is adhered to the first wiring layer 62a via the adhesive layer 114. Subsequently, a conductive element 14c is formed on the first wiring layer 62a and electrically connected to the first wiring layer 62a. In some embodiments, the conductive element 14c may be a metal pillar. The material of the conductive element 14c may be a conductive metal, such as copper; or another metal or a combination of metals.

[0082] refer to Figure 24An encapsulation 13 is formed to surround at least one semiconductor die 11 and a conductive element 14c. The encapsulation 13 is formed of an encapsulation material, and the Young's modulus of the encapsulation 13 is between 0.001 GPa and 1 GPa. In some embodiments, the encapsulation material includes a liquid polymer, such as epoxy resin, rubber, silicone rubber, silicone molding compound, or polyimide. In some embodiments, the encapsulation material may include a silicon filler. The content of the silicon filler in the encapsulation material may be from about 1% to about 30% by weight. The above-described encapsulation material can be used to form the encapsulation 13 instead of commonly used molding compounds. The encapsulation material can be formed by coating, application, or molding. After a curing process, the encapsulation material is cured to become the encapsulation 13. Due to its low Young's modulus, the encapsulation 13 disclosed herein is soft. Therefore, the semiconductor encapsulation structure 1c disclosed herein ( Figure 4 The semiconductor package structure 1c disclosed herein can be bent to attach to a substrate, insert, or printed circuit board during reflow processes. Therefore, the warpage problem is solved. Figure 4 It can meet the conventional requirements for total warpage.

[0083] refer to Figure 25 A second wiring layer 62b is formed on at least one semiconductor die 11 and package 13, and the second wiring layer 62b is electrically connected to the active surface 111 of the semiconductor die 11 and the conductive element 14c. In some embodiments, the wiring layer 62b may include a first redistribution layer 621b, a first dielectric layer 622b, a second redistribution layer 623b, and a second dielectric layer 624b. The first redistribution layer 621b is disposed on the first dielectric layer 622b. The second dielectric layer 624b covers the first redistribution layer 621b and the second redistribution layer 623b. The first redistribution layer 621b may include a seed layer and a conductive layer. The seed layer may be made of, for example, titanium or copper. In some embodiments, the seed layer may include a titanium layer and a copper layer. The conductive layer may be made of, for example, a conductive metal, such as copper; or another metal or a combination of metals. However, in some embodiments, the seed layer may be omitted. The first re-layer 621b may include at least one conductive via 625b disposed in a via of the first dielectric layer 622b, and at least one conductive pad. In some embodiments, the first re-layer 621b may further include at least one trace. The conductive via 625b is electrically connected to the conductive post 113 of the semiconductor die 11.

[0084] In some embodiments, the first dielectric layer 622b may be made of an insulating or dielectric material, such as polypropylene (PP). It should be noted that the first dielectric layer 622b may comprise or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) including a photoinitiator. The first dielectric layer 622b defines at least one through-hole extending through the first dielectric layer 622b.

[0085] In some embodiments, the second redistribution layer 623b is electrically connected to the first redistribution layer 621b. The second redistribution layer 623b may include a seed layer and a conductive layer. The seed layer may be made of, for example, titanium or copper. In some embodiments, the seed layer may include a titanium layer and a copper layer. The conductive layer may be made of, for example, a conductive metal, such as copper; or another metal or combination of metals. However, in some embodiments, the seed layer may be omitted. The second redistribution layer 623b may include at least one conductive via 626b disposed in a via of the second dielectric layer 624b, and at least one conductive pad. In some embodiments, the second redistribution layer 621b may further include at least one trace. In some embodiments, the second redistribution layer 623b is electrically connected to the first redistribution layer 621b through the conductive via 626b.

[0086] In some embodiments, the second dielectric layer 624b may be made of an insulating or dielectric material, such as polypropylene (PP). It should be noted that the second dielectric layer 624b may comprise or be formed of a cured photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) including a photoinitiator. The second dielectric layer 624b defines at least one through-hole extending through the second dielectric layer 624b.

[0087] refer to Figure 26 Multiple solder balls 15c are mounted on the second wiring layer 62b, and the solder balls 15c are electrically connected to the second wiring layer 62b. The material of the solder connector 15c can be: a conductive metal, such as tin; or another metal or a combination of metals.

[0088] refer to Figure 27 The carrier 61 and release layer 63 are removed to form a semiconductor wafer-level package 2c. The semiconductor wafer-level package 2c includes at least one semiconductor die 11, a first wiring layer 62a, a second wiring layer 62b, a package body 13, and a plurality of conductive elements 14c. The semiconductor die 11 has an active surface 111 and a rear surface 112. The second wiring structure 62b is electrically connected to the active surface 111 of the semiconductor die 11. The first wiring layer 62a is disposed adjacent to the rear surface 112 of the semiconductor die 11, and the second wiring layer 62b is disposed adjacent to the active surface 111 of the semiconductor die 11. The package body 13 surrounds at least one semiconductor die 11. The package body 13 is formed of a packaging material, and the Young's modulus of the package body 13 is between 0.001 GPa and 1 GPa. The conductive elements 14c are embedded in the package body 13 and are electrically connected to the first wiring layer 62a and the second wiring layer 62b.

[0089] Subsequently, a monomerization process is performed to cut semiconductor wafer-level packages 2c to form such Figure 4Each of the semiconductor package structures 1c shown.

[0090] Unless otherwise specified, spatial descriptions are indicated relative to the orientation shown in the figures, such as "above," "below," "up," "left," "right," "down," "top," "bottom," "vertical," "horizontal," "side," "above," "below," "upper part," "above," "below," etc. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantage of the embodiments disclosed herein is that they will not deviate from such arrangements.

[0091] As used herein, the terms “approximately,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples where the event or situation occurred precisely or very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the two numerical values ​​may be considered “substantially” the same or equal.

[0092] If the displacement between two surfaces does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered to be coplanar or substantially coplanar.

[0093] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within that range, as if each numerical value and subrange were explicitly specified.

[0094] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between artistic representations in this disclosure and actual equipment due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically described. This specification and drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A semiconductor package structure comprising: Semiconductor dies with active surfaces; At least one wiring structure electrically connected to the active surface of the semiconductor die; A package that surrounds the semiconductor die, wherein the package is formed of a package material and the Young's modulus of the package is between 0.001 GPa and 1.0 GPa, wherein the package defines a recessed portion disposed on the periphery of the semiconductor package structure; Multiple conductive elements are embedded in the package and electrically connected to the at least one wiring structure, wherein a portion of the conductive elements protrudes from the recessed portion of the package; Multiple solder connectors are electrically connected to the bottom of the at least one wiring structure; and A substrate electrically connected to the plurality of solder connectors, wherein the warp shape of at least one wiring structure is different from the warp shape of the substrate.

2. The semiconductor packaging structure according to claim 1, wherein the plurality of conductive elements are solder balls.

3. The semiconductor packaging structure according to claim 2, wherein the material of the plurality of conductive elements is tin.

4. The semiconductor packaging structure according to claim 1, wherein the height of the plurality of conductive elements is greater than the thickness of the semiconductor die.

5. The semiconductor packaging structure according to claim 1, wherein the package comprises silicone rubber and a variety of silicon fillers, and the content of the silicon fillers in the package is 1% to 30% by weight.

6. A semiconductor wafer-level package comprising: At least one semiconductor die having an active surface; At least one wiring layer electrically connected to the active surface of the semiconductor die; A package that surrounds the at least one semiconductor die, wherein the package is formed of a package material and the Young's modulus of the package is between 0.001 GPa and 1 GPa, wherein the package defines a recessed portion disposed on the periphery of the semiconductor die; Multiple conductive elements are embedded in the package and electrically connected to the at least one wiring layer, wherein a portion of the conductive elements protrudes from the recessed portion of the package; and Multiple solder connectors are electrically connected to the bottom of the at least one wiring structure; and A substrate electrically connected to the plurality of solder connectors, wherein the warp shape of at least one wiring structure is different from the warp shape of the substrate.

7. The semiconductor wafer-level package of claim 6, wherein the plurality of conductive elements are solder balls.

8. The semiconductor wafer-level packaging according to claim 6, wherein the packaging material comprises silicone rubber and a variety of silicon fillers, and the content of the silicon fillers in the packaging material is 1% to 30% by weight.

9. A semiconductor manufacturing process, comprising: (a) Provide a carrier; (b) Forming a wiring layer on the carrier; (c) Mount at least one semiconductor die on the wiring layer; (d) Forming a package and a plurality of conductive elements, wherein the package surrounds the at least one semiconductor die, the conductive elements are embedded in the package and electrically connected to the wiring layer, wherein the package is formed of a package material and the Young's modulus of the package is between 0.001 GPa and 1 GPa, wherein the package defines a recessed portion adjacent to the semiconductor die, and a portion of the conductive elements protrudes from the recessed portion of the package; (e) Forming a plurality of solder connectors to be electrically connected to the wiring layer; (f) Electrically connecting the substrate to the plurality of solder connectors; and (g) Perform a reflow process, wherein the warpage shape of the wiring layer is different from the warpage shape of the substrate.

10. The semiconductor manufacturing process of claim 9, wherein step (d) comprises: (d1) Forming the package that surrounds the at least one semiconductor die; (d2) Forming a plurality of perforations extending through the package; and (d3) The conductive element is formed in the perforation.

11. The semiconductor manufacturing process of claim 10, wherein in step (d2), a laser is used to drill the perforation.

12. The semiconductor manufacturing process of claim 9, wherein step (d) comprises: (d1) Forming the conductive element electrically connected to the wiring layer; and (d2) Forming the package that surrounds the at least one semiconductor die and the conductive element.

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