Semiconductor device and manufacturing method

Abstract

The present invention provides a semiconductor device and a manufacturing method, wherein fluctuations in the characteristics of a temperature sensor are preferably suppressed in the semiconductor device. The semiconductor device comprises: a semiconductor substrate having a drift region of a first conductivity type provided therein; a transistor portion provided on the semiconductor substrate; a diode portion provided on the semiconductor substrate; a well region of a second conductivity type exposed on the upper surface of the semiconductor substrate; a temperature detection portion adjacent to the diode portion and provided above the well region in a plan view; and an upper surface-side lifetime control region provided on the upper surface side of the semiconductor substrate relative to the diode portion and in a region that does not overlap with the temperature detection portion in a plan view.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method. Background Art

[0002] Conventionally, there is known a technique of providing a temperature sensor on a semiconductor substrate on which semiconductor elements such as insulated gate bipolar transistors (IGBTs) are formed (for example, see Patent Documents 1 to 3).

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2017-147435

[0004] Patent Document 2: Japanese Patent Application Laid-Open No. 2008-235405

[0005] Patent Document 3: Japanese Patent Application Laid-Open No. 2016-12647 Summary of the Invention

[0006] Technical issues

[0007] In a semiconductor device, it is desirable to suppress characteristic fluctuations of a temperature sensor.

[0008] Technical Solution

[0009] In order to solve the above-mentioned problems, in a first embodiment of the present invention, a semiconductor device is provided having a semiconductor substrate provided with a drift region of a first conductivity type. The semiconductor device may include a transistor portion provided on the semiconductor substrate. The semiconductor device may include a diode portion provided on the semiconductor substrate. The semiconductor device may include a well region of a second conductivity type exposed on the upper surface of the semiconductor substrate. The semiconductor device may include a temperature detection portion, which is adjacent to the diode portion in a plan view and is provided above the well region. The semiconductor device may include an upper surface-side lifetime control region, which is provided on the upper surface side of the semiconductor substrate in the diode portion and is provided in an area that does not overlap with the temperature detection portion in a plan view.

[0010] In a plan view, the temperature detection portion may be sandwiched between the adjacent diode portions.

[0011] In a second embodiment of the present invention, a semiconductor device is provided that includes a semiconductor substrate having a drift region of a first conductivity type. The semiconductor device may include an active portion having a transistor portion and a diode portion provided on the semiconductor substrate. The semiconductor device may include a voltage-resistant structure portion provided on the semiconductor substrate and surrounding the active portion when viewed from above. The semiconductor device may include a well region of a second conductivity type exposed on the upper surface of the semiconductor substrate. The semiconductor device may include a temperature detection portion provided between the active portion and the voltage-resistant structure portion when viewed from above and provided above the well region. The semiconductor device may include an upper surface-side lifetime control region provided on the upper surface side of the semiconductor substrate in the diode portion and provided in an area that does not overlap with the temperature detection portion when viewed from above.

[0012] The distance between the temperature detection portion and the upper surface-side lifetime control region is 90 μm or less in a plan view.

[0013] The upper surface-side lifetime control region may be provided in a region that does not overlap with the well region in a plan view.

[0014] The transistor portion and the diode portion may include a trench portion extending from a surface of the semiconductor substrate to the inside thereof. A portion of the trench portion may be provided inside the well region.

[0015] The diode portion may include a cathode region of the second conductivity type provided within the semiconductor substrate and exposed on the lower surface of the semiconductor substrate. In a plan view, an end portion of the upper surface-side lifetime control region may be disposed between the cathode region and the temperature detection portion.

[0016] In a third embodiment of the present invention, a semiconductor device is provided that includes a semiconductor substrate having a drift region of a first conductivity type. The semiconductor device may include a transistor portion provided on the semiconductor substrate. The semiconductor device may include a diode portion provided on the semiconductor substrate. The semiconductor device may include a well region of a second conductivity type exposed on the upper surface of the semiconductor substrate. The semiconductor device may include a temperature detection portion provided above the well region. The semiconductor device may include an upper surface-side lifetime control region, wherein the upper surface-side lifetime control region is provided on the upper surface side of the semiconductor substrate in the diode portion and is at a distance of 90 μm or less from the temperature detection portion when viewed from above.

[0017] In a fourth aspect of the present invention, a semiconductor device is provided that includes a semiconductor substrate having a drift region of a first conductivity type. The semiconductor device may include a well region of a second conductivity type exposed on the upper surface of the semiconductor substrate. The semiconductor device may include a temperature detection portion disposed above the well region. The semiconductor device may include an upper surface-side lifetime control region, the upper surface-side lifetime control region being disposed in a region overlapping with the temperature detection portion when viewed from above and containing a lifetime control agent. The temperature detection portion may not contain a lifetime control agent.

[0018] In a fifth aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method can form a temperature detection portion above a semiconductor substrate. The method can form a mask portion to shield the temperature detection portion. The method can introduce a lifetime control agent from the upper surface side of the semiconductor substrate to form an upper surface-side lifetime control region in an area that does not overlap with the temperature detection portion when viewed from above.

[0019] In a sixth aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method can introduce a lifetime control agent from the upper surface side of a semiconductor substrate to form an upper surface lifetime control region. The method can also form a temperature detection portion above the semiconductor substrate at a position overlapping the upper surface lifetime control region.

[0020] It should be noted that the above summary of the invention does not list all the essential features of the present invention. In addition, sub-combinations of these feature groups may also constitute other inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 1 is a diagram showing the structure of the upper surface of a semiconductor device 100 according to an embodiment of the present invention.

[0022] Figure 2 It is magnified Figure 1 Top view of area A in FIG.

[0023] Figure 3 Yes Figure 2 An example of the BB cross section in FIG.

[0024] Figure 4 It is a diagram showing another example of the planar structure of the semiconductor device 100 .

[0025] Figure 5 It is magnified Figure 4 Top view of area C in FIG.

[0026] Figure 6 Yes Figure 5 FIG. 1 is a diagram showing an example of a DD cross section in FIG.

[0027] Figure 7It is a diagram showing another example of the planar structure of the semiconductor device 100 .

[0028] Figure 8 It is a diagram showing another example of the planar structure of the semiconductor device 100 .

[0029] Figure 9 It is magnified Figure 8 Top view of area E in FIG.

[0030] Figure 10 It is a diagram showing another example of the planar structure of the semiconductor device 100 .

[0031] Figure 11 It means in Figures 1 to 10 FIG. 1 is a diagram showing an example of a method for manufacturing the semiconductor device 100 described in .

[0032] Figure 12 It is a cross-sectional view illustrating an example of the semiconductor device 200 .

[0033] Figure 13 2 is a diagram showing an example of a method for manufacturing the semiconductor device 200 .

[0034] Figure 14 It is a cross-sectional view illustrating another example of the semiconductor device 200 .

[0035] Figure 15 Yes Figure 14 FIG. 1 is a diagram showing an example of a method for manufacturing a semiconductor device 200 .

[0036] Figure 16 is a cross-sectional view showing another example of the semiconductor device 200 .

[0037] Figure 17 is a cross-sectional view showing another example of the semiconductor device 200 .

[0038] Explanation of symbols

[0039] 10···Semiconductor substrate, 12···Emitter region, 14···Base region, 15···Contact region, 18···Drift region, 20···Buffer region, 21···Upper surface, 22···Collector region, 23···Lower surface, 24···Collector, 30···Dummy trench portion, 38···Interlayer insulating film, 40···Trench gate portion, 48···Gate runner, 48-1···Outer peripheral portion, 48-2···Inner portion, 50···Gate metal layer, 52···Emitter, 56···Contact hole, 60···Mesa portion, 70···Transistor portion, 80···Diode portion, 82···Cathode region, 90···boundary region, 100···semiconductor device, 102···active portion, 103···temperature detection region, 104···gate pad, 106···anode pad, 107···current detection portion, 108···cathode pad, 109···current detection pad, 110···upper surface side lifetime control region, 112···well region, 120···temperature detection portion, 122···temperature detection wiring, 126···N-type region, 128···P-type region, 140···outer peripheral end, 150···voltage-resistant structure portion, 200···semiconductor device, 202···mask portion DETAILED DESCRIPTION

[0040] The present invention will be described below by way of embodiments of the invention, but the following embodiments do not limit the invention of the claims. In addition, not all combinations of features described in the embodiments are essential to the solution of the invention.

[0041] In this specification, one side parallel to the depth direction of a semiconductor substrate is referred to as "upper," and the other side is referred to as "lower." Of the two principal surfaces of a substrate, layer, or other component, one is referred to as the upper surface, and the other is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity.

[0042] In each embodiment, an example is shown in which the first conductivity type is n-type (sometimes described as N-type) and the second conductivity type is p-type (sometimes described as P-type). However, the first conductivity type can also be p-type and the second conductivity type can be n-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are of opposite polarity. In addition, N+ type (or P+ type) means that the doping concentration is higher than that of N type (or P type), and N- type (or P- type) means that the doping concentration is lower than that of N type (or P type).

[0043] In this specification, technical matters may be described using rectangular coordinate axes such as the X-axis, Y-axis, and Z-axis. In this specification, the plane parallel to the upper surface of the semiconductor substrate is referred to as the XY plane, and the depth direction perpendicular to the upper surface of the semiconductor substrate is referred to as the Z-axis.

[0044] In this specification, the doping concentration refers to the concentration of the donor or acceptor impurity. In this specification, the difference between the donor and acceptor concentrations may be used as the doping concentration. In addition, when the doping concentration distribution in the doped region has a peak, the peak value can be used as the doping concentration in the doped region. In cases where the doping concentration in the doped region is approximately uniform, the average value of the doping concentration in the doped region can be used as the doping concentration.

[0045] Figure 1 This figure shows the structure of the top surface of a semiconductor device 100 according to one embodiment of the present invention. Semiconductor device 100 includes a semiconductor substrate 10. Semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, or the like. In this example, semiconductor substrate 10 is a silicon substrate. In this specification, the outer peripheral end of semiconductor substrate 10 when viewed from above is referred to as outer peripheral end 140. "Viewed from above" refers to viewing the semiconductor substrate 10 from the top surface side, in a direction perpendicular to the top surface (the Z-axis direction).

[0046] The semiconductor device 100 includes an active portion 102, a temperature detection portion 120, a temperature detection wiring 122, an upper surface lifetime control region 110, a gate metal layer 50, a gate runner 48, and a voltage-resistant structure portion 150. The active portion 102 is a region where the main current flows between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in the on state. In other words, it is a region where current flows in the depth direction of the semiconductor substrate 10 from the upper surface to the lower surface, or from the lower surface to the upper surface. The active portion 102 can be a region surrounded by the gate metal layer 50. The active portion 102 can be a region covered by the emitter described later. In addition, within the region covered by the emitter, the region sandwiched when viewed from above can also be set as the active portion 102. The region where the pads are provided can be excluded from the active portion 102. Semiconductor elements such as transistors and diodes are provided in the active portion 102.

[0047] At least a portion of the gate metal layer 50 is provided between the active portion 102 and the peripheral end 140 in a plane parallel to the upper surface of the semiconductor substrate 10. The gate metal layer 50 is formed of metal and supplies a gate voltage to the element provided in the active portion 102. The gate metal layer 50 is formed above the semiconductor substrate 10 and is insulated from the semiconductor substrate 10 by an insulating film. The gate metal layer 50 can be arranged to surround the active portion 102 in a plane parallel to the upper surface of the semiconductor substrate 10. The gate metal layer 50 is electrically connected to the gate pad 104. The gate pad 104 can be provided in the area surrounded by the gate metal layer 50 in a plan view, or it can be provided between the gate metal layer 50 and the peripheral end 140. Pads such as the anode pad 106 and the cathode pad 108 connected to the temperature detection unit 120 can be provided in the area surrounded by the gate metal layer 50 or between the gate metal layer 50 and the peripheral end 140.

[0048] The gate runner 48 electrically connects the gate metal layer 50 and the elements provided in the active portion 102. The gate runner 48 can be formed of a semiconductor such as polysilicon doped with impurities. The gate runner 48 is formed above the semiconductor substrate 10 and is insulated from the semiconductor substrate 10 by an insulating film. The gate runner 48 can be provided along the gate metal layer 50. The gate runner 48 of this example is provided so as to surround the active portion 102 when viewed from above. At least a portion of the gate runner 48 can overlap with the gate metal layer 50 when viewed from above. As an example, an interlayer insulating film is provided between the gate runner 48 and the gate metal layer 50, but the gate runner 48 and the gate metal layer 50 are electrically connected via a contact hole provided in the interlayer insulating film. In each figure, the gate runner 48 is indicated by a thick solid line.

[0049] The gate runner 48 may also be disposed in a region overlapping with the active portion 102. For example, the gate runner 48 may be disposed so as to intersect the active portion 102 in a plan view. Providing the gate runner 48 in a region overlapping with the active portion 102 allows a gate voltage with a small delay and voltage drop to be supplied to a region separated from the gate metal layer 50. Furthermore, the gate runner 48 may be disposed so as to surround a pad such as the gate pad 104 in a plan view.

[0050] The active portion 102 includes a transistor portion 70 and a diode portion 80. In the various drawings, the region of the transistor portion 70 is sometimes indicated by I, and the region of the diode portion 80 is sometimes indicated by F. The transistor portion 70 includes transistors such as IGBTs. The transistor portion 70 is a region in which a P+ type collector region is exposed on the lower surface of the semiconductor substrate 10, and a unit structure including an N+ type emitter region and a MOS gate structure is periodically formed on the upper surface of the semiconductor substrate 10. The diode portion 80 includes diodes such as a freewheeling diode (FWD). The diode portion 80 is a region in which an N+ type cathode region is exposed on the lower surface of the semiconductor substrate 10.

[0051] In this example, the diode portion 80 is arranged in a region sandwiched between the transistor portion 70 in a plan view. Alternatively, the diode portion 80 may be surrounded by the transistor portion 70 in a plan view. A P+ type well region may be provided in the active portion 102. Even if a portion of the transistor portion 70 surrounding the diode portion 80 is replaced with a well region in a plan view, the diode portion 80 is still surrounded by the transistor portion 70 in this specification. In other words, the state in which the diode portion 80 is surrounded by the transistor portion 70 and the well region on the upper surface of the semiconductor substrate 10 is also referred to as the diode portion 80 being surrounded by the transistor portion 70 in this specification.

[0052] The temperature detection portion 120 is arranged above the semiconductor substrate 10 to detect the temperature of the semiconductor substrate 10. In this example, the temperature detection portion 120 is a PN junction diode formed from a semiconductor material such as polysilicon. The temperature detection wiring 122 connects the temperature detection portion 120 to the anode pad 106 and the cathode pad 108. In this example, the anode pad 106 and the cathode pad 108 are arranged between the end of the active portion 102 and the outer peripheral end 140*. Therefore, the temperature detection wiring 122 extends from the temperature detection portion 120 toward the end of the active portion 102 and is connected to the anode pad 106 and the cathode pad 108 arranged outside the end of the active portion 102. The temperature detection wiring 122 can be a metal wiring arranged above the semiconductor substrate 10 or a semiconductor wiring such as polysilicon. In a plan view, a P+ type well region can be arranged in the area of ​​the semiconductor substrate 10 that overlaps with the temperature detection portion 120 and the temperature detection wiring 122.

[0053] The temperature detection section 120 is arranged adjacent to the diode section 80 in a plan view. The temperature detection section 120 and the diode section 80 being adjacent means that, in a plan view, the transistor section 70 is not provided between the temperature detection section 120 and the diode section 80. Alternatively, the temperature detection section 120 and the diode section 80 may be considered adjacent if no N+ type emitter region is provided between them. A well region may be provided between the temperature detection section 120 and the diode section 80 in a plan view.

[0054] The temperature detection portion 120 of this example is sandwiched between the adjacent diode portions 80 in the X-axis direction when viewed from above. The temperature detection portion 120 can be surrounded by the adjacent diode portions 80 when viewed from above. When viewed from above, even if a part of the diode portion 80 surrounding the temperature detection portion 120 is replaced with a well region, the temperature detection portion 120 is still surrounded by the diode portion 80 in this specification. That is, in this specification, the state in which the temperature detection portion 120 is surrounded by the diode portion 80 and the well region on the upper surface of the semiconductor substrate 10 is also referred to as the temperature detection portion 120 being surrounded by the diode portion 80. The temperature detection portion 120 of this example is surrounded by the well region and the diode portion 80 below the temperature detection wiring 122. In addition, the diode portion 80 of this example is surrounded by the well region and the transistor portion 70 below the temperature detection wiring 122.

[0055] The voltage-resistant structure 150 is provided on the upper surface of the semiconductor substrate 10 between the active portion 102 and the peripheral end 140 of the semiconductor substrate 10. The voltage-resistant structure 150 of this example is provided between the gate metal layer 50 and the peripheral end 140. The voltage-resistant structure 150 can be arranged in a ring shape on the upper surface of the semiconductor substrate 10 in a manner surrounding the active portion 102. The voltage-resistant structure 150 of this example is arranged along the peripheral end 140 of the semiconductor substrate 10. The voltage-resistant structure 150 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The voltage-resistant structure 150 has a structure such as a guard ring, a field plate, a surface electric field reduction, or a combination thereof.

[0056] The upper-side lifetime control region 110 is provided on the upper surface side of the semiconductor substrate 10 in the diode portion 80. The upper surface side of the semiconductor substrate 10 may refer to a region located closer to the upper surface than the center in the depth direction of the semiconductor substrate 10. Furthermore, when lifetime control regions are provided at different depths of the semiconductor substrate 10, the uppermost lifetime control region may be defined as the upper-side lifetime control region 110.

[0057] The upper surface side lifetime control region 110 is a region where a lifetime control agent is intentionally introduced by injecting impurities into the interior of the semiconductor substrate 10. The lifetime of electrons or holes in the region where the lifetime control agent is intentionally introduced is shorter than the lifetime of carriers in the region where the lifetime control agent is not intentionally introduced. The lifetime control agent can be a recombination center of carriers, a crystal defect, a hole, a compound hole, a dangling bond formed by holes, or a compound defect or dislocation of holes, compound holes, dangling bonds formed by holes and elements constituting the semiconductor substrate 10, or a rare gas element such as helium or neon, hydrogen, etc. By providing the upper surface side lifetime control region 110 in the diode portion 80, the carrier lifetime in the diode portion 80 is adjusted, and the loss during reverse recovery can be reduced. It should be noted that the upper surface side lifetime control region 110 can be formed by electron beam irradiation. In the case of electron beam irradiation, due to its strong penetrating power, the lifetime control agent is distributed roughly uniformly from the top surface to the bottom surface, whether irradiated from the top surface or from the bottom surface of the semiconductor substrate 10. However, if any position on the top surface side is set as the top surface side lifetime control region 110, the same discussion as for other lifetime control agents applies.

[0058] The upper surface side lifetime control region 110 may be provided on the entire diode portion 80 in a plan view, or may be provided on a portion thereof. Figure 1 In FIG. 1 , the region where the upper surface side lifetime control region 110 is provided is shaded with oblique lines. Figure 1 In the example, the upper surface side lifetime control region 110 is provided in the entire diode portion 80. The upper surface side lifetime control region 110 is provided in a region that does not overlap with the temperature detection portion 120 when viewed from above. The upper surface side lifetime control region 110 may also be provided between the diode portion 80 and the temperature detection portion 120 when viewed from above. In addition, the upper surface side lifetime control region 110 may be provided in at least a portion of the transistor portion 70. Figure 1 In the example, the upper surface lifetime control region 110 is provided in the portion of the transistor portion 70 that is in contact with the diode portion 80. However, in other examples, the upper surface lifetime control region 110 may be provided over a wider range of the transistor portion 70. For example, the upper surface lifetime control region 110 may be provided over the entire transistor portion 70. By also providing the upper surface lifetime control region 110 in the transistor portion 70, it is possible to suppress the flow of holes from the base region 14 of the transistor portion 70 to the cathode region 82 of the diode portion 80 during reverse recovery of the diode portion 80, thereby reducing reverse recovery loss.

[0059] As an example, the upper surface-side lifetime control region 110 is formed by irradiating a lifetime control agent, such as helium or protons, from the upper surface side of the semiconductor substrate 10. By arranging the upper surface-side lifetime control region 110 so as not to overlap with the temperature detection portion 120, it is possible to suppress irradiation of the temperature detection portion 120 with the lifetime control agent, such as helium, during the formation of the upper surface-side lifetime control region 110. Therefore, it is possible to suppress injection of the lifetime control agent into the temperature detection portion 120 and suppress fluctuations in the characteristics of the temperature detection portion 120. In this example, since the temperature detection portion 120 is provided adjacent to the diode portion 80, the temperature of the diode portion 80 during operation can be detected with high accuracy. Furthermore, by providing the upper surface-side lifetime control region 110 on the diode portion 80, the carrier lifetime in the diode portion 80 can be adjusted, and injection of the lifetime control agent into the temperature detection portion 120 adjacent to the diode portion 80 can be suppressed, thereby also suppressing fluctuations in the characteristics of the temperature detection portion 120.

[0060] Figure 2 It is magnified Figure 1 A top view of region A in FIG. Region A includes a portion of the transistor portion 70, a portion of the diode portion 80, and a portion of the temperature detection portion 120. The semiconductor device 100 of this embodiment includes a trench gate portion 40, a dummy trench portion 30, a well region 112, an emitter region 12, a base region 14, and a contact region 15 formed inside the upper surface side of the semiconductor substrate 10. An interlayer insulating film is provided above the semiconductor substrate 10, and an emitter is provided above the interlayer insulating film, but Figure 2 The emitter electrode can be connected to the emitter region 12, base region 14, contact region 15 and well region 112 on the upper surface of the semiconductor substrate 10 through a contact hole provided in the interlayer insulating film. In addition, the temperature detection unit 120 is arranged above the interlayer insulating film.

[0061] Metal portions such as the emitter and gate metal layer 50 can be formed of aluminum or an aluminum-silicon alloy. Each electrode can have a barrier metal formed of titanium or a titanium compound below the region formed of aluminum, or a plug formed of tungsten in the contact hole.

[0062] The trench gate portion 40 is arranged to extend along a predetermined extension direction on the upper surface of the semiconductor substrate 10. In this example, the extension direction of each trench portion is parallel to the extension direction (Y-axis direction) of the temperature detection wiring 122. The trench gate portion 40 of this example has a length in the Y-axis direction and a width in the X-axis direction on the upper surface of the semiconductor substrate 10. The trench gate portion 40 has a groove arranged from the upper surface of the semiconductor substrate 10 toward the inside, a gate insulating film covering the inner wall of the groove, and a gate electrode surrounded by the gate insulating film. The gate electrode in the trench gate portion 40 is connected to the gate channel 48 or the gate metal layer 50. The trench gate portion 40 is extended to a position overlapping with the gate channel 48 or the gate metal layer 50 when viewed from above.

[0063] The dummy trench portion 30 extends along a predetermined extension direction (in this example, the Y-axis direction) on the upper surface of the semiconductor substrate 10. The dummy trench portion 30 in this example has a length in the Y-axis direction and a width in the X-axis direction on the upper surface of the semiconductor substrate 10. The dummy trench portion 30 includes a groove extending inward from the upper surface of the semiconductor substrate 10, a dummy insulating film covering the inner wall of the groove, and a dummy electrode surrounded by the dummy insulating film. The dummy electrode in the dummy trench portion 30 is connected to the emitter 52.

[0064] In the transistor portion 70, one or more trench gate portions 40 are arranged in a manner separated from each other along the width direction of the trench gate portion 40 (in this example, the X-axis direction). In this specification, the direction in which each trench portion is arranged is sometimes referred to as the arrangement direction. In the transistor portion 70, one or more trench gate portions 40 and one or more dummy trench portions 30 may be alternately arranged along the arrangement direction.

[0065] In the diode portion 80, one or more dummy trench portions 30 are arranged along the arrangement direction. In this specification, the trench gate portion 40 and the dummy trench portion 30 are sometimes referred to as trench portions. Furthermore, in the arrangement direction of the trench portions, the region of the semiconductor substrate 10 sandwiched between the two trench portions is referred to as a mesa portion 60. The mesa portion 60 can refer to the region extending from the top surface of the semiconductor substrate 10 to the same depth as the bottom end of the trench portion. The transistor portion 70 and the diode portion 80 each have one or more mesa portions 60.

[0066] An N+ type emitter region 12 is exposed on the upper surface of the mesa portion 60 of the transistor portion 70. The emitter region 12 is provided in contact with the trench gate portion 40. A P+ type contact region 15 may also be exposed on the upper surface of the mesa portion 60 of the transistor portion 70. The emitter region 12 and the contact region 15 are connected to the emitter electrode via a contact hole provided in the interlayer insulating film.

[0067] The contact region 15 may be in contact with at least one of the trench gate portion 40 and the dummy trench portion 30, or may be separated from at least one of the trench gate portion 40 and the dummy trench portion 30. In the mesa portion 60 of the transistor portion 70 of this embodiment, the emitter region 12 and the contact region 15 are alternately arranged along the extension direction of the trench portion. In the mesa portion 60 of other embodiments, the emitter region 12 and the contact region 15 may each be in the shape of a stripe having a length in the extension direction of the trench portion. In this case, in a plan view, the emitter region 12 is provided at both ends of the mesa portion 60 in contact with each trench portion, and the contact region 15 is provided so as to be sandwiched by the emitter region 12.

[0068] A P-type base region 14 is exposed on the upper surface of the mesa portion 60 of the diode portion 80. The base region 14 of the mesa portion 60 is connected to the emitter via a contact hole provided in the interlayer insulating film. The base region 14 of the diode portion 80 functions as an anode region. The doping concentration of the contact region 15 is higher than that of the base region 14. Furthermore, the base region 14 is provided below the emitter region 12 and the contact region 15 in the mesa portion 60 of the transistor portion 70.

[0069] A well region 112 is provided in a region of the semiconductor substrate 10 below the temperature detection portion 120. The entire temperature detection portion 120 may be disposed at a position overlapping the well region 112. The well region 112 may be provided over a wider range than the temperature detection portion 120 in a plan view.

[0070] The groove portion that does not face the well region 112 in the extending direction of the groove portion (in this example, the Y-axis direction) can be provided parallel to the temperature detection portion 120 and the temperature detection wiring 122 and extending in the Y-axis direction. The end of the groove portion that faces the well region 112 in the Y-axis direction can be provided at a position overlapping with the well region 112. In this example, no groove portion is provided below the temperature detection portion 120.

[0071] exist Figure 2 In FIG. 1 , the range where the cathode region 82 is provided and the range where the upper surface side lifetime control region 110 is provided are indicated by dotted lines. The cathode region 82 of the diode portion 80 can be provided separately from the well region 112 and the temperature detection portion 120 in a plan view. Figure 2 As shown, in a top view, the transistor portion 70 is not provided between the cathode region 82 and the temperature detection portion 120. In other words, the emitter region 12 is not provided between the cathode region 82 and the temperature detection portion 120. In addition, the trench gate portion 40 is not provided between the cathode region 82 and the temperature detection portion 120. Therefore, the temperature detection portion 120 is provided adjacent to the diode portion 80. The temperature detection portion 120 of this example is adjacent to the diode portion 80 in both the X-axis direction and the Y-axis direction.

[0072] The upper surface side lifetime control region 110 is arranged to overlap with the entire cathode region 82 when viewed from above. The upper surface side lifetime control region 110 can be arranged in a range wider than the cathode region 82 when viewed from above. The upper surface side lifetime control region 110 can also be arranged between the well region 112 and the cathode region 82 when viewed from above. Among them, the upper surface side lifetime control region 110 can be arranged in a range that does not overlap with the well region 112 when viewed from above. By setting the upper surface side lifetime control region 110 near the well region 112, it is possible to control the lifetime of carriers in a wide range while suppressing the injection of lifetime control agents into the temperature detection part 120. In other examples, the upper surface side lifetime control region 110 can be set to a position in contact with the well region 112, or can be set in a range overlapping with the well region 112.

[0073] Figure 3 Yes Figure 2 FIG1 is a diagram showing an example of a BB cross section in FIG1 . The BB cross section is an XZ plane passing through the temperature detection unit 120, the diode unit 80, and the transistor unit 70. In this cross section, the semiconductor device 100 includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, the collector electrode 24, the temperature detection unit 120, and the temperature detection wiring 122.

[0074] Semiconductor substrate 10 has an upper surface 21 and a lower surface 23. Interlayer insulating film 38 is formed to cover at least a portion of upper surface 21 of semiconductor substrate 10. Through-holes such as contact holes 56 are formed in interlayer insulating film 38. Contact holes 56 expose upper surface 21 of semiconductor substrate 10. Contact holes 56 can be provided for each mesa portion 60 of transistor section 70 and diode section 80. Interlayer insulating film 38 can be made of silicate glass such as PSG or BPSG, an oxide film, a nitride film, or a laminate of these films.

[0075] The emitter 52 is formed on the upper surface of the semiconductor substrate 10 and the interlayer insulating film 38. The emitter 52 is also formed inside the contact hole 56 and is connected to the emitter region 12 and the contact region 15 (see FIG. Figure 2 ) and is in contact with the base region 14. The emitter 52 of this example is not arranged in the region where the temperature detection portion 120 is provided.

[0076] The collector electrode 24 is formed on the lower surface 23 of the semiconductor substrate 10. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0077] Temperature detection unit 120 is provided above upper surface 21 of semiconductor substrate 10. An interlayer insulating film 38, such as an oxide film, is provided between temperature detection unit 120 and upper surface 21 of semiconductor substrate 10. In this embodiment, temperature detection unit 120 is a PN junction diode having an N-type region 126 and a P-type region 128. Each of N-type region 126 and P-type region 128 can be connected to temperature detection wiring 122.

[0078] In this example, the semiconductor substrate 10 is provided with an N-type drift region 18, an N+ type emitter region 12, a P-type base region 14, a P+ type well region 112, an N+ type buffer region 20, an N+ type cathode region 82 and a P+ type collector region 22.

[0079] Emitter region 12 is provided in contact with upper surface 21 of semiconductor substrate 10 in mesa portion 60 of transistor portion 70. Emitter region 12 has a higher doping concentration than drift region 18. Emitter region 12 contains N-type impurities such as phosphorus.

[0080] The base region 14 is provided between the emitter region 12 and the drift region 18. The base region 14 contains P-type impurities such as boron. An N+ type accumulation region having a higher doping concentration than the drift region 18 may be provided between the base region 14 and the drift region 18.

[0081] The well region 112 is provided below the temperature detection portion 120 and the temperature detection wiring 122. The well region 112 is a P+ type region having a higher doping concentration than the base region 14. The well region 112 may be exposed on the upper surface 21 of the semiconductor substrate 10. The well region 112 may be provided at a position deeper than the base region 14. In this example, the base region 14 is provided at a position shallower than the lower end of the groove portion, and the well region 112 is provided at a position deeper than the lower end of the groove portion. The well region 112 may be provided at Figure 1 Below the gate metal layer 50 and gate runner 48 are illustrated.

[0082] The collector region 22 is disposed in contact with the lower surface 23 of the semiconductor substrate 10. The doping concentration of the collector region 22 may be higher than the doping concentration of the base region 14. The collector region 22 may contain the same P-type impurities as the base region 14, or may contain different P-type impurities.

[0083] The cathode region 82 is disposed in contact with the lower surface 23 of the semiconductor substrate 10. The doping concentration of the cathode region 82 is higher than the doping concentration of the drift region 18. The buffer region 20 is disposed between the collector region 22, the cathode region 82, and the drift region 18, and has one or more doping concentration peaks with a higher donor concentration than that of the drift region 18. The buffer region 20 contains N-type impurities such as hydrogen. The buffer region 20 can function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22.

[0084] The trench gate portion 40 extends from the upper surface 21 of the semiconductor substrate 10 through the emitter region 12 and the base region 14 to the drift region 18. The trench gate portion 40 includes a trench formed on the upper surface 21 of the semiconductor substrate 10, a gate insulating film covering the inner wall of the trench, and a gate electrode surrounded by the gate insulating film. Figure 3 In FIG. 1 , the gate electrode is shaded with oblique lines. The gate electrode is formed of a conductive material such as polysilicon.

[0085] The gate electrode includes a region facing the base region 14. The trench gate portion 40 in this cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10, but the gate electrode is connected to the gate runner 48 or the gate metal layer 50 in other cross sections. When a predetermined gate voltage is applied to the gate electrode, a channel having an electron inversion layer is formed in the surface layer of the interface between the trench gate portion 40 and the base region 14.

[0086] The dummy trench portion 30 penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 and reaches the drift region 18. The dummy trench portion 30 provided in the transistor portion 70 also penetrates the emitter region 12. The dummy trench portion 30 includes a groove formed on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film covering the inner wall of the groove, and a dummy electrode surrounded by the dummy insulating film. Figure 3 In the figure, dummy electrodes are shaded with oblique lines. The dummy electrodes are formed of a conductive material such as polysilicon.

[0087] The dummy trench portion 30 in this cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10, but the dummy electrode is connected to the emitter 52 in other cross sections. By providing the dummy trench portion 30 connected to the emitter potential, the gate-collector capacitance of the semiconductor device 100 can be reduced.

[0088] In the transistor portion 70, a collector region 22 is provided in a region in contact with the lower surface 23 of the semiconductor substrate 10. Holes are injected from the collector region 22, thereby modulating the conductivity of the drift region 18 of the transistor portion 70. A trench gate portion 40 and a dummy trench portion 30 are provided in the transistor portion 70. Furthermore, an emitter region 12 and a base region 14 are provided in the mesa portion 60 of the transistor portion 70.

[0089] In the diode portion 80, a cathode region 82 is provided in an area in contact with the lower surface 23 of the semiconductor substrate 10. In addition, a collector region 22 is also provided in an area in contact with the lower surface 23 of the semiconductor substrate 10 below the well region 112. Thus, the distance between the well region 112 provided at a deep position and the cathode region 82 is increased, and the withstand voltage can be ensured. In addition, a dummy groove portion 30 is provided in the diode portion 80. A base region 14 is provided in the mesa portion 60 of the diode portion 80. It should be noted that the collector region 22 can be provided in an area in contact with the lower surface 23 of the semiconductor substrate 10 where the cathode region 82 is not provided. In this example, the collector region 22 is provided in an area overlapping with the well region 112 and an area overlapping with the temperature detection portion 120. In addition, in a plan view, a collector region 22 is also provided in an area between the diode portion 80 and the temperature detection portion 120.

[0090] In this specification, the region of the active portion 102 between the diode portion 80 and the temperature detection portion 120 in a top view is referred to as the boundary region 90. In the boundary region 90, the collector region 22 is provided on the lower surface 23 of the semiconductor substrate 10. Neither the emitter region 12 nor the trench gate portion 40 is provided in the boundary region 90. As shown in this example, even though the boundary region 90 is provided between the diode portion 80 and the temperature detection portion 120, the diode portion 80 is adjacent to the temperature detection portion 120 because the transistor portion 70 is not provided between the diode portion 80 and the temperature detection portion 120. A well region 112 is provided in a portion of the boundary region 90. The well region 112 of the boundary region 90 can be provided continuously with the well region 112 below the temperature detection portion 120. A dummy trench portion 30 can be provided in the boundary region 90. In the boundary region 90, at least one dummy trench portion 30 can be disposed within the well region 112. The base region 14 can be provided in the mesa portion 60 of the boundary region 90. Furthermore, contact holes 56 for connecting emitter 52 to well region 112 may be provided in interlayer insulating film 38 in boundary region 90. Providing contact holes 56 allows holes to be extracted from well region 112 even when semiconductor device 100 is turned off.

[0091] An upper surface-side lifetime control region 110 can be provided in at least a portion of the boundary region 90. The upper surface-side lifetime control region 110 of the boundary region 90 is provided continuously with the upper surface-side lifetime control region 110 of the diode portion 80. By also providing the upper surface-side lifetime control region 110 in the boundary region 90, the lifetime of carriers in the region near the diode portion 80 can also be adjusted. On the other hand, the upper surface-side lifetime control region 110 is provided at a position that does not overlap with the temperature detection portion 120 when viewed from above. Thus, even if the lifetime control agent is irradiated from the upper surface 21 side of the semiconductor substrate 10, irradiation of the lifetime control agent to the temperature detection portion 120 can be suppressed. Therefore, irradiation of the lifetime control agent from the upper surface 21 side of the semiconductor substrate 10 is facilitated. Compared to the case where the lifetime control agent is irradiated from the lower surface 23 side of the semiconductor substrate 10, the range of the lifetime control agent is shortened, so the position where the upper surface-side lifetime control region 110 is formed can be controlled with good precision.

[0092] In this example, the end position of the cathode region 82 on the side of the temperature detection portion 120 in the arrangement direction of the groove portion (X-axis direction) is set to Xc, the end position of the upper surface side lifetime control region 110 on the side of the temperature detection portion 120 is set to Xk, the end position of the well region 112 on the side of position Xk is set to Xw, and the end position of the temperature detection portion 120 on the side of position Xw is set to Xs.

[0093] The end position Xk of the upper-surface-side lifetime control region 110 is set between the end position Xc of the cathode region 82 and the end position Xs of the temperature detection portion 120. The end position Xk of the upper-surface-side lifetime control region 110 can be set between the end position Xc of the cathode region 82 and the end position Xw of the well region 112. In another example, the end position Xk of the upper-surface-side lifetime control region 110 can also be set between the end position Xw of the well region 112 and the end position Xs of the temperature detection portion 120. It should be noted that the distance in the X-axis direction between the end position Xw of the well region 112 and the end position Xc of the cathode region 82 on the temperature detection portion 120 side is at least longer than the length of the drift region 18 from the lower end of the well region 112 to the upper end of the buffer region 20 in the Z-axis direction, and can preferably be longer than the length from the lower end of the well region 112 to the upper end of the collector region 22 in the Z-axis direction, and can more preferably be greater than the substrate thickness of the semiconductor substrate 10.

[0094] The distance between the end position Xk of the upper surface-side lifetime control region 110 and the end position Xs of the temperature detection unit 120, when viewed from above, can be 90 μm or less. By reducing this distance, the area over which the upper surface-side lifetime control region 110 is provided can be expanded. This distance can be 10 μm or greater, or 50 μm or greater. Maintaining this distance further reduces the risk of the lifetime control agent being irradiated onto the temperature detection unit 120.

[0095] The upper surface lifetime control region 110 can be located above or below the lower end of the well region 112. The upper surface lifetime control region 110 is located below the lower end of the trench. The depth of the upper surface lifetime control region 110 is the position where the concentration distribution of the lifetime control agent in the depth direction reaches its peak.

[0096] Figure 4 This figure shows another example of a top-view structure of a semiconductor device 100. The temperature detection portion 120 of this example is surrounded by the diode portion 80 when viewed from above, but is disposed adjacent to the diode portion 80. The temperature detection portion 120 of this example is adjacent to both the diode portion 80 and the transistor portion 70 in the Y-axis direction. The temperature detection portion 120 may have a length in the X-axis direction. This configuration enables the temperature of the semiconductor substrate 10 to be detected with high accuracy both during the period when the transistor portion 70 is in the on state and during the period when the diode portion 80 is in the on state.

[0097] exist Figure 4 In the example shown in FIG, the transistor portion 70 and the diode portion 80 are alternately arranged in the X-axis direction. The transistor portion 70 and the diode portion 80 may each have a length in the Y-axis direction and a width in the X-axis direction. In the Y-axis direction, a boundary region 90 may be provided between the diode portion 80 and the gate runner 48 (or the gate metal layer 50).

[0098] In this example, the temperature detection wiring 122 extends from the temperature detection portion 120 in the X-axis direction and is connected to the anode pad 106 and the cathode pad 108. In addition, in a plan view, the temperature detection portion 120 and the temperature detection wiring 122 are surrounded by the gate flow channel 48. The gate flow channel 48 surrounding the temperature detection portion 120 extends along the temperature detection wiring 122 in the direction toward the anode pad 106 and the cathode pad 108 to the end of the active portion 102. In addition, the gate pad 104 is arranged on the opposite side of the anode pad 106 and the cathode pad 108 across the active portion 102. The gate flow channel 48 surrounding the temperature detection portion 120 can be extended in the direction toward the gate pad 104 to the end of the active portion 102. The active portion 102 can be divided into multiple parts in the Y-axis direction by the gate flow channel 48. In each divided region of the active portion 102, the transistor portion 70 and the diode portion 80 can be alternately arranged in the X-axis direction.

[0099] Figure 5 It is magnified Figure 4 A top view of region C in the diagram. Figure 5In the enlarged views of FIG, etc., the emitter region 12, the contact region 15, and the base region 14 on the upper surface of each mesa portion 60 are sometimes omitted. In this example, the temperature detection portion 120 and the temperature detection wiring 122 are surrounded by the gate runner 48 in a plan view. The gate runner 48 is provided between the temperature detection portion 120 and the transistor portion 70, and between the temperature detection portion 120 and the diode portion 80. The well region 112 is provided below the temperature detection portion 120, below the temperature detection wiring 122, and below the gate runner 48. The well region 112 can be provided in a wider range than the gate runner 48.

[0100] The trench portion in this example extends in a direction perpendicular to the extending direction of the temperature detection wiring 122 (the Y-axis direction). The trench gate portion 40 of the transistor portion 70 in this example extends to a position overlapping with the gate flow channel 48 and is connected to the gate flow channel 48. Furthermore, the dummy trench portion 30 of the transistor portion 70 and the diode portion 80 may extend to a position overlapping with the well region 112.

[0101] The cathode region 82 is arranged apart from the temperature detection unit 120 in the Y-axis direction. The cathode region 82 may be arranged apart from the gate flow channel 48 or may be arranged apart from the well region 112 in the Y-axis direction.

[0102] The upper-side lifetime control region 110 is provided in a region overlapping with the diode portion 80. In this example, the Y-axis end of the upper-side lifetime control region 110 is positioned between the temperature detection portion 120 and the cathode region 82. This allows the area in which the upper-side lifetime control region 110 is provided to be expanded, and injection of a lifetime control agent into the temperature detection portion 120 can be suppressed. The X-axis end of the upper-side lifetime control region 110 is positioned at the transistor portion 70.

[0103] The temperature detection portion 120 of this embodiment includes multiple PN junctions each having an N-type region 126 and a P-type region 128. Each PN junction is connected in series via temperature detection wiring 122. In other words, the P-type region 128 of any PN junction is connected to the N-type region 126 of another PN junction. The multiple PN junctions can be arranged along the X-axis. At least one PN junction can be positioned opposite the diode portion 80 in the Y-axis direction. At least one PN junction can also be positioned opposite the transistor portion 70 in the Y-axis direction.

[0104] Figure 6 Yes Figure 5FIG2 is a diagram showing an example of a DD cross section in FIG2 . In this example, a temperature detection portion 120, a gate runner 48, and an emitter 52 are provided above the upper surface 21 of the semiconductor substrate 10. The gate runner 48 can be arranged across the temperature detection portion 120 in the Y-axis direction. The emitter 52 is provided in a region that does not overlap with the gate runner 48 and the temperature detection portion 120. The well region 112 is provided below the gate runner 48 and the temperature detection portion 120.

[0105] In the Y-axis direction, a boundary region 90 is provided between the gate runner 48 and the cathode region 82. A well region 112 is provided in the boundary region 90 between the cathode region 82 and the gate runner 48. The well region 112 in the boundary region 90 can be provided continuously with the well region 112 below the temperature detection portion 120. The end of the dummy trench portion 30 in the Y-axis direction can be provided in the boundary region 90. In addition, a contact hole for connecting the emitter 52 to the well region 112 can be provided in the interlayer insulating film 38 in the boundary region 90.

[0106] An upper-surface-side lifetime control region 110 may be provided in at least a portion of the boundary region 90. The upper-surface-side lifetime control region 110 of the boundary region 90 is provided continuously with the upper-surface-side lifetime control region 110 of the diode portion 80. Providing the upper-surface-side lifetime control region 110 in the boundary region 90 also allows adjustment of the carrier lifetime in the vicinity of the diode portion 80. Furthermore, the upper-surface-side lifetime control region 110 is provided at a position that does not overlap with the temperature detection portion 120 when viewed from above. This prevents irradiation of the temperature detection portion 120 with the lifetime control agent even when irradiated from the upper surface 21 of the semiconductor substrate 10.

[0107] In this example, the end position of the cathode region 82 on the side of the temperature detection portion 120 in the extension direction of the groove portion (Y-axis direction) is set to Yc, the end position of the upper surface side lifetime control region 110 on the side of the temperature detection portion 120 is set to Yk, the end position of the well region 112 on the side of position Yk is set to Yw, the end position of the gate flow channel 48 on the side of position Yw is set to Yg, and the end position of the temperature detection portion 120 on the side of position Yw is set to Ys.

[0108] The end position Yk of the upper surface-side lifetime control region 110 is set between the end position Yc of the cathode region 82 and the end position Ys of the temperature detection unit 120. The end position Yk of the upper surface-side lifetime control region 110 can be between the end position Yc of the cathode region 82 and the end position Yg of the gate runner 48. The end position Yk of the upper surface-side lifetime control region 110 can be set between the end position Yw of the well region 112 and the end position Yg of the gate runner 48. The end position Yk of the upper surface-side lifetime control region 110 can be set between the end position Yc of the cathode region 82 and the end position Yw of the well region 112.

[0109] The distance between the end position Yk of the upper surface-side lifetime control region 110 and the end position Ys of the temperature detection unit 120, when viewed from above, can be 90 μm or less. Reducing this distance can expand the area where the upper surface-side lifetime control region 110 is located. This distance can be 10 μm or more, or 50 μm or more. Maintaining this distance further reduces the risk of the lifetime control agent being irradiated onto the temperature detection unit 120.

[0110] Figure 7 This is a diagram showing another example of a top view structure of the semiconductor device 100. The semiconductor device 100 of this example is different from the semiconductor device 100 in that the diode portion 80 and the transistor portion 70 are alternately arranged along the X-axis direction. Figure 1 The semiconductor device 100 shown is different. Figures 1 to 3 The temperature detection unit 120 of this embodiment is the same as the semiconductor device 100 described in Figure 1 Similarly to the example of , the temperature detection unit 120 is provided so as to be surrounded by the diode unit 80 in a plan view. The temperature detection unit 120 of this example is surrounded by any of the diode units 80 discretely provided in the X-axis direction.

[0111] The transistor portion 70 and the diode portion 80 may each have a length in the Y-axis direction and a width in the X-axis direction. A boundary region 90 may be provided between the diode portion 80 and the gate runner 48 (or the gate metal layer 50 ) in the Y-axis direction.

[0112] In this example, the gate flow channel 48 may be provided so as to surround the temperature detection portion 120 and the temperature detection wiring 122 in a plan view. In addition, the gate flow channel 48 may be provided so as to divide the active portion 102. The positional relationship among the upper surface side lifetime control region 110, cathode region 82, well region 112, gate flow channel 48, and temperature detection portion 120 may be the same as Figures 1 to 6 The example is the same as described in .

[0113] Figure 8 This is a diagram showing another example of a top view structure of the semiconductor device 100. In this example, the active portion 102 is Figure 4Similarly to the example of , the transistor portion 70 and the diode portion 80 are alternately arranged along the X-axis direction. In this example, the temperature detection wiring 122 extends along the Y-axis direction. Figure 4 In addition, the gate pad 104, the anode pad 106, and the cathode pad 108 are arranged in the Y-axis direction with the active portion 102 interposed therebetween. Figure 4 In addition, the temperature detection unit 120 has a length in the Y-axis direction. Figure 4 The examples shown are different. Other constructions can be Figures 4 to 6 The same as the semiconductor device 100 described in .

[0114] Furthermore, semiconductor device 100 of this example includes a current detection portion 107 and a current detection pad 109. Current detection portion 107 has the same structure as transistor portion 70. Current detection pad 109 detects the current flowing through current detection portion 107. Based on the current flowing through current detection portion 107 and the area ratio between current detection portion 107 and transistor portion 70, the current flowing through transistor portion 70 can be estimated. Current detection portion 107 and current detection pad 109 can be arranged so as to be surrounded by gate flow channel 48. It should be noted that semiconductor devices of other examples may also include current detection portion 107 and current detection pad 109.

[0115] Figure 9 It is magnified Figure 8 Top view of region E in the figure. In region E, Figure 2 The region A shown similarly includes a portion of the transistor portion 70, a portion of the diode portion 80, and a portion of the temperature detection portion 120. The temperature detection portion 120 in this example is adjacent to the diode portion 80 in the Y-axis direction and adjacent to the transistor portion 70 in the X-axis direction. Figure 9 In the example, the temperature detection portion 120 is sandwiched between the two transistor portions 70 in the X-axis direction. A boundary region 90 may be provided between the temperature detection portion 120 and the transistor portion 70. Even with such a structure, the temperatures of the diode portion 80 and the transistor portion 70 can be detected with good accuracy. The positional relationship between the upper surface side lifetime control region 110, the cathode region 82, the well region 112, the gate flow channel 48, and the temperature detection portion 120 may be the same as that of the upper surface side lifetime control region 110, the cathode region 82, the well region 112, the gate flow channel 48, and the temperature detection portion 120. Figures 1 to 7 The example is the same as described in .

[0116] Figure 10 FIG. 1 is a diagram showing another example of a top view structure of a semiconductor device 100. The temperature detection unit 120 of the semiconductor device 100 of this example is provided between the active unit 102 and the withstand voltage structure 150 in a top view. The structure of the active unit 102 is similar to that of the Figures 4 to 9 The active portion 102 of any of the embodiments described above is the same.

[0117] The gate runner 48 of this embodiment has an outer peripheral portion 48-1 that extends along the outer peripheral end 140 of the semiconductor substrate 10. The shape of the outer peripheral portion 48-1 is generally rectangular when viewed from above. The outer peripheral portion 48-1 surrounds the active portion 102 when viewed from above. The corners of the rectangular shape of the outer peripheral portion 48-1 may be curved. The gate runner 48 includes an inner portion 48-2 within the region surrounded by the outer peripheral portion 48-1, which demarcates a temperature detection region 103 where the temperature detection portion 120 is located. The temperature detection portion 120 is located in the temperature detection region 103 surrounded by the outer peripheral portion 48-1 and the inner portion 48-2. In this embodiment, the temperature detection region 103 is located between the active portion 102 and the outer peripheral portion 48-1. Neither the transistor portion 70 nor the diode portion 80 is located in the temperature detection region 103. The temperature detection wiring 122, the anode pad 106, and the cathode pad 108 may be located in the temperature detection region 103.

[0118] The temperature detection section 120 can be disposed adjacent to the diode section 80. In this example, the transistor section 70 and the diode section 80 are arranged alternately along the X-axis direction. The temperature detection region 103 is disposed at the end of the active section 102 in the Y-axis direction. The temperature detection section 120 can be disposed adjacent to the diode section 80 in the Y-axis direction. The temperature detection section 120 can also be disposed adjacent to the transistor section 70 in the Y-axis direction. The temperature detection section 120 can have a length in the X-axis direction.

[0119] In this example, the upper surface side lifetime control region 110 is also provided in the diode portion 80 and is provided in a region that does not overlap with the temperature detection portion 120. The upper surface side lifetime control region 110 can be provided in a region that does not overlap with the inner portion 48-2 of the gate flow channel 48. The upper surface side lifetime control region 110 can be provided in a region that does not overlap with the well region 112 disposed below the inner portion 48-2 of the gate flow channel 48. The positional relationship among the upper surface side lifetime control region 110, the cathode region 82, the well region 112, the gate flow channel 48, and the temperature detection portion 120 can be as follows: Figures 1 to 9 The example is the same as described in .

[0120] Figure 11 Yes Figures 1 to 10 FIG1 is a diagram illustrating an example of a method for manufacturing semiconductor device 100 described in . This example manufacturing method includes a first step S1102 and a second step S1104. The structure on the upper surface 21 side of semiconductor substrate 10 may be formed before the first step S1102. The structure on the upper surface 21 side may include at least one of the trenches, emitter region 12, contact region 15, base region 14, well region 112, interlayer insulating film 38, and emitter electrode 52.

[0121] In the first step S1102, the temperature detection portion 120 is formed above the semiconductor substrate 10. Also, in S1102, a mask portion 202 is formed to shield the temperature detection portion 120. The mask portion 202 may be a photoresist formed on the temperature detection portion 120. Alternatively, the mask portion 202 may be a metal mask disposed above the temperature detection portion 120.

[0122] In the second step S1104, a lifetime control agent is introduced from the upper surface 21 side of the semiconductor substrate 10 and annealed, thereby forming the upper surface-side lifetime control region 110 in a region that does not overlap with the temperature detection portion 120 when viewed from above. After the lifetime control agent is introduced, the mask portion 202 is removed. The structure on the lower surface 23 side of the semiconductor substrate 10 can be formed before the first step S1102 or after the second step S1104. The structure on the lower surface 23 side can include at least one of the buffer region 20, the collector region 22, the cathode region 82, and the collector electrode 24.

[0123] By using this method, the temperature detection unit 120 can be formed without injecting a lifetime control agent into the temperature detection unit 120. Figures 1 to 10 The upper surface side lifetime control region 110 described in .

[0124] Figure 12 This is a cross-sectional view illustrating an example of a semiconductor device 200. The semiconductor device 200 of this example may have the same Figures 1 to 11 The semiconductor device 100 has the same structure as that described in FIG. Figure 12 Shown in Figure 3 The same cross section, but the semiconductor device 200 may also have Figure 3 It should be noted that in this example, the emitter 52 is arranged above the well region 112, and the temperature detection unit 120 is arranged above the emitter 52. It should be noted that in the examples of the respective figures, the interlayer insulating film 38 may be a film formed by laminating in multiple steps.

[0125] In the semiconductor device 200, the upper-surface-side lifetime control region 110 is provided in a region that overlaps with the temperature detection portion 120 when viewed from above. The upper-surface-side lifetime control region 110 below the temperature detection portion 120 can be provided continuously with the upper-surface-side lifetime control region 110 of the diode portion 80. It should be noted that the temperature detection portion 120 does not contain the same lifetime control agent as the upper-surface-side lifetime control region 110. For example, while the upper-surface-side lifetime control region 110 contains a lifetime control agent such as helium, the temperature detection portion 120 does not contain such a lifetime control agent. This structure also suppresses fluctuations in the characteristics of the temperature detection portion 120.

[0126] The upper surface-side lifetime control region 110 may be formed at a position deeper than the lower end of the well region 112. In another example, the upper surface-side lifetime control region 110 may be formed at the same depth as the well region 112. In this case, a portion of the upper surface-side lifetime control region 110 is formed inside the well region 112.

[0127] Figure 13 This diagram illustrates an example method for manufacturing semiconductor device 200. The manufacturing method of this example includes a first step S1302 and a second step S1304. The structure on the upper surface 21 side of semiconductor substrate 10 may be formed before the first step S1302. The structure on the upper surface 21 side may include at least one of the trenches, emitter region 12, contact region 15, base region 14, well region 112, interlayer insulating film 38, and emitter electrode 52.

[0128] In the first step S1302, a lifetime control agent is introduced from the upper surface 21 side of the semiconductor substrate 10 and annealed, thereby forming the upper surface lifetime control region 110. The upper surface lifetime control region 110 is also formed below the region where the temperature detection unit 120 is arranged. In this example, the upper surface lifetime control region 110 is also formed in the region overlapping with the well region 112 in a plan view. The upper surface lifetime control region 110 can be formed so as to overlap the entire well region 112. The upper surface lifetime control region 110 can also be formed over the entire active portion 102.

[0129] In the second step S1104, a temperature detection portion 120 is formed above the semiconductor substrate 10. The temperature detection portion 120 is formed at a position overlapping the upper lifetime control region 110 in a plan view. After the temperature detection portion 120 is formed, a protective film covering the temperature detection portion 120 may be formed.

[0130] The structure on the lower surface 23 side of the semiconductor substrate 10 may be formed before the first step S1102, between the first step S1102 and the second step S1104, or after the second step S1104. The structure on the lower surface 23 side may include at least one of the buffer region 20, the collector region 22, the cathode region 82, and the collector electrode 24.

[0131] Figure 14 1 is a cross-sectional view illustrating another example of the semiconductor device 200. In this example, the upper surface side lifetime control region 110 of the semiconductor device 200 is also provided in a region overlapping with the temperature detection unit 120 in a plan view. Figure 3 The semiconductor devices 100 shown are identical.

[0132] Figure 15 Yes Figure 14 FIG. 1 is a diagram showing an example of a method for manufacturing a semiconductor device 200. The manufacturing method of this example also has Figure 13 In the first step S1302, in step S1504 after S1302, the emitter 52 and the interlayer insulating film 38 corresponding to the area where the temperature detection unit 120 is to be formed are etched. Then, in the second step S1506, the interlayer insulating film 38, the temperature detection unit 120 and the temperature detection wiring 122 are formed. The steps after S1506 are the same as Figure 13 Same as the example.

[0133] Figure 16 1 is a cross-sectional view showing another example of a semiconductor device 200. The semiconductor device 200 of this example includes a temperature detection wiring 122 between the interlayer insulating film 38 and the temperature detection unit 120. Figures 12 to 15 The temperature detection wiring 122 can be formed by the same steps as the emitter 52. Figure 13 The emitter electrode 52 formed in the first step S1302 is patterned, and a part of the region is used as the temperature detection wiring 122 .

[0134] In this example, the temperature detection wiring 122 is formed of the same material as the emitter 52. Furthermore, the temperature detection wiring 122 can be provided at the same depth (position in the Z-axis direction) as the emitter 52. An interlayer insulating film 38 is provided between the emitter 52 and the temperature detection wiring 122. The interlayer insulating film 38 can be provided in the region other than where the emitter 52 is removed.

[0135] Figure 17 2 is a cross-sectional view showing another example of a semiconductor device 200. In the semiconductor device 200 of this example, the temperature detection portion 120 and the temperature detection wiring 122 are in contact with each other in a direction parallel to the upper surface 21 of the semiconductor substrate 10 (for example, the X-axis direction). Figures 12 to 15 The temperature detection wiring 122 can be formed by the same steps as the emitter 52. Figure 13 The emitter electrode 52 formed in the first step S1302 is patterned, and a part of the region is used as the temperature detection wiring 122 .

[0136] An interlayer insulating film 38 and a temperature detection portion 120 are provided in the region excluding the emitter 52. The temperature detection wiring 122 in this example is formed of the same material as the emitter 52. The temperature detection wiring 122 can be provided at the same depth position (position in the Z-axis direction) as the emitter 52. Furthermore, the temperature detection portion 120, the emitter 52, and the temperature detection wiring 122 can be provided at the same depth position. In this example, an interlayer insulating film 38 can be provided between the emitter 52 and the temperature detection wiring 122. Alternatively, the temperature detection wiring 122 can be covered by the interlayer insulating film 38.

[0137] In addition, Figures 12 to 17 In the semiconductor device 200 shown, the upper surface-side lifetime control region 110 can be formed before forming the polysilicon of the emitter 52 and the temperature detection portion 120. In this case, with a portion of the interlayer insulating film 38 formed on the upper surface 21 of the semiconductor substrate 10 (for example, a portion having the same thickness as the interlayer insulating film 38 formed below the temperature detection portion 120), the upper surface-side lifetime control region 110 can be formed by introducing a lifetime control agent from the upper surface 21 side of the semiconductor substrate 10 and performing annealing.

[0138] By using this method, the temperature detection unit 120 can be formed without injecting a lifetime control agent into the temperature detection unit 120. Figure 12 In this example, since the mask portion 202 is not used, the semiconductor device 200 can be manufactured using a simple process.

[0139] While the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be appreciated by those skilled in the art that various modifications or improvements can be added to the above embodiments. As can be seen from the claims, such modifications or improvements are also included within the technical scope of the present invention.

[0140] It should be noted that the order in which actions, processes, steps, and stages, etc., of the devices, systems, programs, and methods described in the claims, specifications, and drawings may be executed in any order, unless otherwise expressly stated, such as "before" or "before," and unless the results of previous processing are used in subsequent processing. Even if the action flow in the claims, specifications, and drawings is described using phrases such as "first" or "next" for convenience, it does not necessarily mean that the actions must be executed in that order.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor substrate provided with a drift region of a first conductivity type; a transistor portion, which is provided on the semiconductor substrate; a diode portion, which is disposed on the semiconductor substrate; a well region of the second conductivity type, which is exposed on the upper surface of the semiconductor substrate; a temperature detection portion, adjacent to the diode portion in a plan view and disposed above the well region; as well as an upper surface side lifetime control region provided on the upper surface side of the semiconductor substrate in the diode portion and provided in a region not overlapping with the temperature detection portion in a plan view; The temperature detection portion is sandwiched between the adjacent diode portions in a plan view, and the upper surface side lifetime control region is arranged on the entire diode portion in a plan view. The diode portion includes a cathode region of a first conductivity type, the cathode region being provided inside the semiconductor substrate and exposed on a lower surface of the semiconductor substrate. In a plan view, an end portion of the upper surface-side lifetime control region is arranged between the cathode region and the temperature detection portion.

2. The semiconductor device according to claim 1, wherein The upper surface-side lifetime control region is provided in a region that does not overlap with the well region in a plan view.

3. The semiconductor device according to claim 1 or 2, wherein: The transistor portion and the diode portion have a trench portion extending from the surface of the semiconductor substrate to the inside. A portion of the trench portion is provided inside the well region.

4. The semiconductor device according to claim 1 or 2, wherein: The upper surface side lifetime control region contains a lifetime control agent, The temperature detection portion does not contain the life control agent.

5. A semiconductor device, characterized in that: have: a semiconductor substrate provided with a drift region of a first conductivity type; an active portion including a transistor portion and a diode portion provided on a semiconductor substrate; a voltage-resistant structure portion provided on the semiconductor substrate and surrounding the active portion in a plan view; a well region of the second conductivity type, which is exposed on the upper surface of the semiconductor substrate; a temperature detection portion, which is disposed between the active portion and the voltage-resistant structure portion in a plan view and is disposed above the well region; as well as an upper surface side lifetime control region provided on the upper surface side of the semiconductor substrate in the diode portion and provided in a region not overlapping with the temperature detection portion in a plan view; In a plan view, a distance between the temperature detection portion and the upper surface-side lifetime control region is 90 μm or less.

6. The semiconductor device according to claim 5, wherein The upper surface-side lifetime control region is provided in a region that does not overlap with the well region in a plan view.

7. The semiconductor device according to claim 5 or 6, wherein: The transistor portion and the diode portion have a trench portion extending from the surface of the semiconductor substrate to the inside. A portion of the trench portion is provided inside the well region.

8. The semiconductor device according to claim 7, wherein The diode portion includes a cathode region of the second conductivity type, the cathode region being provided inside the semiconductor substrate and exposed on the lower surface of the semiconductor substrate. In a plan view, an end portion of the upper surface-side lifetime control region is arranged between the cathode region and the temperature detection portion.

9. The semiconductor device according to claim 5 or 6, wherein: The upper surface side lifetime control region contains a lifetime control agent, The temperature detection portion does not contain the life control agent.

10. The semiconductor device according to claim 7, wherein The upper surface side lifetime control region contains a lifetime control agent, The temperature detection portion does not contain the life control agent.

11. The semiconductor device according to claim 8, wherein The upper surface side lifetime control region contains a lifetime control agent, The temperature detection portion does not contain the life control agent.

12. A semiconductor device, characterized in that: have: a semiconductor substrate provided with a drift region of a first conductivity type; a transistor portion, which is provided on the semiconductor substrate; a diode portion, which is disposed on the semiconductor substrate; a well region of the second conductivity type, which is exposed on the upper surface of the semiconductor substrate; a temperature detection portion, which is disposed above the well region; as well as An upper surface-side lifetime control region is provided on the upper surface side of the diode portion and the distance between the upper surface-side lifetime control region and the temperature detection portion is 90 μm or less in a plan view.

13. The semiconductor device according to claim 12, wherein The upper surface side lifetime control region contains a lifetime control agent, The temperature detection portion does not contain the life control agent.

14. A method for manufacturing a semiconductor device, characterized in that: The method for manufacturing a semiconductor device according to any one of claims 1 to 13, A temperature detection portion is formed above the semiconductor substrate. forming a mask portion for shielding the temperature detection portion, A lifetime control agent is introduced from the upper surface side of the semiconductor substrate to form an upper surface side lifetime control region in a region that does not overlap with the temperature detection portion in a plan view.

15. A method for manufacturing a semiconductor device, characterized in that: The method for manufacturing a semiconductor device according to any one of claims 1 to 13, A lifetime control agent is introduced from the upper surface side of the semiconductor substrate to form an upper surface side lifetime control region. A temperature detection portion is formed above the semiconductor substrate. In the step of forming the temperature detection portion, the temperature detection portion is formed at a position overlapping with the upper surface-side lifetime control region in a plan view.

16. A semiconductor device, characterized in that: have: a semiconductor substrate provided with a drift region of a first conductivity type; a transistor portion, which is provided on the semiconductor substrate; a diode portion, which is disposed on the semiconductor substrate; a well region of the second conductivity type, which is exposed on the upper surface of the semiconductor substrate; a temperature detection portion, which is surrounded by the adjacent diode portion in a plan view and is disposed above the well region; as well as an upper surface side lifetime control region provided on the upper surface side of the semiconductor substrate in the diode portion and provided in a region not overlapping with the temperature detection portion in a plan view; In a plan view, the temperature detection portion is sandwiched between the adjacent diode portions so that the transistor portion is not provided between the adjacent diode portions, and the upper surface side lifetime control region is arranged over the entire diode portion in a plan view.

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