Semiconductor device with through silicon via and method for manufacturing the same

Abstract

Provided are a semiconductor device having a through-silicon via and a method for manufacturing the same. The semiconductor device includes: a first insulating interlayer, the first insulating interlayer being disposed on a first surface of a substrate; a pad pattern, the pad pattern being disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through-silicon via, the through-silicon via passing through the substrate and the first insulating interlayer and contacting the first copper pattern of the pad pattern. The through-silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion below the first portion and extending to a portion of the first copper pattern in the pad pattern. The through-silicon via has a curved portion at a boundary between the first portion and the second portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0135569 filed in the Korean Intellectual Property Office on November 7, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Apparatuses and methods consistent with example embodiments relate to semiconductor devices and methods of manufacturing the same. More particularly, example embodiments relate to semiconductor devices including through-silicon vias (TSVs) formed through a silicon substrate and connected to pads and methods of manufacturing the same. Background Art

[0004] In a multi-chip package, stacked semiconductor chips may be electrically connected to each other using, for example, conductive bumps. In this case, through-silicon vias electrically connecting the conductive bumps to pads of the semiconductor chips may be formed in the semiconductor device.

[0005] In addition, a through hole may be formed through the substrate to expose the pad pattern formed in the insulating interlayer. When forming the through hole, re-sputtering of the metal included in the pad pattern may cause metal contaminants to adhere to the lower sidewall of the through hole adjacent to the pad pattern. Due to the metal contaminants, the reliability of the semiconductor device may be poor. Summary of the invention

[0006] One or more example embodiments provide a semiconductor device having a TSV.

[0007] One or more example embodiments provide a method of manufacturing a semiconductor device having a TSV.

[0008] According to one aspect of example embodiments, a semiconductor device is provided. The semiconductor device includes: a first insulating interlayer, the first insulating interlayer is disposed on a first surface of a substrate; a pad pattern, the pad pattern is disposed on a lower surface of the first insulating interlayer, the pad pattern includes a first copper pattern; and a through-silicon via, the through-silicon via passes through the substrate and the first insulating interlayer and contacts the first copper pattern of the pad pattern. The through-silicon via includes a first portion that passes through the substrate and the first insulating interlayer, and a second portion that is below the first portion and extends to a portion of the first copper pattern in the pad pattern, and the through-silicon via has a bent portion at a boundary between the first portion and the second portion.

[0009] According to one aspect of an example embodiment, a method for manufacturing a semiconductor device is provided. In the method for manufacturing a semiconductor device, a first insulating interlayer is formed on a first surface of a substrate. A pad pattern including a first copper pattern is formed on a lower surface of the first insulating interlayer. A through hole is formed through the substrate and the first insulating interlayer to expose a portion of the surface of the first copper pattern in the pad pattern. A through silicon via is formed in the through hole. The through silicon via contacts the first copper pattern of the pad pattern. The through silicon via includes a first portion that passes through the substrate and the first insulating interlayer, and a second portion of the first copper pattern below the first portion and extending to the pad pattern. The through silicon via has a curved portion at a boundary between the first portion and the second portion.

[0010] According to one aspect of an example embodiment, a method for manufacturing a semiconductor device is provided. In the method for manufacturing a semiconductor device, a first insulating interlayer is formed on a first surface of a substrate. A pad pattern is formed on a lower surface of the first insulating interlayer. The pad pattern includes a first copper pattern and a first barrier pattern on an upper surface and a sidewall of the first copper pattern. A first through hole is formed through the substrate and the first insulating interlayer to expose a portion of an upper surface of the first barrier pattern in the pad pattern. A sacrificial layer is formed on an inner surface of the first through hole. The sacrificial layer formed on the bottom of the first through hole, and the first barrier pattern and the upper surface of the first copper pattern below the bottom of the first through hole are etched to form a second through hole having a width less than a width of the first through hole. The sacrificial layer and copper contaminants on the sacrificial layer are etched to form a through hole. A through silicon via may be formed in the through hole. The through silicon via may contact the first copper pattern of the pad pattern.

[0011] In example embodiments, metal contaminants may not be generated at a portion adjacent to a lower sidewall of the TSV, so that reliability defects due to the metal contaminants may be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a cross-sectional view illustrating a semiconductor device including a through silicon via (TSV) according to example embodiments;

[0014] Figure 2 yes Figure 1 an enlarged cross-sectional view of portion "A" in FIG.

[0015] Figures 3 to 12are cross-sectional views illustrating stages of a method of manufacturing a semiconductor device including a through silicon via according to example embodiments; and

[0016] Fig.13 is a diagram showing a method including Figure 1 A cross-sectional view of a multi-chip package of a semiconductor device is shown. DETAILED DESCRIPTION

[0017] Figure 1 is a cross-sectional view illustrating a semiconductor device 190 including a TSV according to example embodiments. Figure 2 yes Figure 1 An enlarged cross-sectional view of portion “A” in FIG.

[0018] refer to Figure 1 and Figure 2 , the semiconductor device 190 may include a substrate 100a, a first insulating interlayer 110, a pad pattern 116, and a through silicon via 168. In addition, the semiconductor device 190 may further include an insulating liner 152b, a circuit element 102, a first wiring structure 144, a second wiring structure 132, a pad electrode 134, a second insulating interlayer 118, a third insulating interlayer 140, and a fourth insulating interlayer 142.

[0019] The substrate 100a may include a semiconductor material. The substrate 100a may include, for example, a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. In an example embodiment, the bare substrate 100 (see Figure 3 ) to reduce the thickness of the bare substrate 100, forming the substrate 100a. For example, the substrate 100a may include single crystal silicon.

[0020] A circuit element 102 including a transistor may be formed on a first surface 1 of the substrate 100a. The first surface 1 of the substrate 100a may be the front surface of the substrate 100a, and the first surface 1 of the substrate 100a may be the surface on which the circuit element 102 is formed. In addition, a second surface 2 of the substrate 100a may be opposite to the first surface 1 of the substrate 100a, and the second surface 2 may be the back surface of the substrate 100a. The circuit element 102 may include, for example, a memory cell, a pixel of an image sensor, a logic device, etc.

[0021] The first insulating interlayer 110 may be formed to cover the first surface 1 of the substrate 100a. That is, the first insulating interlayer 110 may be formed on the first surface 1 of the substrate 100a and may cover the circuit element 102. The first insulating interlayer 110 may include, for example, silicon oxide. However, example embodiments are not limited thereto, and the first insulating interlayer 110 may include other insulating materials.

[0022] The second insulating interlayer 118 may cover a lower surface of the first insulating interlayer 110. A pad pattern 116 and a first wiring structure 144 may be formed in the second insulating interlayer 118.

[0023] The pad pattern 116 and the first wiring structure 144 may contact the lower surface of the first insulating interlayer 110 and may be located inside the second insulating interlayer 118. Therefore, the pad pattern 116 and the first wiring structure 144 may be disposed downward from the lower surface of the first insulating interlayer 110.

[0024] The pad pattern 116 may be spaced apart from a region where the circuit element 102 may be formed. In example embodiments, the pad pattern 116 may be electrically connected to the circuit element 102 through a wiring.

[0025] The pad pattern 116 may include a first barrier pattern 112 , a first seed copper pattern 113 , and a first copper pattern 114 .

[0026] The first barrier pattern 112 may include a first portion contacting the lower surface of the first insulating interlayer 110 and a second portion protruding downward from an edge of the first portion. Therefore, the first barrier pattern 112 may have a cylindrical shape forming an inner space. The first barrier pattern 112 may include, for example, tantalum, tantalum nitride, etc. The first seed copper pattern 113 may be conformally formed on the inner surface of the cylindrical shape of the first barrier pattern 112. The first copper pattern 114 may be formed on the first seed copper pattern 113 and may fill the inner space of the first seed copper pattern 113.

[0027] Therefore, in the pad pattern 116, the sidewall and the upper surface of the first copper pattern 114 may be covered by the first seed copper pattern 113 and the first barrier pattern 112. The first copper pattern 114, the first seed copper pattern 113, and the first barrier pattern 112 may be sequentially stacked. The first barrier pattern 112 may not be formed on the lower surface of the first copper pattern 114.

[0028] In example embodiments, a plurality of contact plugs 130 may be formed in the second insulating interlayer 118 , and the contact plugs 130 may contact a lower surface of the pad pattern 116 .

[0029] The first wiring structure 144 may be located in a region where the circuit element 102 is formed and may be electrically connected to the circuit element 102. In example embodiments, the first wiring structure 144 may also include a first barrier pattern 112, a first seed copper pattern 113, and a first copper pattern 114, and may be similar to a stacked structure of the pad pattern 116.

[0030] The third insulating interlayer 140 may cover the lower surface of the second insulating interlayer 118. The second wiring structure 132 may be formed in the third insulating interlayer 140. The second wiring structure 132 may be electrically connected to the pad pattern 116 and / or the first wiring structure 144. In example embodiments, the second wiring structure 132 may include a barrier pattern, a seed copper pattern, and a copper pattern, and may be similar to the stacked structure of the pad pattern 116.

[0031] The fourth insulating interlayer 142 may cover the lower surface of the third insulating interlayer 140. The pad electrode 134 may be formed in the fourth insulating interlayer 142 and may be electrically connected to the pad pattern 116. In example embodiments, the pad electrode 134 may contact the second wiring structure 132. In example embodiments, the pad electrode 134 may include, for example, aluminum.

[0032] In example embodiments, a support substrate 200 may be further formed on a lower surface of the fourth insulating interlayer 142 .

[0033] A through-silicon via 168 may be formed through the substrate 100 a and the first insulating interlayer 110 , such that the through-silicon via 168 may contact the first copper pattern 114 of the pad pattern 116 .

[0034] The through silicon via 168 may include a second barrier pattern 162 a , a second seed copper pattern 164 a , and a second copper pattern 166 a . An insulating liner 152 b may surround a sidewall of the through silicon via 168 .

[0035] A through silicon via 168 may be formed to fill the through hole 160 penetrating the substrate 100 a and the first insulating interlayer 110 to expose the first copper pattern 114 .

[0036] The through hole 160 may have a first portion passing through the substrate 100a and the first insulating interlayer 110, and a second portion of the first copper pattern 114 below the first portion and extending to the pad pattern 116. The first portion of the through hole 160 may be disposed above the upper surface of the pad pattern 116. The first portion and the second portion of the through hole 160 may be connected to each other. In addition, the boundary between the first portion and the second portion of the through hole 160 may be curved. In this case, the width W1 of the first portion of the through hole 160 may be greater than the width W2 of the second portion of the through hole 160.

[0037] In example embodiments, a sidewall of the first portion of the through hole 160 may have a slope such that a width of the first portion may gradually increase from the first surface 1 of the substrate 100 a toward the second surface 2 of the substrate 100 a .

[0038] A lower surface of the first portion of the via 160 may expose a portion of an upper surface of the first barrier pattern 112 in the pad pattern 116. A lower surface of the second portion of the via 160 may expose a portion of the first copper pattern 114 in the pad pattern 116. In example embodiments, a sidewall of the second portion of the via 160 may expose the first barrier pattern 112, the first seed copper pattern 113, and the first copper pattern 114 in the pad pattern 116.

[0039] Since the through-silicon via 168 is formed in the through-hole 160 , a sidewall profile of the through-silicon via 168 may be substantially the same as a sidewall profile of the through-hole 160 .

[0040] The through silicon via 168 may include a first portion passing through the substrate 100a and the first insulating interlayer 110, and a second portion of the first copper pattern 114 below the first portion and extending to the pad pattern 116. A boundary between the first portion and the second portion of the through silicon via 168 may be curved. In addition, a width of the first portion of the through silicon via 168 may be greater than a width of the second portion of the through silicon via 168. In example embodiments, a width of the first portion of the through silicon via 168 at a boundary between the substrate 100a and the first insulating interlayer 110 may be greater than a width of the second portion of the through silicon via 168 at an upper surface of the pad pattern 116.

[0041] The second barrier pattern 162 a included in the through silicon via 168 may contact at least a portion of an upper surface of the first barrier pattern 112 in the pad pattern 116 .

[0042] The second barrier pattern 162a of the through-silicon via 168 may be conformally formed on the inner surface of the through-hole 160. Therefore, the second barrier pattern 162a of the through-silicon via 168 may contact at least a portion of the upper surface of the first barrier pattern 112. In addition, the second barrier pattern 162a may have a first bent portion between the first portion and the second portion of the through-silicon via 168. The second seed copper pattern 164a may be conformally formed on the surface of the second barrier pattern 162a. Therefore, the second seed copper pattern 164a may also include a second bent portion.

[0043] The second copper pattern 166a may be formed on the second seed copper pattern 164a to fill the through hole 160. Therefore, the second copper pattern 166a may have a third bent portion. In the second copper pattern 166a, the width of the upper portion formed above the third bent portion may be greater than the width of the lower portion formed below the third bent portion. In addition, the third bent portion may be located above the upper surface of the pad pattern 116.

[0044] The through silicon via 168 may be isolated from the substrate 100a by the insulating liner 152b. The insulating liner 152b may include, for example, silicon oxide. The lower surface of the insulating liner 152b may be located between the upper surface of the first insulating interlayer 110 and the upper surface of the pad pattern 116. Therefore, the lower surface of the insulating liner 152b may be spaced apart from the upper surface of the pad pattern 116, and the lower sidewall of the through silicon via 168 may contact the first insulating interlayer 110.

[0045] Metal contaminants (eg, copper contaminants) do not adhere to the surface of the insulating liner 152b. Therefore, the insulating liner 152b can have excellent insulation. In addition, reliability defects of the semiconductor device 190 due to metal contaminants can be reduced.

[0046] Figures 3 to 12 are cross-sectional views illustrating stages of a method of fabricating a semiconductor device including a through silicon via according to example embodiments.

[0047] refer to Figure 3 , a circuit element 102 including a transistor may be formed on a first surface of the bare substrate 100 .

[0048] A first insulating interlayer 110 may be formed on a first surface of the bare substrate 100 to cover the circuit element 102. The first insulating interlayer 110 may include, for example, silicon oxide.

[0049] After forming the first insulating interlayer 110, a plurality of lower contact plugs may be further formed to be electrically connected to the circuit element 102. Then, a planarization process may be performed so that the upper surface of the first insulating interlayer 110 may be planarized. In this way, the front end of line (FEOL) process of the semiconductor device may be completed.

[0050] When the subsequent process is performed, the circuit element 102 should not be degraded. Therefore, preferably, the subsequent process may be performed at a temperature lower than about 500°C.

[0051] A lower second insulating interlayer 118a may be formed on the first insulating interlayer 110. Portions of the lower second insulating interlayer 118a may be etched to form a plurality of first openings, which may expose an upper surface of the first insulating interlayer 110. A pad pattern 116 and a first wiring structure 144 may be formed to fill the first openings, respectively.

[0052] In particular, a first barrier layer may be formed on the inner surface of the first opening and the lower second insulating interlayer 118a. The first barrier layer may include, for example, tantalum, tantalum nitride, etc. A first seed copper layer may be conformally formed on the first barrier layer. The first barrier layer and the first seed copper layer may be formed by a physical vapor deposition process such as a sputtering process. A first copper layer may be formed on the first seed copper layer. For example, the first copper layer may be formed by an electroplating process. Then, the first copper layer, the first seed copper layer, and the first barrier layer are planarized until the upper surface of the lower second insulating interlayer 118a is exposed to form a pad pattern 116 and a first wiring structure 144 filling each first opening. Both the pad pattern 116 and the first wiring structure 144 may include a first barrier pattern 112, a first seed copper pattern 113, and a first copper pattern 114.

[0053] In example embodiments, the first wiring structure 144 may contact the lower contact plug so that the first wiring structure 144 may be electrically connected to the circuit element 102. In example embodiments, the pad pattern 116 may be positioned to face a through-silicon via to be formed subsequently.

[0054] refer to Figure 4 , an upper second insulating interlayer 118b may be formed to cover the lower second insulating interlayer 118a, the pad pattern 116, and the first wiring structure 144. A contact plug 130 may be formed to penetrate the upper second insulating interlayer 118b to be electrically connected to the pad pattern 116. Since the lower second insulating interlayer 118a and the upper second insulating interlayer 118b are formed of the same material, the lower second insulating interlayer 118a and the upper second insulating interlayer 118b may be merged into the second insulating interlayer 118. The second insulating interlayer 118 will be described below.

[0055] An upper wiring may be further formed on the second insulating interlayer 118. In example embodiments, a third insulating interlayer 140 may be formed on the second insulating interlayer 118. A second wiring structure 132 may be formed in the third insulating interlayer 140.

[0056] A fourth insulating interlayer 142 may be formed on the third insulating interlayer 140 and the second wiring structure 132. A pad electrode 134 may be formed in the fourth insulating interlayer 142. In example embodiments, the second wiring structure 132 and the pad electrode 134 may be electrically connected to the pad pattern 116. In addition, the pad pattern 116 may be electrically connected to the circuit element 102 through wiring. In this way, a wiring process of a back end of line (BEOL) of a semiconductor device may be completed.

[0057] refer to Figure 5, the support substrate 200 may be attached to the fourth insulating interlayer 142. Then, the bare substrate 100 is turned over so that the second surface of the bare substrate 100 may be located at the upper side. The second surface of the bare substrate 100 may be ground to form a substrate 100a having a thickness smaller than that of the bare substrate 100. Thereafter, a protective layer may be further formed on the second surface 2 of the substrate 100a.

[0058] Since the second surface 2 of the substrate 100a may face upward, the first barrier pattern 112 may correspond to the top of the pad pattern 116. That is, in the pad pattern 116, the sidewall and the upper surface of the first copper pattern 114 may be covered by the sequentially stacked first seed copper pattern 113 and the first barrier pattern 112. In addition, the first barrier pattern 112 may contact the lower surface of the first insulating interlayer 110.

[0059] A portion of the substrate 100a may be etched from the second surface 2 to the first surface 1 of the substrate 100a, and a portion of the first insulating interlayer 110 under the substrate 100a may be sequentially etched to form a preliminary via hole 150. The preliminary via hole 150 may be formed to penetrate the substrate 100a opposite to the pad pattern 116. In example embodiments, the aspect ratio of the preliminary via hole 150 may be between about 10:1 and about 100:1.

[0060] The etching process may include an anisotropic etching process. For example, the etching process may include a reactive ion etching (RIE) process. In example embodiments, the sidewall of the preliminary through hole 150 may have a slope such that the width of the preliminary through hole 150 gradually decreases from the second surface 2 of the substrate 100a toward the first surface 1.

[0061] refer to Figure 6 , a first insulating liner layer 152 may be formed on inner surfaces of the substrate 100 a and the preliminary through hole 150 .

[0062] In example embodiments, the first insulating liner layer 152 formed on the inner surface of the preliminary via hole 150 may have a first thickness, and the first insulating liner layer 152 formed on the second surface 2 of the substrate 100 a may have a second thickness greater than the first thickness.

[0063] refer to Figure 7 , the first insulating liner layer 152 may be anisotropically etched, and then a portion of the first insulating interlayer 110 below the bottom of the preliminary via hole 150 may be etched to form a first via hole 150 a exposing an upper surface of the first barrier pattern 112 .

[0064] In the etching process, the first insulating liner layer 152 formed on the second surface 2 of the substrate 100a may be partially etched. In some example embodiments, the first insulating liner layer 152 formed on the second surface 2 of the substrate 100a may be completely removed.

[0065] Thus, a second insulating liner layer 152a may be formed on the sidewall of the first via hole 150a and the second surface 2 of the substrate 100a. A lower surface of the second insulating liner layer 152a formed in the first via hole 150a may be spaced apart from an upper surface of the first barrier pattern 112.

[0066] The etching process may stop at the upper surface of the first barrier pattern 112 so that the first seed copper pattern 113 and the first copper pattern 114 are not exposed by the bottom of the first through hole 150 a .

[0067] refer to Figure 8 A sacrificial layer 154 may be conformally formed on the second insulating liner layer 152a and the first barrier pattern 112 and the first insulating interlayer 110 exposed by the first via hole 150a. The sacrificial layer 154 may be formed in the first via hole 150a to have a third thickness.

[0068] In example embodiments, a sacrificial layer 154 may be conformally formed in the first through hole 150a having a high aspect ratio, and the sacrificial layer 154 may include a material that can be easily removed by wet etching. When the sacrificial layer 154 is removed, the second insulating liner layer 152a and the first insulating interlayer 110 including silicon oxide may not be removed. Therefore, the sacrificial layer 154 may include a material having a high etching selectivity relative to silicon oxide. In addition, the sacrificial layer 154 may be formed of a material that can be formed at a temperature lower than about 500°C. In example embodiments, the sacrificial layer 154 may be formed by a physical vapor deposition process such as a sputtering process.

[0069] In example embodiments, the sacrificial layer 154 may be formed of titanium, titanium nitride, etc. For example, the sacrificial layer 154 may be formed of a titanium layer.

[0070] refer to Fig. 9 , the sacrificial layer 154 on the bottom of the first through hole 150a may be anisotropically etched, and then the first barrier pattern 112, the first seed copper pattern 113, and the upper surface of the first copper pattern 114 under the bottom of the first through hole 150a may be partially etched to form a second through hole 150b. The second through hole 150b may be formed under the first through hole 150a, and the second through hole 150b may be connected to the first through hole 150a. The width of the second through hole 150b may be smaller than the width of the first through hole 150a.

[0071] The etching process may include an anisotropic etching process. For example, the etching process may include a RIE process.

[0072] When etching the first seed copper pattern 113 and the first copper pattern 114, the etched copper may be re-sputtered to the lower sidewalls of the first and second vias 150a and 150b. Therefore, copper contaminants 156 may be attached to the surface of the sacrificial layer 154 corresponding to the lower sidewalls of the first and second vias 150a and 150b.

[0073] refer to Fig.10 , the sacrificial layer 154 may be removed by an isotropic etching process. The isotropic etching process may include, for example, a wet etching process. The sacrificial layer 154 may be etched to form a through hole 160 including a first through hole 150a and a second through hole 150b.

[0074] By removing the sacrificial layer 154, the copper contaminant 156 attached to the sacrificial layer 154 may also be removed. That is, the copper contaminant 156 may be removed together with the sacrificial layer 154. Therefore, the copper contaminant 156 does not remain on the second insulating liner layer 152a and the first insulating interlayer 110 exposed by the through hole 160. When the wet etching process is performed, the sacrificial layer 154 and the copper contaminant 156 may be removed without damaging the second insulating liner layer 152a.

[0075] In example embodiments, when the sacrificial layer 154 is formed of titanium, the sacrificial layer 154 may be easily removed by a wet etching process. In this case, the etchant may include, for example, dilute hydrofluoric acid (DHF) or KOH and H 2 O 2 of mixed solution.

[0076] The via 160 may have a first portion passing through the substrate 100a and the first insulating interlayer 110, and a second portion of the first copper pattern 114 below the first portion and extending to the pad pattern 116. The first portion of the via 160 may be located above an upper surface of the pad pattern 116.

[0077] The width W1 of the first portion of the through hole 160 may be greater than the width W2 of the second portion. The first portion and the second portion of the through hole 160 may communicate with each other. In addition, the through hole 160 may have a bent portion at a boundary between the first portion and the second portion.

[0078] In example embodiments, a bottom of a first portion of the via hole 160 may expose a portion of an upper surface of the first barrier pattern 112. In example embodiments, a second portion of the via hole 160 may be bent due to a thickness of the sacrificial layer 154. In example embodiments, a bottom of a second portion of the via hole 160 may expose a portion of an upper surface of the first copper pattern 114.

[0079] refer to Fig.11 A second barrier layer 162 may be conformally formed on the second insulating liner layer 152a and the first insulating interlayer 110, the first barrier pattern 112, the first seed copper pattern 113, and the first copper pattern 114 exposed by the through hole 160. In addition, a second seed copper layer 164 may be conformally formed on the second barrier layer 162.

[0080] The second barrier layer 162 and the second seed copper layer 164 may each be formed along a curved portion between the first and second portions of the via 160. The second barrier layer 162 may contact an upper surface of the first barrier pattern 112. The second barrier layer 162 may include, for example, tantalum, tantalum nitride, or the like.

[0081] The second barrier layer 162 and the second seed copper layer 164 may be formed by a physical vapor deposition process such as a sputtering process.

[0082] refer to Fig.12 , a second copper layer 166 may be formed on the second seed copper layer 164 to completely fill the through hole 160. The second copper layer 166 may be formed by, for example, an electroplating process.

[0083] The second copper layer 166, the second seed copper layer 164, the second barrier layer 162, and the second insulating liner layer 152a may be planarized until the second surface 2 of the substrate 100a may be exposed to form a through-silicon via 168 in the through-hole 160 and an insulating liner 152b on the sidewall of the through-silicon via 168 and surrounding the through-silicon via 168, as shown in FIG. Figure 1 The through silicon via 168 may include a second barrier pattern 162a, a second seed copper pattern 164a, and a second copper pattern 166a.

[0084] The bottom of the insulating liner 152b may be located between the upper surface of the first insulating interlayer 110 and the upper surface of the pad pattern 116. Therefore, the bottom of the insulating liner 152b may be spaced apart from the upper surface of the pad pattern 116.

[0085] As described above, the copper contaminants 156 generated by the etching process may be deposited on the sidewalls of the sacrificial layer 154. Therefore, when the sacrificial layer 154 is removed, the copper contaminants 156 may be removed together with the sacrificial layer 154.

[0086] The through silicon via 168 formed by the above process may have a first portion passing through the substrate 100a and the first insulating interlayer 110, and a second portion of the first copper pattern 114 below the first portion and extending to the pad pattern 116. In addition, a boundary between the first portion and the second portion of the through silicon via 168 may have a curved portion. The second barrier pattern 162a included in the through silicon via 168 may contact at least a portion of an upper surface of the first barrier pattern 112 included in the pad pattern 116.

[0087] Fig.13 is a cross-sectional view illustrating a multi-chip package according to example embodiments.

[0088] refer to Fig.13 , the multi-chip package may include a package substrate 300 , a first semiconductor device 190 , a second semiconductor device 205 , a first conductive bump 400 , a second conductive bump 410 , a molding member 500 , and external connection terminals 600 .

[0089] The package substrate 300 may include an insulating substrate and a conductive pattern. The conductive pattern may be formed in the insulating substrate. Each conductive pattern may have an upper portion exposed by the upper surface of the insulating substrate and a lower portion exposed by the lower surface of the insulating substrate.

[0090] The first semiconductor device 190 may be disposed over an upper surface of the package substrate 300. In example embodiments, the first semiconductor device 190 may have Figure 1 The structures of the semiconductor devices shown are substantially the same. Therefore, the same reference numerals may refer to the same elements, and any further description of the same elements may be omitted for the sake of brevity.

[0091] In the first semiconductor device 190, an upper pad 180 may be further formed on an upper surface of the through silicon via 168. In addition, an upper insulating layer 182 may be further formed on a side of the upper pad 180.

[0092] The first conductive bump 400 may be disposed between the package substrate 300 and the first semiconductor device 190. In example embodiments, the first conductive bump 400 may respectively contact an upper portion of a conductive pattern of the package substrate 300 and a pad electrode of the first semiconductor device 190. Thus, the package substrate 300 and the first semiconductor device 190 may be electrically connected through the first conductive bump 400.

[0093] The second semiconductor device 205 may be stacked over the first semiconductor device 190. The second semiconductor device 205 may include a pad 210. The pad 210 may be disposed at a lower surface of the second semiconductor device 205.

[0094] The second conductive bump 410 may be disposed between the first semiconductor device 190 and the second semiconductor device 205. In example embodiments, the second conductive bump 410 may contact the upper pad 180 of the first semiconductor device 190 and the pad 210 of the second semiconductor device 205. Thus, the through-silicon via 168 of the first semiconductor device 190 and the second semiconductor device 205 may be electrically connected to each other.

[0095] The molding member 500 may be formed on an upper surface of the package substrate 300 to cover the first semiconductor device 190 and the second semiconductor device 205. The molding member 500 may include an epoxy molding compound (EMC).

[0096] The external connection terminals 600 may be mounted on the lower surface of the package substrate 300. The external connection terminals 600 may be electrically connected to the conductive patterns of the package substrate 300. The external connection terminals 600 may include solder balls.

[0097] In an example embodiment, if Fig.13 As shown, the multi-chip package may include two stacked semiconductor devices. However, in some example embodiments, the multi-chip package may include three or more stacked semiconductor devices. In this case, each stacked semiconductor device may include, except for the top semiconductor device, Figure 1 A through silicon via is shown.

[0098] In example embodiments, the through silicon via may not contain copper contaminants, and thus, reliability defects due to copper contaminants may be reduced.

[0099] It should be understood that when an element or layer is referred to as being "on," "above," or "on," or "connected to" or "coupled to" another element or layer, the element or layer may be directly on, above, on, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element or layer is referred to as being "directly on," "above," or "on," or "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more thereof.

[0100] The foregoing is illustrative of example embodiments and should not be construed as limiting thereof. Although several example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without materially departing from the novel teachings and advantages of the present disclosure. It is therefore intended that all such modifications be included within the scope of the present disclosure as defined in the claims. In the claims, means-plus-function clauses are intended to cover structures described herein as performing the described function, not only structural equivalents, but also equivalent structures. It should therefore be understood that the foregoing is illustrative of various example embodiments and should not be construed as limited to the particular example embodiments disclosed, and that modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device include: a first insulating interlayer, the first insulating interlayer being disposed on a first surface of the substrate; A pad pattern, the pad pattern being disposed on a lower surface of the first insulating interlayer, the pad pattern comprising a first copper pattern; a through silicon via, the through silicon via passing through the substrate and the first insulating interlayer and contacting the first copper pattern of the pad pattern; as well as an insulating liner disposed on a sidewall of the through silicon via, The bottom of the insulating pad is arranged between the upper surface of the first insulating intermediate layer and the upper surface of the pad pattern. wherein the through silicon via comprises a first portion passing through the substrate and the first insulating interlayer, and a second portion below the first portion and extending to a portion of the first copper pattern in the pad pattern, wherein the lower sidewall and the bottom of the second portion contact the first copper pattern, and The through silicon via has a curved portion at a boundary between the first portion and the second portion.

2. The semiconductor device according to claim 1, in, A width of the first portion at a boundary between the substrate and the first insulating interlayer is greater than a width of the second portion at an upper surface of the pad pattern.

3. The semiconductor device according to claim 1, in, The through silicon via is formed in a through hole penetrating the substrate and the first insulating interlayer and extending to an upper portion of the pad pattern to expose a portion of a surface of the first copper pattern.

4. The semiconductor device according to claim 3, in, The through silicon via includes a second barrier pattern, a second seed copper pattern, and a second copper pattern, and The stacked structure of the second barrier pattern and the second seed copper pattern is conformally formed on the surface of the through hole, and the second copper pattern is formed on the second seed copper pattern to fill the through hole.

5. The semiconductor device according to claim 1, in, The pad pattern includes the first copper pattern, a first seed copper pattern and a first barrier pattern, and The stacked structure of the first seed copper pattern and the first barrier pattern is conformally formed on the upper surface and sidewalls of the first copper pattern.

6. The semiconductor device according to claim 5, in, The first barrier pattern in the pad pattern contacts the lower surface of the first insulating interlayer, and Wherein, a bottom of the first portion of the through silicon via contacts an upper surface of the first barrier pattern.

7. The semiconductor device according to claim 1, in, forming circuit elements on the first surface of the substrate, and Wherein, the first insulating intermediate layer covers the circuit element.

8. A method for manufacturing a semiconductor device, the method include: forming a first insulating interlayer on the first surface of the substrate; forming a pad pattern including a first copper pattern on a lower surface of the first insulating interlayer; forming a through hole passing through the substrate and the first insulating interlayer to expose a portion of a surface of the first copper pattern in the pad pattern; forming an insulating liner and a through silicon via in the through hole, the through silicon via contacting the first copper pattern of the pad pattern, wherein the through silicon via comprises a first portion passing through the substrate and the first insulating interlayer, and a second portion of the first copper pattern below the first portion and extending to the pad pattern, The bottom of the insulating pad is arranged between the upper surface of the first insulating intermediate layer and the upper surface of the pad pattern. wherein the lower sidewall and the bottom of the second portion directly contact the first copper pattern, and The through silicon via has a curved portion at a boundary between the first portion and the second portion.

9. The method according to claim 8, further comprising: include: forming a second insulating interlayer on the lower surface of the first insulating interlayer, Wherein, the pad pattern is formed in the second insulating interlayer.

10. The method according to claim 9, in, Forming the pad pattern includes: forming an opening in the second insulating interlayer to expose the lower surface of the first insulating interlayer; forming a first barrier pattern and a first seed copper pattern on sidewalls and a bottom of the opening; and forming the first copper pattern on the first seed copper pattern to fill the opening, The sidewall and the upper surface of the first copper pattern are in contact with the stacked structure including the first seed copper pattern and the first barrier pattern.

11. The method according to claim 8, in, Forming the through hole comprises: forming a first through hole passing through the substrate and the first insulating interlayer to expose an upper surface of a first barrier pattern of the pad pattern, wherein the first barrier pattern is arranged between the first through hole and the first copper pattern; forming a sacrificial layer on the sidewall and bottom of the first through hole; etching the sacrificial layer formed on the bottom of the first through hole and the surfaces of the first barrier pattern and the first copper pattern below the bottom of the first through hole to form a second through hole, wherein a width of the second through hole is smaller than a width of the first through hole; and The sacrificial layer and copper contaminants on the sacrificial layer are removed.

12. The method according to claim 11, further comprising: include: Before forming the first through hole, etching the substrate and the first insulating interlayer to form a preliminary through hole spaced apart from an upper surface of the pad pattern; as well as The insulating liner is formed on a sidewall of the preliminary through hole.

13. The method according to claim 11, in, The sacrificial layer is removed by an isotropic etching process.

14. The method according to claim 11, in, The sacrificial layer is formed by a sputtering process, and Wherein, the sacrificial layer comprises titanium or titanium nitride.

15. A method for manufacturing a semiconductor device, the method include: forming a first insulating interlayer on the first surface of the substrate; forming a pad pattern on a lower surface of the first insulating interlayer, the pad pattern comprising a first copper pattern and a first barrier pattern on an upper surface and a sidewall of the first copper pattern; forming a first through hole passing through the substrate and the first insulating interlayer to expose a portion of an upper surface of the first barrier pattern in the pad pattern; forming a sacrificial layer on an inner surface of the first through hole; etching the sacrificial layer formed on the bottom of the first through hole and the first barrier pattern and the upper surface of the first copper pattern below the bottom of the first through hole to form a second through hole, wherein the width of the second through hole is smaller than the width of the first through hole; removing the sacrificial layer and copper contaminants on the sacrificial layer to form a through hole; and forming an insulating liner and a through silicon via in the through hole, the through silicon via contacting the first copper pattern of the pad pattern, The bottom of the insulating pad is arranged between the upper surface of the first insulating intermediate layer and the upper surface of the pad pattern. wherein the through silicon via comprises a first portion passing through the substrate and the first insulating interlayer, and a second portion below the first portion and extending to a portion of the first copper pattern in the pad pattern, and The lower sidewall and the bottom of the second portion contact the first copper pattern.

16. The method according to claim 15, in, The sacrificial layer is removed by an isotropic etching process.

17. The method according to claim 15, in, The sacrificial layer is formed by a sputtering process, and Wherein, the sacrificial layer comprises titanium or titanium nitride.

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