Display device and method of manufacturing the same

Abstract

A display device and a manufacturing method thereof are disclosed. The display device may include: a substrate; a first layer on the substrate, the first layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness; a second layer on the first layer; an active pattern on the second layer, the active pattern overlapping only the first portion of the first layer; a gate electrode on the active pattern; a source electrode and a drain electrode on the gate electrode and connected to the active pattern; a first electrode connected to one of the source electrode and the drain electrode; a pixel defining layer on the first electrode, the pixel defining layer having an opening portion exposing at least a portion of the first electrode; a light emitting layer in the opening portion on the first electrode; and a second electrode on the light emitting layer.

Description

Technical Field

[0001] Exemplary embodiments of the present invention generally relate to a display device, and more particularly, to a display device including a polycrystalline silicon substrate and a method of manufacturing the display device. Background Art

[0002] An active matrix (AM) type organic light emitting display device may include a pixel driving circuit in each pixel and the pixel driving circuit may include a thin film transistor (TFT) using silicon. The TFT may be formed of amorphous silicon or polycrystalline silicon.

[0003] Because the active layer having a source electrode, a drain electrode, and a channel is formed of amorphous silicon (a-Si), an amorphous silicon TFT used in a pixel driving circuit may have a resistance of 1 square centimeter per volt per second (cm2). 2 / Vs) or lower low electron mobility. Therefore, amorphous silicon TFTs have recently been replaced by polycrystalline silicon (poly-Si) TFTs. Compared with amorphous silicon TFTs, polycrystalline silicon TFTs have higher electron mobility and safer light exposure. Therefore, polycrystalline silicon TFTs can be suitable for use as active layers of driving TFTs and / or switching TFTs of AM-type organic light-emitting display devices.

[0004] Polycrystalline silicon can be manufactured according to several methods. These methods can generally be classified as methods of polycrystalline silicon deposition or methods of amorphous silicon deposition and crystallization.

[0005] Examples of a method of polysilicon deposition include chemical vapor deposition (CVD), sputtering, vacuum evaporation, and the like.

[0006] Examples of a method of depositing and crystallizing amorphous silicon include solid phase crystallization (SPC), excimer laser crystallization (ELC), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), sequential lateral solidification (SLS), and the like.

[0007] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0008] The display device and the manufacturing method thereof constructed according to the principles and exemplary embodiments of the present invention can prevent defects such as stains from being generated in a high temperature process such as excimer laser annealing (ELA) for making active patterns in amorphous silicon TFTs of a display. For example, the first buffer layer having a first portion with a relatively thin thickness and the active pattern overlapping the first portion of the first buffer layer can prevent ELA stains from being generated in the active pattern of the display device by hydrogen diffused upward from the first buffer layer during the laser crystallization process.

[0009] In addition, in an exemplary method of manufacturing a display device according to the principles of the present invention, after forming a first buffer layer including a first portion having a relatively thin thickness and an amorphous silicon layer, the amorphous silicon layer can be crystallized and patterned to form a polysilicon pattern overlapping the first portion of the first buffer layer. Therefore, a display device without ELA stains can be manufactured.

[0010] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0011] According to one aspect of the present invention, a display device includes: a substrate; a first layer arranged on the substrate, the first layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness; a second layer arranged on the first layer; an active pattern arranged on the second layer, the active pattern overlapping only with the first portion of the first layer; a gate electrode arranged on the active pattern; a source electrode and a drain electrode arranged on the gate electrode, the source electrode and the drain electrode being connected to the active pattern; a first electrode connected to one of the source electrode and the drain electrode; a pixel defining layer arranged on the first electrode, the pixel defining layer having an opening portion exposing at least a portion of the first electrode; a light emitting layer arranged in the opening portion on the first electrode; and a second electrode arranged on the light emitting layer.

[0012] The second layer may include a third portion having a third thickness and a fourth portion having a fourth thickness less than the third thickness.

[0013] The third portion of the second layer may overlap the first portion of the first layer, and the fourth portion of the second layer may overlap the second portion of the first layer.

[0014] The first thickness may be smaller than the third thickness.

[0015] An upper surface of the second layer may be substantially planarized.

[0016] The active pattern may not overlap the second portion of the first layer.

[0017] The first layer may include a buffer layer including silicon nitride.

[0018] The second layer may include a buffer layer including silicon oxide.

[0019] The first layer may have a first hydrogen concentration and the second layer may have a second hydrogen concentration, the first hydrogen concentration being greater than the second hydrogen concentration.

[0020] The active pattern may include polysilicon.

[0021] The active pattern may include a source region and a drain region connected to the source electrode and the drain electrode, respectively, and a channel region disposed between the source region and the drain region.

[0022] The first layer may further include an alignment mark.

[0023] According to another aspect of the present invention, a method for manufacturing a display device is provided, the method comprising the steps of: forming a first layer on a substrate including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness; forming a second layer on the first layer; and forming a polysilicon pattern on the second layer that overlaps only with the first portion of the first layer.

[0024] The step of forming the first layer may include the steps of forming a first inorganic layer having a second thickness on a substrate using silicon nitride, and partially etching a portion of the first inorganic layer corresponding to the first portion.

[0025] The step of forming the polysilicon pattern may include the steps of forming a polysilicon layer on the second layer, and etching a portion of the polysilicon layer overlapping only the second portion.

[0026] The step of forming a polysilicon layer may include the steps of forming an amorphous silicon layer on the second layer and crystallizing the amorphous silicon layer.

[0027] The step of partially etching a portion of the first inorganic layer corresponding to the first portion may include the steps of: forming a first photoresist layer on the first inorganic layer, placing a first photomask on the first photoresist layer so that a first light-transmitting portion of the first photomask corresponds to the first portion and a first light-blocking portion of the first photomask corresponds to the second portion, exposing and developing the first photoresist layer to form a first photoresist pattern, and using the first photoresist pattern as an etching stopper to partially etch the first inorganic layer.

[0028] The step of etching the portion of the polysilicon layer overlapping the second portion may include the steps of: forming a second photoresist layer on the polysilicon layer; placing a second photomask on the second photoresist layer so that a second light-transmitting portion of the second photomask corresponds to the second portion and a second light-blocking portion of the second photomask corresponds to the first portion, exposing and developing the second photoresist layer to form a second photoresist pattern, and etching the polysilicon layer using the second photoresist pattern as an etching stopper.

[0029] The step of forming the first layer may further include the step of forming an alignment mark, and the second photomask may be aligned with the first layer using the alignment mark.

[0030] The step of forming the second layer may include the steps of forming a second inorganic layer with silicon oxide on the first layer, and planarizing an upper surface of the second inorganic layer.

[0031] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

[0033] Figure 1 is a plan view of an exemplary embodiment of a polysilicon substrate constructed according to the principles of the present invention.

[0034] Figure 2 is a cross-sectional view of an exemplary embodiment of a polysilicon substrate constructed according to the principles of the present invention.

[0035] Figure 3 yes Figure 2 A plan view of a polysilicon pattern in a polysilicon substrate.

[0036] Figure 4 , Figure 5 , Fig. 6A , Figure 7 , Fig. 8A , Fig. 9 , Fig.10 , Fig.11 , Fig.12 is a cross-sectional view for explaining a method of manufacturing a polycrystalline silicon substrate according to an exemplary embodiment, and Figure 6B and Figure 8B This is a plan view for explaining the method.

[0037] Fig.13 and Fig.14 is a cross-sectional view for explaining a method of manufacturing a polycrystalline silicon substrate according to another exemplary embodiment.

[0038] Fig.15 is a plan view of an exemplary embodiment of a display device constructed according to the principles of the present invention.

[0039] Fig.16 It is used for Fig.15An equivalent circuit diagram of a representative pixel of a display device is illustrated.

[0040] Fig.17 is a cross-sectional view of an exemplary embodiment of a display device constructed according to the principles of the present invention. DETAILED DESCRIPTION

[0041] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. "Embodiment" and "implementation" as used herein are interchangeable words, which are non-limiting examples of devices or methods using one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments may be implemented without these specific details or using one or more equivalent settings. In other cases, known structures and devices are shown in the form of block diagrams in order to avoid unnecessary obscurity of various exemplary embodiments. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, configuration, and features of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0042] Unless otherwise specified, the exemplary embodiments shown should be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged, and / or rearranged without departing from the inventive concept.

[0043] Cross-hatching and / or shading are generally provided in the drawings to clarify the boundaries between adjacent elements. Therefore, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other feature, attribute, characteristic, etc. of the elements, unless otherwise stated. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the exemplary embodiments can be implemented differently, the order of a particular process can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same figure numbers represent the same elements.

[0044] When an element such as a layer is referred to as being "on" another element or layer, "connected to" another element or layer, or "coupled to" another element or layer, it can be directly on another element or layer, connected to another element or layer, or coupled to another element or layer, or there can be an intermediate element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" another element or layer, or "directly coupled to" another element or layer, there is no intermediate element or layer. For this reason, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intermediate element. In addition, the D1 axis, the D2 axis, and the D3 axis are not limited to the three axes of a rectangular coordinate system such as the x, y, and z axes, and can be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis can be perpendicular to each other, or different directions that are not perpendicular to each other can be represented. For the purpose of this disclosure, "at least one of X, Y, Z" and "at least one selected from the group consisting of X, Y, Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0046] For descriptive purposes, spatially relative terms such as "below," "beneath," "under," "lower," "above," "upper," "on," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein and thereby describe the relationship of one element to another element shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the drawings. For example, if the device in the figure is flipped, elements described as being "below" or "beneath" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary term "below" can include both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein are interpreted accordingly.

[0047] The terms used here are for the purpose of describing specific embodiments and are not restrictive. As used herein, the singular forms "one", "an", "said / the" are also intended to include plural forms, unless the context clearly states otherwise. In addition, when used in this specification, the term "comprising" specifies the presence of the features, integral bodies, steps, operations, elements, components, and / or their groups, but does not exclude the presence or increase of one or more other features, integral bodies, steps, operations, elements, components, and / or their groups. It should also be noted that as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than terms of degree, and therefore, are used to explain the inherent deviations of measured values, calculated values, and / or specified values ​​that will be recognized by those of ordinary skill in the art.

[0048] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views, which are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the exemplary embodiments disclosed herein should not be interpreted as being limited to the shapes of the specifically illustrated areas, but rather include deviations in shape due to, for example, manufacturing. In this manner, the areas shown in the drawings may be schematic in nature and the shapes of these areas may not reflect the actual shapes of the areas of the device and, therefore, are not necessarily restrictive.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. Unless explicitly defined herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0050] Hereinafter, a polycrystalline silicon substrate, a method of manufacturing the polycrystalline silicon substrate, and a display device according to exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0051] In the following, reference will be made to Figures 1 to 3 A polycrystalline silicon substrate according to an exemplary embodiment will be described.

[0052] Figure 1 is a plan view of an exemplary embodiment of a polysilicon substrate constructed in accordance with the principles of the present invention.

[0053] Reference Figure 1According to an exemplary embodiment, the polycrystalline silicon substrate may include a first region 1A and a second region 2A adjacent to the first region 1A. For example, the second region 2A may surround the first region 1A. In an exemplary embodiment, the polycrystalline silicon substrate may be a polycrystalline silicon substrate of a display device. For example, the first region 1A and the second region 2A may correspond to a display region and a peripheral region of the display device, respectively.

[0054] Figure 2 is a cross-sectional view of an exemplary embodiment of a polysilicon substrate constructed according to the principles of the present invention.

[0055] Reference Figure 2 , the polysilicon substrate according to an exemplary embodiment may include a substrate 110, a buffer layer, and a polysilicon pattern 140. In an exemplary embodiment, the polysilicon substrate may further include a first alignment mark AM1 and a second alignment mark AM2.

[0056] The substrate 110 may be an insulating substrate including glass, quartz, ceramic, etc. In an exemplary embodiment, the substrate 110 may be an insulating flexible substrate including plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyetheretherketone (PEEK), polycarbonate (PC), polyarylate, polyethersulfone (PES), polyimide (PI), etc.

[0057] The buffer layer may be disposed on the substrate 110. The buffer layer may provide a planarized surface over the substrate 110. The buffer layer may prevent impurities from penetrating over the substrate 110 through the substrate 110. The buffer layer may include a first buffer layer 120 and a second buffer layer 130.

[0058] The first buffer layer 120 may be disposed on the substrate 110. In an exemplary embodiment, the first buffer layer 120 may include silicon nitride (SiN x ).

[0059] The first buffer layer 120 may have a relatively high hydrogen concentration. Silicon nitride included in the first buffer layer 120 may contain a relatively large amount of hydrogen. For example, the first buffer layer 120 may have a hydrogen concentration of about 16% to about 20%.

[0060] The first buffer layer 120 may include a first portion 121 and a second portion 122. The first portion 121 and the second portion 122 may have different thicknesses from each other. The first portion 121 may have a first thickness TH1, and the second portion 122 may have a second thickness TH2 greater than the first thickness TH1. For example, the first thickness TH1 may be about 50 angstroms. The second thickness TH2 may be in the range of about 300 angstroms to about 200 angstroms, and may be about 500 angstroms. Therefore, the first buffer layer 120 may have a concavo-convex shape in which the second portion 122 protrudes upward from the first portion 121 .

[0061] The first buffer layer 120 may further include a first alignment mark AM1. The first alignment mark AM1 may be formed in the second region 2A. The first alignment mark AM1 may be used to align the polysilicon pattern 140 with the first buffer layer 120.

[0062] The second buffer layer 130 may be disposed on the first buffer layer 120. In exemplary embodiments, the second buffer layer 130 may include silicon oxide (SiOx).

[0063] The second buffer layer 130 may have a relatively low hydrogen concentration. Silicon oxide included in the second buffer layer 130 may include a relatively small amount of hydrogen. Therefore, the hydrogen concentration of the first buffer layer 120 may be greater than that of the second buffer layer 130.

[0064] The second buffer layer 130 may include a third portion 131 and a fourth portion 132. The third portion 131 and the fourth portion 132 may have different thicknesses from each other. The third portion 131 may have a third thickness TH3, and the fourth portion 132 may have a fourth thickness TH4 less than the third thickness TH3. For example, the third thickness TH3 may be about 3000 angstroms, and the fourth thickness TH4 may be in the range of about 2550 angstroms to about 2700 angstroms.

[0065] The third portion 131 of the second buffer layer 130 may overlap the first portion 121 of the first buffer layer 120, and the fourth portion 132 of the second buffer layer 130 may overlap the second portion 122 of the first buffer layer 120. In one embodiment, the first thickness TH1 of the first portion 121 may be less than the third thickness TH3 of the third portion 131.

[0066] In an exemplary embodiment, the upper surface of the second buffer layer 130 may be substantially flattened. When the upper surface of the substrate 110 is flattened, the sum of the first thickness TH1 and the third thickness TH3 may be substantially equal to the sum of the second thickness TH2 and the fourth thickness TH4. Therefore, the second buffer layer 130 may have a concavo-convex shape in which the third portion 131 protrudes downward from the fourth portion 132.

[0067] The polysilicon pattern 140 may be disposed on the second buffer layer 130. The polysilicon pattern 140 may include polysilicon.

[0068] The polysilicon pattern 140 may overlap the first portion 121 of the first buffer layer 120. The polysilicon pattern 140 may not overlap the second portion 122 of the first buffer layer 120. Since the third portion 131 and the fourth portion 132 of the second buffer layer 130 overlap the first portion 121 and the second portion 122 of the first buffer layer 120, respectively, the polysilicon pattern 140 may overlap the third portion 131 of the second buffer layer 130 and may not overlap the fourth portion 132 of the second buffer layer 130.

[0069] Figure 3 yes Figure 2 FIG. 1 is a plan view of a polysilicon pattern 140 of a polysilicon substrate in FIG.

[0070] Reference Figure 3 , the polysilicon pattern 140 may have a curved and elongated shape in a plan view. Because the polysilicon pattern 140 overlaps the first portion 121 of the first buffer layer 120, the first portion 121 may have substantially the same curved and elongated shape in a plan view as the polysilicon pattern 140. In addition, because the third portion 131 of the second buffer layer 130 overlaps the first portion 121 of the first buffer layer 120, the third portion 131 may have substantially the same curved and elongated shape in a plan view as the polysilicon pattern 140.

[0071] Refer again Figure 2 , the second alignment mark AM2 may be formed in the process of forming the polysilicon pattern 140. For example, the second alignment mark AM2 may be formed in the second region 2A by etching the polysilicon layer. Therefore, the second alignment mark AM2 may be formed in the second region 2A. The second alignment mark AM2 may be formed to overlap with the first alignment mark AM1. Therefore, whether the polysilicon pattern 140 and the first buffer layer 120 are aligned may be determined by checking whether the first alignment mark AM1 and the second alignment mark AM2 overlap with each other.

[0072] In the following, reference will be made to Figures 4 to 12 A method of manufacturing a polycrystalline silicon substrate according to an exemplary embodiment is described.

[0073] Figure 4 , Figure 5 , Fig. 6A , Figure 7 , Fig. 8A , Fig. 9 , Fig.10 , Fig.11 , Fig.12 is a cross-sectional view for explaining a method of manufacturing a polycrystalline silicon substrate according to an exemplary embodiment, and Figure 6B and Figure 8B It is a floor plan.

[0074] Reference Figure 4 , a first inorganic layer 120' may be formed on the substrate 110. The first inorganic layer 120' may be formed to have a second thickness TH2. For example, the second thickness may be about 500 angstroms. The first inorganic layer 120' may be formed of silicon nitride. For example, the first inorganic layer 120' may be formed by a method such as low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, vacuum evaporation, etc.

[0075] Reference Figure 5 , Fig. 6A and Figure 6B , the first inorganic layer 120' may be partially etched to form a first buffer layer 120 including a first portion 121 and a second portion 122. The first portion 121 may have a first thickness TH1, and the second portion 122 may have a second thickness TH2 greater than the first thickness TH1. Therefore, the first buffer layer 120 may have a concavo-convex shape in which the second portion 122 protrudes upward from the first portion 121.

[0076] First, a first photoresist layer 150 may be formed on the first inorganic layer 120'. In an exemplary embodiment, the first photoresist layer 150 may include a positive photoresist. Therefore, an exposed portion of the first photoresist layer 150 may be removed, and an unexposed portion of the first photoresist layer 150 may remain.

[0077] Then, a first photomask 160 may be placed on the first photoresist layer 150. The first photomask 160 may include a first light-transmitting portion 161 and a first light-blocking portion 162. The first light-transmitting portion 161 may transmit light, and the first light-blocking portion 162 may block light. For example, the light transmittance of the first light-transmitting portion 161 may be about 100%, and the light transmittance of the first light-blocking portion 162 may be about 0%. The first photomask 160 may be placed so that the first light-transmitting portion 161 corresponds to the first portion 121, and so that the first light-blocking portion 162 corresponds to the second portion 122. The first light-transmitting portion 161 may have a curved and elongated shape in a plan view.

[0078] Then, the first photoresist layer 150 may be exposed and developed using the first photomask 160. A portion of the first photoresist layer 150 exposed by the first light-transmitting portion 161 may be removed, and another portion of the first photoresist layer 150 not exposed by the first light-blocking portion 162 may remain, and thus a first photoresist pattern 150' may be formed.

[0079] Then, the first inorganic layer 120' may be partially etched using the first photoresist pattern 150' as an etch barrier. For example, the first inorganic layer 120' may be etched by dry etching.

[0080] The first portion of the first inorganic layer 120' not covered by the first photoresist pattern 150' may be partially etched, and the first thickness TH1 may be maintained. In other words, the first portion of the first inorganic layer 120' may be etched by the second thickness TH2 minus the thickness of the first thickness TH1. For example, the first thickness TH1 may be in the range of about 50 angstroms to about 200 angstroms. In an exemplary embodiment, the first portion of the first inorganic layer 120' may be partially etched by controlling the etching time. For example, when the etching time for completely etching the first inorganic layer 120' is 100, the first portion of the first inorganic layer 120' may be partially etched by adjusting the etching time to a value greater than 0 and less than 100. The partially etched first portion of the first inorganic layer 120' may correspond to the first portion 121 of the first buffer layer 120. The first portion 121 of the first buffer layer 120 may have a curved and elongated shape in a plan view.

[0081] The second portion of the first inorganic layer 120 ′ covered by the first photoresist pattern 150 ′ may not be etched and may maintain the second thickness TH2 . The unetched second portion of the first inorganic layer 120 ′ may correspond to the second portion 122 of the first buffer layer 120 .

[0082] The first alignment mark AM1 may be formed in the process of forming the first buffer layer 120. The first alignment mark AM1 may be formed in the second region 2A by partially etching the first inorganic layer 120'. The first alignment mark AM1 may be used to align the polysilicon pattern 140 with the first buffer layer 120 in a subsequent process.

[0083] Reference Figure 7 , a second inorganic layer 130' may be formed on the first buffer layer 120. The second inorganic layer 130' may be formed to have a third thickness TH3. For example, the third thickness TH3 may be about 3000 angstroms. The second inorganic layer 130' may be formed along the contour of the first buffer layer 120. For example, a portion of the second inorganic layer 130' formed on the relatively thick second portion 122 may protrude upward relative to another portion of the second inorganic layer 130' formed on the relatively thin first portion 121. Therefore, the second inorganic layer 130' may include a protruding portion PP formed on the second portion 122 of the first buffer layer 120.

[0084] The second inorganic layer 130' may be formed of silicon oxide. For example, the second inorganic layer 130' may be formed by methods such as low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, vacuum evaporation, etc.

[0085] Reference Fig. 8A and Figure 8B , the upper surface of the second inorganic layer 130' may be planarized to form a second buffer layer 130 including a third portion 131 and a fourth portion 132. The second buffer layer 130 may have a substantially planarized upper surface. The third portion 131 may have a third thickness TH3, and the fourth portion 132 may have a fourth thickness TH4 less than the third thickness TH3. Therefore, the second buffer layer 130 may have a concave-convex shape in which the third portion 131 protrudes downward from the fourth portion 132.

[0086] The protruding portion PP of the second inorganic layer 130' may be polished to planarize the upper surface of the second inorganic layer 130'. In an exemplary embodiment, the upper surface of the second inorganic layer 130' may be planarized by chemical mechanical polishing. For example, the first portion of the second inorganic layer 130' formed on the relatively thick second portion 122 may be polished by the third thickness TH3 minus the fourth thickness TH4, and the second portion of the second inorganic layer 130' formed on the relatively thick second portion 122 may not be polished. The unpolished second portion of the second inorganic layer 130' may correspond to the third portion 131 of the second buffer layer 130, and the polished first portion of the second inorganic layer 130' may correspond to the fourth portion 132 of the second buffer layer 130.

[0087] Reference Fig. 9 , an amorphous silicon layer 140' may be formed on the second buffer layer 130. The amorphous silicon layer 140' may be formed of amorphous silicon. For example, the amorphous silicon layer 140' may be formed by a method such as LPCVD, APCVD, PECVD, sputtering, vacuum evaporation, or the like.

[0088] When the upper portion of the amorphous silicon layer 140' is exposed to air, a natural oxide layer may be formed on the amorphous silicon layer 140'. When the natural oxide layer remains on the amorphous silicon layer 140', in a subsequent process of crystallizing the amorphous silicon layer 140' to form a polycrystalline silicon layer, the surface roughness of the polycrystalline silicon layer may increase due to the natural oxide layer. Therefore, ozone (O 3 ), hydrofluoric acid, etc. to clean the amorphous silicon layer 140' to remove the natural oxide layer. In addition, the amorphous silicon layer 140' may be rinsed with deionized water (DW) after cleaning.

[0089] Reference Fig.10, the amorphous silicon layer 140' may be crystallized to form a polycrystalline silicon layer 140".

[0090] In an exemplary embodiment, the amorphous silicon layer 140' may be crystallized by excimer laser annealing (ELA). The polycrystalline silicon layer 140" may be formed by irradiating the amorphous silicon layer 140' with a laser beam. The laser may intermittently generate a laser beam to irradiate the amorphous silicon layer 140'. For example, the laser may be an excimer laser for generating a laser beam having a relatively short wavelength with relatively high power and relatively high efficiency. The excimer laser may include, for example, an inert gas, an inert gas halide, a mercury halide, an inert gas acid compound, and a polyatomic excimer. An example of an inert gas is Ar. 2 , Kr 2 , and Xe 2 Examples of noble gas halides are ArF, ArCl, KrF, KrCl, XeF, and XeCl. Examples of mercury halides are HgCl, HgBr, and HgI. Examples of noble gas acid compounds are ArO, KrO, and XeO. Examples of polyatomic excimers are Kr 2 F and Xe 2 F.

[0091] When the energy of the laser beam irradiated on the amorphous silicon layer 140' is relatively large during the process of forming the polycrystalline silicon layer 140", the laser beam may affect the buffer layer located below the amorphous silicon layer 140'. For example, during the process of forming the polycrystalline silicon layer 140", hydrogen contained in the buffer layer may diffuse into the polycrystalline silicon layer 140", and an ELA stain ES having a stripe shape may be formed on the polycrystalline silicon layer 140" according to the hydrogen. Specifically, hydrogen emitted from the first buffer layer 120 having a relatively high hydrogen concentration may diffuse upward, thereby forming an ELA stain ES at the polycrystalline silicon layer 140". The second buffer layer 130 having a relatively low hydrogen concentration may be used to prevent hydrogen emitted from the first buffer layer 120 from flowing into the polycrystalline silicon layer 140".

[0092] Therefore, ELA stains ES may basically not be formed in a portion of the polysilicon layer 140" disposed on a relatively thin first portion 121 of the first buffer layer 120 and a relatively thick third portion 131 of the second buffer layer 130. ELA stains ES may be formed in another portion of the polysilicon layer 140" disposed on a relatively thick second portion 122 of the first buffer layer 120 and a relatively thin fourth portion 132 of the second buffer layer 130.

[0093] Reference Fig.11 and Fig.12, the polysilicon layer 140 ″ may be etched to form a polysilicon pattern 140 . The polysilicon pattern 140 may overlap the first portion 121 of the first buffer layer 120 . The polysilicon pattern 140 may not overlap the second portion 122 of the first buffer layer 120 .

[0094] First, a second photoresist layer 170 may be formed on the polysilicon layer 140 ″. In an exemplary embodiment, the second photoresist layer 170 may include a positive photoresist. Therefore, an exposed portion of the second photoresist layer 170 may be removed, and an unexposed portion of the second photoresist layer 170 may remain.

[0095] Then, a second photomask 180 may be placed on the second photoresist layer 170. The second photomask 180 may include a second light-transmitting portion 181 and a second light-blocking portion 182. The second light-transmitting portion 181 may transmit light, and the second light-blocking portion 182 may block light. For example, the light transmittance of the second light-transmitting portion 181 may be about 100%, and the light transmittance of the second light-blocking portion 182 may be about 0%. The second photomask 180 may be placed so that the second light-transmitting portion 181 corresponds to the second portion 122 of the first buffer layer 120, and so that the second light-blocking portion 182 corresponds to the first portion 121 of the first buffer layer 120. The second light-blocking portion 182 may have a curved and elongated shape in a plan view.

[0096] In an exemplary embodiment, the second photomask 180 may be aligned with the first buffer layer 120 using the first alignment mark AM1. The alignment mark of the second photomask 180 may be aligned with the first alignment mark AM1 formed in the first buffer layer 120, so that the second light-transmitting portion 181 of the second photomask 180 may be aligned with the second portion 122 of the first buffer layer 120 and the second light-blocking portion 182 of the second photomask 180 may be aligned with the first portion 121 of the first buffer layer 120.

[0097] Then, the second photoresist layer 170 may be exposed and developed using the second photomask 180. A portion of the second photoresist layer 170 exposed by the second light-transmitting portion 181 may be removed, and another portion of the second photoresist layer 170 not exposed by the second light-blocking portion 182 may remain. Thus, a second photoresist pattern 170' may be formed.

[0098] Then, the polysilicon layer 140 ″ may be etched using the second photoresist pattern 170 ′ as an etch barrier. For example, the polysilicon layer 140 ″ may be etched by dry etching.

[0099] The first portion of the polysilicon layer 140″ not covered by the second photoresist pattern 170′ may be substantially etched and removed. The second portion of the polysilicon layer 140″ covered by the second photoresist pattern 170′ may not be etched and remain. The unetched second portion of the polysilicon layer 140″ may correspond to the polysilicon pattern 140. The polysilicon pattern 140 may be formed as shown in FIG. Figure 3 It may have a curved and elongated shape in plan view as shown.

[0100] The second alignment mark AM2 may be formed in the process of forming the polysilicon pattern 140. The second alignment mark AM2 may be formed in the second region 2A by etching the polysilicon layer 140". The second alignment mark AM2 may be formed to overlap with the first alignment mark AM1. Therefore, it may be determined whether the polysilicon pattern 140 and the first buffer layer 120 are aligned by checking whether the first alignment mark AM1 and the second alignment mark AM2 overlap with each other. The second alignment mark AM2 may be used to align other layers with the polysilicon pattern 140 in subsequent processes.

[0101] The ELA stain ES may be substantially not formed at a first portion of the polysilicon layer 140″ disposed over a relatively thin first portion 121 of the first buffer layer 120 and a relatively thick third portion 131 of the second buffer layer 130. Because the first portion of the polysilicon layer 140″ corresponds to the polysilicon pattern 140, the polysilicon substrate according to the illustrated embodiment may include a polysilicon pattern 140 without the ELA stain ES. The ELA stain ES may be formed at a second portion of the polysilicon layer 140″ disposed over a relatively thick second portion 122 of the first buffer layer 120 and a relatively thin fourth portion 132 of the second buffer layer 130. However, the second portion of the polysilicon layer 140″ may be removed during etching of the polysilicon layer 140″.

[0102] In the following, reference will be made to Figures 4 to 10 , Fig.13 and Fig.14 A method of manufacturing a polycrystalline silicon substrate according to an exemplary embodiment will be described.

[0103] To avoid redundancy, references will not be repeated Figures 4 to 10 , Fig.13 and Fig.14 The elements of the method for manufacturing a polycrystalline silicon substrate are described and are similar to those described with reference to Figures 4 to 12 Those elements of the method of manufacturing a polycrystalline silicon substrate described are substantially the same or similar.

[0104] Fig.13 and Fig.14 is a cross-sectional view illustrating a method of manufacturing a polycrystalline silicon substrate according to another exemplary embodiment.

[0105] Reference Fig.13 and Fig.14 , the polysilicon layer 140 ″ may be etched to form a polysilicon pattern 140 . The polysilicon pattern 140 may overlap the first portion 121 of the first buffer layer 120 . The polysilicon pattern 140 may not overlap the second portion 122 of the first buffer layer 120 .

[0106] First, a third photoresist layer 190 may be formed on the polysilicon layer 140 ″. In an exemplary embodiment, the third photoresist layer 190 may include a negative photoresist. Therefore, an exposed portion of the third photoresist layer 190 may remain, and an unexposed portion of the third photoresist layer 190 may be removed.

[0107] Then, a first photomask 160 used in forming the first buffer layer 120 may be placed on the third photoresist layer 190. The first photomask 160 may include a first light-transmitting portion 161 and a first light-blocking portion 162. The first photomask 160 may be placed such that the first light-transmitting portion 161 corresponds to the first portion 121 of the first buffer layer 120, and such that the first light-blocking portion 162 corresponds to the second portion 122 of the first buffer layer 120.

[0108] In an exemplary embodiment, the first photomask 160 may be aligned with the first buffer layer 120 using a first alignment mark AM1. The alignment mark of the first photomask 160 may be aligned with the first alignment mark AM1 formed in the first buffer layer 120 so that the first light-transmitting portion 161 of the first photomask 160 may be aligned with the first portion 121 of the first buffer layer 120 and the first light-blocking portion 162 of the first photomask 160 may be aligned with the second portion 122 of the first buffer layer 120.

[0109] Then, the third photoresist layer 190 may be exposed and developed using the first photomask 160. A portion of the third photoresist layer 190 exposed by the first light-transmitting portion 161 may remain, and another portion of the third photoresist layer 190 not exposed by the first light-blocking portion 162 may be removed. Thus, a third photoresist pattern 190' may be formed.

[0110] Then, the polysilicon layer 140 ″ may be etched using the third photoresist pattern 190 ′ as an etch barrier. For example, the polysilicon layer 140 ″ may be etched by dry etching.

[0111] A first portion of the polysilicon layer 140 ″ covered by the third photoresist pattern 190 ′ may not be etched and remain. A second portion of the polysilicon layer 140 ″ not covered by the third photoresist pattern 190 ′ may be substantially etched and removed. The unetched first portion of the polysilicon layer 140 ″ may correspond to the polysilicon pattern 140 .

[0112] In the following, reference will be made to Figures 15 to 17 A display device according to an exemplary embodiment is described.

[0113] Fig.15 is a plan view of an exemplary embodiment of a display device constructed according to the principles of the present invention.

[0114] Reference Fig.15 , the display device according to the exemplary embodiment may include a display area DA and a peripheral area PA adjacent to the display area DA. For example, the peripheral area PA may surround the display area DA. Fig.15 The display device shown may include Figure 1 For example, the display area DA and the peripheral area PA may correspond to the first area 1A and the second area 2A of the polycrystalline silicon substrate, respectively.

[0115] The display area DA may include a plurality of pixels PX. The display area DA may display an image formed by combining respective lights emitted from the pixels PX. The peripheral area PA may be a non-display area including a driver for transmitting a driving signal to the pixels PX.

[0116] Fig.16 It is shown Fig.15 0 is an equivalent circuit diagram of a representative pixel PX of the display device in FIG.

[0117] Reference Fig.16 , a display device according to an exemplary embodiment may include signal lines and pixels PX connected to the signal lines and arranged in a substantially matrix shape.

[0118] The signal line may include a gate line GL for transmitting a gate signal (or a scan signal), a data line DL for transmitting a data voltage, and a driving voltage line PL for transmitting a driving voltage ELVDD. The gate line GL may extend along a basic row direction. The data line DL and the driving voltage line PL may cross the gate line GL and may extend along a basic column direction. Each pixel PX may include a driving transistor TR1, a switching transistor TR2, a storage capacitor CST, and an organic light emitting diode OLED.

[0119] The driving transistor TR1 may include a control terminal connected to the switching transistor TR2, an input terminal connected to the driving voltage line PL, and an output terminal connected to the organic light emitting diode OLED. The driving transistor TR1 may transmit an output current Id to the organic light emitting diode OLED, and the magnitude of the output current Id varies according to a voltage between the control terminal and the output terminal of the driving transistor TR1.

[0120] The switching transistor TR2 may include a control terminal connected to the gate line GL, an input terminal connected to the data line DL, and an output terminal connected to the driving transistor TR1. The switching transistor TR2 may transmit a data voltage applied to the data line DL to the driving transistor TR1 in response to a gate signal applied to the gate line GL.

[0121] The storage capacitor CST may connect the control terminal and the input terminal of the driving transistor TR1. The storage capacitor CST may store a data voltage applied to the control terminal of the driving transistor TR1 and may maintain the data voltage after the switching transistor TR2 is turned off.

[0122] The organic light emitting diode OLED may include an anode connected to the output terminal of the driving transistor TR1 and a cathode connected to the common voltage ELVSS. The organic light emitting diode OLED may emit light with different brightness according to the output current Id of the driving transistor TR1, thereby displaying an image.

[0123] In an exemplary embodiment, each pixel PX may include two thin film transistors (eg, a driving transistor TR1 and a switching transistor TR2) and one capacitor CST, however, the exemplary embodiment is not limited thereto. For example, in another exemplary embodiment, each pixel PX may include three or more thin film transistors and two or more capacitors.

[0124] Fig.17 is a cross-sectional view of an exemplary embodiment of a display device constructed according to the principles of the present invention.

[0125] Reference Fig.17 According to an exemplary embodiment, the display device may include a substrate 210, a buffer layer disposed on the substrate 210, a thin film transistor TR1 disposed on the buffer layer, and a display element disposed on the thin film transistor TR1. In an exemplary embodiment, the display device may include an organic light emitting diode OLED as a display element. However, the exemplary embodiment is not limited thereto. For example, in other exemplary embodiments, the display device may include a liquid crystal element, an electrophoretic element, an electrowetting element, etc.

[0126] Fig.17 The thin film transistor TR1 and the organic light emitting diode OLED shown in FIG. Fig.16 The driving transistor TR1 shown in FIG. 1 corresponds to the organic light emitting diode OLED. The display device according to the embodiment shown in FIG. 1 may include a Figure 2 A polysilicon substrate of an exemplary embodiment is shown.

[0127] The buffer layer may include a first buffer layer 220 including silicon nitride and a second buffer layer 230 formed on the first buffer layer 220 and including silicon oxide. The first buffer layer 220 may include a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The second buffer layer 230 may include a third portion having a third thickness and overlapping the first portion, and a fourth portion having a fourth thickness less than the third thickness and overlapping the second portion. The upper surface of the second buffer layer 230 may be substantially planarized.

[0128] The thin film transistor TR1 may be formed on the buffer layer. The thin film transistor TR1 may include an active pattern AP, a gate insulating layer IL1, a gate electrode GE, an insulating interlayer IL2, a source electrode SE, and a drain electrode DE stacked sequentially. The thin film transistor TR1 may perform a switching operation of causing current to flow through the active pattern AP according to a signal applied to the gate electrode GE.

[0129] The active pattern AP may be formed on the second buffer layer 230. The active pattern AP may overlap with the first portion of the first buffer layer 220, and may not overlap with the second portion of the first buffer layer 220.

[0130] By implanting ions into Figure 2 The active pattern AP is formed in a portion of the polysilicon pattern 140 in the ion implantation process. Since the polysilicon pattern 140 is partially doped by the ion implantation process, the active pattern AP including the source region SR, the channel region CR, and the drain region DR may be formed. The ions may be n-type impurities or p-type impurities.

[0131] In an exemplary embodiment, impurities having a concentration lower than that of the ion implantation process may be doped into the polysilicon pattern 140 to form a low-concentration doped region between the channel region CR and the source region SR and between the channel region CR and the drain region DR. The low-concentration doped region may be used as a buffer in the active pattern AP so that the electrical characteristics of the thin film transistor TR1 may be improved.

[0132] A gate insulating layer IL1 may be formed on the active pattern AP. The gate insulating layer IL1 may be disposed on the buffer layer and cover the active pattern AP. The gate insulating layer IL1 may insulate the gate electrode GE from the active pattern AP. For example, the gate insulating layer IL1 may be formed of silicon oxide, silicon nitride, or the like.

[0133] The gate electrode GE may be formed on the gate insulating layer IL1. The gate electrode GE may overlap the active pattern AP. The gate electrode GE may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), or an alloy thereof, and may have a single-layer structure or a multi-layer structure including different metal layers. For example, the gate electrode GE may include a three-layer structure of molybdenum, aluminum, and molybdenum, a double-layer structure of copper and titanium, etc.

[0134] An insulating interlayer IL2 may be formed on the gate electrode GE. The insulating interlayer IL2 may be disposed on the gate insulating layer IL1 and cover the gate electrode GE. The insulating interlayer IL2 may insulate the source electrode SE and the drain electrode DE from the gate electrode GE.

[0135] The insulating interlayer IL2 may include an inorganic insulating layer, an organic insulating layer, or a combination thereof. For example, the insulating interlayer IL2 may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof, or may include an insulating metal oxide such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. When the insulating interlayer IL2 includes an organic insulating layer, the insulating interlayer IL2 may include polyimide, polyamide, acrylic resin, phenolic resin, benzocyclobutene (BCB), etc.

[0136] A source electrode SE and a drain electrode DE electrically connected to the source region SR and the drain region DR of the active pattern AP, respectively, may be formed on the insulating interlayer IL2. For example, each of the source electrode SE and the drain electrode DE may include Au, Ag, Al, Cu, Ni, Pt, Mg, Cr, W, Mo, Ti, or an alloy thereof, and may have a single-layer structure or a multi-layer structure including different metal layers. For example, each of the source electrode SE and the drain electrode DE may include a three-layer structure of molybdenum, aluminum, and molybdenum, a double-layer structure of copper and titanium, etc.

[0137] A flat layer (or passivation layer) IL3 may be formed on the source electrode SE and the drain electrode DE. The flat layer IL3 may be disposed on the insulating interlayer IL2 and cover the source electrode SE and the drain electrode DE. The flat layer IL3 may include an inorganic insulating layer, an organic insulating layer, or a combination thereof. For example, the flat layer IL3 may have a single-layer structure or a multilayer structure including silicon nitride or silicon oxide. When the flat layer IL3 includes an organic insulating layer, the flat layer IL3 may include polyimide, polyamide, acrylic resin, phenolic resin, benzocyclobutene (BCB), etc.

[0138] An organic light emitting diode OLED may be formed on the planar layer IL3. The organic light emitting diode OLED may include a first electrode E1, a light emitting layer EL, and a second electrode E2 stacked sequentially. The organic light emitting diode OLED may emit light according to a driving current received from the thin film transistor TR1 to display an image.

[0139] The first electrode E1 may be formed on the planar layer IL3. The first electrode E1 may be connected to one of the source electrode SE and the drain electrode DE. For example, the first electrode E1 may be connected to the drain electrode DE. The first electrode E1 may be a pixel electrode of a display device. The first electrode E1 may be formed as a transmissive electrode or a reflective electrode according to the light emitting type of the display device. If the first electrode E1 is formed as a transmissive electrode, the first electrode E1 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium oxide (In 2 O 3 )、ZnO、SnO 2 ), etc. If the first electrode E1 is formed as a reflective electrode, the first electrode E1 may include Au, Ag, Al, Cu, Ni, Pt, Mg, Cr, W, Mo, Ti, etc., and may have a multi-layered structure including materials used in a transmissive electrode.

[0140] A pixel defining layer PDL may be formed on the planar layer IL3. The pixel defining layer PDL may have an opening portion exposing at least a portion of the first electrode E1. For example, the pixel defining layer PDL may include an organic insulating material.

[0141] The light emitting layer EL may be formed over the first electrode E1. The light emitting layer EL may be formed on the upper surface of the first electrode E1 exposed by the opening portion of the pixel defining layer PDL.

[0142] The light emitting layer EL may include a low molecular weight polymer or a high molecular weight polymer. For example, the light emitting layer EL may include copper phthalocyanine, nitrogen (N), N'-diphenylbenzidine, tris-(8-hydroxyquinoline)aluminum, etc. as a low molecular weight polymer. The light emitting layer EL may include poly (3,4-ethylenedioxythiophene), polyaniline, polyphenylene vinylene, polyfluorene, etc. as a high molecular weight polymer.

[0143] In an exemplary embodiment, the light emitting layer EL may emit red light, green light or blue light. In another exemplary embodiment, when the light emitting layer EL emits white light, the light emitting layer EL may have a multilayer structure including a red light emitting layer, a green light emitting layer and a blue light emitting layer, or a single layer structure including a red light emitting material, a green light emitting material and a blue light emitting material.

[0144] In exemplary embodiments, a hole injection layer and / or a hole transport layer may be further formed between the first electrode E1 and the light emitting layer EL, or an electron transport layer and / or an electron injection layer may be further formed on the light emitting layer EL.

[0145] The second electrode E2 may be formed on the light emitting layer EL. The second electrode E2 may be a common electrode of the display device. Depending on the light emitting type of the display device, the second electrode E2 may be formed as a transmissive electrode or a reflective electrode. For example, when the second electrode E2 is formed as a transmissive electrode, the second electrode E2 may include lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), or a combination thereof.

[0146] A thin film encapsulation layer TFE may be formed on the second electrode E2. The thin film encapsulation layer TFE may cover the organic light emitting diode OLED to protect the organic light emitting diode OLED from external materials. The thin film encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. For example, the thin film encapsulation layer TFE may include: a first thin film encapsulation layer TFE1 including an inorganic material, a second thin film encapsulation layer TFE2 formed on the first thin film encapsulation layer TFE1 and including an organic material, and a third thin film encapsulation layer TFE3 formed on the second thin film encapsulation layer TFE2 and including an inorganic material.

[0147] The display device according to the exemplary embodiment may be applied to a display device included in a computer, a notebook, a mobile phone, a smart phone, a smart tablet, a PMP, a PDA, an MP3 player, or the like.

[0148] Although certain exemplary embodiments and implementations of polycrystalline silicon substrates, methods for manufacturing polycrystalline silicon substrates, and display devices manufactured according to these exemplary embodiments have been described herein, other embodiments and modifications will be apparent from the description herein. Therefore, the inventive concept is not limited to these embodiments, but is limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that are apparent to those of ordinary skill in the art.

Claims

1. A display device, wherein the display device comprises: substrate; a first layer disposed on the substrate, the first layer comprising a first portion having a first thickness and a second portion having a second thickness greater than the first thickness; a second layer disposed on the first layer; an active pattern disposed on the second layer, the active pattern overlapping only a first portion of the first layer; a gate electrode disposed on the active pattern; a source electrode and a drain electrode disposed on the gate electrode, the source electrode and the drain electrode being connected to the active pattern; a first electrode connected to one of the source electrode and the drain electrode; a pixel defining layer disposed on the first electrode, the pixel defining layer having an opening portion exposing at least a portion of the first electrode; a light emitting layer disposed in the opening portion on the first electrode; as well as A second electrode disposed on the light-emitting layer, wherein the second layer includes a third portion having a third thickness and a fourth portion having a fourth thickness less than the third thickness, The third portion of the second layer overlaps the first portion of the first layer, and the fourth portion of the second layer overlaps the second portion of the first layer.

2. The display device according to claim 1, wherein the first thickness is smaller than the third thickness. The display device according to claim 1 , wherein an upper surface of the second layer is planarized.

4. The display device of claim 1, wherein the active pattern does not overlap the second portion of the first layer.

5. The display device according to claim 1, wherein the first layer comprises a buffer layer, the buffer layer comprising silicon nitride.

6. The display device according to claim 1, wherein the second layer comprises a buffer layer, the buffer layer comprising silicon oxide. 7 . The display device according to claim 1 , wherein the first layer has a first hydrogen concentration and the second layer has a second hydrogen concentration, the first hydrogen concentration being greater than the second hydrogen concentration.

8. A method for manufacturing a display device, wherein the method comprises the steps of: forming a first layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness on a substrate; forming a second layer on the first layer; and forming a polysilicon pattern on the second layer that overlaps only the first portion of the first layer, wherein the second layer includes a third portion having a third thickness and a fourth portion having a fourth thickness less than the third thickness, The third portion of the second layer overlaps the first portion of the first layer, and the fourth portion of the second layer overlaps the second portion of the first layer.

Images