Display panel and display device

Abstract

The present invention is applicable to the field of display technology and provides a display panel and a display device, comprising a first substrate and a second substrate arranged opposite to each other; the first substrate comprises a first base layer; a main spacer and an auxiliary spacer; the second substrate comprises a second base layer, a dielectric layer, a raised portion arranged inside and / or on the surface of the dielectric layer, corresponding to the main spacer; and a gap portion opened in the dielectric layer, corresponding to the auxiliary spacer. The present invention sets a raised portion on the second base layer of the second substrate and opens a gap portion on the dielectric layer of the second substrate; the main spacer is opposite to the raised portion, and the auxiliary spacer is opposite to the gap portion and can extend into the gap portion. Due to the setting of the raised portion and the gap portion, the step difference of the panel is increased, and the increase amount is the sum of the thickness of the raised portion and the depth of the gap portion. The maximum increase that can be made is the sum of the thickness of the raised portion and the thickness of the dielectric layer, thereby effectively increasing the step difference, increasing liquid crystal redundancy, and improving panel quality.

Description

Technical Field

[0001] The present invention belongs to the field of display technology, and in particular relates to a display panel and a display device. Background Art

[0002] The liquid crystal display panel is mainly composed of a color filter (CF) substrate and a thin film transistor (TFT) array substrate, which are spaced a certain distance apart and sealed around the periphery. This structure formed by the two substrates in a box is also called a liquid crystal box, and the box is filled with liquid crystal material. Among them, the CF substrate is a key material for realizing the color display of the liquid crystal display, and it also affects the optical properties such as display brightness and contrast. The CF substrate mainly includes a glass substrate (GS), a black matrix (BM), a color resist (CR), ITO (Indium Tin Oxides, indium tin oxide) and a post spacer (PS). PS is used to maintain a stable gap between the TFT substrate and the CF substrate.

[0003] There are generally two types of PS within a liquid crystal cell: the main PS (MPS) that maintains the cell gap under normal circumstances, and the auxiliary PS (SPS) that provides support when the cell thickness decreases. Under abnormal circumstances, such as when the temperature is too high, the liquid crystal expands, reducing the support force of the MPS. As the liquid crystal expands, it can aggregate locally, causing gravitational mura (uneven brightness and spots). The amount of liquid crystal at the boundary where gravitational mura appears is defined as L1. When the temperature is too low, the liquid crystal shrinks, reducing the cell thickness. The SPS generates support, preventing the cell thickness from decreasing further. However, vacuum bubbles may still form in some local spaces due to the absence of liquid crystal. The amount of liquid crystal at the boundary where vacuum bubbles appear is defined as L2. The amount of liquid crystal between L1 and L2 is called the LC margin. Within this range, gravitational mura and vacuum bubbles will not appear. The larger the LC margin, the better, within a reasonable range.

[0004] As the cell gap decreases, the MPS and SPS successively contact the TFT substrate, creating a PS step. If the step is too small, the liquid crystal cannot fill the cell after shrinking, which can easily lead to vacuum bubbles and a small LC margin. A suitable step is essential for ensuring a sufficiently large LC margin and is also a key factor in improving LCD panel quality. Therefore, a new solution for increasing the step is needed to increase the LC margin. Summary of the Invention

[0005] An object of the present invention is to provide a display panel, aiming to solve the technical problem of a small LC margin of the display panel.

[0006] The present invention is implemented as follows: a display panel includes a first substrate and a second substrate arranged opposite to each other;

[0007] The first substrate includes:

[0008] First grassroots level;

[0009] a main spacer disposed on the first base layer; and

[0010] an auxiliary spacer, disposed on the first base layer;

[0011] The second substrate includes:

[0012] a second base layer, spaced apart from the first base layer;

[0013] a dielectric layer, disposed on a side of the second base layer close to the first base layer;

[0014] an elevated portion, disposed inside and / or on the surface of the dielectric layer, corresponding to the main spacer; and

[0015] The avoidance portion is formed in the dielectric layer, corresponds to the sub-spacer, and can be inserted into the sub-spacer.

[0016] In one embodiment, the raised portion includes a semiconductor layer, a metal layer, and a transparent conductive layer stacked sequentially from the first base layer to the second base layer.

[0017] In one embodiment, the dielectric layer includes a first protective layer and a second protective layer stacked on the second base layer;

[0018] The semiconductor layer and the metal layer are arranged between the first protective layer and the second protective layer;

[0019] The transparent conductive sheet layer is disposed on the surface of the second protective layer close to the first base layer;

[0020] The semiconductor layer and the metal layer push the corresponding portion of the second protective layer and the transparent conductive layer to abut against the main spacer.

[0021] In one embodiment, the second substrate further includes a driving circuit, the driving circuit including a first metal layer, a semiconductor active layer, a second metal layer, and a pixel electrode, the first metal layer being disposed between the second base layer and the first protective layer, the semiconductor active layer and the second metal layer being disposed between the first protective layer and the second protective layer, and the pixel electrode being disposed on a side of the second protective layer close to the first substrate;

[0022] The semiconductor layer and the semiconductor active layer are formed on the first protective layer at intervals in the same process;

[0023] The metal sheet layer and the second metal layer are formed at intervals in the same process, wherein the metal sheet layer is formed on the semiconductor sheet layer, and the second metal layer is formed on the semiconductor active layer;

[0024] The transparent conductive layer and the pixel electrode are formed on the second protective layer at intervals in the same process.

[0025] In one embodiment, the semiconductor layer and the semiconductor active layer have the same thickness; and / or

[0026] The metal sheet layer and the second metal layer have the same thickness; and / or

[0027] The transparent conductive layer and the pixel electrode have the same thickness.

[0028] In one embodiment, the thickness of the semiconductor layer is greater than the thickness of the semiconductor active layer; and / or

[0029] The thickness of the metal sheet layer is greater than the thickness of the second metal layer; and / or

[0030] The thickness of the transparent conductive layer is greater than the thickness of the pixel electrode.

[0031] In one embodiment, the second metal layer includes a data line, a source electrode and a drain electrode, and the distance between the metal layer and the data line is greater than 5 μm; the projection of the metal layer on the second base layer covers the projection of the semiconductor layer and the transparent conductive layer on the second base layer.

[0032] In one embodiment, the bottom area of ​​the gap portion is greater than or equal to the area of ​​the free end of the sub-spacer;

[0033] The air-avoiding portion extends from the surface of the second protective layer close to the first substrate to the interior of the second protective layer; or

[0034] The air-avoiding portion extends from the surface of the second protective layer close to the first substrate to the surface of the first protective layer; or

[0035] The air-avoiding portion extends from the surface of the second protective layer close to the first substrate to the interior of the first protective layer; or

[0036] The avoidance portion extends from a surface of the second protection layer close to the first substrate to the second base layer.

[0037] In one embodiment, the height of the main spacer is greater than or equal to the height of the sub-spacer.

[0038] Another object of the present invention is to provide a display device comprising a thin film transistor array substrate and a color filter substrate disposed opposite to each other;

[0039] The color filter substrate comprises:

[0040] First grassroots level;

[0041] a black matrix, disposed on the first base layer;

[0042] a color resist layer, disposed on the first base layer and the black matrix, comprising color resist blocks of at least three different colors, wherein the color resist blocks of different colors are separated by the black matrix;

[0043] a main spacer disposed on the black matrix; and

[0044] A sub-spacer, disposed on the black matrix;

[0045] The thin film transistor array substrate comprises:

[0046] a second base layer, spaced apart from the first base layer;

[0047] a first protective layer, disposed on a side of the second base layer close to the first base layer;

[0048] a second protective layer, disposed on a side of the first protective layer close to the first base layer;

[0049] A driving circuit is layered inside and on the surface of the first protective layer and the second protective layer;

[0050] a raised portion corresponding to the main spacer, comprising a semiconductor layer, a metal layer, and a transparent conductive layer, wherein the semiconductor layer and the metal layer are stacked between the first protective layer and the second protective layer, and the transparent conductive layer is disposed on a side of the second protective layer close to the first base layer; the orthographic projection of the raised portion on the first base layer covers the orthographic projection of the main spacer on the first base layer; and

[0051] The avoidance portion corresponds to the sub-spacer and is opened from the surface of the second protection layer toward the second base layer, allowing the sub-spacer to extend into.

[0052] The display panel and display device provided by the present invention are provided with a raised portion on the second base layer of the second substrate, and a gap portion is opened on the dielectric layer of the second substrate. The main spacer is opposite to the raised portion, and the auxiliary spacer is opposite to the gap portion and can extend into the gap portion. Due to the provision of the raised portion and the gap portion, the step difference of the panel is increased. The increase amount is the sum of the thickness of the raised portion and the depth of the gap portion. The maximum increase that can be made is the sum of the thickness of the raised portion and the thickness of the dielectric layer, thereby effectively increasing the step difference, increasing liquid crystal redundancy, and improving panel quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 is a first cross-sectional schematic diagram of a display panel provided by an embodiment of the present invention;

[0054] Figure 2 yes Figure 1 A partial cross-sectional schematic diagram of the display panel shown;

[0055] Figure 3 is a schematic planar structural diagram of a second substrate of a display panel provided by an embodiment of the present invention;

[0056] Figure 4 yes Figure 3 Schematic diagram of half of the structure in the middle A-direction section;

[0057] Figure 5 yes Figure 3 Schematic diagram of the other half of the structure in the middle A-direction section;

[0058] Figure 6 is a second cross-sectional schematic diagram of a display panel provided by an embodiment of the present invention;

[0059] Figure 7 This is a third cross-sectional schematic diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0061] It should be noted that when a component is referred to as being "fixed on" or "disposed on" another component, it may be directly or indirectly located on the other component. When a component is referred to as being "connected to" another component, it may be directly or indirectly connected to the other component. The directions or positions indicated by the terms "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are based on the directions or positions shown in the accompanying drawings and are only for the convenience of description and cannot be understood as limitations on this technical solution. The terms "first" and "second" are only used for the purpose of convenience of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. "Multiple" means two or more, unless otherwise clearly and specifically defined.

[0062] In order to illustrate the technical solution of the present invention, the following is a detailed description with reference to specific drawings and embodiments.

[0063] See also Figure 1 and Figure 2 The display panel provided by the embodiment of the present invention includes a first substrate 1 and a second substrate 2 arranged opposite to each other; the first substrate 1 and the second substrate 2 are assembled and edge-sealed to form a display panel. It can be understood that for a liquid crystal display panel, liquid crystal material is poured between the first substrate 1 and the second substrate 2. The first substrate 1 mainly includes a first base layer 11, a main spacer 12 and an auxiliary spacer 13 arranged on the first base layer 11. The main spacer 12 and the auxiliary spacer 13 are used to support the gap of the liquid crystal cell. Of course, the first substrate 1 also includes other functional structures to cooperate with the second substrate 2 to achieve the display function. The second substrate 2 includes a second base layer 21 and a dielectric layer 22 arranged on the side of the second base layer 21 close to the first base layer 11. The second base layer 21 serves as the main supporting structure of the second substrate 2 and is used to carry other functional devices and circuits. The second base layer 21 is arranged relative to the first base layer 11 to form a space for accommodating liquid crystal material. The second substrate 2 also includes a raised portion 23, which is arranged inside the dielectric layer 22, or on the surface of the dielectric layer 22, or in layers inside and on the surface of the dielectric layer 22. The raised portion 23 corresponds to the main spacer 12, and can specifically be directly opposite along the vertical direction of the first base layer 11 and the second base layer 21. The second substrate 2 also includes a gap 24, which is opened in the dielectric layer 22 and corresponds to the auxiliary spacer 13. Specifically, it can be directly opposite along the vertical direction of the first base layer 11 and the second base layer 21. The gap 24 can allow the auxiliary spacer 13 to extend into. Of course, the second substrate 2 also includes other functional structures arranged on the second base layer 21 to cooperate with the first substrate 1 to realize the display function. In the natural state, the main spacer 12 and the portion corresponding to the raised portion 23 are against each other. In low temperature conditions, the liquid crystal contracts, and the auxiliary spacer 13 extends into the gap 24 and abuts against the bottom of the gap 24.

[0064] In this display panel, based on the arrangement of the raised portion and the avoidance portion, the step difference L = D0 + D + H, where D0 is the height difference between the main spacer 12 and the auxiliary spacer 13, and the height difference refers to the vertical distance between the free ends of the main spacer 12 and the auxiliary spacer 13. D is the thickness of the raised portion, and H is the depth of the avoidance portion 24. The avoidance portion 24 is provided in the dielectric layer 22, and the depth H is greater than 0 and less than or equal to the thickness D4 of the dielectric layer 22. Therefore, the step difference L is greater than D0 + D and less than or equal to D0 + D + D4. When the depth of the avoidance portion 24 is equal to the thickness of the dielectric layer 22, the step difference is maximum.

[0065] In the display panel provided by the embodiment of the present invention, a raised portion 23 is provided on the second base layer 21 of the second substrate 2, and a gap portion 24 is provided on the dielectric layer 22 of the second substrate 2. The main spacer 12 is opposite to the raised portion 23, and the auxiliary spacer 13 is opposite to the gap portion 24 and can extend into the gap portion. Due to the provision of the raised portion 23 and the gap portion 24, the step difference of the panel is increased. The increase amount is the sum of the thickness of the raised portion 23 and the depth of the gap portion 24. The maximum increase that can be made is the sum of the thickness of the raised portion 23 and the thickness of the dielectric layer 22, thereby effectively increasing the step difference, increasing liquid crystal redundancy, and improving panel quality.

[0066] See Figure 1 In this embodiment, the first substrate 1 may be, but is not limited to, a color filter substrate, and the second substrate 2 may be, but is not limited to, a thin film transistor array substrate. When the first substrate 1 is a color filter substrate, the first substrate 1 further includes a black matrix 14 and may further include a color resist layer 15, wherein the black matrix 14 is arranged on the side of the first base layer 11 facing the second base layer 21, and the color resist layer 15 is arranged on the side of the first base layer 11 and the black matrix 14 facing the second base layer 21. The color resist layer 15 includes at least three color resist blocks of different colors, such as red, green, and blue blocks, or red, green, blue, and white blocks, etc. The black matrix 14 is in a grid shape, and its horizontal and vertical lines intersect to define multiple sub-regions, each sub-region corresponds to a sub-pixel, and each color resist block corresponds to a sub-region. Optionally, the main spacer 12 and the auxiliary spacer 13 can be arranged on the black matrix 14, or can be arranged on the color resist block in the area corresponding to the black matrix 14. Correspondingly, the second substrate 2 is a thin film transistor array substrate. The second substrate 2 further includes a driving circuit. The driving circuit is provided based on the second base layer 21 and is protected by the dielectric layer 22 .

[0067] refer to Figure 2As one implementation of the raised portion 23, the raised portion 23 includes a semiconductor layer 231, a metal layer 232, and a transparent conductive layer 233 stacked sequentially from the first base layer 11 to the second base layer 21. Because the raised portion 23 is located on the opposite side of the main spacer 12, the top of the main spacer 12 faces the raised portion 23, and the auxiliary spacer 13 faces the gap 24, resulting in a step height L = D0 + D1 + D2 + D3 + H, where D1 is the thickness of the semiconductor layer 231, D2 is the thickness of the metal layer 232, and D3 is the thickness of the transparent conductive layer 233. D1 + D2 + D3 = D.

[0068] Based on the structure of the raised portion 23, the second substrate 2 can be a thin film transistor array substrate, which can be optimized in terms of process. Figures 3 to 5 A driving circuit is provided on the second base layer 21. The driving circuit includes a first metal layer 211, a semiconductor active layer 212, a second metal layer 213, and a pixel electrode 214. During the five steps of manufacturing the thin-film transistor array substrate, the first metal layer 211, the first protective layer 221, the semiconductor active layer 212, the second metal layer 213, the second protective layer 222, and the pixel electrode 214 are formed. The first protective layer 221 and the second protective layer 222 constitute the dielectric layer 22. The first metal layer 211 is disposed between the second base layer 21 and the first protective layer 221, the semiconductor active layer 212 and the second metal layer 213 are disposed between the first protective layer 221 and the second protective layer 222, and the pixel electrode 214 is disposed on the side of the second protective layer 222 closest to the first substrate 1. The first metal layer 211 typically includes a scan line 2111 and a gate 2112. The first protective layer 221 is used to protect the first metal layer 211. The semiconductor active layer 212 is disposed at a corresponding position on the first protective layer 221, corresponding to the gate 2112. The second metal layer 213 is formed on the semiconductor active layer 212 and the first protective layer 221, and includes a source and a drain electrode overlapped above the semiconductor active layer 212. It also includes a data line 2131 laid on the first protective layer 221. The data line 2131 intersects with the scan line 2111 in a direction perpendicular to the first base layer 11. The data line 2131 is connected to the source or drain electrode to provide display signals, that is, to provide voltage signals for achieving liquid crystal deflection. The second protective layer 222 is formed on the second metal layer 213 to protect the second metal layer 213 and also supports the pixel electrode 214. The pixel electrode 214 is connected to the source or drain of the second metal layer 213 through a conductive via.

[0069] The first protective layer 221 and the second protective layer 222 can be formed sequentially from the same or different insulating materials through a film forming process. The insulating material can be a transparent organic material or inorganic material (e.g., SiNx) with good thermal conductivity. In addition, the thickness of the first protective layer 221 and the second protective layer 222 can be the same or different, and this embodiment is not strictly limited.

[0070] Correspondingly, the raised portion 23 can be formed simultaneously in the five steps, referring to Figure 4 and Figure 5 During the manufacturing process of the semiconductor active layer 212, a semiconductor layer 231 is simultaneously formed at corresponding locations on the first protective layer 221. During the manufacturing process of the second metal layer 213, a metal layer 232 is simultaneously formed on the semiconductor layer 231. During the manufacturing process of the pixel electrode 214, a transparent conductive layer 233 is simultaneously formed at corresponding locations on the second protective layer 222. After the semiconductor layer 231 and the metal layer 232 are formed, the second protective layer 222 naturally rises at locations corresponding to the semiconductor layer 231 and the metal layer 232, forming a convex portion. During the manufacturing process of the pixel electrode 214, the transparent conductive layer 233 is formed precisely on this convex portion. The semiconductor layer 231 and the metal layer 232 push the corresponding portions of the second protective layer 222 and the transparent conductive layer 233 against the main spacer 12.

[0071] To further simplify the manufacturing process during the five steps described above, the semiconductor layer 231 and the semiconductor active layer 212 can have the same thickness; the metal layer 232 and the second metal layer 213 can have the same thickness; and the transparent conductive layer 233 and the pixel electrode 214 can have the same thickness. This eliminates the need for etching the same material to different degrees, which improves efficiency.

[0072] In another embodiment, in order to further increase the step difference, the thickness of the semiconductor layer 231 can be greater than the thickness of the semiconductor active layer 212; the thickness of the metal layer 232 can be greater than the thickness of the second metal layer 213; and the thickness of the transparent conductive layer 233 can be greater than the thickness of the pixel electrode 214. In this way, the step difference can be increased as much as possible, the liquid crystal redundancy can be improved, and the quality of the display panel and the liquid crystal display can be improved.

[0073] In another embodiment, the thickness of one or two of the semiconductor layer 231, the metal layer 232, and the transparent conductive layer 233 may be made the same as the thickness of the corresponding layer structure, which may be set according to the operational difficulty of the actual process.

[0074] In one embodiment, during the manufacturing process of the second metal layer 213, data lines 2131, source and drain electrodes, and a metal sheet layer 232 are formed. An insulating space is required between the metal sheet layer 232 and the data lines 2131, with the spacing greater than 5 μm. Furthermore, during the manufacturing process of the semiconductor active layer 212, the spacing between the formed semiconductor sheet layer 231 and the pre-formed data lines 2131 is greater than 5 μm. This ensures that insulation requirements are met while process errors are controllable. Similarly, during the manufacturing process of the pixel electrode 214, the distance between the transparent conductive sheet layer 233 and the pixel electrode 214 is greater than 5 μm.

[0075] In one embodiment, the metal sheet layer 232, the semiconductor sheet layer 231, and the transparent conductive sheet layer 233 are all block-shaped structures, which may be polygonal, circular, elliptical, or the like, and their areas are equal to or slightly larger than the cross-sectional area of ​​the main spacer 12 or the area of ​​the free end of the main spacer 12. The metal sheet layer 232 is larger than the semiconductor sheet layer 231 and the transparent conductive sheet layer 233, i.e., the projection of the metal sheet layer 232 on the second base layer 21 covers the projections of the semiconductor sheet layer 231 and the transparent conductive sheet layer 233 on the second base layer 21. Alternatively, the metal sheet layer 232 and the semiconductor sheet layer 231 may be of the same size, both larger than the transparent conductive sheet layer 233, although this embodiment is not strictly limited thereto.

[0076] refer to Figure 3 and Figure 5 In the five steps of the array substrate manufacturing process, the avoidance portion 24 is formed during the manufacturing process of the second protective layer 222. During this process, a via hole is required to be opened in the second protective layer 222 to connect the pixel electrode 214 and the source or drain. At the same time, a groove can be formed in the second protective layer 222 at the location corresponding to the subspacer 13 to form the avoidance portion 24. Optionally, the depth of the avoidance portion 24 can be the same as, less than, or greater than the depth of the via hole. The bottom area of ​​the avoidance portion 24 is greater than or equal to the area of ​​the free end of the subspacer 13, so that the subspacer 13 can touch the bottom of the avoidance portion 24.

[0077] As a first structure of the avoidance portion 24 , the avoidance portion 24 extends from the surface of the second protection layer 222 close to the first substrate 1 to the interior of the second protection layer 222 , and the depth H is less than the thickness D42 of the second protection layer 222 .

[0078] As the second structure of the air-avoiding portion 24, refer to Figure 6 The avoidance portion 24 extends from the surface of the second protection layer 222 close to the first substrate 1 to the surface of the first protection layer 221 , and the depth H is equal to the thickness D42 of the second protection layer 222 .

[0079] As a third structure of the air-avoiding portion 24, refer to Figure 7The avoidance portion 24 extends from the surface of the second protective layer 222 close to the first substrate 1 to the inside of the first protective layer 221 ; the depth H is greater than the thickness D42 of the second protective layer 222 and less than the total thickness D4 of the dielectric layer 22 .

[0080] As a fourth structure of the space-avoiding portion 24, refer to Figure 1 The avoidance portion 24 extends from the surface of the second protection layer 222 close to the first substrate 1 to the second base layer 21 , and the depth H is equal to the total thickness D4 of the dielectric layer 22 .

[0081] Among the structures of the above-mentioned space-avoiding portion 24, the fourth structure may be selected to make the step difference larger.

[0082] In one embodiment, the height of the main spacer 12 is equal to the height of the auxiliary spacer 13. Due to the aforementioned step difference L = D0 + D1 + D2 + D3 + H, when the height of the main spacer 12 is equal to the height of the auxiliary spacer 13, D0 is zero, and L = D1 + D2 + D3 + H, which still has a large step difference value. This can reduce the complexity and difficulty of the spacer manufacturing process. A mask with the same transmittance at all locations can be used to produce main spacers 12 and auxiliary spacers 13 with consistent heights. This is easier to implement in terms of process, easily ensuring that the height of the main and auxiliary spacers 13 is consistent, and avoiding the use of a complex mask structure, which avoids the problem of poor height consistency of spacers of different heights.

[0083] In another embodiment, the height of the main spacer 12 is greater than the height of the auxiliary spacer 13. When the height of the raised portion 23 is constant, the height of the auxiliary spacer 13 is less than the height of the main spacer 12, which can make the distance between the free end of the auxiliary spacer 13 and the bottom of the air-avoidance portion 24 larger, thereby increasing the step difference. Spacers of different heights can be formed at one time through a special mask. For example, structures with different ultraviolet transmittances are set on the mask corresponding to the positions of the main spacer 12 and the auxiliary spacer 13, so that the etching depth of the spacer material is different, forming spacers of different heights. Specifically, a grayscale mask (GTM), a slit mask (SSM) or a semi-transparent membrane mask (HTM) can be used to reduce the local ultraviolet transmittance and etch away a predetermined thickness of the spacer material according to the predetermined height of the main spacer 12 and the auxiliary spacer 13 to form a main spacer 12 and an auxiliary spacer 13 of a predetermined height.

[0084] In this embodiment, it is understood that while the step difference is preferably as large as possible within a certain range, it is not suitable for unlimited increase. The deformation of the second base layer 21 and the first base layer 11 has a certain critical value, that is, the variation space of the liquid crystal cell thickness has a certain limit. When the liquid crystal molecules shrink to a certain extent, the second base layer 21 and the first base layer 11 reach their maximum deformation and cannot be further compressed. At this time, as the liquid crystal molecules further shrink, vacuum bubbles may appear. In this case, if the auxiliary spacer 13 still does not contact the bottom of the airtight portion 24, it cannot play the role of supporting the cell thickness, and thus the auxiliary spacer 13 loses its function. Generally, the step difference can range from 0.4-0.8mm.

[0085] In this embodiment, the black matrix 14 on the second base layer 21 defines a plurality of sub-pixel regions, and the main spacers 12 and the auxiliary spacers 13 can be disposed in different sub-pixel regions. For example, the main spacer 12 is disposed in the red sub-pixel region, and the auxiliary spacer 13 is disposed in the green sub-pixel region or the blue sub-pixel region; or, the main spacer 12 is disposed in the green sub-pixel region, and the auxiliary spacer 13 is disposed in the red sub-pixel region or the blue sub-pixel region; or, the main spacer 12 is disposed in the blue sub-pixel region, and the auxiliary spacer 13 is disposed in the red sub-pixel region.

[0086] In this embodiment, the black matrix 14 is arranged corresponding to the positions of the scan line 2111, the data line 2131 and the thin film transistor device. The gate 2112 and the source and drain of the thin film transistor device are arranged close to the scan line 2111, and the gate 2112 is connected to the scan line 2111.

[0087] refer to Figure 3 On the second base layer 21, the raised portion 23 is located in the area covered by the black matrix 14 and is located on the same side of the scan line 2111 as the gate 2112. Its position relative to the scan line 2111 is the same as or similar to the position of the gate 2112 relative to the scan line 2111. At the same time, it maintains a certain relative distance from the data line 2131 to prevent conduction. Setting the raised portion 23 here is easy to implement in terms of process and does not affect the pixel aperture ratio. Similarly, the avoidance portion 24 is located in the area covered by the black matrix 14 and is located on the same side of the scan line 2111 as the gate 2112. Its position relative to the scan line 2111 is the same as or similar to the position of the gate 2112 relative to the scan line 2111. The raised portion 23 and the avoidance portion 24 are respectively arranged in different sub-pixel areas.

[0088] In one embodiment, to achieve deflection and regular alignment of the liquid crystal molecules, a first common electrode 16 and a first alignment film are sequentially disposed on the color resist layer 15 of the first substrate 1, and a second alignment film is disposed on the pixel electrode 214 of the second substrate 2. The first common electrode 16 and the pixel electrode 214 form an inter-electrode capacitance. The first alignment film and the second alignment film are used to control the orientation of the liquid crystal molecules in a natural state.

[0089] In one embodiment, reference Figure 3 The second substrate 2 further includes a second common electrode 2113 , which is formed during the manufacturing process of the first metal layer 211 and is used to form a storage capacitor with the pixel electrode 214 .

[0090] In one embodiment, the main spacer 12 and the auxiliary spacer 13 may be truncated cone-shaped structures, with a larger diameter at the end connected to the first base layer 11 and a smaller diameter at the free end. The main spacer 12 and the auxiliary spacer 13 may also be cylindrical with the same diameter. In other embodiments, the main spacer 12 and the auxiliary spacer 13 may also be truncated cone-shaped or prism-shaped.

[0091] The display panel provided in the embodiment of the present invention is mainly used for liquid crystal displays, and liquid crystal displays including the display panel are also within the scope of protection of the present invention. The liquid crystal display also includes a backlight module for providing illumination, and the backlight module can be an edge-type backlight module or a direct-type backlight module.

[0092] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: comprising a first substrate and a second substrate arranged opposite to each other; The first substrate includes: First grassroots level; a main spacer disposed on the first base layer; and A subspacer is provided on the first base layer; there is a height difference between the main spacer and the subspacer, the height of the subspacer is smaller than the height of the main spacer, and the range of the height difference is 0.4-0.8 mm; The second substrate includes: a second base layer, spaced apart from the first base layer; a dielectric layer, disposed on a side of the second base layer close to the first base layer; an elevated portion, disposed inside and / or on the surface of the dielectric layer, corresponding to the main spacer; and a space-avoiding portion, formed in the dielectric layer and corresponding to the sub-spacer, into which the sub-spacer can extend; The raised portion includes a semiconductor layer, a metal layer, and a transparent conductive layer stacked in sequence from the first base layer to the second base layer; The dielectric layer includes a first protective layer and a second protective layer stacked on the second base layer; The semiconductor layer and the metal layer are arranged between the first protective layer and the second protective layer; The transparent conductive sheet layer is disposed on the surface of the second protective layer close to the first base layer; The semiconductor layer and the metal layer push the corresponding portion of the second protective layer and the transparent conductive layer to abut against the main spacer; The second substrate further includes a driving circuit, the driving circuit including a first metal layer, a semiconductor active layer, a second metal layer, and a pixel electrode, the first metal layer being disposed between the second base layer and the first protective layer, the semiconductor active layer and the second metal layer being disposed between the first protective layer and the second protective layer, and the pixel electrode being disposed on a side of the second protective layer close to the first substrate; The semiconductor layer and the semiconductor active layer are formed on the first protective layer at intervals in the same process; The metal sheet layer and the second metal layer are formed at intervals in the same process, wherein the metal sheet layer is formed on the semiconductor sheet layer, and the second metal layer is formed on the semiconductor active layer; The transparent conductive layer and the pixel electrode are formed on the second protective layer at intervals in the same process; The avoidance portion extends from a surface of the second protection layer close to the first substrate to the second base layer.

2. The display panel according to claim 1, wherein The semiconductor layer and the semiconductor active layer have the same thickness; and / or The metal sheet layer and the second metal layer have the same thickness; and / or The transparent conductive layer and the pixel electrode have the same thickness.

3. The display panel according to claim 1, wherein The thickness of the semiconductor layer is greater than the thickness of the semiconductor active layer; and / or The thickness of the metal sheet layer is greater than the thickness of the second metal layer; and / or The thickness of the transparent conductive layer is greater than the thickness of the pixel electrode.

4. The display panel according to claim 1, wherein: The second metal layer includes a data line, a source electrode and a drain electrode, and the distance between the metal layer and the data line is greater than 5μm; the projection of the metal layer on the second base layer covers the projection of the semiconductor layer and the transparent conductive layer on the second base layer.

5. The display panel according to claim 1, wherein The bottom area of ​​the space-avoiding portion is greater than or equal to the area of ​​the free end of the sub-spacer.

6. A display panel, characterized in that: It comprises a first substrate and a second substrate arranged opposite to each other; wherein the first substrate is a thin film transistor array substrate, and the second substrate is a color filter substrate; The color filter substrate comprises: First grassroots level; a black matrix, disposed on the first base layer; a color resist layer, disposed on the first base layer and the black matrix, comprising color resist blocks of at least three different colors, wherein the color resist blocks of different colors are separated by the black matrix; a main spacer disposed on the black matrix; and A subspacer is provided on the black matrix; there is a height difference between the main spacer and the subspacer, the height of the subspacer is smaller than the height of the main spacer, and the range of the height difference is 0.4-0.8 mm; The thin film transistor array substrate comprises: a second base layer, spaced apart from the first base layer; a first protective layer, disposed on a side of the second base layer close to the first base layer; a second protective layer, disposed on a side of the first protective layer close to the first base layer; A driving circuit is layered inside and on the surface of the first protective layer and the second protective layer; a raised portion corresponding to the main spacer, comprising a semiconductor layer, a metal layer, and a transparent conductive layer, wherein the semiconductor layer and the metal layer are stacked between the first protective layer and the second protective layer, and the transparent conductive layer is disposed on a side of the second protective layer close to the first base layer; the orthographic projection of the raised portion on the first base layer covers the orthographic projection of the main spacer on the first base layer; and a gap portion, corresponding to the sub-spacer, opened from the surface of the second protective layer toward the second base layer, and allowing the sub-spacer to extend into; The second substrate further includes a driving circuit, the driving circuit including a first metal layer, a semiconductor active layer, a second metal layer, and a pixel electrode, the first metal layer being disposed between the second base layer and the first protective layer, the semiconductor active layer and the second metal layer being disposed between the first protective layer and the second protective layer, and the pixel electrode being disposed on a side of the second protective layer close to the first substrate; The semiconductor layer and the semiconductor active layer are formed on the first protective layer at intervals in the same process; The metal sheet layer and the second metal layer are formed at intervals in the same process, wherein the metal sheet layer is formed on the semiconductor sheet layer, and the second metal layer is formed on the semiconductor active layer; The transparent conductive layer and the pixel electrode are formed on the second protective layer at intervals in the same process; The avoidance portion extends from a surface of the second protection layer close to the first substrate to the second base layer.

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