Apparatus and method for initializing a channel in a non-volatile memory device

Abstract

A method for initializing a channel in a non-volatile memory device including memory blocks, the memory blocks including multiple word lines and multiple string select lines, the method including applying a voltage to the multiple string select lines; converting bit lines passing through the block into a floating state; and releasing the floating state of the bit lines.

Description

[0001] Cross - reference to related applications

[0002] This non - provisional patent application claims priority to Korean Patent Application No. 10 - 2018 - 0137949, filed on November 12, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to an apparatus and method for initializing channels in a memory device, and more particularly, to an apparatus and method for initializing channels in a non - volatile memory device capable of reducing power consumption. Background Art

[0004] Discussion of related art

[0005] NAND flash is a type of non - volatile memory that does not require power to retain data. 3D NAND flash consists of multiple layers of NAND flash stacked on top of each other. Compared to NAND flash arranged in a planar structure, this 3D NAND flash has significantly improved performance in terms of integration density, storage capacity, speed, durability, and power consumption.

[0006] Each layer includes strings and string selection lines, where each string includes memory cells connected between a string selection transistor and a ground selection transistor. The memory cells can be organized in an array of rows and columns, where word lines connect the rows and bit lines connect the columns.

[0007] When performing a read or write verification operation in a non - volatile memory device, when the selected and unselected string selection lines are initialized, power may be unnecessarily consumed due to the influence of parasitic capacitance present in the word lines. Summary of the Invention

[0008] At least one exemplary embodiment of the present inventive concept provides an apparatus and method for initializing channels in a non - volatile memory device, capable of reducing power consumption by controlling bit lines when initializing selected and unselected string selection lines during a read operation or a write verification operation.

[0009] According to an exemplary embodiment of the present inventive concept, a method for initializing channels in a non - volatile memory device having a memory block including a plurality of word lines and a plurality of string selection lines includes: applying a voltage to the plurality of string selection lines; converting bit lines passing through the memory block into a floating state; and releasing the floating state of the bit lines.

[0010] According to an exemplary embodiment of the inventive concept, a method for initializing a channel in a nonvolatile memory device having a memory block including a plurality of word lines and a plurality of string select lines includes: converting bit lines passing through the memory block into a floating state; applying a voltage to the plurality of string select lines; and releasing the floating state of the bit lines.

[0011] According to an exemplary embodiment of the inventive concept, an apparatus for initializing a channel in a nonvolatile memory device having a memory block including a plurality of word lines and a plurality of string select lines includes: a voltage generator that applies a voltage to the plurality of string select lines; a first circuit that converts bit lines passing through the memory block into a floating state; and a second circuit that releases the floating state of the bit lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a schematic diagram showing a case of initializing channels of selected / unselected strings with a voltage applied from bit lines by turning on all string select lines in a block;

[0014] Figure 2 is a schematic diagram showing in Figure 1 the operation of an exemplary change in voltage appearing in each element in a block;

[0015] Figure 3 is a schematic diagram showing a case of initialization by turning off unselected string select lines in a block;

[0016] Figure 4 is a schematic diagram showing in Figure 1 the operation of an exemplary soft erase phenomenon that may occur;

[0017] Figure 5 is a flowchart showing a method for initializing a channel in a nonvolatile memory device according to an exemplary embodiment of the inventive concept;

[0018] Figure 6 is a flowchart showing a method for initializing a channel in a nonvolatile memory device according to an exemplary embodiment of the inventive concept;

[0019] Figure 7 is a graph showing a change in voltage appearing in each element in a block according to a method for initializing a channel in a nonvolatile memory device according to an exemplary embodiment based on the inventive concept;

[0020] Figure 8is a graph showing changes in voltages occurring in each element of a block in a method for initializing a channel in a non-volatile memory device according to an exemplary embodiment based on the inventive concept;

[0021] Figure 9 is a graph showing a state before a floating state in a method for initializing a channel in a non-volatile memory device according to an exemplary embodiment of the inventive concept;

[0022] Figure 10 is a graph showing a time point for controlling conversion into a floating state in a method for initializing a channel in a non-volatile memory device according to an exemplary embodiment of the inventive concept;

[0023] Figure 11 and Figure 12 is a graph showing a time point for controlling conversion into a floating state and a time point for releasing (e.g., exiting) the floating state in a method for initializing a channel in a non-volatile memory device according to an exemplary embodiment of the inventive concept;

[0024] Figure 13 is a flowchart showing a method for initializing a channel in a non-volatile memory device according to an exemplary embodiment of the inventive concept; and

[0025] Figure 14 is a block diagram showing a device for initializing a channel in a non-volatile memory device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0026] Details of other embodiments may be included in the detailed description and the drawings.

[0027] With reference to the exemplary embodiments described in detail below with reference to the accompanying drawings, the inventive concept and the manner of implementing its features will become apparent. However, the inventive concept may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. These embodiments are provided to make the disclosure thorough and complete, and to convey the scope of the invention to those skilled in the art. Throughout the specification, the same reference numerals refer to the same elements.

[0028] A semiconductor memory (e.g., a non-volatile memory device) that may be used in an embodiment of the inventive concept includes a memory cell array including a plurality of memory blocks. The memory cell array may be connected to an address decoder through word lines, string selection lines, and ground selection lines, and connected to a read / write circuit through bit lines. Each memory block may include a plurality of memory cells and a plurality of select transistors. The memory cells of each memory block may be stacked in a direction perpendicular to the substrate to form a 3D structure.

[0029] The address decoder can be connected to the memory cell array through word lines, string select lines, and ground select lines. The address decoder can receive an address from an external device, decode a row address from the received address, and select word lines, string select lines, and ground select lines based on the decoded row address. The address decoder can transfer a voltage from the external device to the selected and unselected string select lines, word lines, and ground select lines.

[0030] The read / write circuit can be connected to the memory cell array through bit lines. The read / write circuit can receive a decoded column address from the address decoder and select some of the bit lines using the decoded column address. The read / write circuit can receive data from an external device and write the received data into the memory cell array.

[0031] In an exemplary embodiment, each of the memory blocks includes a plurality of cell strings. For example, a first group of cell strings can be arranged spaced apart from each other in a vertical direction to form a first column of cell strings, and a second group of cell strings can be arranged spaced apart from each other in a vertical direction to form a second column of cell strings, where the first column and the second column are spaced apart from each other. There can be additional columns of cell strings near the first column and the second column, but for the sake of discussion, only two columns are discussed here.

[0032] Each cell string of the first column of cell strings can include a ground select transistor, a plurality of memory cells, and a string select transistor stacked in a height direction perpendicular to the substrate. Similarly, each cell string of the second column of cell strings can include a ground select transistor, a plurality of memory cells, and a string select transistor stacked in a height direction perpendicular to the substrate.

[0033] The first one of the cell strings of the first column of cell strings can be connected to the first one of the cell strings of the second column of cell strings through a first string select line to form a first row, the second one of the cell strings of the first column of cell strings can be connected to the second one of the cell strings of the second column of cell strings through a second string select line to form a second row, and so on.

[0034] For example, the select transistors in the first cell string of the first column of cell strings and the first cell string of the second column of cell strings can be commonly connected to the first string select line, the select transistors in the second cell string of the first column of cell strings and the second cell string of the second column of cell strings can be commonly connected to the second string select line, and so on. The first column of cell strings can be connected to a first bit line, the second column of cell strings can be connected to a second bit line, and so on.

[0035] Memory cells at the same height from the substrate can be commonly connected to the same word line, and memory cells at different heights can be connected to different word lines. The ground select transistors of the cell strings can be commonly connected to a common source line. The 3D NAND flash memory structure can be constituted by the above-mentioned memory blocks.

[0036] Figure 1 It is a schematic diagram showing the case where all the string selection lines in a conduction block (e.g., one block in a memory block) are turned on, and the channels of the selected / unselected strings (e.g., one of the above-mentioned unit strings) are initialized with the voltage applied from the bit line. Figure 1 It shows a single bit line BL, string selection lines SSL0, SSL1, SSL2, SSL3, SSL4, SSL5, SSL6, and SSL7, virtual word lines DumWL, word lines WL0, WL1, …, WL94, WL95, WL96, …, WL190, and WL191, ground selection lines GSL0, GSL1, GSL3, and GSL3, and a common source line CSL. Although Figure 1 It shows 8 string selection lines SSL, 192 word lines WL, and 4 ground selection lines GSL, but the inventive concept is not limited thereto. For example, there may be fewer or more than 8 string selection lines SSL, fewer or more than 192 word lines WL, and fewer or more than 4 ground selection lines GSL. In addition, the virtual word line DumWL may be omitted.

[0037] Figure 2 It is a graph showing the change in voltage in each element in the block during the operation of Figure 1 Figure 3 It is a schematic diagram showing the case of initialization by disconnecting the unselected string selection lines in the block. For example, Figure 3 It shows the schematic diagram of Figure 1 but further shows that the unselected string selection lines SSL2 - SSL7 in area A of the block are disconnected during initialization. Figure 4 It is a schematic diagram showing an exemplary soft erasure phenomenon that may occur during the operation of Figure 1

[0038] Each of the memory blocks in the 3D NAND flash memory can be divided into a plurality of sub - blocks. Some of the string selection lines can be used to select a given one of the sub - blocks. When applying a read operation and / or a write verification operation to the 3D NAND flash memory using multiple string selection lines SSL, a process of initializing each string (e.g., each unit string) can be performed. However, due to the parasitic capacitance existing on one or more word lines of the semiconductor memory, power may be consumed unnecessarily.

[0039] For example, as Figure 1 and Figure 2As shown, when applying a method of turning on all string selection lines existing in a memory block, initializing channels of selected and unselected strings with a voltage applied from a bit line, and simultaneously applying a voltage to word lines, it may increase the voltage difference between channels to be initialized and word lines, such that it may increase the consumption of charges causing parasitic capacitance existing in the word lines.

[0040] When, as Figure 2 shown in the second graph, 0V is applied to the bit line BL, and as Figure 2 shown in the first graph, a voltage is also applied to the word line WL, in the state where all string selection lines shown in Figure 1 are turned on, a relatively large potential difference may occur between the word line WL having a relatively high voltage value and the bit line BL to which 0V is applied. During the initialization of this method, there may be a case where parasitic capacitances existing on all string selection lines need to be charged, such that power consumption inevitably increases.

[0041] As Figure 3 shown, when reducing the amount of consumed charges by blocking the connection between the bit line BL and channels of unselected string selection lines by turning off unselected string selection lines in region A, due to the influence of the set word line WL voltage, there may be a problem that unselected cells are programmed to an unexpected value by boosting channels of unselected strings. For example, as Figure 4 shown, when a negative voltage is applied to the selected word line WL3, a degradation phenomenon, i.e., soft erase due to the potential difference with the boosting channel, may occur. In the example shown in Figure 4 , the string selection line SSL and the gate selection line GSL output a ground voltage GND, a high voltage HV is applied to the dummy word lines DUM0 and DUM1, a read voltage is applied to the word lines WL0, WL2, and WL4, and the word line WL3 outputs a negative voltage –XXV.

[0042] Accordingly, at least one embodiment of the inventive concept provides a method for initializing channels in a non-volatile memory device, which can solve the power consumption problem of the initialization methods shown in Figure 1 and Figure 2 without causing the problem of degradation phenomena of the initialization methods shown in Figure 3 and Figure 4 .

[0043] Figure 5 is a flowchart showing a method for initializing channels in a non-volatile memory device according to an exemplary embodiment of the inventive concept; Figure 6 is a flowchart showing a method for initializing channels in a non-volatile memory device according to an exemplary embodiment of the inventive concept; Figure 7is a graph showing changes in voltages that occur in each element in a block, of a method for initializing a channel in a non-volatile memory device according to an exemplary embodiment based on the inventive concept; and Figure 13 is a flowchart showing a method for initializing a channel in a non-volatile memory device according to an exemplary embodiment of the inventive concept.

[0044] According to an exemplary embodiment of the inventive concept, a method for initializing a channel in a non-volatile memory device including a plurality of word lines and a plurality of string select lines in a memory block, includes: applying a voltage to the plurality of string select lines included in the memory block (S100); converting bit lines passing through the block into a floating state (S200); and releasing the floating state of the bit lines (S300), as Figure 5 shown. For example, when reading a given memory cell, the value of the bit line may become a first voltage indicating that the memory cell is 0 or a second different voltage indicating that the memory cell is 1. When the bit line has a floating voltage between the first voltage and the second voltage, the bit line may be referred to as being in a floating state.

[0045] In addition, as Figure 6 shown, in a method for initializing a channel in a non-volatile memory device according to an exemplary embodiment of the inventive concept, the release of the floating state of the bit lines (S300) is performed after a step (S250) of starting to remove the voltage applied to unselected string select lines among the plurality of string select lines. In addition, in Figure 6 the release of the floating state of the bit lines (S300) is completed before a step (S350) of applying a voltage required for sensing to the bit lines. For example, sensing may be a read of a memory cell connected to the bit line.

[0046] In a method for initializing a channel in a non-volatile memory device according to an exemplary embodiment of the inventive concept, by floating bit lines BL in a manner different from a method of initializing a channel by applying 0V or any other arbitrary voltage during an on-period of multiple string selection lines or all string selection lines included in a memory block, a voltage difference between a word line and a channel can be reduced, thereby reducing a charge amount causing parasitic capacitance in the word line. More specifically, during a period in which selected and unselected string selection lines are turned on to initialize a channel of a non-volatile memory device, the bit lines BL can be floated by turning off a switch (e.g., a transistor) provided between the bit lines BL and a bit line driver. For example, the bit line driver can be implemented by the above-described read / write circuit. For example, there can be transistors between each input / output terminal of the bit line driver, and each of these transistors is connected to a different one of the bit lines, and each of these transistors can be individually turned off as needed to float a corresponding bit line. Accordingly, a channel capacitance at a word line WL can be minimized by preventing a voltage applied from the bit lines BL from affecting the channel.

[0047] Referring Figure 7 to a first graph of

[0048] , it can be seen that the bit lines BL can remain floating for a predetermined period during a period in which selected string selection lines (Sel.SSL) and unselected string selection lines (Unsel.SSL) are turned on to increase a voltage. This can be distinguished from a method of applying a fixed voltage value (e.g., 0V) to the bit lines BL during a period in which selected string selection lines (Sel.SSL) and unselected string selection lines (Unsel.SSL) are turned on to increase a voltage. Figure 2 When a fixed voltage value is applied to the bit lines BL during a period in which all string selection lines are turned on to increase a voltage, during an initial time period in which a voltage of an unselected word line (Unsel.WL) increases, a voltage applied to an unselected string selection line can remain at 0V, as Figure 7 shown in a third graph of

[0049] (i.e., time points indicated by upward and downward arrows in a graph of Figure 7 ), but a problem of consuming a large amount of charge may occur.

[0050] However, when the bit lines are floated for a predetermined period (during which selected and unselected string selection lines are turned on to increase a voltage) by turning off transistors connecting the bit lines BL and the bit line driver, a voltage applied to an unselected string selection line can slightly increase (e.g., increase to about 0.5V), asFigure 3 and Figure 4 When using the method described in, since the channels of each unselected string select line may be over-boosted by the word line voltage set, the voltage applied to any one or more unselected string select lines may be boosted to a high enough value (e.g., to about 3V) such that the unselected cells are programmed to an unexpected value, as shown by curve B in the third graph of Figure 7 For example, as shown in.

[0051] Therefore, at least one embodiment of the inventive concept prevents the occurrence of deterioration phenomena such as soft erasure by keeping in a floating state while turning on multiple string select lines included in a memory block, and at the same time reduces the amount of power consumed. In this floating state, a specific voltage is not applied to the bit line BL for a controlled predetermined period.

[0052] The starting point of the "predetermined period" during which the bit line remains in the floating state may occur not only after the voltage is applied to the multiple string select lines included in the memory block, but also before the voltage is applied to the multiple string select lines.

[0053] Over-floating can be prevented by adjusting the floating period such that the transition of the bit line to the floating state occurs after the voltage is applied to the multiple string select lines. Even if the transition of the bit line to the floating state occurs slightly later than the application of the voltage to the multiple string select lines, the possibility of over-floating is relatively small. Therefore, as shown in the first and second graphs of Figure 7 The starting point of the "predetermined period" during which the bit line remains in the floating state can be set to slightly later than the time point when the voltage is applied to the multiple string select lines.

[0054] Therefore, as shown in Figure 5 The order of applying a voltage to multiple string select lines (S100) included in a memory block and converting the bit line passing through the memory block to a floating state (S200) can be interchanged, so that, as shown in Figure 13 The conversion of the bit line passing through the block to a floating state (S600) and the application of a voltage to multiple string select lines (S700) included in the memory block occur in sequence.

[0055] The release of the floating state of the bit line can occur after the step of starting to remove the voltage applied to the unselected string select lines among the multiple string select lines. Refer to Figure 7, after the time point when the voltage applied to the unselected string select line (Unsel.SSL) starts to decrease, for example, after the time point when the unselected string select line is turned off, the release of the floating state of the bit line can be performed. In addition, the release of the floating state of the bit line can be completed before applying the voltage required for sensing to the bit line. In an exemplary embodiment, the release of the floating state of the bit line can be achieved by converting the off-state of the transistor provided between the bit line BL and the bit line driver into its on-state. For example, the release of the floating state can be achieved by applying a control signal sufficient to turn on the transistor to the gate of the transistor.

[0056] Figure 8 is a graph showing the change in voltage that occurs in each element in a block in a method for initializing a channel in a non-volatile memory device according to an exemplary embodiment based on the inventive concept.

[0057] At Figure 7 In the embodiment shown, the bit line is held in a floating state during a predetermined period in which the selected string select line and the unselected string select line are turned on to raise the voltage. At the same time, in Figure 8 In the embodiment shown, the selected string select line and the unselected string select line are turned on in a state where the bit line is not provided with a floating state, and a desired direct current (DC) voltage is applied to the bit line using a transistor for a predetermined period in which the voltage rises. For example, as Figure 8 shown, in a state where the drain terminal of a P-type metal-oxide-semiconductor (PMOS) transistor is connected to the bit line and an appropriate DC voltage is applied to the source terminal of the PMOS according to the voltage value between 0V and the drive voltage VDD to be supplied to the drain terminal, by controlling the input signal applied to the gate terminal of the PMOS transistor to be turned on / off (ON / OFF), the voltage applied to the bit line can be controlled to have a constant DC voltage value for a predetermined period.

[0058] Figure 9 is a graph showing the state before the floating state in a method for initializing a channel in a non-volatile memory device according to an exemplary embodiment of the inventive concept; Figure 10 is a graph showing the time point for controlling the conversion into the floating state in a method for initializing a channel in a non-volatile memory device according to an exemplary embodiment of the inventive concept; and Figure 11 And Figure 12It is a graph showing the time points for controlling the entry into the floating state and the release of the floating state in a method for initializing a channel in a non-volatile memory device according to an exemplary embodiment of the inventive concept.

[0059] The method for initializing a channel in a non-volatile memory device according to an exemplary embodiment of the inventive concept may further include: applying a constant voltage of 0V to the driving voltage VDD to the bit line (S50) before converting the bit line passing through the memory block into the floating state (S200). In Figure 7 it, an embodiment is shown in which the bit line is set to the floating state during a predetermined period, in which the selected string selection line and the unselected string selection line are turned on to increase the voltage. In Figure 8 it, an embodiment is shown in which the bit line is set to have an expected DC voltage value during a predetermined period. In Figure 9 it, an embodiment is shown in which a part of the predetermined period has an expected DC voltage while the remaining period has the floating state.

[0060] As Figure 6 shown, before applying a voltage to the plurality of string selection lines included in the memory block (S100), applying a constant voltage of 0V to the driving voltage VDD to the bit line (S50) is performed. Although Figure 13 not shown in it, before converting the bit line passing through the memory block into the floating state (S600), applying a constant voltage of 0V to the driving voltage VDD to the bit line (S50) may be performed.

[0061] In a different way from Figure 7 it, Figure 9 it is shown that the time point for converting the bit line into the floating state is set after the time point for applying a voltage to the plurality of string selection lines, and a constant voltage of 0V to the driving voltage VDD or a smaller voltage is applied to the bit line before converting the bit line into the floating state. The constant voltage may be preset as needed. When a constant voltage value greater than 0V is applied to the bit line before converting the bit line into the floating state, it can be expected that the voltage difference between the word line and the bit line can be reduced, thereby reducing the amount of charge consumed during the period of applying the constant voltage value.

[0062] In the method for initializing a channel in a non-volatile memory device according to an exemplary embodiment of the inventive concept, depending on the address of the word line, the time point for converting the bit line passing through the memory block into the floating state or the time point for releasing the floating state is set differently.

[0063] The driving voltages applied to drive a plurality of word lines present in a memory block may be different from each other as needed. For example, the voltage applied to a specific word line may be higher or lower than the voltage applied to another word line. Considering that the word line with a relatively high applied voltage may be higher than the word line with a relatively low applied voltage, the time point at which the conversion to or release of the floating state occurs can be controlled in view of the boosting degree of the string selection line.

[0064] For example, as the voltage value applied to the word line becomes larger, the time point at which the bit line passing through the memory block is converted into the floating state can be delayed, as shown by curves a, b, c, and d shown. Figure 10 Therefore, the boosting degree of the string selection line can be controlled by reducing the floating period.

[0065] In addition, the time point at which the bit line passing through the memory block is converted into the floating state is delayed, and at the same time, the time point at which the floating state is released is advanced. As shown, the time points at which the bit line passing through the block is converted into the floating state and the time point at which the floating state is released can be controlled together, as shown by curves a, b, c, and d. Although not shown in the figure, embodiments of the inventive concept may include those embodiments that control the floating period by fixing the time point at which the bit line passing through the memory block is converted into the floating state and controlling the time point at which the floating state is released. Figure 11

[0066] According to an exemplary embodiment of the inventive concept, in a method for initializing a channel in a non-volatile memory device including a plurality of word lines passing through a memory block, depending on the direction in which the voltage is applied to the word line, the floating period can be controlled differently for a plurality of bit lines.

[0067] The point at which the voltage is applied to the memory block can be predefined. For example, assuming that a plurality of bit lines BL0, BL1, BL2, BL3,... and BLn are sequentially present in the memory block, and a voltage is applied to the word line near the point where BL0 is located, then as the bit line gets closer to the point where the voltage is applied, the time point at which the bit line passing through the block is converted into the floating state can be delayed or the time point at which the floating state is released can be advanced. This can also appropriately control the boosting degree of the string selection line.

[0068] According to an exemplary embodiment of the inventive concept, in a method for initializing a channel in a non-volatile memory device including a plurality of memory blocks, depending on the address of one memory block, the time point at which the bit line passing through one of the memory blocks is converted into the floating state or the time point at which the floating state is released is set differently.

[0069] ​When a voltage is applied to a plurality of memory blocks included in a non-volatile memory device, since time delays may occur due to resistance components in the memory device, the time points at which the voltage starts to be applied to each memory block may be different. Accordingly, in consideration of the occurrence of such time delays, the floating points of bit lines may also be differently controlled depending on the addresses of the memory blocks, as Figure 12 shown. For example, as the memory block is farther from the point where the voltage is applied, at least one of the time points at which the bit lines passing through the memory block are converted into a floating state or the time points at which the floating state is released may be controlled as shown by curves a, b, c, and d in Figure 12 .

[0070] Figure 14 is a block diagram illustrating an apparatus for initializing a channel in a non-volatile memory device according to an exemplary embodiment of the inventive concept.

[0071] According to an embodiment of the inventive concept, an apparatus 10 for initializing a channel in a non-volatile memory device including a plurality of word lines and a plurality of string selection lines in a memory block includes a string selection line voltage application unit 100 (e.g., a voltage generator), a bit line floating conversion unit 200 (e.g., a first control circuit), and a bit line floating release unit 300 (e.g., a second control circuit).

[0072] The string selection line voltage application unit 100 may apply a voltage to the plurality of string selection lines included in the memory block.

[0073] The bit line floating conversion unit 200 may convert the bit lines passing through the memory block into a floating state. For example, the bit line floating conversion unit 200 may be implemented by a first control circuit and a voltage generator. One or more switches may be connected between each bit line and a bit line driver. The first control circuit may apply a control signal to a given one of the switches to turn on the given switch, thereby converting the corresponding bit line into a floating state. Specifically, the bit line floating conversion unit 200 may apply a constant voltage of 0V or higher to the drive voltage or lower to the bit line before the bit line is converted into a floating state. For example, the voltage generator may be used to apply the constant voltage.

[0074] The bit line floating release unit 300 may release the floating state of the bit lines. Specifically, the bit line floating release unit 300 may release the floating state of the bit lines after a time point at which the voltage applied to the unselected string selection lines among the plurality of string selection lines starts to be removed and before a time point at which a voltage required for sensing is applied to the bit lines. For example, the bit line floating release unit 300 may be implemented by a second control circuit. The second control circuit may apply a control signal to a given one of the switches to close the given switch to release the floating state of the bit lines.

[0075] The time point at which the bit line floating conversion unit 200 enters the floating state or the time point at which the bit line floating release unit 300 releases the floating state can be set differently depending on the address of the word line. Specifically, when the voltage value applied to the word line becomes larger, the time point at which the bit line floating conversion unit 200 enters the floating state can be delayed, or the time point at which the bit line floating release unit 300 releases the floating state can be advanced.

[0076] When multiple bit lines pass through a memory block, the time point at which the bit line floating conversion unit 200 enters the floating state or the time point at which the bit line floating release unit 300 releases the floating state can be set differently for each bit line depending on the direction in which the voltage is applied to the word line. Specifically, when the bit line gets closer to the point where the voltage is applied, the time point at which the bit line floating conversion unit 200 enters the floating state can be delayed, or the time point at which the bit line floating release unit 300 releases the floating state can be advanced.

[0077] When multiple memory blocks are present in a non-volatile memory device and the bit lines pass through multiple memory blocks, the time point at which the bit line floating conversion unit 200 enters the floating state or the time point at which the bit line floating release unit 300 releases the floating state can be set differently depending on the address of the block. Specifically, when the memory block is farther from the point where the voltage is applied, the time point at which the bit line passing through the block is converted into the floating state can be delayed, or both the time point at which the bit line passing through the memory block is converted into the floating state and the time point at which the floating state is released can be delayed.

[0078] The function performed by the string selection line voltage application unit 100 can correspond to the operation of applying a voltage to multiple string selection lines included in a memory block in a method for initializing a channel of the non-volatile memory device ( Figure 2 S100 in Figure 13 S700 in Figure 2 The function performed by the bit line floating conversion unit 200 can correspond to the operation of converting a bit line passing through a memory block into a floating state in a method for initializing a channel of the non-volatile memory device ( Figure 13 S200 in Figure 13 S600 in Figure 2 The function performed by the bit line floating release unit 300 can correspond to the operation of releasing the floating state of a bit line in a method for initializing a channel of the non-volatile memory device ( Figure 2 S300 in Figure 13 S800 in Figure 13 ).

[0079] Therefore, since the detailed description of the device 10 for initializing a channel in a non-volatile memory device can be understood by referring to the detailed description of the method for initializing a channel in a non-volatile memory device and its corresponding drawings, overlapping explanations thereof will be omitted.

[0080] The term "unit" used in the present disclosure may refer to software components and hardware components, such as a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC). The unit performs certain functions. A module is not meant to be limited to software or hardware components. A unit may be configured to be stored on an addressable storage medium and configured to run on one or more processors. As will be understood by those skilled in the art, a unit may include components such as software components, object-oriented software components, class components, and task components, as well as processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided in the components and units may be combined into a smaller number of components and modules, or may be further separated into additional components and modules. In addition, the components and modules may be implemented to run one or more CPUs in a device.

[0081] Those skilled in the art should understand that the inventive concept may be embodied in other specific forms without departing from the scope of the inventive concept. Therefore, it is understood that the above embodiments are illustrative in all respects and not restrictive. It should be understood that the scope of the inventive concept may be defined by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents may be included within the scope of the inventive concept.

[0082] In a method for initializing a channel in a non-volatile memory device according to at least one exemplary embodiment of the inventive concept, when performing a read or write verification operation, power consumption may be reduced by controlling bit lines when initializing selected and unselected string selection lines.

[0083] Although the exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept.

Claims

1. A method for initializing a channel in a non-volatile memory device including memory blocks, the memory blocks including a plurality of word lines and a plurality of string select lines, the method comprising: Applying a voltage to the plurality of string select lines; Converting the bit line passing through the memory block into a floating state by disconnecting the transistor connecting the bit line and the bit line driver; Releasing the floating state of the bit line; And Wherein, in the conversion of the bit line passing through the memory block to the floating state, a constant voltage from 0V or higher to the drive voltage or lower is applied to the bit line before converting the bit line into the floating state.

2. The method according to claim 1, wherein, The releasing of the floating state of the bit line is performed after the time point of starting to remove the voltage applied to the unselected string select lines among the plurality of string select lines and is completed before the time point of applying the voltage required for sensing to the bit line.

3. The method according to claim 1, wherein The converting of the bit line passing through the memory block into the floating state is converted from a state where the bit line is not provided in the floating state to a state where a constant voltage of 0V or higher to the drive voltage or lower is applied.

4. The method according to claim 1, wherein The time point of converting the bit line into the floating state or the time point of releasing the floating state of the bit line is set differently depending on the address of one of the word lines.

5. The method according to claim 4, wherein when the voltage value applied to one word line becomes larger, the time point of converting the bit line into the floating state is delayed or the time point of releasing the floating state of the bit line is advanced.

6. The method according to claim 1, wherein the bit line is one of a plurality of bit lines passing through the memory block, Among them, The time point of converting the bit line into the floating state or the time point of releasing the floating state of the bit line is set differently for each of the bit lines depending on the direction of the voltage applied to one of the word lines.

7. The method according to claim 1, wherein the bit line is one of a plurality of bit lines passing through the memory block, and Wherein when the bit line is closer to the point where the voltage is applied, the time point of converting the bit line into the floating state is delayed or the time point of releasing the floating state of the bit line is advanced.

8. The method according to claim 1, wherein the non-volatile memory device includes a plurality of memory blocks, and the bit line passes through the plurality of memory blocks, Wherein the time point of converting the bit line into the floating state or the time point of releasing the floating state of the bit line is set differently depending on the address of the memory block.

9. The method according to claim 8, wherein, When the memory block is farther from the point where the voltage is applied, the time point of converting the bit line into the floating state is delayed.

10. A method for initializing a channel in a non-volatile memory device including memory blocks, the memory blocks including a plurality of word lines and a plurality of string select lines, the method comprising: Converting the bit line passing through the memory block into a floating state by disconnecting the transistor connecting the bit line and the bit line driver; Applying a voltage to the plurality of string select lines; And Releasing the floating state of the bit line; And Among them, in the conversion of the bit line passing through the memory block to the floating state, a constant voltage from 0V or higher to the driving voltage or lower is applied to the bit line before converting the bit line to the floating state.

11. An apparatus for initializing a channel in a nonvolatile memory device including a memory block, the memory block including a plurality of word lines and a plurality of string selection lines, the apparatus including: A voltage generator that applies a voltage to the plurality of string selection lines; A first control circuit that converts the bit line passing through the memory block to a floating state by disconnecting a transistor connecting the bit line and a bit line driver; A second control circuit that releases the floating state of the bit line; And Among them, before the bit line is converted to the floating state, the first control circuit applies a constant voltage from 0V or higher to the driving voltage or lower to the bit line.

12. The apparatus according to claim 11, wherein the second control circuit releases the floating state of the bit line after a time point when starting to remove the voltage applied to the unselected string selection lines among the plurality of string selection lines and before a time point when applying a voltage required for sensing to the bit line.

13. The device according to claim 11, wherein, The time point when the first control circuit converts the bit line to the floating state or the time point when the second control circuit releases the floating state of the bit line is set differently depending on the address of one of the word lines.

14. The device according to claim 13, wherein, When the voltage value applied to one word line becomes larger, the time point when the first control circuit converts the bit line to the floating state is delayed, or the time point when the second control circuit releases the floating state of the bit line is advanced.

15. The device according to claim 11, wherein, The time point when the first control circuit converts the bit line to the floating state or the time point when the second control circuit releases the floating state of the bit line is set differently depending on the direction in which the voltage is applied to one of the word lines.

16. The apparatus according to claim 15, wherein the bit line is one of a plurality of bit lines passing through the memory block, and Among them, when the bit line is closer to the point where the voltage is applied, the time point when the first control circuit converts the bit line to the floating state is delayed, or the time point when the second control circuit releases the floating state of the bit line is advanced.

17. The apparatus according to claim 11, wherein the nonvolatile memory device includes a plurality of memory blocks, and the bit line passes through the plurality of memory blocks, Among them, The time point when the first control circuit converts the bit line to the floating state or the time point when the second control circuit releases the floating state of the bit line is set differently depending on the address of the memory block.

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