An on-chip transformer with a substrate voltage-withstand structure

Abstract

An on-chip transformer with a substrate withstand voltage structure includes a substrate, a first metal winding and a second metal winding, wherein the first metal winding is arranged on the first surface of the substrate, and the second metal winding is arranged on the second surface of the substrate opposite to the first surface; the substrate includes a first doping region, a second doping region and a third region, wherein the first doping region is located between the first metal winding and the third region of the substrate, and the second doping region is located between the second metal winding and the third region of the substrate; the doping concentrations of the first doping region and the second doping region are higher than the doping concentration of the third region of the substrate. The present invention significantly improves the isolation capability of the on-chip transformer by introducing a doping structure into the substrate. On the other hand, the doping concentration of the third region of the substrate of the present invention can be achieved by selecting a corresponding substrate, and only one or two additional doping processes are required to form the first doping region and the second doping region, and the process is simple.

Description

Technical Field

[0001] The invention relates to an integrated circuit and an electronic element, and in particular to an on-chip transformer with a substrate withstand voltage structure. Background Art

[0002] Digital isolators and integrated isolated power supplies are widely needed in areas such as high-reliability data bus interfaces and high-voltage device drivers. On-chip transformers are key components of digital isolators and integrated isolated power supplies. High-performance on-chip transformers need to have a high inductance / resistance ratio and high isolation capability.

[0003] like Figure 1 As shown, it is a schematic diagram of the structure of an existing on-chip transformer, including a substrate, a first metal winding, a second metal winding and an isolation layer. The first metal layer and the second metal layer are arranged on the surface of the substrate, the first metal winding of the on-chip transformer is arranged on the first metal layer, the second metal winding of the on-chip transformer is arranged on the second metal layer, and the isolation layer is arranged between the first metal layer and the second metal layer. Since it is difficult to realize two thick metal layers on the same surface of the substrate at the same time, the thickness of the metal layer of the on-chip transformer is generally not more than ten microns, and the inductance / resistance ratio is small.

[0004] like Figure 2 As shown, it is a schematic diagram of the structure of another existing on-chip transformer, including a substrate, a first metal winding, and a second metal winding. The first surface of the substrate is provided with a first metal layer, and the second surface of the substrate opposite to the first surface is provided with a second metal layer. The first metal winding of the on-chip transformer is provided on the first metal layer, and the second metal winding of the on-chip transformer is provided on the second metal layer. Since only one metal layer needs to be implemented on the same surface of the substrate, the metal layer of the on-chip transformer can be embedded in the substrate, thereby achieving a thickness of tens of microns or even hundreds of microns, significantly improving the inductance / resistance ratio. However, there is a breakdown path through the substrate between the first metal winding and the second metal winding of the on-chip transformer, and the on-chip transformer substrate is generally silicon, which is a semiconductor, so it is necessary to add an isolation layer between the first metal winding and the substrate silicon and / or between the second metal winding and the substrate silicon. When the metal winding is embedded in the substrate, there is a large step on the substrate surface, and the isolation layer needs to be prepared on the substrate surface with a very deep groove, and it is difficult to obtain sufficient effective thickness and isolation strength, and the isolation capability is weak. Summary of the invention

[0005] The purpose of the present invention is to address the defects of the background technology and propose an on-chip transformer with a substrate withstand voltage structure. The on-chip transformer of the present invention introduces an appropriate doping structure into the substrate so that the silicon substrate can provide a certain isolation capability, thereby improving the isolation capability of the on-chip transformer.

[0006] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0007] An on-chip transformer with a substrate withstand voltage structure, characterized in that the on-chip transformer comprises a substrate, a first metal winding and a second metal winding, the first metal winding is arranged on a first surface of the substrate, and the second metal winding is arranged on a second surface of the substrate opposite to the first surface;

[0008] The substrate is a semiconductor, and includes a first doping region, a second doping region and a third region;

[0009] The first doped region is located between the first metal winding and the third region of the substrate, and the second doped region is located between the second metal winding and the third region of the substrate;

[0010] The doping concentrations of the first doping region and the second doping region are higher than the doping concentration of the third region of the substrate.

[0011] Furthermore, the first doping region and the second doping region have the same doping type, and the doping type of the first doping region and the second doping region is opposite to the doping type of the third region of the substrate.

[0012] Furthermore, the first doping region is p-type doped, the second doping region is n-type doped, and the third region of the substrate is p-type or n-type doped.

[0013] Furthermore, the doping concentration of the third region of the substrate is less than 10 15 cm -3 .

[0014] Furthermore, the average doping concentration of the first doping region of the substrate is greater than 20 times the doping concentration of the third region of the substrate, and the average doping concentration of the second doping region of the substrate is greater than 20 times the doping concentration of the third region of the substrate.

[0015] Furthermore, the average doping concentration of the first doping region of the substrate is greater than 10 17 cm -3 The average doping concentration of the second doping region of the substrate is greater than 10 17 cm -3 .

[0016] Furthermore, a first isolation layer may be provided between the first metal winding and the first doped region of the substrate, and a second isolation layer may be provided between the second metal winding and the second doped region of the substrate.

[0017] Furthermore, the thickness of the first isolation layer is greater than 1 micron, and the thickness of the second isolation layer is greater than 1 micron.

[0018] Further, the first metal winding is arranged on the first surface of the substrate, and the second metal winding is arranged on the second surface of the substrate. In this case, the thickness of the first metal winding is greater than 10 microns, and the thickness of the second metal winding is greater than 10 microns.

[0019] Furthermore, the first metal winding is embedded in the first surface of the substrate, and the second metal winding is embedded in the second surface of the substrate. In this case, the thickness of the first metal winding is greater than 50 microns, and the thickness of the second metal winding is greater than 50 microns.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] The present invention provides an on-chip transformer with a substrate voltage-resistant structure, which significantly improves the isolation capability of the on-chip transformer by introducing a doping structure into the substrate. On the other hand, the doping concentration of the third region of the substrate of the present invention can be achieved by selecting a corresponding substrate, and only one or two additional doping processes are required to form the first doping region and the second doping region, and the process is simple. At the same time, the present invention sets a first isolation layer between the first metal winding and the first doping region, and sets a second isolation layer between the second metal winding and the second doping region to maximize the isolation capability of the on-chip transformer. The first metal winding of the present invention can still be embedded in the first surface of the substrate, and the second metal winding can still be embedded in the second surface of the substrate to increase the thickness of the first metal winding and the second metal winding, thereby improving the inductance / resistance ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural schematic diagram of an existing on-chip transformer;

[0023] Figure 2 is a schematic diagram of the structure of another existing on-chip transformer;

[0024] Figure 3 A schematic structural diagram of an on-chip transformer with a substrate withstand voltage structure provided by the present invention;

[0025] Figure 4 A schematic structural diagram of an on-chip transformer with a substrate withstand voltage structure provided in Example 1;

[0026] Figure 5 A schematic structural diagram of an on-chip transformer with a substrate withstand voltage structure provided in Example 2;

[0027] Figure 6 A schematic structural diagram of an on-chip transformer with a substrate voltage-withstanding structure provided in Example 3. DETAILED DESCRIPTION

[0028] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments.

[0029] An on-chip transformer with a silicon-based substrate withstand voltage structure, such as Figure 3 As shown, it includes a substrate, a first metal winding, and a second metal winding. The first metal winding is arranged on the first surface of the substrate, and the second metal winding is arranged on the second surface of the substrate opposite to the first surface. The substrate is a semiconductor. The substrate is provided with a first doping region near the first surface, and the substrate is provided with a second doping region near the second surface. The first doping region and the second doping region have the same doping type (i.e., both are p-type or both are n-type). The doping types of the first doping region and the second doping region are opposite to the doping types of other regions of the substrate (hereinafter referred to as the third region). The doping concentrations of the first doping region and the second doping region are much higher than the doping concentration of the third region of the substrate. Due to the different doping types, a first pn junction is formed between the first doping region and the third region of the substrate, and a second pn junction is formed between the second doping region and the third region of the substrate. When the doping type of the first doping region and the second doping region is n-type, and the doping type of the third region of the substrate is p-type, if the voltage of the first metal winding is much higher than that of the second metal winding, the first pn junction is reverse biased and withstands voltage, and if the voltage of the first metal winding is much lower than that of the second metal winding, the second pn junction is reverse biased and withstands voltage. When the doping type of the first doping region and the second doping region is p-type, and the doping type of the third region of the substrate is n-type, if the voltage of the first metal winding is much higher than that of the second metal winding, the second pn junction has a reverse bias withstand voltage, and if the voltage of the first metal winding is much lower than that of the second metal winding, the first pn junction has a reverse bias withstand voltage. Since the doping concentration of the first doping region and the second doping region is much higher than that of the third region of the substrate, the depletion region is mainly located in the third region of the substrate when the first pn junction and the second pn junction are reverse biased, and the reverse withstand voltage capability is approximately given by the following single-sided abrupt junction reverse breakdown voltage formula, where VB is the reverse breakdown voltage, W is the depletion region thickness, and E is the reverse breakdown voltage. C is the substrate critical electric field, ε is the substrate dielectric constant, N B is the doping concentration of the third region of the substrate,

[0030] VB=0.5WE C =εE C 2 / (2qN B )

[0031] When N B Less than 2×10 14 cm -3 When VB is 1 kV, it can exceed 1 kV (reference: "Semiconductor Device Physics and Technology (Second Edition)", written by Shi Min [USA], translated by Zhao Heming, Qian Min, Huang Qiuping, Suzhou University Press, 2002.12, pages 115-117). Therefore, the substrate doping structure introduced in the present invention can significantly improve the isolation capability of the on-chip transformer.

[0032] An on-chip transformer with a silicon-based substrate withstand voltage structure, such as Figure 3 As shown, it includes a substrate, a first metal winding, and a second metal winding. The first metal winding is arranged on the first surface of the substrate, and the second metal winding is arranged on the second surface of the substrate opposite to the first surface. The substrate is a semiconductor. The substrate is provided with a first doping region near the first surface, and the substrate is provided with a second doping region near the second surface. The first doping region is p-type doped, and the second doping region is n-type doped. The doping concentrations of the first doping region and the second doping region are much higher than the doping concentrations of other regions of the substrate (hereinafter referred to as the third region). When the doping type of the third region of the substrate is p-type, a pn junction is formed between the third region of the substrate and the second doping region; when the doping type of the third region of the substrate is n-type, a pn junction is formed between the first doping region and the third region of the substrate. When the voltage of the second metal winding is much higher than that of the first metal winding, the pn junction is reverse biased and withstands voltage. Since the doping concentrations of the first doping region and the second doping region are much higher than those of the third region of the substrate, the depletion region is mainly located in the third region of the substrate when the pn junction is reverse biased. When the thickness of the depletion region is less than the thickness of the third region of the substrate, the reverse withstand voltage capability is approximately given by the following single-sided abrupt junction reverse breakdown voltage formula, where VB is the reverse breakdown voltage, W is the depletion region thickness, and E is C is the substrate critical electric field, ε is the substrate dielectric constant, N B is the doping concentration of the third region of the substrate,

[0033] VB=0.5WE C =εE C 2 / (2qN B )

[0034] When N B Less than 2×10 14 cm -3 , VB can exceed 1kV (reference: "Semiconductor Device Physics and Technology (Second Edition)", [US] Shi Min, Zhao Heming, Qian Min, Huang Qiuping translation, Suzhou University Press, 2002.12, pp. 115-117). B Very low, when reverse biased, the third region of the substrate between the first doping region and the second doping region may be completely depleted. At this time, the first doping region, the third region, and the second doping region form a pin diode. The reverse withstand voltage capability is approximately given by the following formula, where T is the thickness of the third region of the substrate: VB = TE C Therefore, the substrate doping structure introduced in the present invention can significantly improve the unidirectional isolation capability of the on-chip transformer.

[0035] An on-chip transformer with a silicon-based withstand voltage structure includes a substrate, a first metal winding, and a second metal winding. The first metal winding is arranged on the first surface of the substrate, and the second metal winding is arranged on the second surface of the substrate opposite to the first surface. The substrate is a semiconductor, and the substrate includes a first doping region, a second doping region, and a third region. The first doping region of the substrate is close to the first surface of the substrate, and the second doping region of the substrate is close to the second surface of the substrate. Preferably, the average doping concentration of the first doping region and the second doping region is greater than 100 times the doping concentration of the third region of the substrate. Preferably, the substrate doping concentration used in the on-chip transformer processing is the doping concentration of the third region of the substrate. Preferably, the doping concentration of the third region of the substrate is less than 10 15 cm -3 Preferably, the first doping region is formed by ion implantation on the first surface of the substrate, and the second doping region is formed by ion implantation on the second surface of the substrate. Preferably, the first doping region and the second doping region are formed by impurity diffusion on the substrate. Preferably, the average doping concentration of the first doping region is greater than 10 17 cm -3 , the average doping concentration of the second doping region is greater than 10 17 cm -3 .

[0036] Example 1

[0037] like Figure 4 As shown, in the on-chip transformer of Embodiment 1, the first metal winding is arranged on the first surface of the substrate, and the second metal winding is arranged on the second surface of the substrate. The thickness of the first metal winding is greater than 10 microns, and the thickness of the second metal winding is greater than 10 microns. The preparation process of the first metal winding includes copper electroplating, and the preparation process of the second metal winding includes copper electroplating.

[0038] Example 2

[0039] like Figure 5 As shown, in the on-chip transformer of Embodiment 2, the first metal winding is embedded in the first surface of the substrate, and the second metal winding is embedded in the second surface of the substrate. The thickness of the first metal winding is greater than the line width, and the thickness of the second metal winding is greater than the line width. The thickness of the first metal winding is greater than 50 microns, and the thickness of the second metal winding is greater than 50 microns. The preparation process of the first metal winding includes copper electroplating, and the preparation process of the second metal winding includes copper electroplating.

[0040] Example 3

[0041] like Figure 6As shown, in the on-chip transformer of Example 3, a first isolation layer is provided between the first metal winding and the first doped region of the substrate, and a second isolation layer is provided between the second metal winding and the second doped region of the substrate. The first isolation layer and the second isolation layer are silicon oxide; the first isolation layer and the second isolation layer are prepared by thermal oxidation or enhanced chemical vapor deposition. The thickness of the first isolation layer is greater than 1 micron, and the thickness of the second isolation layer is greater than 1 micron. The specific preparation process is: select a doping concentration of less than 10 15 cm -3 A silicon substrate is provided, a first groove having a first metal winding pattern is formed on the front side of the silicon substrate by photolithography and deep silicon etching, and a second groove having a second metal winding pattern is formed on the back side of the silicon substrate by photolithography and deep silicon etching; the silicon substrate is doped with impurities of a different doping type from that of the substrate, silicon oxide chemical vapor deposition is performed on the front side of the silicon substrate, silicon oxide chemical vapor deposition is performed on the back side of the silicon substrate, a copper electroplating seed layer is physically deposited on the front side of the silicon substrate, a copper electroplating seed layer is physically deposited on the back side of the silicon substrate, double-sided copper electroplating is performed to form a first metal winding and a second metal winding filling the first groove and the second groove, and the electroplated copper beyond the substrate surface and the copper electroplating seed layer outside the groove are removed by polishing and / or etching.

Claims

1. An on-chip transformer with a substrate withstand voltage structure, characterized in that: The on-chip transformer comprises a substrate, a first metal winding and a second metal winding, wherein the first metal winding is arranged on a first surface of the substrate, and the second metal winding is arranged on a second surface of the substrate opposite to the first surface; the substrate comprises a first doping region, a second doping region and a third region, wherein the first doping region is located between the first metal winding and the third region of the substrate, and the second doping region is located between the second metal winding and the third region of the substrate; the doping concentrations of the first doping region and the second doping region are higher than the doping concentration of the third region of the substrate; The average doping concentration of the first doping region of the substrate is greater than 20 times the doping concentration of the third region of the substrate, and the average doping concentration of the second doping region of the substrate is greater than 20 times the doping concentration of the third region of the substrate; The doping concentration of the third region of the substrate is less than 10 15 cm -3 The average doping concentration of the first doping region of the substrate is greater than 10 17 cm -3 The average doping concentration of the second doping region of the substrate is greater than 10 17 cm -3 .

2. The on-chip transformer with a substrate withstand voltage structure according to claim 1, characterized in that: The first doping region and the second doping region have the same doping type, and the doping types of the first doping region and the second doping region are opposite to the doping type of the third region of the substrate.

3. The on-chip transformer with a substrate withstand voltage structure according to claim 1, characterized in that: The first doping region is p-type doped, the second doping region is n-type doped, and the third region of the substrate is p-type or n-type doped.

4. The on-chip transformer with a substrate withstand voltage structure according to claim 1, characterized in that: A first isolation layer is arranged between the first metal winding and the first doping region of the substrate, and a second isolation layer is arranged between the second metal winding and the second doping region of the substrate.

5. The on-chip transformer with a substrate withstand voltage structure according to claim 4, characterized in that: The thickness of the first isolation layer is greater than 1 micron, and the thickness of the second isolation layer is greater than 1 micron.

6. The on-chip transformer with a substrate withstand voltage structure according to claim 1, characterized in that: The first metal winding is disposed on the first surface of the substrate, and the second metal winding is disposed on the second surface of the substrate. At this time, the thickness of the first metal winding is greater than 10 microns, and the thickness of the second metal winding is greater than 10 microns.

7. The on-chip transformer with a substrate withstand voltage structure according to claim 1, characterized in that: The first metal winding is embedded in the first surface of the substrate, and the second metal winding is embedded in the second surface of the substrate. At this time, the thickness of the first metal winding is greater than 50 microns, and the thickness of the second metal winding is greater than 50 microns.

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