Memory controller, method for operating a memory controller, and memory system

Abstract

A memory controller, a method for operating the memory controller, and a memory system are provided. The memory system includes: a memory device including a plurality of memory cells constituting a plurality of subsets; and a memory controller for controlling the memory device. The memory controller controls the memory device to manage a read count indicating the number of read operations performed by the memory device for each subset in the plurality of subsets, and performs a recovery operation on the subset based on the read count corresponding to the subset among the plurality of subsets. Each subset in the plurality of subsets includes a plurality of pages. Each of the plurality of pages is a unit for performing a read operation in the plurality of memory cells.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2018-0141955, filed on November 16, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The disclosure relates to a memory controller and a memory system, and more particularly, to a memory controller that performs a recovery operation, a method of operating the memory controller, and a memory system including the memory controller. Background Art

[0003] As a nonvolatile memory device, a resistive memory device such as a phase change RAM (PRAM), a resistive RAM (RRAM), and a magnetic RAM (MRAM) uses a variable resistance element that stores data by changing the resistance state as a memory cell. The commonality of the materials constituting the resistive memory device is that the resistance value changes according to the magnitude and / or direction of the current or voltage, and has a nonvolatile characteristic of maintaining the resistance value even when the current or voltage is cut off.

[0004] In this case, the resistance of a resistive memory cell included in the resistive memory device varies according to a voltage applied to another memory cell. As the resistance varies, the reliability of data may not be ensured or the memory cell itself may deteriorate. Summary of the invention

[0005] A memory controller is disclosed for managing the number of read operations of memory cells in units of subsets so as to maintain resistance distribution of the memory cells.

[0006] According to one aspect of the disclosure, a memory system is provided, comprising: a memory device, comprising: a plurality of memory cells constituting a plurality of subsets; and a memory controller, configured to: manage a read count indicating the number of read operations performed by the memory device in each of the plurality of subsets, and perform a recovery operation on the subset based on the read count corresponding to a subset among the plurality of subsets, wherein each of the plurality of subsets comprises a plurality of pages, and wherein each of the plurality of pages is a unit for performing a read operation in the plurality of memory cells.

[0007] According to another aspect of the disclosure, there is provided a method of operating a memory controller for controlling the operation of a memory device, wherein the memory device includes a plurality of memory cells constituting a plurality of subsets, the method comprising: sending a read command to the memory device; increasing a read count of a subset among the plurality of subsets corresponding to the read command; and performing a recovery operation on the subset based on the read count corresponding to the subset, wherein the subset includes a plurality of pages, and wherein each of the plurality of pages is a unit for performing a read operation in the plurality of memory cells.

[0008] According to another aspect of the disclosure, a memory controller for controlling a memory device is provided, wherein the memory device includes a plurality of memory cells constituting a plurality of subsets, and the memory controller includes: a memory configured to: store one or more instructions; and at least one processor configured to: execute the one or more instructions to manage a read count indicating the number of read commands sent to the memory device for each subset in the plurality of subsets, determine, for a subset among the plurality of subsets, whether the read count reaches a first reference value, and based on a result of the determination that the read count reaches the first reference value, output an instruction to perform a recovery operation for the subset corresponding to the read count, wherein each subset in the plurality of subsets includes a plurality of pages, and wherein each of the plurality of pages is a unit for performing a read operation in the plurality of memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The disclosed embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating a memory system according to an example embodiment of the disclosure;

[0011] Figure 2 It is shown that the Figure 1 A block diagram of a memory controller in a memory system;

[0012] Figure 3 It is shown that the Figure 1 A block diagram of a memory device in a memory system;

[0013] Figure 4 It is shown Figure 3 A block diagram of an implementation example of a memory cell array;

[0014] Figure 5 It is shown Figure 4 A circuit diagram of an example embodiment of a memory block;

[0015] Figure 6 It is used to explain Figure 5a graph of example characteristics of a memory cell;

[0016] Figure 7 It is shown Figure 4 A circuit diagram of an example embodiment of a memory block;

[0017] Figure 8 is a flowchart for explaining a method of operating a memory controller according to a disclosed example embodiment;

[0018] Fig. 9 is a flowchart for explaining a method of operating a memory system according to a disclosed example embodiment;

[0019] Fig.10 is a flowchart for explaining a method of operating a memory system according to a disclosed example embodiment;

[0020] Fig.11 is a flowchart for explaining a method of operating a memory system according to a disclosed example embodiment; and

[0021] Fig.12 is a flowchart for explaining a method of operating a memory controller according to a disclosed example embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, disclosed embodiments will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 is a block diagram illustrating a memory system 10 according to an example embodiment of the disclosure.

[0024] Reference Figure 1 , the memory system 10 may include a memory controller 100 and a memory device 200 .

[0025] The memory controller 100 may control the memory device 200 to write data into the memory device 200 or read data stored in the memory device 200 in response to a write / read request from the host HOST. For example, the memory controller 100 may provide an address ADDR, a command CMD (e.g., a read command RCMD, a write command WCMD, a recovery command recCMD, and a rewrite command reWCMD), and a control signal CTRL to the memory device 200, thereby controlling the provision of a programming (or writing) operation and a reading operation with respect to the memory device 200. In addition, data DATA to be written and data DATA to be read may be sent and received between the memory controller 100 and the memory device 200. Figure 1, although the re-write command reWCMD is illustrated as a command different from the write command WCMD, the disclosure is not limited thereto, and the re-write command reWCMD may be included in the write command WCMD rather than as a separate command.

[0026] The memory controller 100 may receive a request based on a logical address from the host HOST. The flash translation layer FTL driven by the processor 110 of the memory controller 100 may convert the logical address into a physical address of the memory device 200. The memory controller 100 may transmit the converted physical address to the memory device 200.

[0027] The memory controller 100 may count the read operations performed in the memory device 200. For example, the memory controller 100 may count the number of read commands RCMD sent to the memory device 200. In one embodiment, the memory controller 100 may manage the read count RCNT of each of the subsets SUB-SET_1 to SUB-SET_z. That is, the memory controller 100 may manage the read count RCNT in units of subsets.

[0028] The memory controller 100 may count write operations performed in the memory device 200. That is, the memory controller 100 may count the number of write commands WCMD sent to the memory device 200. In one embodiment, the memory controller 100 may manage the write count WCNT of each of the subsets SUB-SET_1 to SUB-SET_z. That is, the memory controller 100 may manage the write count WCNT on a subset unit basis.

[0029] However, the disclosure is not limited thereto, and the memory controller 100 may not manage the write count WCNT based on a subset unit. According to another embodiment, the memory controller 100 may not manage the read count RCNT based on a subset unit. According to another embodiment, units for managing the read count RCNT and the write count WCNT in the memory controller 100 may be different from each other.

[0030] The memory controller 100 may determine whether to perform a recovery operation for each of the subsets SUB-SET_1 to SUB-SET_z based on the read count RCNT. In this case, the recovery operation may refer to an operation for reducing errors in a read operation for the subsets SUB-SET_1 to SUB-SET_z by preventing degradation of a resistance distribution corresponding to data stored in the subsets SUB-SET_1 to SUB-SET_z.

[0031] In one embodiment, when at least one of the subsets SUB-SET_1 to SUB-SET_z requires a recovery operation, the memory controller 100 may send a recovery command recCMD to the memory device 200. In response to the recovery command recCMD, the control circuit 230 of the memory device 200 may provide a recovery voltage to the subset corresponding to the recovery command recCMD.

[0032] In one embodiment, when at least one of the subsets SUB-SET_1 to SUB-SET_z requires a recovery operation, the memory controller 100 may send a rewrite command reWCMD to the memory device 200. The memory device 200 may perform a rewrite operation on the subset requiring a recovery operation in response to the rewrite command reWCMD. That is, the memory device 200 may rewrite the data DATA written in the subset requiring a recovery operation.

[0033] The memory controller 100 may perform a wear leveling operation on each of the subsets SUB-SET_1 to SUB-SET_z based on the write count WCNT When data is written to the same memory cell through the wear leveling operation, degradation of the memory cell may be prevented.

[0034] The memory controller 100 may include a counter CNT driven by the processor 110. When a read operation is performed on a specific memory cell, the counter CNT may increase a read count RCNT of a subset including the specific memory cell. In addition, when a write operation is performed on the specific memory cell, the counter CNT may increase a write count WCNT of a subset including the specific memory cell.

[0035] The memory device 200 may include a memory cell array 210 and a control circuit 230. The memory cell array 210 may include a plurality of memory cells (eg, Figure 5 MC in), wherein each memory cell is arranged in an area where a plurality of first signal lines and a plurality of second signal lines intersect each other. That is, the memory cell array 210 may be a memory cell array having a cross-point structure. In one embodiment, the plurality of first signal lines may be a plurality of word lines, and the plurality of second signal lines may be a plurality of bit lines. In another embodiment, the plurality of first signal lines may be a plurality of bit lines, and the plurality of second signal lines may be a plurality of word lines.

[0036] In one embodiment, the plurality of memory cells may include a resistive memory cell including a variable resistance element. For example, when the variable resistance element includes a phase change material (e.g., germanium-antimony-tellurium (Ge-Sb-Te, GST)) and the resistance of the variable resistance element changes based on temperature, the memory device 200 may be a PRAM. Alternatively, for example, when the variable resistance element includes an upper electrode, a lower electrode, and a composite metal oxide between the upper electrode and the lower electrode, the memory device 200 may be an RRAM. Alternatively, for example, when the variable resistance element includes an upper electrode of a magnet, a lower electrode of a magnet, and a dielectric between the upper electrode and the lower electrode, the memory device 200 may be an MRAM. Therefore, the memory device 200 may be referred to as a resistive memory device, and the memory system 10 may be referred to as a resistive memory system.

[0037] In one embodiment, each of the plurality of memory cells may be a single-layer cell (SLC) storing one bit of data. In this case, the memory cell may have two different resistance distributions according to the stored data. In another embodiment, each of the plurality of memory cells may be a multi-layer cell (MLC) capable of storing two bits of data. In this case, the memory cell may have four resistance distributions according to the stored data. In another embodiment, each of the plurality of memory cells may be a triple-layer cell (TLC) capable of storing three bits of data. In this case, the memory cell may have eight resistance distributions according to the stored data. However, the disclosure is not limited thereto. In one embodiment, the memory cell array 210 may include memory cells each capable of storing 4 bits or more of data, and the memory cell array 210 may include single-layer cells, multi-layer cells, and / or triple-layer cells.

[0038] The memory cell array 210 may include subsets SUB-SET_1 to SUB-SET_z. Each subset may be a unit in which the memory controller 100 manages the read count RCNT, and may include a plurality of pages as a unit for performing a read operation / write operation. In addition, each subset may include a plurality of pages connected to different memory bays (e.g., Figure 4 The memory cells of one word line in each of the BAYs in FIG.

[0039] The control circuit 230 may control the operation of the memory device 200. In one embodiment, in response to the command CMD received from the memory controller 100, the control circuit 230 may control the voltage level of the voltage applied to the first signal line and the second signal line connected to the memory cell array 210, or the timing at which the voltage is applied. In one embodiment, the control circuit 230 may perform a recovery operation on at least one of the subsets SUB-SET_1 to SUB-SET_z in response to the command CMD received from the memory controller 100. The memory device 200 according to the embodiment may perform the recovery operation to prevent the degradation of the resistance distribution of the memory cells included in the subsets SUB-SET_1 to SUB-SET_z.

[0040] Figure 2 is shown in detail including Figure 1 1 is a block diagram of a memory controller 100 in a memory system 10 of the present invention.

[0041] Reference Figure 2 , the memory controller 100 may include a processor 110 , a random access memory (RAM) 120 , an error correction code (ECC) circuit 130 , a host interface 140 , a memory interface 150 , and a bus 160 .

[0042] The processor 110 may include a central processing unit or a microprocessor, etc., and the processor 110 may control the overall operation of the memory controller 100. The processor 110 may communicate with the host HOST through the host interface 140, and may communicate with the memory device 200 through the memory interface 150. The processor 110 may use the RAM 120 as an operating memory, a cache memory, or a buffer memory for controlling the memory device 200.

[0043] In one embodiment, at least one of the flash translation layer FTL and the counter CNT may be implemented in the form of software, such as firmware, operating system, and application. In one embodiment, at least one of the flash translation layer FTL and the counter CNT may be implemented in the processor 110 in the form of hardware, such as circuits or intellectual property (IP). In one embodiment, at least one of the flash translation layer FTL and the counter CNT may be implemented in the form of a combination of hardware and software associated with the processor 110. In one embodiment, at least one of the flash translation layer FTL and the counter CNT may be provided as a separate module separate from the processor 110.

[0044] The memory controller 100 embedded according to the disclosure may use the counter CNT to manage the read count RCNT as the number of times the read command is sent, and may determine whether to perform a recovery operation based on the read count RCNT. Therefore, the memory controller 100 may prevent the degradation of the resistance distribution of the memory cells included in the memory device 200 through the recovery operation. In one embodiment, the units for managing the read count RCNT and the write count WCNT in the memory controller 100 may be the same as the subset units, respectively.

[0045] The RAM 120 may be used as an operating memory, a cache memory, or a buffer memory of the processor 110. The RAM 120 may store codes and instructions executed by the processor 110. The RAM 120 may store data processed by the processor 110. The RAM 120 may include an SRAM (static RAM). In one embodiment, the processor 110 may be configured to drive firmware for controlling the memory controller 100, and the firmware may be loaded into the RAM 120 to be driven.

[0046] The ECC circuit 130 may perform ECC encoding based on data to be written to the memory device 200 through the memory interface 150. The ECC encoded data may be transmitted to the memory device 200 through the memory interface 150. The ECC circuit 130 may perform ECC decoding on data received from the memory device 200 through the memory interface 150.

[0047] The host interface 140 may interface with the host HOST to receive a request for a memory operation from the host HOST. For example, the host interface 140 receives various requests (such as read data and write data) from the host HOST, and in response, generates various internal signals for memory operations of the memory device 200.

[0048] The memory interface 150 may provide an interface between the memory controller 100 and the memory device 200, for example, write data may be transmitted to the memory device 200 via the memory interface 150 and read data may be received from the memory device 200 via the memory interface 150. In addition, the memory interface 150 may provide commands and addresses to the memory device 200. In addition, the memory interface 150 may receive a plurality of pieces of information from the memory device 200 to provide the received information to the memory controller 100.

[0049] The bus 160 may be configured to provide a channel between components of the memory controller 100. In one embodiment, the bus 160 of the memory controller 100 may be divided into a control bus and a data bus. The data bus may transmit data within the memory controller 100, and the control bus may be configured to transmit control information (such as commands, addresses) within the memory controller 100. The data bus and the control bus may be separated from each other so as not to interfere with or affect each other.

[0050] Figure 3 It is shown that the Figure 1 1 is a block diagram of a memory device 200 in a memory system 10 of FIG. 1 .

[0051] Reference Figure 3 , the memory device 200 may include a memory cell array 210, a write / read circuit 220, a control circuit 230, a reference signal generating circuit 240, a voltage generating circuit 250, a row decoder (X-DEC) 260 and a column decoder (Y-DEC) 270.

[0052] The memory cell array 210 may include a plurality of memory cells, and the plurality of memory cells may be connected to a plurality of first signal lines and a plurality of second signal lines. In one embodiment, the plurality of first signal lines may be a plurality of word lines WL, and the plurality of second signal lines may be a plurality of bit lines BL. When various voltage signals or current signals are provided through the plurality of word lines WL and the plurality of bit lines BL, data may be written to or read from the selected memory cell, and a write operation or a read operation may be prevented from being performed on the remaining or unselected memory cells. This will be referred to later. Figure 4 An example description of memory cells constituting the memory cell array 210 is described.

[0053] An address ADDR for indicating a memory cell to be accessed according to the command CMD may be received in the memory device 200, and the address ADDR may include a row address RA for selecting a word line WL of the memory cell array 210 and a column address CA for selecting a bit line BL of the memory cell array 210. The row decoder 260 performs a word line selection operation in response to the row address RA, and the column decoder 270 may perform a bit line selection operation in response to the column address CA.

[0054] The write / read circuit 220 may be connected to the first signal line and / or the second signal line of the memory cell array 210 to write data to the memory cell or read data from the memory cell. The write / read circuit 220 may include a sense amplifier 221, a write driver 223, and a data comparison-write unit (DCW unit) 225. Figure 3In the embodiment, although the write / read circuit 220 may include a data comparison-write unit 225, the data comparison-write unit 225 is not limited thereto, and the data comparison-write unit 225 may have a configuration separate from the write / read circuit 220 and may be configured to control the operation of the write / read circuit 220.

[0055] The sense amplifier 221 may be connected to the memory cell array 210 via the bit line BL. In a read operation, the sense amplifier 221 may receive a data voltage through the bit line BL to amplify the received data voltage. To this end, the sense amplifier 221 may be implemented to include a plurality of sense amplifier circuits SA for sensing and amplifying the data voltage. For example, each sense amplifier circuit SA may be implemented to compare the data voltage with a reference voltage and output the result of the comparison as a digital level data signal. One sense amplifier circuit SA may be connected to one memory compartment (e.g., Figure 4 BAY in ).

[0056] The data comparison-write unit 225 may be connected to the sense amplifier 221 and the write driver 223. The data comparison-write unit 225 may be connected to the sense amplifier 221 and the write driver 223. Figure 1 The data comparison-write unit 225 may control the sense amplifier 221 and the write driver 223 to perform a comparison-write operation or a re-write operation in response to a control signal CTRL_RW of the control circuit 230.

[0057] For example, when the data requested to be written is the same as the data stored in the memory cell, the data comparison-write unit 225 may control the write driver 223 to maintain the data stored in the memory cell when the comparison-write operation is performed. When the data requested to be written is not the same as the data stored in the memory cell, the data comparison-write unit 225 may control the write driver 223 to allow the data requested to be written to be rewritten into the memory cell.

[0058] In addition, for example, when the rewrite operation is performed, the data comparison-write unit 225 may control the sense amplifier 221 and the write driver 223 to perform a rewrite operation for writing the requested write data to the memory cell regardless of the data stored in the memory cell. That is, unlike the comparison-write operation, when the rewrite operation is performed, the data comparison-write unit 225 may control the sense amplifier 221 not to perform the pre-read operation, and may control the write driver 223 to allow the requested write data to be rewritten to the corresponding memory cell. For example, even if the written data and the newly requested data are the same, the newly requested data may be rewritten to the memory cell. For example, a write pulse may be applied to at least one of the memory cells in the page where the write operation is performed, in which the written data and the newly requested data are the same. For example, a write pulse for a write operation may be applied to all memory cells in the page where the write operation is performed.

[0059] The voltage generating circuit 250 may generate a write voltage Vwrite for a write operation, and may generate a read voltage Vread for a read operation. In addition, the voltage generating circuit 250 may generate a recovery voltage Vrecov for a recovery operation. The write voltage Vwrite may include a set pulse, a reset pulse, etc. as various voltages related to the write operation. The recovery voltage Vrecov may be a voltage related to the recovery operation, and may include a recovery pulse. The recovery pulse may have a voltage level different from the set pulse and the reset pulse, or the duration of the recovery pulse may be different from the set pulse and the reset pulse. The write voltage Vwrite, the read voltage Vread, and the recovery voltage Vrecov may be supplied to the bit line BL through the column decoder 270, or may be supplied to the word line WL through the row decoder 260.

[0060] The reference signal generating circuit 240 may generate a reference voltage Vref and a reference current Iref as various reference signals related to a data reading operation. For example, the sense amplifier 221 may be connected to a node (e.g., a sense node) of the bit line BL to determine data, and the data value may be determined by a comparison operation on the voltage of the sense node and the reference voltage Vref. Alternatively, when a current sensing method is applied, the reference signal generating circuit 240 may generate a reference current Iref to provide the reference current Iref to the memory cell array 210, and the data value may be determined by comparing the voltage of the sense node caused by the reference current Iref with the reference voltage Vref.

[0061] The write / read circuit 220 may provide a determination result of the read data to the control circuit 230. The control circuit 230 may control a write operation and a read operation of the memory cell array 210 with reference to the determination result.

[0062] The control circuit 230 may output various control signals CTRL_RW based on the command CMD, the address ADDR, and the control signal CTRL received from the memory controller 100 to write data to the memory cell array 210 or read data from the memory cell array 210. The control circuit 230 may perform a recovery operation based on the command CMD, the address ADDR, and the control signal CTRL received from the memory controller 100. For example, the control circuit 230 may control the voltage generating circuit 250, the column decoder 270, and the row decoder 260 to send a signal to a subset (e.g., Figure 1 For example, the control circuit 230 may control the voltage generating circuit 250, the column decoder 270, and the row decoder 260 to rewrite the data into the subset corresponding to the rewrite command reWCMD (for example, Figure 1 at least one of the subsets SUB-SET_1 to SUB-SET_z in the.

[0063] Figure 4 It is shown Figure 3 2 is a block diagram of an implementation example of a memory cell array 210. Figure 3 The memory cell array 210 may be implemented as a memory block group TILE_GR in which memory blocks TILE1 to TILE4 are arranged along the row direction and the column direction in the plan view. In this case, the memory block group TILE_GR may include a plurality of memory compartments BAY1 to BAY128, and the memory blocks TILE1 to TILE4 may be arranged in each memory compartment BAY. The memory compartment BAY may include a plurality of memory cells connected to the memory cells included in the memory cell group TILE_GR. Figure 3 A memory cell of one of the plurality of sense amplifier circuits in sense amplifier 221 is configured to receive a sense amplifier 221 of the memory cell.

[0064] Figure 4 128 memory compartments BAY1 to BAY128 are shown, wherein four memory tiles TILE1 to TILE4 constitute one memory compartment BAY. The disclosure is not limited thereto, and the number of memory compartments BAY1 to BAY128 and the number of memory tiles TILE1 to TILE4 may be configured differently according to embodiments.

[0065] Reference Figure 4, the memory block group TILE_GR may be set as a memory area where data is written or read in units of page PAGE. A page PAGE may be a collection of selected memory cells among the memory cells that simultaneously perform a write operation or a read operation. The page PAGE may include memory cells included in each of the different memory compartments BAY1 to BAY128 of the memory block group TILE_GR. For example, when it is assumed that the data bits corresponding to one page unit are 128 bits (or 16 bytes), one bit of data may be written or read in each of the 128 memory compartments BAY1 to BAY128 included in the memory block group TILE_GR.

[0066] One subset SUB-SET may include memory cells included in each of the different memory compartments BAY1 to BAY128 of the memory tile group TILE_GR. In one embodiment, one subset SUB-SET may include a plurality of pages PAGE. Therefore, the memory controller 100 may more easily manage the read count of the subset SUB-SET.

[0067] In one embodiment, memory cells connected to one word line in each of the different memory compartments BAY1 to BAY128 may be included in one subset SUB-SET. In one embodiment, memory cells corresponding to the same word line address in each of the plurality of memory compartments BAY1 to BAY128 are included in the same subset SUB-SET. In one embodiment, memory cells corresponding to the same word line address in each of the plurality of memory tiles TILE to TILE4 are included in the same subset. Figure 5 and Figure 7 Describes the memory cells that make up a subset of a block.

[0068] Figure 5 It is shown Figure 4 1 is a circuit diagram of an example embodiment of a memory tile TILE2.

[0069] Reference Figure 5 , the memory block TILE2 may include a plurality of word lines WL0 to WLm, a plurality of bit lines BL0 to BLm, and a plurality of memory cells MC, where m is an integer greater than 0. Here, the number of word lines WL, the number of bit lines BL, and the number of memory cells MC may be variously changed according to embodiments.

[0070] According to an embodiment, each of the plurality of memory cells MC may include a variable resistance element R and a selection element D. Here, the variable resistance element R may be referred to as a variable resistance element or a variable resistance material, and the selection element D may be referred to as a switching element. Figure 5Unlike the memory cell MC shown in FIG. 1 , each of the plurality of memory cells MC may include only the variable resistance element R, may include the variable resistance element R and a bidirectional diode, or may include the variable resistance element R and a transistor.

[0071] In one embodiment, the variable resistance element R may be connected between one of the plurality of word lines WL0 to WLm and the selection element D, and the selection element D may be connected between the variable resistance element R and one of the plurality of bit lines BL0 to BLm. However, the disclosure is not limited thereto, and the selection element D may be connected between one of the plurality of word lines WL0 to WLm and the variable resistance element R, and the variable resistance element R may be connected between the selection element D and one of the plurality of bit lines BL0 to BLm.

[0072] The selection element D may be connected between any one of the plurality of bit lines BL0 to BLm and the variable resistance element R, and the supply of current to the variable resistance element R may be controlled according to the voltage applied to the connected word line and bit line. In one embodiment, the selection element D may be a PN junction diode or a PIN junction diode, the anode of the diode may be connected to the variable resistance element R, and the cathode of the diode may be connected to the plurality of bit lines BL0 to BLm. In this case, when the voltage difference between the anode and the cathode of the diode is greater than the threshold voltage of the diode, the diode may be turned on, and current may be supplied to the variable resistance element R.

[0073] Figure 6 is the explanation Figure 5 Graph of example characteristics of a memory cell MC. Figure 6 1 shows an ideal distribution of a single-layer cell in which the memory cell MC is programmed with one bit. Figure 6 , the horizontal axis represents resistance, and the vertical axis indicates the number of memory cells.

[0074] Reference Figure 5 and Figure 6 , the variable resistance element R of the memory cell MC may have a low resistance state LRS or a high resistance state HRS. The operation of switching the variable resistance element R from the high resistance state HRS to the low resistance state LRS by applying a set pulse to the memory cell MC is called a set operation or a set write operation. In addition, the operation of switching the variable resistance element R from the low resistance state LRS to the high resistance state HRS by applying a reset pulse to the memory cell is called a reset operation or a reset write operation.

[0075] Any resistance between the distribution due to the low resistance state LRS and the distribution due to the high resistance state HRS can be set as the threshold resistance Rth (REF). In the read operation of the memory cell MC, when the read result of the read operation is greater than the threshold resistance Rth, the read result can be determined as reset data (logic "0") as the high resistance state HRS, and when the read result of the read operation is equal to or less than the threshold resistance Rth, the read result can be determined as set data (logic "1") as the low resistance state LRS.

[0076] When it is assumed that data is read out from a selected memory cell MC_sel of the memory block TILE2, the third bit line BL2 and the third word line WL2 connected to the selected memory cell MC_sel can both be provided with a selection voltage, and a non-selection voltage can be applied to the other bit lines BL0 to BL1, BL3 to BLm and the other word lines WL0 to WL1 and WL3 to WLm.

[0077] The unselected memory cells connected to the third word line WL2 connected to the selected memory cell MC_sel may change the resistance value by the selection voltage applied to the third word line WL2, so read interference in which the resistance distribution is widened may occur. Read interference may mean that pressure is applied to the unselected memory cells instead of the selected memory cells to perform a read operation. For example, the resistance value of the unselected memory cells may increase due to read interference, and the resistance distribution may become widened. Therefore, when the number of read operations in other memory cells connected to the same word line connected to a specific memory cell increases, the resistance distribution of the specific memory cell may deteriorate. Since the memory cell reduces the sensing margin between the set data of logic "1" and the reset data of logic "0", it may cause the problem that the memory cell is fixed in the reset state.

[0078] Refer again Figure 4 and Figure 5 , Figure 5 Memory cells included in one memory block among the memory cells constituting the subset Sub-Set are shown. Memory cells MC connected to the same word line among the memory cells MC included in one memory block TILE2 may be included in the same subset. In one embodiment, memory cells connected to different word lines may be included in different subsets. For example, memory cells MC connected to the first word line WL0 may be included in one subset SUB-SET, memory cells MC connected to the second word line WL1 may be included in another subset SUB-SET, and memory cells MC connected to the (m+1)th word line WLm may be included in another subset SUB-SET.

[0079] The memory controller 100 and the memory device 200 according to the disclosure may manage a read count of each subset cell, and may perform a recovery operation for each subset cell.

[0080] Since the subset SUB-SET includes memory cells connected to the same word line, when a read operation is performed on a portion of the selected memory cells included in the subset including the unselected memory cells, the read count is also increased for the unselected memory cells. Therefore, even if unselected memory cells exist due to repetition of the read operation, read disturbance can be prevented from occurring in the unselected memory cells by connecting to the same word line (e.g., the third word line WL2) as the selected memory cells (e.g., MC_sel). That is, despite the presence of unselected memory cells, degradation of the resistance distribution can be prevented by applying a selection voltage to the connected word line.

[0081] Figure 7 It is shown Figure 4 1. Circuit diagram of an example embodiment of a memory tile TILE2 in FIG. Figure 7 is a diagram showing memory cells included in one block among memory cells constituting a subset Sub-Set′.

[0082] Reference Figure 7 , among the memory cells MC included in a memory block TILE2, the memory cells MC connected to the same word line may be included in the same subset Sub-Set'. In one embodiment, the memory cells MC connected to some word lines among the multiple word lines WL0 to WLm may be included in the same subset Sub-Set'. For example, the memory cells MC connected to two word lines among the word lines WL0 to WLm connected to a memory block TILE2 may be included in the same subset Sub-Set'. The memory cells MC connected to the first word line WL0 and the second word line WL1 may be included in one subset Sub-Set', and the memory cells MC connected to the third word line WL2 and the fourth word line WL3 may be included in another subset Sub-Set'. The memory cells MC connected to the mth word line WLm-1 and the (m+1)th word line WLm may be included in another subset Sub-Set'. Figure 7 , a plurality of memory cells in each subset included in the memory block TILE2 are shown to be connected to two word lines, but the disclosure is not limited thereto, and the plurality of memory cells may be connected to three or more word lines.

[0083] Since the memory controller 100 and the memory device 200 according to the disclosure manage the read count and perform the recovery operation based on the subset Sub-Set' cells, the degradation of the memory cells due to the repeated execution of the read operation can be prevented. Since the subset Sub-Set' includes all the memory cells connected to the same word line, when the read operation is performed for some of the selected memory cells included in the subset Sub-Set' (for example, the memory cells constituting one page), the read count for the unselected memory cells included in the subset Sub-Set' is also increased. Therefore, since the selected voltage is applied to the connected word line even if the memory cell is not selected, the resistance distribution degradation can be prevented.

[0084] Figure 8 is a flowchart for explaining a method of operating the memory controller 100 according to the disclosed example embodiment.

[0085] Reference Figure 1 and Figure 8 , the memory controller 100 may receive a read request and a logical address from the external host HOST, and the memory controller 100 may perform a read operation. For example, a flash translation layer (FTL) may convert the logical address into a physical address of the memory device 200. In step S10, the memory controller 100 may send a read command to the memory device 200.

[0086] In step S20, the memory controller 100 may increase the read count of a subset including memory cells corresponding to the transmitted read command (e.g., memory cells constituting one page). For example, a corresponding subset may be detected based on a physical address corresponding to the read command, and the read count of the detected subset may be increased.

[0087] In one embodiment, when a read command is sent, the memory controller 100 may increase the read count of the subset corresponding to the read command by a constant value. In one embodiment, when a read command is sent, the memory controller 100 may increase the read count so that the physical address ADDR according to the subset corresponding to the read command has a read weight. For example, the degree of occurrence of read interference may vary according to the arrangement of the word lines to be connected among the memory cells, the read weight may be calculated by reflecting the read interference, and the read count may be increased by the read weight.

[0088] In step S30, the memory controller 100 may perform a recovery operation on the subset based on the read count. For example, when the read count exceeds a specific value, a recovery operation may be performed on the subset corresponding to the read count. Fig. 9 etc. to describe step S30.

[0089] Each time a read operation is performed on a page, read disturbance may occur in the subset containing the page. When read disturbance accumulates, data stored in unselected memory cells may be changed, so the reliability of the data may be difficult to ensure. The recovery operation may include: applying a recovery pulse to the memory cell to restore the changed resistance distribution back to the original state, and reading valid data from the memory cell and rewriting the read data. When the recovery operation is performed, the reliability of the data can be restored because the influence of the read disturbance is removed.

[0090] The memory controller 100 according to the disclosure may perform a recovery operation on the subset based on the read count managed by the counter CNT. Therefore, the reliability of the data written to the memory device 200 through the recovery operation may be guaranteed.

[0091] Fig. 9 is a flowchart for explaining a method of operating the memory system 10 according to a disclosed example embodiment.

[0092] Reference Figure 1 , Figure 8 and Fig. 9 , the memory controller 100 may execute steps S31 and S32 to perform Figure 8 In step S30. In step S31, the memory controller 100 may determine whether the read count of the subset whose read count has been increased in step S20 has reached the first reference value N. That is, in step S31, the memory controller 100 may determine whether the read count of the subset is equal to or greater than the first reference value N. When the read count does not reach the first reference value N, the process may be terminated. When the read count reaches the first reference value N, the memory controller 100 may perform step S32. In this case, the first reference value N may be a value stored in the memory controller 100 as a predetermined value.

[0093] In step S32, the memory controller 100 may send a resume command recCMD to the memory device 200 for the subset whose read count has reached the first reference value N. For example, the memory controller 100 may send the resume command recCMD and the physical address ADDR corresponding to the subset.

[0094] The memory device 200 may receive a recovery command recCMD and perform a recovery operation on a subset corresponding to the recovery command recCMD. In step S110, the memory device 200 may provide a recovery voltage (i.e., a recovery pulse) to the subset. In this case, the recovery pulse may have a different voltage level or a different pulse duration from the set pulse and the reset pulse used to write data to the memory cell. When the recovery pulse is applied, the resistance of the memory cells included in the subset may be reduced, and the width of the resistance distribution may be reduced.

[0095] In step S40 , the memory controller 100 may reset the read count of the subset. In one embodiment, step S40 and step S110 may be performed in parallel with each other.

[0096] Fig.10 is a flowchart for explaining a method of operating the memory system 10 according to a disclosed example embodiment. Fig.10 Step S30a may be Figure 8 An embodiment of step S30.

[0097] Reference Figure 1 , Figure 8 and Fig.10 , the memory controller 100 may perform steps S33a to S36a to perform step S30a. In step S33a, the memory controller 100 may determine whether the read count of the subset whose read count has been increased in step S20 has reached the second reference value M. That is, in step S33a, the memory controller 100 may determine whether the read count of the subset is equal to or greater than the second reference value M. When the read count does not reach the second reference value M, the process may be terminated. When the read count reaches the second reference value M, the memory controller 100 may perform steps S34a to S36a. In this case, the second reference value M may be a value stored in the memory controller 100 as a predetermined value, and may be the same as Fig. 9 The first reference value N in may be the same or different value.

[0098] In step S34a, the memory controller 100 may send a read command RCMD to the memory device 200 for the subset whose read count has reached the second reference value M. For example, the memory controller 100 may send a read command (RCMD) and a physical address (ADDR) corresponding to the subset.

[0099] In step S120 , the memory device 200 may receive the read command RCMD and may read the data written in the corresponding subset. In step S130 , the memory device 200 may send the read data to the memory controller 100 .

[0100] In step S35a, the memory controller 100 may correct errors of the data received from the memory device 200. For example, the memory controller 100 may correct errors in the data read from the subset through an ECC decoding operation.

[0101] In step S36a, the memory controller 100 may send a rewrite command reWCMD for the subset and the error-corrected data to the memory device 200. In this case, the memory controller 100 may send the physical address of the subset to the memory device 200 together. However, the memory device 200 and the memory controller 100 may be described as performing an ECC operation, but are not limited thereto. In one embodiment, the memory device 200 may include an ECC circuit therein, and the memory device 200 may directly perform an ECC operation (e.g., an on-chip ECC operation) while being controlled by the memory controller 100.

[0102] In step S140, the memory device 200 receives a rewrite command reWCMD for a subset and the error-corrected data, and may rewrite the corrected data to the subset. In this case, the rewrite operation may represent a write operation, rather than a compare-write operation. For example, even if the written data and the newly requested write data are the same, the write operation may be performed by rewriting the corresponding memory cell. For example, a write pulse for a write operation may be applied to at least one of the memory cells in a page included in the subset where the write operation is performed, wherein, in the at least one of the memory cells, the written data and the newly requested write data are the same. For example, a write pulse for a write operation may be applied to all memory cells in a page included in the subset where the write operation is performed.

[0103] However, the memory device 200 may be described as performing a re-write operation instead of a compare-write operation, but is not limited thereto. In one embodiment, in step S36a, the memory controller 100 may send a write command WCMD for a subset and error-corrected data to the memory device 200, and in step S140, the memory device 200 may perform a compare-write operation on the corrected data in the subset SUB-SET.

[0104] In addition, the memory controller 100 may be described as performing an ECC operation, but is not limited thereto. The memory controller 100 may not perform an ECC operation including an ECC decoding operation and an ECC encoding operation. Therefore, in one embodiment, in step S140, the memory device 200 may rewrite the data read in step S120 without performing an ECC operation.

[0105] In step S40 , the memory controller 100 may reset the read count of the subset. In one embodiment, step S40 and step S140 may be performed in parallel.

[0106] Fig.11 is a flowchart for explaining a method of operating the memory system 10 according to a disclosed example embodiment. Fig.11 Step S30b may be Figure 8 An embodiment of step S30.

[0107] Reference Figure 1 , Figure 8 and Fig.11 , the memory controller 100 may perform steps S31b to S36b to perform step S30b. In step S31b, the memory controller 100 may determine whether the read count of the subset whose read count has been increased in step S20 has reached the first reference value N. When the read count has not reached the first reference value N, the process may be terminated. When the read count reaches the first reference value N, the memory controller 100 may perform steps S32b and S33b.

[0108] In step S32b, the memory controller 100 may send a resume command recCMD to the memory device 200 for the subset whose read count has reached the first reference value N. For example, the memory controller 100 may send the resume command recCMD and the physical address ADDR corresponding to the subset.

[0109] The memory device 200 may receive the resume command recCMD to perform a resume operation on the subset corresponding to the received resume command recCMD. In step S110, the memory device 200 may provide a resume pulse to the subset.

[0110] In step S33b, the memory controller 100 may determine whether the read count of the subset has reached the second reference value M. When the read count has not reached the second reference value M, the process may be terminated. When the read count reaches the second reference value M, the memory controller 100 may perform steps S34b to S36b. In this case, the second reference value M may be a value greater than the first reference value N. That is, even after the memory controller 100 performs step S32b and the memory device 200 performs step S110, the memory controller 100 may further perform step S34b to step S36b. Figure 8 The steps S10 and S20 are performed, so that the read count of the subset can be increased from the first reference value N to reach the second reference value M.

[0111] In step S34b, the memory controller 100 may send a read command RCMD to the memory device 200 for the subset whose read count reaches the second reference value M. For example, the memory controller 100 may send the read command RCMD and the physical address ADDR corresponding to the subset.

[0112] In step S120 , the memory device 200 receives the read command RCMD to read the data written in the subset corresponding to the received read command RCMD. In step S130 , the memory device 200 may send the read data to the memory controller 100 .

[0113] In step S35b, the memory controller 100 may correct errors in the data received from the memory device 200. For example, the memory controller 100 may correct errors in the data read from the subset through an ECC decoding operation.

[0114] In step S36b, the memory controller 100 may transmit a rewrite command reWCMD for the subset and the error-corrected data to the memory device 200. In this case, the memory controller 100 may transmit the physical address of the subset to the memory device 200 together.

[0115] In step S140, the memory device 200 receives a rewrite command reWCMD for the subset and the error-corrected data, and may rewrite the corrected data to the subset. In this case, the rewrite operation may represent a write operation, rather than a compare-write operation. For example, a write pulse for a write operation may be applied to at least one of the memory cells in which the corresponding written data is the same as the corresponding newly requested write data. For example, a write pulse for a write operation may be applied to all memory cells in a page included in the subset in which the write operation is performed.

[0116] However, the memory device 200 may be described as performing a re-write operation instead of a comparison and write operation, but is not limited thereto. In one embodiment, in step S36b, the memory controller 100 may send a write command WCMD for a subset and error-corrected data to the memory device 200, and in step S140, the memory device 200 may perform a comparison-write operation on the corrected data in the subset SUB-SET.

[0117] In step S40 , the memory controller 100 may reset the read count of the subset. In one embodiment, step S40 and step S140 may be performed in parallel.

[0118] Fig.12 is a flowchart for explaining a method of operating the memory controller 100 according to an example embodiment disclosed. Figure 8 The same reference numerals as in the reference numerals in FIG.

[0119] Reference Figure 1 and Fig.12, the memory controller 100 may perform steps S21, S23, and S25 before performing the recovery operation of step S30. In this case, step S30 may be Fig. 9 Step S30, Fig.10 Step S30a and Fig.11 One of the steps S30b.

[0120] In step S21, the memory controller 100 may check whether a request for a specific subset whose read count has been increased in step S20 is received from the host HOST. When a request for the subset is not received, the memory controller 100 may perform a recovery operation based on step S30.

[0121] In step S21, the memory controller 100 may confirm whether the memory controller 100 has received a request for a subset from the host HOST. If a request for a subset is received from the host HOST, the memory controller 100 may confirm whether a read request for the subset is received from the host HOST in step S23. When a read request for a subset is received, the memory controller 100 may preferentially perform step S30. That is, when there is a read request from the host HOST for a memory cell included in the subset, the memory controller 100 may preferentially perform a recovery operation before performing a read operation based on the read request received from the host HOST. The memory controller 100 may perform a read operation based on the read request after the recovery operation based on step S30 is completed. Since the recovery operation is performed before performing a read operation on the memory cell included in the subset, the reliability of the data written to the subset may be improved. If a request for a subset is not received from the host HOST in step S21, the memory controller 100 may perform a recovery operation on the subset based on the read count in step S30.

[0122] When the memory controller 100 receives a request (e.g., a write request) other than a read request for the subset, the memory controller 100 may perform step S25. In step S25, the memory controller 100 may perform an operation on the subset based on the request from the host HOST. After step S25 is completed, the memory controller 100 may perform step S30. That is, when there is a request other than a read request for the memory cells included in the subset from the host HOST, the memory controller 100 may perform an operation based on the request, and then may perform step S30.

[0123] Although the disclosure has been described with reference to the embodiments shown in the drawings, it will be appreciated that various modifications and equivalent embodiments may be made by those skilled in the art without departing from the scope of the inventive concept. Therefore, the true scope of protection of the disclosure should be determined by the technical concept of the claims.

[0124] While the disclosure has been particularly shown and described with reference to disclosed embodiments, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the claims.

Claims

1. A memory system, comprising: A memory device comprising: a plurality of memory cells constituting a plurality of subsets; and The memory controller is configured as: managing, for each subset of the plurality of subsets, a read count, wherein the read count indicates a number of read operations performed by a memory device on a corresponding subset of the plurality of subsets; determining whether a read count of a corresponding subset among the plurality of subsets satisfies a criterion; and performing a recovery operation on the corresponding subset among the plurality of subsets based on a result of a determination that the read count of the corresponding subset among the plurality of subsets satisfies a criterion, Each of the plurality of subsets includes a plurality of pages. wherein each of the plurality of pages is a unit for performing a read operation in the plurality of memory cells, and When the read count reaches a first reference value, the memory device is configured to provide a restore pulse to the subset corresponding to the read count.

2. The memory system according to claim 1, wherein: Memory cells connected to the same word line among the plurality of memory cells are included in the same subset.

3. The memory system according to claim 1, wherein: The memory controller is also configured to manage a write count indicating a number of write operations performed by the memory devices in each of the plurality of subsets.

4. The memory system according to claim 1, wherein: The restore pulse has a voltage level different from that of a pulse used for a write operation.

5. The memory system according to claim 1, wherein: The recovery pulse has a pulse duration different from that of a pulse used for a write operation.

6. The memory system according to claim 1, wherein: When the read count reaches a second reference value, the memory device is configured to read out data written in the subset corresponding to the read count and send the read data to the memory controller.

7. The memory system according to claim 6, wherein: The memory controller is also configured to receive data read from the subset, correct errors in the received data, and send error-corrected data to the memory device.

8. The memory system according to claim 7, wherein: The memory device is configured to write error correction data to the subset corresponding to the read count.

9. The memory system according to claim 8, wherein: The memory device is also configured to rewrite the error correction data in the memory cell even when the read data and the error correction data are identical.

10. The memory system according to claim 8, wherein: The memory device is further configured to perform a data compare-write operation on the subset corresponding to the read count.

11. A method of operating a memory controller, the memory controller being used to control the operation of a memory device, wherein: The memory device includes a plurality of memory cells constituting a plurality of subsets, the method comprising: sending a read command to the memory device; incrementing a read count of a subset among the plurality of subsets corresponding to the read command, wherein the read count indicates a number of read operations performed by the memory device on the subset; determining whether the read counts of the subset meet a criterion; and Based on a result of a determination that the read count of the subset satisfies a criterion, performing a restore operation on the subset, wherein the subset includes a plurality of pages, wherein each of the plurality of pages is a unit for performing a read operation in the plurality of memory cells, and When the read count of the subset reaches a first reference value, the memory device is configured to provide a restore pulse to the subset.

12. The method according to claim 11, wherein: The steps to perform a recovery operation include: determining whether the read count reaches a first reference value; and Based on determining that the read count reaches the first reference value, a resume command is sent to the memory device.

13. The method according to claim 11, wherein: The steps to perform a recovery operation include: determining whether the read count reaches a second reference value; Based on determining that the read count reaches a second reference value, sending a read command for the subset corresponding to the read count; correcting errors in data read from the subset; and A rewrite command and the corrected data for the subset are sent to the memory device to allow the corrected data to be rewritten to the subset.

14. The method according to claim 11, further comprising: The read count is reset after the restore operation is complete.

15. The method according to claim 11, further comprising: confirming whether a request for the subset is received from the host, When no request for the subset is received, a recovery operation is performed.

16. The method according to claim 11, further comprising: confirming whether a read request for the subset is received from the host, When a read request for the subset is received, an operation according to the read request is performed after performing a recovery operation.

17. The method according to claim 11, further comprising: confirming whether a request for the subset is received from the host, Wherein, when a request other than a read request for the subset is received, a recovery operation is performed after performing an operation according to the request.

18. A memory controller for controlling a memory device, wherein: The memory device includes a plurality of memory cells constituting a plurality of subsets, the memory controller including: A memory configured to: store one or more instructions; and At least one processor configured to: executing the one or more instructions to manage, for each of the plurality of subsets, a read count, wherein the read count indicates a number of read commands sent to a memory device for a corresponding subset of the plurality of subsets, determining whether a read count of a corresponding subset among the plurality of subsets satisfies a criterion, and outputting an instruction to perform a recovery operation on the corresponding subset among the plurality of subsets based on a result of the determination that the read count of the corresponding subset among the plurality of subsets satisfies the criterion, Each of the plurality of subsets includes a plurality of pages. wherein each of the plurality of pages is a unit for performing a read operation in the plurality of memory cells, and When the read count reaches a first reference value, the memory device is configured to provide a restore pulse to the subset corresponding to the read count.

19. The memory controller according to claim 18, in, The at least one processor is further configured to: Based on a result of the determination that the read count reaches the first reference value, sending a resume command to the memory device so that a resume pulse is provided to the subset corresponding to the read count, and When the read count reaches a second reference value, sending a rewrite command so that the data is rewritten to the subset, wherein the first reference value is less than the second reference value, and Among the plurality of memory cells, memory cells connected to the same word line are included in the same subset.

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