GaN High Electron Mobility Transistor

Abstract

The present invention provides a GaN high electron mobility transistor, comprising: a substrate; a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer; a barrier layer disposed on the channel layer; a doping layer disposed on the barrier layer; a source electrode disposed on the channel layer and located on one side of the barrier layer; a drain electrode disposed on the channel layer and located on the other side of the barrier layer; a gate electrode disposed on the side of the doping layer close to the drain electrode; wherein, a two-dimensional electron gas exists on the side close to the channel layer at the critical point between the channel layer and the barrier layer, and the height of the channel layer at the source electrode is greater than the height of the channel layer at the gate electrode. By making the thickness of the channel layer at the source electrode greater than the thickness of the channel layer at the gate electrode, when the transistor is powered on, the flow direction of the high-concentration 2-DEG is from top to bottom, effectively avoiding or weakening the action of the electric field between the source electrode and the drain electrode, thereby improving the threshold voltage of the transistor.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor materials and device manufacturing. Specifically, it relates to a GaN high electron mobility transistor. Background Art

[0002] Power electronic devices are widely used in fields such as mobile communication, electric vehicles, and industrial control. In recent years, with the rapid development of the electric vehicle industry and the gradual commercialization of 5G technology, the first-generation semiconductor materials represented by Si and the second-generation semiconductor materials represented by GaAs and InP are gradually approaching their theoretical limits and can no longer meet the market demand in application scenarios such as high frequency, high efficiency, high power density, high temperature, and strong radiation environment. Therefore, the third-generation semiconductor materials represented by SiC and GaN are gradually replacing Si-based devices in some fields due to their outstanding performance advantages.

[0003] Due to its large bandgap, high saturated electron mobility, good high-temperature performance, and strong radiation resistance, GaN materials have great advantages in application scenarios such as high voltage, high temperature, high power density, and high efficiency. Currently, GaN-based semiconductor devices have been relatively maturely applied in the aerospace field and the mobile communication field, and have also been commercialized in power semiconductor devices. The GaN high electron mobility transistor (HEMT) has the advantages of fast switching speed, small on-resistance, strong breakdown voltage ability, and good high-temperature performance. Currently, in the voltage range of 100 - 900V, it has obvious performance advantages, and its switching frequency can reach more than ten times that of silicon-based devices. Therefore, the volume of passive components such as inductors and capacitors can be greatly reduced, and the power density can be improved. In addition, since the GaN HEMT device has no reverse recovery loss, the efficiency is significantly improved.

[0004] However, due to the special heterojunction structure characteristics of GaN HEMT devices, under the action of the spontaneous polarization and piezoelectric polarization effects of the material itself, a potential well will be formed at the GaN / AlGaN interface under zero gate bias, and a large amount of two-dimensional electron gas (2-DEG) will exist. This is also the reason why GaN HEMT devices have a high saturated electron mobility. But this also makes the threshold voltage of GaN HEMT devices relatively low. For example, the threshold voltage of P-type gate structure GaN devices in related technologies is relatively low, and the anti-interference ability is weak. Therefore, it is urgent to increase the threshold voltage of GaN HEMT devices without significantly reducing the device performance. Summary of the Invention

[0005] The present invention aims to solve one of the technical problems existing in the prior art or related technologies.

[0006] To this end, a first aspect of the present invention provides a GaN high electron mobility transistor.

[0007] In view of this, a GaN high electron mobility transistor is provided according to a first aspect of the present invention, comprising: a substrate; a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer; a barrier layer disposed on the channel layer; a doped layer disposed on the barrier layer; a source electrode disposed on the channel layer and on one side of the barrier layer; a drain electrode disposed on the channel layer and on the other side of the barrier layer; and a gate electrode disposed on the side of the doped layer close to the drain electrode; wherein, a two-dimensional electron gas exists on the side of the critical point between the channel layer and the barrier layer close to the channel layer, and the height of the channel layer at the source electrode is greater than the height of the channel layer at the gate electrode.

[0008] The GaN high electron mobility transistor proposed by the present invention comprises a substrate, a buffer layer, a channel layer, a barrier layer and a doped layer which are distributed in sequence from bottom to top, and further comprises a source electrode and a drain electrode located at the top of the channel layer, and a gate electrode located above the barrier layer. Among them, the source electrode, the drain electrode and the barrier layer are all disposed on the channel layer, the source electrode and the drain electrode are respectively located on the left and right sides of the barrier layer, and a high-concentration two-dimensional electron gas exists on the side of the critical point between the channel layer and the barrier layer close to the channel layer. There is an electric field from the drain electrode to the source electrode in the transistor. Since there is a high concentration of 2-DEG at the interface between the channel layer and the barrier layer in the non-depletion region, this electric field will cause the high-concentration 2-DEG on the source-side of the gate electrode to move towards the drain side. Therefore, this electric field promotes the conduction of the channel under the gate electrode, which results in a lower threshold voltage of the device in the related art. And in this application, by making the height of the channel layer at the source electrode greater than the height of the channel layer at the gate electrode, that is, the heights of the channel layer are not the same everywhere, the upper boundaries of the channel layer are not at the same height everywhere, and the height of the channel layer under the source electrode is greater than the height of the channel layer under the gate electrode, when the transistor is powered on, the flow direction of the high-concentration 2-DEG is from top to bottom. This way largely avoids or weakens the action of the electric field between the source electrode and the drain electrode, so that the threshold voltage of the device, that is, the transistor of this application, has a large increase. While significantly increasing the threshold voltage of the device, it does not cause a decrease in the current-carrying capacity, and does not affect the device performance, such as the conduction performance, and has strong anti-interference ability. In the related art, the threshold voltage of the P-type gate structure device is generally below 1.5V, while the threshold voltage of the transistor proposed in this application can reach above 3V, and the threshold voltage can be further increased on the premise of appropriately reducing its conduction characteristics, and the threshold voltage can be increased by more than 2 times.

[0009] In addition, according to the theoretical analysis and simulation results, it can be known that when the voltage between the drain and the source is fixed, the drain current of the device is proportional to the gate width (i.e., the effective length between the gate and the barrier layer), and inversely proportional to the length of the cutoff channel (i.e., the channel where a part of the two-dimensional electron gas corresponding to the gate in the direction of the barrier layer in the two-dimensional electron gas is located). In the application, since the height of the channel layer at the source is greater than the height of the channel layer at the gate, compared with the related technology where the thickness and height of the channel layer are the same everywhere, it makes the channel near the gate of the channel layer tend to extend vertically, which can make the length of this part of the channel shorter than the cutoff channel length of the traditional P-type gate, and the contact surface between the gate and the relatively horizontally extending channel increases the gate width. Therefore, as the cutoff channel length decreases and the gate width increases, the current-carrying capacity of the device does not decrease significantly, and due to the existence of this characteristic, after optimizing the structural parameters, the current-carrying capacity of the device can even be increased to a certain extent, and the threshold voltage of the transistor can be increased.

[0010] Moreover, the current-carrying capacity of the device in this application is hardly affected by the concentration of the P-type doping layer, because the influence of the gate width and the cutoff channel length on the current-carrying capacity of the device is much greater than the influence of the P-type doping concentration. At this time, the influence of the P-type doping layer concentration on the current-carrying capacity of the device can be ignored. Since it is still relatively difficult to achieve a high P-type doping concentration in the production process of power devices, the transistor in this application can also reduce the requirements for the process in device production and manufacturing.

[0011] It should be noted that in this application, the height direction of the channel layer is the same as the thickness direction of the channel layer. The height of the channel layer refers to the height where the upper boundary of the channel layer is located. When the heights of the lower boundaries of the channel layer are the same and on the same horizontal plane, the height of each part of the channel layer is equal to the thickness of the channel layer at the corresponding position. The height direction of the channel layer is the same as the height direction of the entire transistor.

[0012] In addition, according to the GaN high electron mobility transistor provided by the above technical solution of the present invention, the following additional technical features may also be included:

[0013] In a possible design, the channel layer includes a horizontal channel layer and a vertical channel layer. The horizontal channel layer extends in the horizontal direction, and the vertical channel layer extends in the thickness direction of the horizontal channel layer and is located on the side of the horizontal channel layer close to the source. The height of the vertical channel layer is greater than the height of the horizontal channel layer.

[0014] In this design, specifically, the channel layer includes a horizontal channel layer and a vertical channel layer. Among them, the horizontal channel layer extends in the horizontal direction, and the vertical channel layer extends in the thickness direction of the horizontal channel layer. Since the extensions of the horizontal channel layer and the vertical channel layer are simple, the overall processing of the channel layer is convenient. Moreover, since the height of the vertical channel layer is greater than the height of the horizontal channel layer, after the transistor is powered on, it is easier for the high-concentration 2-DEG to flow from top to bottom, weakening the effect of the electric field between the source and the drain, thereby increasing the threshold voltage of the transistor. Moreover, the magnitude of the threshold voltage can be increased by adjusting the height difference between the vertical channel layer and the horizontal channel layer, and the threshold voltage can increase as the height difference between the vertical channel layer and the horizontal channel layer increases.

[0015] Among them, it should be noted that the thickness direction of each layer in this application is the direction from the substrate to the barrier layer. The horizontal direction is the relatively horizontal direction and is always perpendicular to the thickness direction of the substrate.

[0016] In a possible design, the source electrode is arranged on the vertical channel layer, and the gate electrode is arranged on the side of the horizontal channel layer away from the buffer layer.

[0017] In this design, specifically, the source electrode is arranged on the vertical channel layer, and the gate electrode is arranged on the side of the horizontal channel layer away from the buffer layer, which is convenient for processing. Further, the source electrode is arranged on the left side of the upper boundary of the vertical channel layer, the drain electrode is arranged on the right side of the upper boundary of the horizontal channel layer, and the gate electrode is located between the source electrode and the drain electrode and above the middle of the horizontal channel layer.

[0018] In a possible design, the barrier layer is distributed in a Z shape in the height direction of the channel layer.

[0019] In this design, specifically, the barrier layer is distributed in a Z shape in the height direction of the channel layer. Since the barrier layer is adjacent to the channel layer, there must be a height difference between the left and right sides of the channel layer. After the transistor is powered on, it is easier for the high-concentration 2-DEG to flow from top to bottom, weakening the effect of the electric field between the source and the drain, thereby increasing the threshold voltage of the transistor.

[0020] Among them, the barrier potential layer can be generally in a Z shape. The middle part of the barrier potential layer can extend vertically, that is, extend in the height direction of the channel layer, or can also extend obliquely.

[0021] In a possible design, the channel layer includes an inclined channel layer. The part of the upper boundary of the inclined channel layer close to the source electrode slopes upward, and the part of the upper boundary of the inclined channel layer close to the drain electrode slopes downward.

[0022] In this design, the channel layer may only include an inclined channel layer. By making the upper boundary of the inclined channel layer near the source part tilt upward and the upper boundary of the inclined channel layer near the drain part tilt downward, the height of the part of the channel layer below the source is greater than the height of the part of the channel layer below the drain. When the transistor is powered on, the flow direction of the high-concentration 2-DEG is from top to bottom. This way, to a great extent, the effect of the electric field between the source and the drain is avoided, and the threshold voltage of the transistor is greatly increased. While significantly increasing the threshold voltage of the device, it does not cause a decrease in the current-carrying capacity.

[0023] Of course, in addition to the inclined channel layer, the channel layer may also include a horizontal channel layer and / or a vertical channel layer. At this time, the inclined channel layer may be located between the horizontal channel layer and the vertical channel layer, which is convenient for processing. Or, the inclined channel layer is located on the side of the horizontal channel layer near the source, or the inclined channel layer is located on the side of the vertical channel layer near the drain, etc. The shape and position of the channel layer can be adjusted according to the magnitude of the required threshold voltage.

[0024] Furthermore, the lower boundary of the inclined channel layer extends in the horizontal direction, which is convenient for processing. Of course, the lower boundary of the inclined channel layer may also have a certain angle with the horizontal plane. The opening of this angle can face the side where the drain is located and is an acute angle.

[0025] In a possible design, the height of the gate is lower than the height of the source.

[0026] In the related art, the heights of the gate, the source, and the drain are the same, so that the thickness and height of the channel layer are also the same everywhere. In this design, by making the height of the gate lower than the height of the source and also lower than the height of the drain, the height of the part of the channel layer corresponding to the drain is also reduced accordingly, which is beneficial to cooperate with the fact that the height of the part of the channel layer below the source is greater than the height of the part of the channel layer below the gate. After the transistor is powered on, it is easier to make the high-concentration 2-DEG flow from top to bottom, weakening the effect of the electric field between the source and the drain, thereby increasing the threshold voltage of the transistor.

[0027] Furthermore, the height of the channel layer at the source is greater than the height of the channel layer at the drain.

[0028] Furthermore, the lower boundary of the source is higher than the lower boundary of the drain. And the upper boundaries of the source and the drain are at the same height.

[0029] In a possible design, the GaN high electron mobility transistor further includes: a passivation layer. The first part of the passivation layer is disposed above the barrier layer, the source, and the drain. The second part of the passivation layer is disposed between the doped layer and the barrier layer. The third part of the passivation layer is disposed between the gate and the barrier layer.

[0030] In this design, the GaN high electron mobility transistor further includes a passivation layer, which includes three parts. The first part is disposed above the barrier layer, the source electrode, and the drain electrode. The second part is disposed between the doping layer and the barrier layer. The third part is disposed between the gate electrode and the barrier layer. The three parts are connected to each other, achieving the enclosure of the gate electrode and the capping of the source electrode and the drain electrode.

[0031] Further, the material of the passivation layer is Si3N4, which can reduce the device leakage current and weaken the current collapse effect of the GaN device.

[0032] In a possible design, the thickness of the channel layer at the source electrode ranges from 1 μm to 2 μm; and / or the thickness of the channel layer at the gate electrode ranges from 400 nm to 600 nm.

[0033] In this design, specifically, the thickness of the channel layer at the source electrode ranges from 1 μm to 2 μm, such as 1.2 μm, 1.5 μm, or 1.8 μm, etc., and the thickness of the channel layer at the gate electrode ranges from 400 nm to 600 nm, such as 420 nm, 500 nm, or 580 nm, etc., so that the threshold voltage can reach more than twice the threshold voltage of the traditional transistor, realizing the high threshold voltage requirement of the transistor. Of course, as the thickness difference between the two parts of the channel layer increases, the threshold voltage will increase slightly, but the device current capacity will decrease slightly at the same time, and the decrease amplitude of the current capacity is slightly greater than the increase amplitude of the threshold voltage. Therefore, the above thickness difference of the channel layer can be adjusted according to actual needs.

[0034] Further, the lower boundary of the channel layer corresponding to the source electrode is flush with the lower boundary of the channel layer corresponding to the gate electrode and is at the same height.

[0035] In a possible design, the thickness of the buffer layer ranges from 1 μm to 2 μm; and / or the thickness of the barrier layer ranges from 15 nm to 30 nm; and / or the width of the doping layer ranges from 150 nm to 250 nm.

[0036] In this design, specifically, the thickness of the buffer layer ranges from 1 μm to 2 μm, such as 1.2 μm, 1.5 μm, or 1.8 μm, etc., the thickness of the barrier layer ranges from 15 nm to 30 nm, such as 15 nm, 20 nm, or 25 nm, etc., and the width of the doping layer ranges from 150 nm to 250 nm, such as 160 nm, 200 nm, or 240 nm, etc., which is beneficial to ensuring that the current capacity of the transistor is basically not affected when the voltage is higher than the self-voltage.

[0037] In a possible design, the substrate is any one of an Si substrate, an SiC substrate, a GaN substrate, and a sapphire substrate; the buffer layer is an AlGaN layer; the channel layer is a GaN layer; the barrier layer is an AlGaN layer; the doping layer is a P-type AlGaN layer or a P-type GaN layer.

[0038] In this design, specifically, the substrate is any one of an Si substrate, an SiC substrate, a GaN substrate, and a sapphire substrate, the buffer layer is an AlGaN layer, the channel layer is a GaN layer, the barrier layer is an AlGaN layer, and the doping layer is a P-type AlGaN layer or a P-type GaN layer, realizing a P-type gate GaN high electron mobility transistor with a high threshold voltage. Specifically, considering both high performance and economy, an Si substrate can be selected. The buffer layer is an Al x Ga 1-x N buffer layer, where the relative molar fraction x of the Al element is less than or equal to 0.1, such as 0.02, 0.05, or 0.08, etc.; the barrier layer is an Al y Ga 1-y N barrier layer, where the relative molar fraction y of the Al element ranges from 0.15 to 0.3. As the thickness of the barrier layer increases, the threshold voltage decreases and the current capacity increases. However, as the molar fraction of the Al element increases, the threshold voltage decreases and the current capacity first increases and then decreases. Furthermore, through the above design, the transistor can achieve a high threshold voltage while not having a great impact on the current capacity. The doping concentration range of the P-type impurity is 3 16 cm -3 to 3 18 cm -3 . Within this range, as the doping concentration increases, the threshold voltage slightly increases and the current capacity is basically not affected. In addition, the materials of the gate, drain, and source can be selected as metal alloys.

[0039] The additional aspects and advantages of the present invention will become apparent in the following description section, or be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and / or additional aspects and advantages of the present invention will become apparent and be easily understood from the description of the embodiments in conjunction with the following drawings, where:

[0041] Figure 1 shows a cross-sectional schematic diagram of a P-type GaN transistor in the related art;

[0042] Figure 2 shows a cross-sectional schematic diagram of a GaN high electron mobility transistor according to an embodiment of the present invention.

[0043] Among them, Figure 1 the corresponding relationship between the reference numerals in the drawings and the component names is:

[0044] 110'substrate, 120'buffer layer, 130'channel layer, 140'two-dimensional electron gas, 150'barrier layer, 160'doping layer, 170'passivation layer, 180'source electrode, 190'gate electrode, 200'drain electrode;

[0045] Figure 2 The corresponding relationship between the reference numerals and the component names in the figure is as follows:

[0046] 110 substrate, 120 buffer layer, 130 channel layer, 140 two-dimensional electron gas, 150 barrier layer, 160 doping layer, 170 passivation layer, 180 source electrode, 190 gate electrode, 200 drain electrode. Specific embodiments

[0047] In order to more clearly understand the above objects, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, without conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

[0048] In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited by the specific embodiments disclosed below.

[0049] The following refers to Figure 2 Describe a GaN high electron mobility transistor according to some embodiments of the present invention.

[0050] Embodiment 1:

[0051] A GaN high electron mobility transistor, as Figure 2 shown, includes: a substrate 110; a buffer layer 120 disposed on the substrate 110; a channel layer 130 disposed on the buffer layer 120; a barrier layer 150 disposed on the channel layer 130; a doping layer 160 disposed on the barrier layer 150; a source electrode 180 disposed on the channel layer 130 and located on one side of the barrier layer 150; a drain electrode 200 disposed on the channel layer 130 and located on the other side of the barrier layer 150; a gate electrode 190 disposed on the side of the doping layer 160 close to the drain electrode 200; wherein, a two-dimensional electron gas 140 is formed on the side of the critical interface between the channel layer 130 and the barrier layer 150 close to the channel layer 130, and the height of the channel layer 130 at the source electrode 180 is greater than the height of the channel layer 130 at the gate electrode 190.

[0052] The GaN high electron mobility transistor proposed by the present invention includes a substrate 110, a buffer layer 120, a channel layer 130, a barrier layer 150, and a doping layer 160 that are sequentially distributed from bottom to top. It also includes a source electrode 180 and a drain electrode 200 located on the top of the channel layer 130, and a gate electrode 190 located above the barrier layer 150. Among them, the source electrode 180, the drain electrode 200, and the barrier layer 150 are all disposed on the channel layer 130. The source electrode 180 and the drain electrode 200 are respectively located on the left and right sides of the barrier layer 150. A high-concentration two-dimensional electron gas 140 is present on the side of the critical point between the channel layer 130 and the barrier layer 150 close to the channel layer 130. There is an electric field from the drain electrode 200 to the source electrode 180 in the transistor. Due to the presence of a high concentration of 2-DEG at the interface between the channel layer 130 and the barrier layer 150 in the non-depletion region, this electric field will cause the high-concentration 2-DEG on the source electrode 180 side of the gate electrode 190 to move towards the drain electrode 200 side. Therefore, this electric field promotes the conduction of the channel under the gate electrode 190, which results in a lower threshold voltage of the device in the related art. Specifically, as Figure 1 shown, the transistor in the related art includes a substrate 110', a buffer layer 120', a channel layer 130', a barrier layer 150', a doping layer 160', a source electrode 180', a drain electrode 200', and a gate electrode 190' from bottom to top. And there is a two-dimensional electron gas 140' on the side of the critical point between the channel layer 130' and the barrier layer 150' close to the channel layer 130'. Since the thickness of the channel layer 130' is the same everywhere, it will naturally cause the high-concentration 2-DEG on the source electrode 180' side of the gate electrode 190' to move towards the drain electrode 200' side after the transistor is powered on. Although the conduction performance is strong, the threshold voltage is low. In this application, by making the height of the channel layer 130 at the source electrode 180 greater than the height of the channel layer 130 at the gate electrode 190, that is, the height of the channel layer 130 is not the same everywhere, that is, the heights of the upper boundaries of the channel layer 130 are not the same everywhere, and the height of the channel layer under the source electrode 180 is greater than the height of the channel layer under the gate electrode 190, when the transistor is powered on, the flow direction of the high-concentration 2-DEG is from top to bottom. This method largely avoids or weakens the action of the electric field between the source electrode 180 and the drain electrode 200, so that the threshold voltage of the device, that is, the transistor of this application, has a large increase. While significantly increasing the threshold voltage of the device, it does not cause a decrease in the current capacity, and does not affect the device performance, such as the conduction performance, and has strong anti-interference ability. The threshold voltage of the P-type gate structure device in the related art is generally below 1.5V, while the threshold voltage of the transistor proposed in this application can reach above 3V. Moreover, on the premise of appropriately reducing its conduction characteristics, the threshold voltage can be further increased, and the threshold voltage can be increased by more than 2 times.

[0053] In addition, according to theoretical analysis and simulation calculation results, when the voltage between the fixed drain 200 and the source 180 is constant, the drain current of the device is proportional to the gate width (i.e., the effective length between the gate 190 and the barrier layer 150), and inversely proportional to the length of the cut-off channel (i.e., the channel where a part of the two-dimensional electron gas 140 corresponding to the gate 190 in the direction of the barrier layer 150 in the two-dimensional electron gas 140). In the application, since the height of the channel layer 130 at the source 180 is greater than the height of the channel layer 130 at the gate 190, compared with Figure 1 the channel layer 130' in the related art shown, where the thickness and height of each part are the same, it makes the channel near the gate 190 of the channel layer 130 tend to extend vertically. The thickness of this part of the channel can be shorter than the cut-off channel length of the traditional P-type gate, and the contact surface between the gate 190 and the relatively horizontally extending channel increases the gate width. Therefore, as the cut-off channel length decreases and the gate width increases, the current capacity of the device does not decrease significantly. Due to the existence of this characteristic, after optimizing the structural parameters, the current capacity of the device can even be increased to a certain extent, and the threshold voltage of the transistor can be increased.

[0054] Moreover, the current capacity of the device in this application is hardly affected by the concentration of the P-type doping layer 160, because the influence of the gate width and the cut-off channel length on the current capacity of the device is much greater than the influence of the P-type doping concentration. At this time, the influence of the concentration of the P-type doping layer 160 on the current capacity of the device can be ignored. Since it is still relatively difficult to achieve a high P-type doping concentration in the production process of power devices, the transistor in this application can also reduce the requirements for the process in device production and manufacturing.

[0055] It should be noted that in this application, the height direction of the channel layer 130 is the same as the thickness direction of the channel layer 130. The height of the channel layer 130 refers to the height where the upper boundary of the channel layer 130 is located. When the heights of the lower boundaries of the channel layer 130 are the same and on the same horizontal plane, the height of each part of the channel layer 130 is equal to the thickness of the channel layer 130 at the corresponding position. The height direction of the channel layer 130 is the same as the height direction of the whole transistor.

[0056] In a specific embodiment, as Figure 2 shown, the channel layer 130 includes a horizontal channel layer and a vertical channel layer. The horizontal channel layer extends in the horizontal direction, and the vertical channel layer extends in the thickness direction of the horizontal channel layer and is located on the side of the horizontal channel layer close to the source 180. The height of the vertical channel layer is greater than the height of the horizontal channel layer.

[0057] In this embodiment, specifically, the channel layer 130 includes a horizontal channel layer and a vertical channel layer. The horizontal channel layer extends in the horizontal direction, and the vertical channel layer extends in the thickness direction of the horizontal channel layer. Since the horizontal channel layer and the vertical channel layer are simple in extension, the overall channel layer 130 is convenient to process. Moreover, since the height of the vertical channel layer is greater than the height of the horizontal channel layer, after the transistor is powered on, it is easier for the high-concentration 2-DEG to flow from top to bottom, weakening the effect of the electric field between the source 180 and the drain 200, thereby increasing the threshold voltage of the transistor. Moreover, the magnitude of the threshold voltage can be increased by adjusting the height difference between the vertical channel layer and the horizontal channel layer, and the threshold voltage can increase as the height difference between the vertical channel layer and the horizontal channel layer increases.

[0058] It should be noted that, in this application, the thickness direction of each layer is the direction from the substrate 110 to the barrier layer 150. The horizontal direction is the relatively horizontal direction and is always perpendicular to the thickness direction of the substrate 110.

[0059] Further, the source 180 is disposed on the vertical channel layer, and the gate 190 is disposed on the side of the horizontal channel layer away from the buffer layer 120. This is convenient for processing. For example, the source 180 is disposed on the left side of the upper boundary of the vertical channel layer, the drain 200 is disposed on the right side of the upper boundary of the horizontal channel layer, and the gate 190 is located between the source 180 and the drain 200 and above the middle of the horizontal channel layer.

[0060] Further, the barrier layer 150 is distributed in a zigzag shape in the height direction of the channel layer 130. Since the barrier layer 150 is adjacent to the channel layer 130, there must be a height difference between the left and right sides of the channel layer 130. After the transistor is powered on, it is easier for the high-concentration 2-DEG to flow from top to bottom, weakening the effect of the electric field between the source 180 and the drain 200, thereby increasing the threshold voltage of the transistor. Among them, the barrier potential layer can be roughly in a zigzag shape. The middle part of the barrier potential layer can extend vertically, that is, extend in the height direction of the channel layer 130, or can also extend obliquely.

[0061] In another specific embodiment, the channel layer 130 includes an inclined channel layer. The upper boundary of the inclined channel layer near the source 180 slopes upward, and the upper boundary of the inclined channel layer near the drain 200 slopes downward.

[0062] In this embodiment, the channel layer 130 may only include an inclined channel layer. By making the upper boundary of the inclined channel layer close to the source 180 tilt upward and the upper boundary of the inclined channel layer close to the drain 200 tilt downward, the height of the part of the channel layer 130 below the source 180 is greater than the height of the part of the channel layer 130 below the drain 200. When the transistor is powered on, the flow direction of the high-concentration 2-DEG is from top to bottom. In this way, the action of the electric field between the source 180 and the drain 200 is avoided to a great extent, resulting in a significant increase in the threshold voltage of the transistor without causing a decrease in the current-carrying capacity while significantly increasing the threshold voltage of the device.

[0063] Of course, in addition to the inclined channel layer, the channel layer 130 may further include a horizontal channel layer and / or a vertical channel layer. At this time, the inclined channel layer may be located between the horizontal channel layer and the vertical channel layer, which is convenient for processing. Or, the inclined channel layer is located on the side of the horizontal channel layer close to the source 180, or the inclined channel layer is located on the side of the vertical channel layer close to the drain 200, etc. The shape and position of the channel layer 130 can be adjusted according to the required magnitude of the threshold voltage.

[0064] Furthermore, the lower boundary of the inclined channel layer extends in the horizontal direction, which is convenient for processing. Of course, the lower boundary of the inclined channel layer may also have a certain angle with the horizontal plane. The opening of this angle may face the side where the drain 200 is located and is an acute angle.

[0065] Embodiment Two:

[0066] Based on the above Embodiment One, as Figure 2 shown, it is further defined that the height of the gate 190 is lower than the height of the source 180.

[0067] As Figure 1 shown in the transistor of the related art, the height of the gate 190' is the same as the height of the source 180' and the height of the drain 200', so that the thickness of the channel layer 130' is also the same everywhere. In this embodiment, by making the height of the gate 190 lower than the height of the source 180 and also lower than the height of the drain 200, the height of the part of the channel layer 130 corresponding to the gate 190 and the drain 200 also decreases accordingly, which is beneficial to matching the height of the part of the channel layer 130 below the source 180 being greater than the height of the part of the channel layer 130 below the gate 190. When the transistor is powered on, it is easier to make the high-concentration 2-DEG flow from top to bottom, weakening the action of the electric field between the source 180 and the drain 200, thereby increasing the threshold voltage of the transistor.

[0068] Furthermore, as Figure 2 shown, the height of the channel layer 130 at the source 180 is greater than the height of the channel layer 130 at the drain 200.

[0069] Further, as Figure 2 shown, the lower boundary of the source electrode 180 is higher than the lower boundary of the drain electrode 200. And the upper boundaries of the source electrode 180 and the drain electrode 200 are at the same height.

[0070] Embodiment Three:

[0071] Based on any of the above embodiments, as Figure 2 shown, it is further defined that the GaN high electron mobility transistor further includes: a passivation layer 170. A first part of the passivation layer 170 is disposed above the barrier layer 150, the source electrode 180, and the drain electrode 200. A second part of the passivation layer 170 is disposed between the doped layer 160 and the barrier layer 150. A third part of the passivation layer 170 is disposed between the gate electrode 190 and the barrier layer 150.

[0072] In this embodiment, the GaN high electron mobility transistor further includes a passivation layer 170. The passivation layer 170 includes three parts. The first part is disposed above the barrier layer 150, the source electrode 180, and the drain electrode 200. The second part is disposed between the doped layer 160 and the barrier layer 150. The third part is disposed between the gate electrode 190 and the barrier layer 150. The three parts are connected to each other, realizing the enclosure of the gate electrode 190 and the capping of the source electrode 180 and the drain electrode 200.

[0073] Further, the material of the passivation layer 170 is Si3N4, which can reduce the device leakage current and weaken the current collapse effect of the GaN device.

[0074] Embodiment Four:

[0075] Based on any of the above embodiments, it is further defined that the thickness of the channel layer 130 at the source electrode 180 ranges from 1 μm to 2 μm; and / or the thickness of the channel layer 130 at the gate electrode 190 ranges from 400 nm to 600 nm.

[0076] In this embodiment, specifically, the thickness of the channel layer 130 at the source electrode 180 ranges from 1 μm to 2 μm, such as 1.2 μm, 1.5 μm, or 1.8 μm, etc. The thickness of the channel layer 130 at the gate electrode 190 ranges from 400 nm to 600 nm, such as 420 nm, 500 nm, or 580 nm, etc., so that the threshold voltage can reach more than twice the threshold voltage of the traditional transistor, realizing the high threshold voltage requirement of the transistor. Of course, as the thickness difference of the channel layer 130 at the above two places increases, the threshold voltage will increase slightly, but the device current capacity will decrease slightly at the same time, and the decrease amplitude of the current capacity is slightly greater than the increase amplitude of the threshold voltage. Therefore, the above thickness difference of the channel layer 130 can be adjusted according to actual needs.

[0077] Further, the lower boundary of the channel layer 130 corresponding to the source electrode 180 is flush with the lower boundary of the channel layer 130 corresponding to the gate electrode 190, and they are at the same height.

[0078] Further, the thickness of the buffer layer 120 ranges from 1 μm to 2 μm; and / or the thickness of the barrier layer 150 ranges from 15 nm to 30 nm; and / or the width of the doping layer 160 ranges from 150 nm to 250 nm. By making the thickness of the buffer layer 120 range from 1 μm to 2 μm, such as 1.2 μm, 1.5 μm or 1.8 μm, etc., making the thickness of the barrier layer 150 range from 15 nm to 30 nm, such as 15 nm, 20 nm or 25 nm, etc., and making the width of the doping layer 160 range from 150 nm to 250 nm, such as 160 nm, 200 nm or 240 nm, etc., it is beneficial to ensure that the current capacity of the transistor is basically not affected when the voltage is higher than the self-voltage.

[0079] Further, the substrate 110 is any one of an Si substrate, an SiC substrate, a GaN substrate and a sapphire substrate; the buffer layer 120 is an AlGaN layer; the channel layer 130 is a GaN layer; the barrier layer 150 is an AlGaN layer; the doping layer 160 is a P-type AlGaN layer or a P-type GaN layer. Specifically, considering both high performance and economy, an Si substrate can be selected. The buffer layer 120 is an Al x Ga 1-x N buffer layer, where the relative molar fraction x of the Al element is 0.05; the barrier layer 150 is an Al y Ga 1-y N barrier layer, where the relative molar fraction y of the Al element ranges from 0.15 to 0.3. As the thickness of the barrier layer 150 increases, the threshold voltage decreases and the current capacity increases. However, as the molar fraction of the Al element increases, the threshold voltage decreases and the current capacity first increases and then decreases. Furthermore, through the above design, the transistor can achieve a high threshold voltage while the current capacity is not greatly affected. The doping concentration range of the P-type impurity is 3 16 to 3 18 cm -3 . Within this range, as the doping concentration increases, the threshold voltage slightly increases and the current capacity is basically not affected. In addition, the materials of the gate electrode 190, the drain electrode 200 and the source electrode 180 can be selected as metal alloys.

[0080] Example Five:

[0081] A GaN high electron mobility transistor according to an embodiment of the present invention is introduced in detail, which includes an Si substrate, an AlxGa1-xN buffer layer, a GaN channel layer, an AlyGa1-yN barrier layer, a P-type GaN layer, and an Si3N4 passivation layer distributed from bottom to top, and also includes a source electrode 180, a gate electrode 190, and a drain electrode 200. Among them, a high-concentration two-dimensional electron gas exists on the side close to the GaN channel layer at the interface between the GaN channel layer and the AlyGa1-yN barrier layer. The source electrode 180 is disposed on the GaN channel layer and on one side of the AlyGa1-yN barrier layer; the drain electrode 200 is disposed on the GaN channel layer and on the other side of the AlyGa1-yN barrier layer; the gate electrode 190 is disposed on the side of the P-type GaN close to the drain electrode.

[0082] Specifically, the thickness of the AlxGa1-xN buffer layer is 1 um to 2 um, and the value of the relative molar fraction x of Al element is less than or equal to 0.1, such as 0.03, 0.05, or 0.07, etc.

[0083] Specifically, the source electrode 180 is disposed on the upper left side of the GaN channel layer, the drain electrode 200 is disposed on the upper right side of the GaN channel layer, the gate electrode 190 is disposed in the middle of the upper part of the GaN channel layer, the thickness of the right side of the GaN channel layer is 500 nm, and the value range of the thickness of the left side is 1 um to 2 um. As the height difference between the left and right sides increases, assuming the left and right sides are the left and right sides when looking straight ahead, the threshold voltage will increase slightly, but the current capacity of the device will decrease slightly at the same time, and the decrease amplitude of the current capacity is slightly larger than the increase amplitude of the threshold voltage. Therefore, the height difference between the left and right sides of the channel layer 130 can be adjusted according to actual needs. Figure 2 When, the threshold voltage will increase slightly, but the current capacity of the device will decrease slightly at the same time, and the decrease amplitude of the current capacity is slightly larger than the increase amplitude of the threshold voltage. Therefore, the height difference between the left and right sides of the channel layer 130 can be adjusted according to actual needs.

[0084] Specifically, the thickness value range of the AlyGa1-yN barrier layer is 15 nm to 30 nm, and the relative molar fraction y of Al element is 0.15 to 0.3. As the thickness of the barrier layer 150 increases, the threshold voltage decreases, and the current capacity increases; as the molar fraction of Al element increases, the threshold voltage decreases, and the current capacity first increases and then decreases.

[0085] Specifically, the width of the P-type GaN layer is 200 nm, and the doping concentration range of P-type impurities is 3 16 -3 18 cm -3 . As the doping concentration increases, the threshold voltage increases slightly, and the current capacity is basically not affected. This is slightly different from traditional devices.

[0086] Specifically, the Si3N4 passivation layer material is mainly used to reduce the leakage current of the device and weaken the current collapse effect of the GaN device.

[0087] By using a traditional horizontal conductive channel (i.e., Figure 1In the transistor shown, the channel where the horizontally extended two-dimensional electron gas is located) is adjusted to a combination of horizontal and vertical channels. The improved conductive channel is approximately Z-shaped, effectively increasing the threshold voltage of the device without significantly affecting the current-carrying capacity. Moreover, in the improved structure, the length of the cutoff channel is reduced while the gate width is increased, so that the current-carrying capacity of the improved device is not significantly degraded. In addition, the current-carrying capacity of the transistor is hardly affected by the concentration of the P-type doping layer, which also requires a very high doping concentration for this P-type doping, reducing the requirements for the process in device manufacturing.

[0088] In the present invention, the term "a plurality of" refers to two or more, unless otherwise clearly defined. Terms such as "mounted", "connected", "connected to", "fixed" and the like should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; "connected" can be a direct connection or an indirect connection through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. In the description of this specification, the description of terms such as "one embodiment", "some embodiments", "specific embodiments" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0089] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A GaN high electron mobility transistor, characterized in that, Comprising: A substrate; A buffer layer disposed on the substrate; A channel layer disposed on the buffer layer; A barrier layer disposed on the channel layer; A doping layer disposed on the barrier layer; A source electrode disposed on the channel layer and on one side of the barrier layer; A drain electrode disposed on the channel layer and on the other side of the barrier layer; A gate electrode disposed on the side of the doping layer close to the drain electrode; Wherein, a two-dimensional electron gas exists on the side of the critical point between the channel layer and the barrier layer close to the channel layer, and the height of the channel layer at the source electrode is greater than the height of the channel layer at the gate electrode; The height of the channel layer at the source electrode is greater than the height of the channel layer at the drain electrode; The channel layer only includes an inclined channel layer, the upper boundary of the inclined channel layer is inclined upward near the source electrode, and the upper boundary of the inclined channel layer is inclined downward near the drain electrode; The height of the lower boundary of the channel layer is the same everywhere; The lower boundary of the inclined channel layer extends in the horizontal direction; The GaN high electron mobility transistor further includes a passivation layer, a first part of the passivation layer is disposed above the barrier layer, the source electrode and the drain electrode, a second part of the passivation layer is disposed between the doping layer and the barrier layer, and a third part of the passivation layer is disposed between the gate electrode and the barrier layer; The material of the passivation layer is Si3N4; The height of the gate electrode is lower than the height of the source electrode, and the height of the gate electrode is lower than the height of the drain electrode.

2. The GaN high electron mobility transistor according to claim 1, wherein The thickness of the channel layer at the source electrode ranges from 1 μm to 2 μm; and / or The thickness of the channel layer at the gate electrode ranges from 400 nm to 600 nm.

3. The GaN high electron mobility transistor according to claim 1, wherein The thickness of the buffer layer ranges from 1 μm to 2 μm; and / or The thickness of the barrier layer ranges from 15 nm to 30 nm; and / or The width of the doping layer ranges from 150 nm to 250 nm.

4. The GaN high electron mobility transistor according to claim 1, wherein The substrate is any one of an Si substrate, an SiC substrate, a GaN substrate and a sapphire substrate; The buffer layer is an Al x Ga 1-x N buffer layer, where the relative molar fraction x of the Al element has a value less than or equal to 0.1; The channel layer is a GaN layer; The barrier layer is Al y Ga 1-y N barrier layer, where the relative molar fraction y of the Al element ranges from 0.15 to 0.3; The doping layer is a P-type AlGaN layer or a P-type GaN layer.

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