Ultra-low power, real-time clock generator and jitter compensation method

Abstract

The present disclosure relates to an ultra-low-power, real-time clock generator and a jitter compensation method. In one embodiment, the clock generator includes a variable modulus divider that receives a high-frequency clock signal and outputs a divided clock signal having a frequency controlled by a modulus control signal generated by a temperature compensation circuit. A jitter filter is coupled to the output of the variable modulus divider and to the temperature compensation circuit and generates a compensated clock signal having a switching edge that is delayed relative to the divided clock signal by a time associated with a quantization error signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Application No. 102018000010577, filed on November 26, 2018, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to electronic systems and methods, and in particular embodiments, to an ultra-low power (ULP), real-time clock (RTC) generator and jitter compensation methods. Background Art

[0004] As is well known, in electronic devices (whether portable or not) such as mobile phones, video or photo cameras, automotive devices, household appliances, data collection terminals, smart card readers, etc., an RTC generator is often used with a clock function to count time even when the corresponding electronic device is turned off. For this reason, it is generally desired that the above-mentioned RTC generator operates at low power and therefore has a low consumption level.

[0005] Typically, an RTC generator includes a resonator for generating an operating frequency equal to a desired value (eg, 32.768 kHz) or a multiple of the desired value, and an electronic module coupled to the resonator for counting time based on the operating frequency.

[0006] While quartz technology has dominated the field of frequency generation for decades (also used in applications such as RTCs), MEMS resonators manufactured using semiconductor technology (particularly silicon) have recently been proposed with greater success.

[0007] In fact, MEMS resonators are characterized by significant size control and considerable cost reduction, thanks to the possibility of utilizing standard processes for manufacturing integrated circuits. Thus, they support the low-cost integration of micromechanical structures and corresponding electronic processing circuits (e.g., ASICs (Application Specific Integrated Circuits)). In addition, MEMS resonators are generally more resistant to shocks and mechanical stresses.

[0008] A MEMS resonator comprises a resonant micromechanical structure fabricated using micromachining techniques that is induced to vibrate at its natural resonant frequency due to external stresses (including an appropriate DC bias and AC drive signal). The resonant micromechanical structure typically includes at least one movable mass anchored to a substrate by suitable constraining elements and driven in resonant motion by the applied bias and drive signal.

[0009] For example, Figure 1Shown is a block diagram of an RTC generator 1 comprising a MEMS resonator 2 and an electronic processing circuit 3 which may be formed by an ASIC.

[0010] The electronic processing circuit 3 typically comprises an amplifier stage (not shown), for example comprising a current-to-voltage converter stage with a gain Gm connected in feedback to the resonant micromechanical structure, which receives the sense signal and converts it into a resonant frequency signal.

[0011] Typically, the electronic processing circuit further comprises an output stage coupled to the output of the amplifier stage of the MEMS resonator and configured to provide an output signal at the operating frequency and having a desired value.

[0012] The MEMS resonator 2 and the electronic processing circuit 3 may each be fabricated in a respective die of semiconductor material, in particular silicon, and may be housed within the same package defining an integrated system (chip).

[0013] In this type of clock generator, the stability of the frequency of the output signal is an important aspect, since it directly represents the quality factor of the device.

[0014] However, the resonant frequency of a MEMS resonator is proportional to the square root of the Young's modulus of the material of the movable mass of the resonating micromechanical structure, which varies depending on the temperature. For example, Figure 2 The relative change Δf / f of the frequency as a function of the temperature of a typical RTC generator is shown.

[0015] A wide range of solutions have been proposed to try to address the problem of resonant frequency variation with temperature. However, improvements can be made to achieve low jitter, as well as low area usage (footprint) and reduced power consumption levels.

[0016] For example, in the IEEE Journal of Solid-State Circuits, Vol. 50, No. 1, January 2015, S. Zaliasl et al. reported “A 3ppm 1.5x 0.8mm 2 A known solution is described in "1.0μA 32.768kHz MEMS-Based Oscillator". The clock generator described in this paper includes a MEMS resonator and a temperature compensation circuit, and is composed of Figure 3 Block diagram representation of .

[0017] Specifically, Figure 3The clock generator includes: a resonant micromechanical structure 10; a current-to-voltage converter stage 11 with a gain Gm, which is connected to the resonant micromechanical structure 10 and generates a resonant signal HFCK at a resonant frequency; a temperature compensation circuit 12, which receives the resonant signal HFCK and a compensation code COD and generates a compensated clock signal CLKO; a code generator 13, which generates the compensation code COD; and an output drive circuit 14.

[0018] The temperature compensation circuit 12 described in the above paper includes a fractional phase-locked loop (PLL), which includes a frequency divider 16 with a variable modulus. The frequency divider 16 divides the resonant signal HFCK by a value N or N+1 based on a control signal (modulus control signal MC) provided by a delta-sigma modulator 17 and controls a PLL circuit 18.

[0019] Here, the code generator 13 is of programmable type and comprises a multiplexer 20 which provides the delta-sigma modulator 17 with a constant value K (for example, set at the factory and provided by a block 21) or a value related to the temperature T detected by a detection block 22 as a compensation code COD.

[0020] The modulus control signal MC generated by the delta-sigma modulator 17 represents the average value of the frequency deviation of the divided clock signal CLK_D relative to the nominal value.

[0021] In use, the frequency divider 16 divides the resonant signal HFCK by N to obtain the desired output frequency (the divided clock signal CLK_D), except when the modulus control signal MC needs to be divided by N+1; in this case, the frequency divider 16 extends the duration of the period of the divided clock signal CLK_D (see also Figure 4 , which is based on the purely illustrative assumption that N=4).

[0022] In practice, the frequency division by a factor of N or N+1 on the part of the frequency divider 16 only results in a frequency of the divided clock signal CLK_D being equal to the nominal frequency on average, but results in each switching of the divided clock signal CLK_D occurring at a time different from the nominal time. Consequently, the divided clock signal CLK_D is subject to a high jitter, which is much higher than the jitter introduced by electronic or thermomechanical noise.

[0023] In order to reduce the jitter of the divided clock signal CLK_D, the above paper uses a PLL circuit 18, which filters the divided clock signal CLK_D and outputs a filtered clock signal CLKO. Figure 4 Indicated in.

[0024] The use of the PLL circuit 18 requires the use of a voltage controlled oscillator (VCO) operating at a multiple of the frequency of the filtered clock signal CLKO. Consequently, the known solutions have high consumption levels and are difficult to use in portable and / or low power supply devices and apparatuses.

[0025] Furthermore, it uses large components, requiring a high area consumption for implementation. For this reason, it is also difficult to use in small portable devices and equipment, and in any case increases the cost of the equipment. On the other hand, existing solutions that enable the design of PLL circuits to significantly reduce the size of these components result in a corresponding increase in design complexity. Summary of the Invention

[0026] Some embodiments provide a clock generator that overcomes the shortcomings of the prior art.

[0027] Some embodiments relate to an ultra-low power, real-time clock generator using a microelectromechanical system (MEMS) resonator.

[0028] According to some embodiments, for example as defined in the accompanying claims, a clock generator and a method for generating a clock signal are provided.

[0029] In some embodiments, a clock generator and corresponding method start from the consideration that the jitter on the output signal of a fractional frequency divider used in the known generator is not of random arbitrary type, but is deterministic and can therefore be compensated.

[0030] In particular, since the delta-sigma modulation module that controls the fractional divider, in addition to generating the control signal for the fractional divider, also contains information related to the value of the quantization error, and indeed the latter is related to the phase error of the clock signal provided by the fractional divider, this information can be used to compensate for the jitter of the clock signal by delaying the corresponding switching edge.

[0031] Alternatively, in some embodiments, compensation for jitter may also be obtained using a delayed sequence of preset values, which are increased until the division modulus of the fractional divider is modified.

[0032] Indeed, in some embodiments, the clock generator does not act on the frequency of the signal, but rather adjusts the phase of a single switching edge. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] For a better understanding of the present invention and its advantages, embodiments of the present invention will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0034] Figure 1 This is a very simplified block diagram of a MEMS resonator-based clock generator;

[0035] Figure 2 shows the frequency variation of a MEMS clock generator according to temperature;

[0036] Figure 3 shows a block diagram of a known MEMS clock generator with temperature correction;

[0037] Figure 4 Shown Figure 3 Example of plotting signals in a MEMS clock generator;

[0038] Figure 5 A block diagram of a MEMS clock generator according to an embodiment of the present invention is shown;

[0039] Figure 6 An embodiment of the present invention is shown Figure 5 A possible implementation of a block of a MEMS clock generator;

[0040] Figure 7 An embodiment of the present invention is shown Figure 5 MEMS clock generators and Figure 6 An example of the behavior of signals in a block;

[0041] Figure 8 A schematic diagram illustrating a method for correcting jitter in a MEMS clock generator according to an embodiment of the present invention is shown;

[0042] Figure 9 An embodiment of the present invention is shown Figure 5 A possible implementation of a block of a MEMS clock generator;

[0043] Figure 10 shows an embodiment of the present invention. Figure 9 a plot of the signals in the blocks shown; and

[0044] Figure 11 An embodiment of the present invention is shown Figure 5 Another possible implementation of a MEMS clock generator block. DETAILED DESCRIPTION

[0045] Figure 5 Shown is a simplified block diagram of a clock generator, designated generally by 30, according to one embodiment of the present invention.

[0046] The clock generator 30 includes a resonant micromechanical structure 31 and an electronic processing circuit 32 coupled to the resonant micromechanical structure 31. For example, the resonant micromechanical structure 31 and the electronic processing circuit 32 may be integrated in respective dies of semiconductor material, in particular silicon, and the dies may be housed in the same package.

[0047] The resonant micromechanical structure 31 of the MEMS type comprises, in a manner known per se (not shown), a movable structure, a drive electrode and a sense electrode. For example, the movable structure may be of the so-called "double clamped" or "two-end clamped" type, although other types of structures, simpler or more complex, may also be used.

[0048] The electronic processing circuit 32 includes: a current / voltage converter stage 33 with a gain Gm, which is connected to the resonant micromechanical structure 31 at an input 32A and generates a high-frequency digital clock signal, hereinafter referred to as the “resonant clock signal HFCK”, which has a frequency equal to the resonant frequency of the resonant micromechanical structure 31, for example, approximately 524 kHz; a frequency divider 34, which receives the resonant clock signal HFCK and generates a divided clock signal DIV at an output 34B having a desired frequency on average (for example, approximately equal to 32 kHz); a jitter suppression filter 35, which is connected to the output of the frequency divider 34 and generates the output clock signal OUT; and a temperature compensation stage 36, which generates a modulus control signal MC and a quantization error signal QE, the modulus control signal MC being provided to the control input 34A of the frequency divider 34, and the quantization error signal QE being provided to the control input 35A of the jitter suppression filter 35.

[0049] The temperature compensation stage 36 may be formed in a known manner and broadly comprises: a temperature sensor 40 configured to measure the temperature of the resonant micromechanical structure 31 and to output a temperature signal T; a compensation code generator circuit 41 receiving the temperature signal T and generating an associated correction code COD, for example based on a stored table or via an appropriate calculation structure; and a digital delta-sigma modulator (DDSM) 42 generating a modulus control signal MC and a quantization error signal QE.

[0050] For better understanding, the delta-sigma modulator 42 can be made in a known manner, for example, as Figure 6 and described below.

[0051] Specifically, Figure 6The delta-sigma modulator 42 includes an adder 45 having a first input 45A receiving a correction code COD, a second input 45B receiving the output of a digital delay element 46, a first output 45C providing a modulus control signal MC, and a second output 45D providing a sum signal SUM, which corresponds to the quantization error signal QE, as discussed below. (Thus, hereinafter, the terms "sum signal SUM" or "quantization error signal QE" will be used generically depending on the context.) The second output 45D of the adder 45 is connected to the input of the digital delay element 46, which thereby provides the sum signal SUM to the second input 45B of the adder 45.

[0052] In practice, the delta-sigma modulator 42 forms an integrator. The value of the sum signal SUM at the second output 45D (in binary code) represents the accumulation of previous values of the correction code COD and, at each counting cycle, is related to the time deviation between the switching edge of the divided clock signal DIV and the corresponding switching edge of the nominal clock (which is insensitive to temperature variations and corresponds to an integer ratio between the frequency of the resonant signal HFCK and the frequency of the divided clock signal DIV). Therefore, the value of the sum signal SUM forms a temporal quantization error at the switching edge of the divided clock signal DIV, while the signal at the first output 45C (modulus control signal MC) indicates an overflow, i.e., when the quantization error reaches a preset maximum value and is to be corrected by modifying the value. Figure 5 The frequency division modulus of the fractional frequency divider 34 is corrected.

[0053] In some embodiments, the value of the sum signal SUM is used to correct jitter in the clock generator. Specifically, in some embodiments, the clock delay generator delays each switching edge of the divided clock signal DIV based on the value of the sum signal SUM provided to the jitter suppression filter 35.

[0054] For a better understanding of the operation of the jitter suppression filter 35, also refer to the following description of Figure 7-Figure 8 .

[0055] First, you can refer to Figure 7 , which means Figure 5 Plot of some signals and related quantities of the clock generator 30.

[0056] Specifically, Figure 7 A series of switching edges of the resonant clock signal HFCK and a corresponding sequence of switching edges of the divided clock signal DIV are shown, which, for simplicity of illustration, result from a division by 2 or 3 (N=2). In particular, first (during the first six pulses of the divided clock signal DIV), a division by 2 is performed; then (after the sixth clock pulse), the temperature compensation stage 36 sets the division modulus to 3, which results in a temporary extension of the period of the divided clock signal DIV.

[0057] In practice, the sum signal SUM, which increases at each predetermined switching edge (e.g., rising edge) of the divided clock signal DIV, reaches its maximum value at the fifth switching edge and starts counting again when the sixth switching edge is received. When this occurs, the signal MC shows an overflow pulse.

[0058] Figure 7 The phase shift of the divided clock signal DIV relative to the nominal situation is also shown. In particular, curve A represents the nominal phase of the periodic signal, which increases linearly without quantization error (nominal phase curve A), curve B (actual phase curve B) represents the phase of the divided clock signal DIV, which is slightly higher than the nominal value of curve A as a result of the division by N, and curve C represents the error caused by the difference between the actual phase curve B and the nominal phase curve A, which is shown on an exaggerated scale.

[0059] As can be seen, the actual phase curve B increases faster (leads the phase) than the nominal phase curve A until an overflow pulse is generated in the modulus control signal MC. After the overflow pulse, the resonant clock signal HFCK is divided by N+1, and the divided clock signal DIV has an extended period. This corresponds to the application of a phase delay, and the actual phase curve B becomes lower than the nominal phase curve A. After this correction, the actual phase curve B begins to increase faster than the nominal phase curve A again.

[0060] Therefore, the above behavior is deterministic and supports point-by-point phase correction of the divided clock signal DIV, such as Figure 8 As shown in the figure.

[0061] Figure 8 The diagram of the sum signal SUM and the offset between the nominal phase curve A and different actual phase curves B1 is shown again on an enlarged scale (here based on the assumption that the correction always keeps the actual phase ahead of the nominal phase and that the actual phase curve B1 is therefore always to the left of the nominal phase curve A). Figure 8 The corresponding relationship between the value of the sum signal SUM at each pulse of the divided clock signal DIV and the corresponding value of the actual phase is also shown, and the corresponding instantaneous error phase is shown by arrow D. Since the error phase is known and is also the value of the sum signal SUM (quantization error QE), the error phase can be corrected by adding a delay equal to the quantization error to the value of the actual phase curve B1 at each cycle of the divided clock signal DIV.

[0062] For this purpose, refer again to Figure 5 , the jitter suppression filter 35 includes a delay generator 37 and a delay selection block 38 .

[0063] In particular, the delay generator 37 generates a plurality of delay pulses Φ[0], Φ[1]…Φ[i]…Φ[k] at the same frequency as the divided clock signal DIV, and the delay selection block 38 selects an appropriate delay pulse Φ[i] according to the instantaneous quantization error QE at each clock pulse.

[0064] Thus, the output clock signal OUT is formed by a sequence of switching edges, each switching edge being delayed with respect to a corresponding switching edge of the divided clock signal DIV by a value that compensates for the jitter.

[0065] In particular, the delay generator block 37 may be formed by a digital-to-time converter (DTC), e.g. Figure 9 The DTC 50 is formed.

[0066] In particular, Figure 9 In the embodiment of the present invention, the DTC 50 includes a plurality of delay stages 60_1, 60_2, ..., 60_i, ..., 60_k, which are sequentially connected and generate corresponding delay signals Φ[1], Φ[2], ..., Φ[i], ..., Φ[k], each delayed by a unit delay τ relative to the previous delay stage 60. The number of delay stages 60 is k=2. n , and the unit delay τ is equal to 1 / 2 of the end-of-scale delay value n In the following, the indexing of the delay stages 60 and the indexing of the delay signal Φ will only appear if necessary for understanding.

[0067] Each i-th delay stage 60_i includes a first inverter 65 and a second inverter 66 connected in series. Specifically, the first inverter 65 is formed by a first PMOS transistor 67 and a first NMOS transistor 68. The first PMOS transistor 67 and the first NMOS transistor 68 have drain terminals coupled together at a first node D coupled to the input of the second inverter 66; gate terminals coupled together at a second node G; and source terminals connected to a power supply line 70 and a ground line 71, respectively, through a second PMOS transistor 72 and a second NMOS transistor 73.

[0068] Except for the first delay stage (delay stage 60_1) which is directly coupled to the output of the divider 34 and receives the divided clock signal DIV, the second node G of each delay stage 60_i forms the input of the same delay stage 60_i connected to the output 66A of the second inverter 66 of the previous delay stage 60_i-1.

[0069] The outputs of the second inverters 66 of the delay stages 60_1, 60_2, ..., 60_i, ..., 60_k provide delayed signals Φ[1], Φ[2], ..., Φ[i], ..., Φ[k]. Each delayed signal Φ[i] is then input to a corresponding subsequent delay stage 60_i+1 (not shown) ..., except for the last delayed signal Φ[k] which is fed back to the input of the delay generator block 37 as described below.

[0070] The delay stage 60 is driven by a delay adjustment circuit 75 , which includes a falling edge adjustment branch 75 f and a rising edge adjustment branch 75 r that are similar to each other.

[0071] Specifically, the falling edge adjustment branch 75f includes a first detector block 76f and a first capacitor 77f. The first detector block 76f is formed by a phase detection and charge pump circuit PD+CP, and receives at its input the last delayed signal Φ[k] and the first reference signal REF f , and has a falling edge output 55f coupled to the gate terminals of the second PMOS transistors 72 of all the delay stages 60. A first capacitor 77f is coupled between the falling edge output 55f of the first detector block 76f and the ground line 71.

[0072] Similarly, the rising edge adjustment branch 75r includes a second detector block 76r and a second capacitor 77r, which are made and connected in the same manner as the corresponding components of the falling edge adjustment branch 75f. The second detector block 76f (also a phase detection and charge pump circuit PD+CP) inputs the last delayed signal Φ[k] and the second reference signal REF r , and has a rising edge output 55 r, which is coupled to the gate terminals of the second NMOS transistors 73 of all delay stages 60.

[0073] Phase detection and charge pump circuits PD+CP, 75r, 75f, configured in a known manner (e.g., as described in the paper "A 17-mW Transmitter and Frequency Synthesizer for 900-MHz GSM Fully Integrated in 0.35-μm CMOS" by E. Hegati, IEEE Journal of Solid-State Circuits, vol. 38, No. 5, May 2003), calculate the phase difference between the respective input signals and provide currents having an average value equal to the detected phase difference on the respective rising edge outputs 55r and falling edge outputs 55f. These currents support control of the conductivity of the second PMOS transistor 72 and the NMOS transistor 73, as well as adjustment of the delay of the delay stage 60, as described below.

[0074] Reference signal REF r and REF f ( Figure 10 (shown in the figure) is a signal with a corresponding pulse of constant width, which is equal to the expected maximum delay (the scaling end value, also called the "maximum delay time ΔT", as described below). Specifically, the first reference signal REF acts on the falling edge of the delayed signal Φ[i] f The second reference signal REF acting on the rising edge of the delayed signal Φ[i] has a transition from low to high at the falling edge of the divided clock signal DIV and returns to low after the maximum delay time ΔT. r The reference signal REF has a transition from high to low at the rising edge of the divided clock signal DIV and returns to high after the maximum delay time ΔT. f and REF r It is generated by a generator circuit (not shown) having only a few logic gates and made in a manner obvious to a person skilled in the art, starting from the resonant signal HFCK based on a maximum delay time ΔT (equal to the scale end value, as described below).

[0075] In fact, the rising edge adjustment branch 75r and the falling edge adjustment branch 75f adjust the phase of the corresponding switching edge of the last delayed signal Φ[k] to the corresponding reference signal REF r and REF f For each regulation branch 75r and 75f, the switching edges being compared are simultaneous under nominal and steady-state conditions, but are typically different at startup of the clock generator 30 (and therefore the DTC 50) and may have a small offset due to electronic noise and / or circuit biasing.

[0076] Specifically, when the DTC 50 is powered on, the offset between the corresponding switching edge and the last delayed signal Φ[k] is detected by detector blocks 76f and 76r. Each of the detector blocks 76f and 76r independently outputs a current related to the detected offset based on the corresponding switching edge. These currents charge the corresponding capacitors 77f and 77r, which in turn generate control voltages Vf and Vr for the second PMOS transistor 72 and the second NMOS transistor 73 of all delay stages 60_i, respectively. The second PMOS transistor 72 and the second NMOS transistor 73 of the delay stage 60_i represent choke elements that adjust the current supplied to the first inverter 65 of each delay stage 60_i based on the corresponding control voltages Vf and Vr, and their sizes are appropriately set. Therefore, depending on the size of the circuit and the phase shift detected by the detector blocks 76f and 76r, the first inverter 65 of each delay stage 60_i generates a delay relative to the input signal (the divided clock signal DIV, or the delayed signal Φ[i-1] provided by the previous delay stage 60_i-1).

[0077] Under steady-state operating conditions, the loop configuration of the DTC 50 is such that the total delay of the entire delay chain is equal to ΔT, i.e., equal to the period of the resonant signal HFCK (in the example considered, 1 / 524 kHz≈1.9 μs), and therefore such that the delay generated by each delay stage 60_1 is, in a first approximation, constant and equal to ΔT / k.

[0078] The above behaviors Figure 10 As can be seen, Figure 10 shows the divided clock signal DIV, the reference signal REF f and REF r , and the delayed signals Φ[1], Φ[2], …, Φ[i], …, Φ[k] that can be obtained therefrom.

[0079] In fact, in Figure 9 In the DTC 50, the delayed signals Φ[1], Φ[2], ..., Φ[k] have (under steady-state conditions and to a first approximation, neglecting any possible electronic noise and offset) constant identical periods and duty cycles, and each of the delayed signals has a different, increasing delay relative to the divided clock signal DIV. The delay increase (hereinafter also referred to as unit delay) of each delayed signal Φ[1], Φ[2], ..., Φ[k] relative to the previous delayed signal in the series is τ=ΔT / k.

[0080] In order to calculate the unit delay τ, and thus the number k of delay stages 60 to be provided for the design of the DTC 50, it is possible to proceed in the following manner.

[0081] In the DTC 50, the number of delay stages 60 is k=2n , i.e. the number of bits required for delay quantization, is associated with the scale end value FSR (also referred to above as the maximum delay ΔT) and the value of the least significant bit LSB (unit delay of each delay stage 60_i). Since the divided clock signal DIV is extended by a factor N or N+1 relative to the period of the resonant signal HFCK, the scale end value is equal to the period T of the resonant signal HFCK. osc , so that the maximum time error imposed on a single edge of the divided clock signal DIV is T osc The value of the least significant bit LSB is related in a known manner to the periodic quantization error σ. It can be shown that for the considered clock generator 30 the periodic quantization error σ is equal to half the value of the least significant bit LSB (σ=LSB / 2) in the worst case.

[0082] According to the relationship

[0083]

[0084] 2 of them n is the number of delay stages 60_i sought, in the example of application considered, where T osc =1 / 524 milliseconds, and the period quantization error σ is 30 ns (an acceptable value for the output clock signal OUT of 32 kHz), we obtain k=2 n =32(n=5).

[0085] In practice, the DTC 50 forms a DLL (Delay Locked Loop) circuit.

[0086] The delay signals Φ[1], Φ[2], ..., Φ[i], ..., Φ[k-1] thus obtained are provided to the delay selection block 38 together with the divided clock signal DIV, which selects the divided clock signal DIV or the delay signals Φ[1], Φ[2], ..., Φ[i], ..., Φ[k-1] having the corresponding delay values in each cycle of the divided clock signal DIV and based on the sum signal SUM, and outputs the corresponding signals DIV, Φ[1], Φ[2], ..., Φ[i], ..., Φ[k-1] as the output clock signal OUT in each cycle. In this way, the output clock signal OUT includes a series of clock pulses, each of which has zero delay (equal to Φ[0] in the case of the divided clock signal DIV) or has a delay equal to the delay signals Φ[1], Φ[2], ..., Φ[i], ..., Φ[k-1] selected each time, thereby taking the reference signal OUT as the output clock signal. Figure 8 The method discussed is to correct the phase error.

[0087] For example, in Figure 11, the delay selection block 38 is formed by a multiplexer 80 having a control input and a data input, the control input receiving the sum signal SUM, and the data input receiving the divided clock signal DIV and the delay signals Φ[1], Φ[2], ..., Φ[k-1].

[0088] As an alternative to the above, the delay selection block 38 can receive all the delay signals Φ[1], Φ[2], ..., Φ[i], ..., Φ[k] (but not the divided clock signal DIV), and in each cycle of the divided clock signal DIV, select one delay signal specified by the sum signal SUM.

[0089] The clock generator 30 and jitter compensation method described herein have many advantages.

[0090] In particular, the jitter filter 35 operating to compensate for phase errors on the individual switching edges of the divided clock signal DIV requires only a few passive components of small size, and thus the area required for its integration is limited.

[0091] The part of the dither filter 35 that operates at high frequency (the frequency of the resonant signal HFCK) and therefore consumes a lot of energy is very small (in fact, only a small number of logic gates generate the reference signal REF f and REF r , as described above). Therefore, the present clock generator has a low power consumption level.

[0092] Unlike most known DLL circuits, this dither filter uses an input signal with a duty cycle much lower than 50% (reference signal REF r and REF f ). For this reason as well, a significant power saving is achieved compared to known solutions.

[0093] Compensating for jitter by introducing a delay on the switching edges of the divided clock signal DIV associated with the value of the sum signal SUM (quantization error QE) of the temperature compensation stage 36 makes it possible to adapt the same delay to temperature variations, thus supporting accurate compensation at all operating temperatures.

[0094] Furthermore, the clock generator and jitter filter described in this article have high stability.

[0095] Finally, it is clear that modifications and variations may be made to the clock generator and the jitter compensation method described and illustrated herein without departing from the scope of the present invention, for example as defined in the appended claims.

[0096] For example, the structure of the delay stage 60 may be different, and each delay stage may include a corresponding unit delay element (eg, a capacitor) for appropriately delaying the switching edge of the divided clock signal DIV.

[0097] According to another embodiment, instead of a series of pulses with different delays selected by the multiplexer 80, the DTC 50 may generate a series of delayed pulses with increasing widths (which are multiples of the unit delay and correspond to the duration of the least significant bit (LSB)) that are subtracted from / added to the divided clock signal DIV based on the instantaneous quantization error in order to modify its switching edges.

[0098] Although the DTC 50 has two different branches (a rising edge regulation branch 75 r and a falling edge regulation branch 75 f ), it is possible to have only one regulation branch (associated with only one of the switching edges, e.g., the rising edge) that corrects a single unit delay per cycle of the dither filter 35 and controls both choke transistors 72_r, 72_f, e.g., via a current mirror.

[0099] According to a different embodiment, compensation for jitter may also be obtained automatically at each cycle of the divided clock signal by using a sequence of delays of preset values, applying increasing delays (up to a maximum, coinciding with the change of modulus from N to N+1).

Claims

1. A clock generator, comprising: a signal input configured to receive a high frequency clock signal; a variable modulus divider coupled to the signal input and having a control input and an output, wherein the control input of the variable modulus divider is configured to receive a modulus control signal, and wherein the output of the variable modulus divider is configured to provide a divided clock signal having jitter; a temperature compensation circuit configured to generate the modulus control signal; as well as a dither filter coupled to the variable modulus divider and configured to: receiving the divided clock signal, and A compensated clock signal is generated having a switching edge that is delayed relative to the divided clock signal by a time associated with the jitter.

2. The clock generator of claim 1 , wherein the temperature compensation circuit is configured to generate a quantization error signal, and wherein the dither filter is coupled to the temperature compensation circuit and is configured to: receiving the quantization error signal; and The switching edge of the compensation clock signal is delayed by a time related to the value of the quantization error signal.

3. The clock generator of claim 2 , wherein the jitter filter comprises: a delay generator configured to receive the divided clock signal and generate a plurality of delayed clock signals, each of the plurality of delayed clock signals having a different delay relative to the divided clock signal; as well as The selection circuit is configured to receive the plurality of delayed clock signals and the quantization error signal, and is configured to periodically select one of the delayed clock signals.

4. The clock generator of claim 3, wherein the delay generator is a delay locked loop (DLL) circuit. The clock generator according to claim 3 , wherein the selection circuit is a multiplexer.

6. The clock generator of claim 3 , wherein the delay generator comprises a plurality of delay stages coupled in cascade to each other, wherein a first delay stage of the plurality of delay stages is configured to receive the divided clock signal, and wherein each delay stage of the plurality of delay stages has an output configured to provide a corresponding delayed clock signal. 7 . The clock generator of claim 6 , wherein each of the plurality of delay stages comprises a first inverter and a second inverter coupled to each other in cascade.

8. The clock generator of claim 7 , wherein the delay generator comprises a delay adjustment circuit configured to receive a reference signal and a first delayed clock signal from among the delayed clock signals and to generate an electrical adjustment amount, and wherein the first inverter of each delay stage is coupled to a first reference voltage line and a second reference voltage line via a first choke element and a second choke element, respectively, each of the first choke elements having a corresponding control terminal coupled together, and each of the second choke elements having a corresponding control terminal coupled together, the first choke element and the second choke element being coupled to the delay adjustment circuit and having a conductivity controlled by the electrical adjustment amount. 9 . The clock generator according to claim 8 , wherein the first choke element and the second choke element are metal oxide semiconductor (MOS) transistors.

10. The clock generator of claim 8, wherein the delay adjustment circuit has an input coupled to a last delay stage of the plurality of delay stages.

11. The clock generator of claim 8 , wherein the delay adjustment circuit comprises a rising edge adjustment branch and a falling edge adjustment branch, wherein the falling edge adjustment branch is configured to receive the first delayed clock signal and a falling edge reference signal, the falling edge adjustment branch having an output coupled to the control terminal of the first choke element, wherein the rising edge adjustment branch is configured to receive the first delayed clock signal and a rising edge reference signal, the rising edge adjustment branch having an output coupled to the control terminal of the second choke element. 12 . The clock generator of claim 11 , wherein the rising edge adjustment branch and the falling edge adjustment branch each comprise a corresponding phase detection and charge pump circuit and a corresponding capacitor.

13. A method for generating a jitter-compensated clock signal in a clock generator, the method comprising: receiving a high frequency clock signal from a signal input of the clock generator; generating a modulus control signal based on a temperature value by a temperature compensation circuit of the clock generator; receiving the modulus control signal by a variable modulus divider of the clock generator, wherein the variable modulus divider is coupled to the signal input; Dividing the high frequency clock signal by the variable modulus divider based on the modulus control signal to generate a divided clock signal with jitter; receiving the divided clock signal by a jitter filter of the clock generator, wherein the jitter filter is coupled to the variable modulus divider; as well as The jitter filter delays a switching edge of the divided clock signal by a time related to the jitter to generate a compensated clock signal.

14. The method of claim 13, wherein delaying the switching edge of the divided clock signal comprises: generating a quantization error signal; generating a plurality of delayed clock signals, each delayed clock signal having a different delay relative to the divided clock signal; as well as One of the delayed clock signals is periodically selected based on the quantization error signal.

15. The method of claim 14, wherein generating the plurality of delayed clock signals comprises: receiving the frequency-divided clock signal; as well as The divided clock signal is delayed by a series of delay stages coupled to each other in cascade, each delay stage generating a corresponding delayed clock signal having a delay relative to a previous delayed clock signal.

16. The method according to claim 14, wherein the plurality of delayed clock signals comprises a delayed clock signal having a maximum delay, the method further comprising: comparing the delayed clock signal with the maximum delay with a reference signal; as well as The delay value of each delayed clock signal is adjusted based on the difference between the delayed clock signal with the maximum delay and the reference signal.

17. The method according to claim 13, further comprising: The high frequency clock signal is generated using a resonant micro-electromechanical system (MEMS) type micro-electromechanical structure.

18. A clock generator comprising: A variable modulus frequency divider, the variable modulus frequency divider comprising: A first input is configured to receive a high frequency clock signal, a second input configured to receive a modulus control signal based on a temperature value, and output, wherein the variable modulus divider is configured to: generate a divided clock signal having a target average clock frequency and jitter at the output of the variable modulus divider; and A jitter filter, the jitter filter comprising: a first input configured to receive the divided clock signal, a second input configured to receive the modulus control signal, and output, wherein the jitter filter is configured to generate a compensated clock signal having the target average clock frequency and compensated jitter at the output of the jitter filter by delaying a switching edge of the divided clock signal based on the modulus control signal.

19. The clock generator of claim 18, wherein the jitter filter further comprises: a delay generator having an input coupled to the first input and configured to generate a plurality of delayed clock signals, wherein each delayed clock signal of the plurality of delayed clock signals has a different delay relative to the divided clock signal; as well as The selection circuit is configured to: receiving the plurality of delayed clock signals, receiving an error signal, and Based on the error signal, one of the delayed clock signals is periodically selected.

20. The clock generator of claim 19, further comprising a temperature compensation stage having a temperature sensor and a digital delta-sigma modulator, wherein the digital delta-sigma modulator is configured to generate the modulus control signal and the error signal.

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