Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device can include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first stack structure block and the second stack structure block, and including a first molding layer and a second molding layer, and a contact plug penetrating the separation structure. A bottom surface of the contact plug can be in contact with the substrate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0149912, filed on November 28, 2018, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor memory devices, and more specifically, to three-dimensional (3D) semiconductor memory devices. Background Technology

[0004] Semiconductor memory devices have been highly integrated to provide superior performance and low manufacturing costs. The integration density of semiconductor memory devices directly affects their cost, leading to the need for highly integrated devices. The integration density of two-dimensional (2D) or planar semiconductor memory devices can be determined primarily by the area occupied by a single memory cell. Therefore, the technique for forming intricate patterns significantly impacts the integration density of 2D or planar semiconductor memory devices. However, the integration density of 2D semiconductor memory devices continues to increase, but remains limited, due to the need for very expensive equipment to form these intricate patterns. Therefore, three-dimensional (3D) semiconductor memory devices have been developed to overcome these limitations. 3D semiconductor memory devices can include memory cells arranged in three dimensions. Summary of the Invention

[0005] Embodiments of the present invention can provide a three-dimensional (3D) semiconductor memory device with improved electrical characteristics.

[0006] According to some examples, a 3D semiconductor memory device may include: a first stacked structure block including a first stacked structure arranged side-by-side on a substrate along a first direction; a second stacked structure block including a second stacked structure arranged side-by-side on the substrate along the first direction; a separation structure disposed on the substrate, located between the first and second stacked structure blocks, and including a first molding layer and a second molding layer; and a contact plug penetrating the separation structure. The bottom surface of the contact plug may contact the substrate.

[0007] According to some examples, a 3D semiconductor memory device can include: a first stack structure block including first stack structures arranged side by side in a first direction on a first substrate; a second stack structure block including second stack structures arranged side by side in the first direction on the first substrate; a separation structure disposed on the first substrate between the first stack structure block and the second stack structure block, and including a first molding layer and a second molding layer; a first contact plug penetrating the separation structure and the first substrate; a second contact plug penetrating the separation structure and connected to the first substrate; and a connection line connecting the first contact plug and the second contact plug.

[0008] According to some examples, a 3D semiconductor memory device can include: a first stack structure block including first stack structures arranged side by side in a first direction on a substrate, wherein the first stack structure block includes a first end portion having a wall structure; a separation structure disposed on the substrate and disposed on a first sidewall of the first end portion of the first stack structure block; and a first contact plug penetrating the separation structure and arranged along the first sidewall of the first end portion. BRIEF DESCRIPTION OF DRAWINGS

[0009] The present inventive concepts will become more apparent in view of the attached drawings and accompanying detailed description.

[0010] Figure 1 FIG. 1 is a schematic circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to some embodiments of the present inventive concepts.

[0011] Figure 2 FIG. 2 is a plan view illustrating a semiconductor wafer including the 3D semiconductor memory device according to some embodiments of the present inventive concepts.

[0012] Figure 3A FIG. 3 is a plan view illustrating a semiconductor chip of FIG. 2. Figure 2 FIG. 4 is an enlarged view of a portion “A” of the semiconductor chip of FIG. 3.

[0013] Figure 3B FIG. 5 is an enlarged view of a portion “B” of the semiconductor chip of FIG. 3. Figure 2 FIG. 6 is an enlarged view of a portion “C” of the semiconductor chip of FIG. 3.

[0014] Figure 4 FIG. 7 is a cross-sectional view taken along line I-I’ of FIG. 3 for illustrating the 3D semiconductor memory device according to some embodiments of the present inventive concepts. Figure 3A FIG. 8 is a cross-sectional view taken along line II-II’ of FIG. 3 for illustrating the 3D semiconductor memory device according to some embodiments of the present inventive concepts.

[0015] Figure 5 FIG. 9 is a cross-sectional view taken along line III-III’ of FIG. 3 for illustrating the 3D semiconductor memory device according to some embodiments of the present inventive concepts. Figure 4 FIG. 10 is a cross-sectional view taken along line IV-IV’ of FIG. 3 for illustrating the 3D semiconductor memory device according to some embodiments of the present inventive concepts.

[0016] Figure 6 FIG. 11 is a cross-sectional view taken along line V-V’ of FIG. 3 for illustrating the 3D semiconductor memory device according to some embodiments of the present inventive concepts. Figure 4 FIG. 12 is a cross-sectional view taken along line VI-VI’ of FIG. 3 for illustrating the 3D semiconductor memory device according to some embodiments of the present inventive concepts.

[0017] Figure 7 is an enlarged view of part "B" of Figure 5

[0018] Figure 8 is a cross-sectional view taken along line I-I' of Figure 4 for illustrating a 3D semiconductor memory device according to some embodiments of inventive concepts.

[0019] Figure 9 is a cross-sectional view taken along line I-I' of Figure 4 for illustrating a 3D semiconductor memory device according to some embodiments of inventive concepts.

[0020] Figure 10 is a cross-sectional view taken along line II-II' of Figure 4 for illustrating a 3D semiconductor memory device according to some embodiments of inventive concepts.

[0021] Figure 11 is an enlarged view of part "A" of Figure 3A

[0022] Figure 12 is a cross-sectional view taken along line I-I' of Figure 11 for illustrating a 3D semiconductor memory device according to some embodiments of inventive concepts.

[0023] Figure 13 is an enlarged view of part "A" of Figure 3A

[0024] Figure 14 is a cross-sectional view taken along line III-III' of Figure 13 for illustrating a 3D semiconductor memory device according to some embodiments of inventive concepts.

[0025] Figure 15 is an enlarged view of part "A" of Figure 3A

[0026] Figure 16 is a cross-sectional view taken along line IV-IV' of Figure 15 for illustrating a 3D semiconductor memory device according to some embodiments of inventive concepts.

[0027] Figure 17 is an enlarged view of part "C" of Figure 16

[0028] Figure 18 is an enlarged view of a semiconductor chip of Figure 2

[0029] ​​​​​​Figure 19 is an enlarged view of a portion "D" of Figure 18

[0030] Figure 20 is an enlarged view of a portion "D" of Figure 18 DETAILED DESCRIPTION

[0031] Figure 1 is a schematic circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to some embodiments of the inventive concept.

[0032] Referring to Figure 1 , the 3D semiconductor memory device can include a common source line CSL, a plurality of bit lines BL0 to BL2, and a plurality of cell strings CSTR disposed between the common source line CSL and the plurality of bit lines BL0 to BL2.

[0033] The bit lines BL0 to BL2 can be arranged two-dimensionally, and the plurality of cell strings CSTR can be connected in parallel to each of the bit lines BL0 to BL2. Accordingly, the cell strings CSTR can be arranged two-dimensionally on the common source line CSL or a substrate.

[0034] Each cell string CSTR can include a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to one of the bit lines BL0 to BL2, and a plurality of memory cell transistors MCT disposed between the ground select transistor GST and the string select transistor SST. The ground select transistor GST, the memory cell transistors MCT, and the string select transistor SST can be connected in series with each other. A ground select line GSL, a plurality of word lines WL0 to WL3, and one of string select lines SSL0, SSL1, and SSL2 disposed between one of the plurality of common source lines CSL and the plurality of bit lines BL0 to BL2 can serve as gate electrodes of the respective ground select transistor GST, memory cell transistors MCT, and string select transistor SST, respectively.

[0035] Figure 2 is a plan view illustrating a semiconductor wafer including a 3D semiconductor memory device according to some embodiments of the inventive concept. Figure 3A is an enlarged view of an un-singulated semiconductor chip of Figure 2 Figure 3B is an enlarged view of an un-singulated semiconductor chip of Figure 2 Figure 4 is an enlarged view of a portion "A" of Figure 3A Figure 5 is an enlarged view of a portion "A" of​​​​​Figure 4 The line I-I' is a cross-sectional view taken to illustrate some embodiments of a 3D semiconductor memory device according to the present invention. Figure 6 It is along Figure 4 The line II-II' is a cross-sectional view taken to illustrate some embodiments of a 3D semiconductor memory device according to the present invention. Figure 7 yes Figure 5 A magnified view of part "B". For descriptive purposes, some of the upper layers of the undivided semiconductor chip are not shown in the figure. It will be understood that a semiconductor chip refers to a semiconductor device (e.g., a semiconductor integrated circuit) separated from a wafer (or a stack of wafers) (e.g., cut from a dicing / dicing operation). For ease of description, this disclosure may refer to such a chip before separation from the wafer as an "undivided chip" and such intermediate structures as "undivided chips". It will be understood that the wafer-separated semiconductor chip described herein will have the same structure as the undivided semiconductor chip. Therefore, unless the context otherwise indicates, the description herein can be applied to both undivided semiconductor chips that are part of a wafer and wafer-separated semiconductor chips.

[0036] Reference Figure 2 and Figure 3A The semiconductor wafer 1000 may include a plurality of unscribed semiconductor chip USCs (or unit chips). The plurality of unscribed semiconductor chip USCs may be spaced apart from each other in a first direction X and a second direction Y intersecting the first direction X. Scribed regions SR1 and SR2 may define the plurality of unscribed semiconductor chip USCs. Scribed regions SR1 and SR2 may include: a first scribe region SR1 extending in the first direction X and a second scribe region SR2 extending in the second direction Y.

[0037] Each un-sliced semiconductor chip USC can include a substrate 100, a block BLK1, a block BLK2, and a block BLK3, a separation structure SRS1, a separation structure SRS2, and a separation structure SRS3, and a first interlayer insulating layer ILD1. The block BLK1, the block BLK2, and the block BLK3 can be disposed on the substrate 100. The block BLK1, the block BLK2, and the block BLK3 can be spaced apart from each other in the second direction Y on a top surface of the substrate 100. The block BLK1, the block BLK2, and the block BLK3 can include a first block BLK1, a second block BLK2, and a third block BLK3. The second block BLK2 and the third block BLK3 can be spaced apart from each other in the second direction Y on the substrate 100, and the first block BLK1 can be disposed between the second block BLK2 and the third block BLK3. The first interlayer insulating layer ILD1 can be disposed on the substrate 100. The first interlayer insulating layer ILD1 can cover sidewalls of the block BLK1, the block BLK2, and the block BLK3 and a top surface of the substrate 100.

[0038] The first to third separation structures SRS1, SRS2 and SRS3 can be disposed on the top surface of the substrate 100. The first separation structure SRS1 can penetrate the first block BLK1 on the top surface of the substrate 100. The first separation structure SRS1 can include a first molding structure MS1 and first to fourth separation layers SL1, SL2, SL3 and SL4. The first molding structure MS1 can include a first portion P1 and a second portion P2. The first portion P1 of the first molding structure MS1 can penetrate the first block BLK1 and can extend in the second direction Y. The second portion P2 of the first molding structure MS1 can penetrate the first block BLK1 and can extend in the first direction X. The first portion P1 and the second portion P2 of the first molding structure MS1 can cross each other. The first block BLK1 can be divided into first to fourth stacked structure blocks STB1, STB2, STB3 and STB4 by the first molding structure MS1. The first stacked structure block STB1 and the second stacked structure block STB2 can be spaced apart from each other in the first direction X with the first portion P1 of the first molding structure MS1 interposed therebetween, the third stacked structure block STB3 and the fourth stacked structure block STB4 can be spaced apart from each other in the first direction X with the first portion P1 of the first molding structure MS1 interposed therebetween. The first stacked structure block STB1 and the third stacked structure block STB3 can be spaced apart from each other in the second direction Y with the second portion P2 of the first molding structure MS1 interposed therebetween, the second stacked structure block STB2 and the fourth stacked structure block STB4 can be spaced apart from each other in the second direction Y with the second portion P2 of the first molding structure MS1 interposed therebetween. The first separation layer SL1 can be disposed between the first molding structure MS1 and the first stacked structure block STB1, the second separation layer SL2 can be disposed between the first molding structure MS1 and the second stacked structure block STB2. The third separation layer SL3 can be disposed between the first molding structure MS1 and the third stacked structure block STB3, the fourth separation layer SL4 can be disposed between the first molding structure MS1 and the fourth stacked structure block STB4.

[0039] The second separation structure SRS2 can penetrate the second block BLK2 on the top surface of the substrate 100. The second separation structure SRS2 can include a second molding structure MS2 and a fifth separation layer SL5 and a sixth separation layer SL6. The second molding structure MS2 can include a first portion PI and a second portion P2. The first portion PI of the second molding structure MS2 can penetrate the second block BLK2 and can extend in the second direction Y. The second portion P2 of the second molding structure MS2 can extend along one sidewall of the second block BLK2 on the top surface of the substrate 100. One sidewall of the second portion P2 of the second molding structure MS2 can be aligned with the first sidewall SI of the substrate 100. The second block BLK2 can be divided into a fifth stacked structure block STB5 and a sixth stacked structure block STB6 by the first portion PI of the second molding structure MS2. The fifth stacked structure block STB5 and the sixth stacked structure block STB6 can be spaced apart from each other in the first direction X with the first portion PI of the second molding structure MS2 interposed therebetween. The fifth separation layer SL5 can be disposed between the fifth stacked structure block STB5 and the second molding structure MS2, and the sixth separation layer SL6 can be disposed between the sixth stacked structure block STB6 and the second molding structure MS2.

[0040] The third separation structure SRS3 can penetrate the third block BLK3 on the top surface of the substrate 100. The third separation structure SRS3 can include a third molding structure MS3 and a seventh separation layer SL7 and an eighth separation layer SL8. The third molding structure MS3 can include a first portion PI and a second portion P2. The first portion PI of the third molding structure MS3 can penetrate the third block BLK3 and can extend in the second direction Y. The second portion P2 of the third molding structure MS3 can extend along one sidewall of the third block BLK3 on the top surface of the substrate 100. One sidewall of the second portion P2 of the third molding structure MS3 can be aligned with the second sidewall S2 of the substrate 100, where the second sidewall S2 is opposite to and parallel with the first sidewall SI. The third block BLK3 can be divided into a seventh stacked structure block STB7 and an eighth stacked structure block STB8 by the first portion PI of the third molding structure MS3. The seventh stacked structure block STB7 and the eighth stacked structure block STB8 can be spaced apart from each other in the first direction X with the first portion PI of the third molding structure MS3 interposed therebetween. The seventh separation layer SL7 can be disposed between the third molding structure MS3 and the seventh stacked structure block STB7, and the eighth separation layer SL8 can be disposed between the third molding structure MS3 and the eighth stacked structure block STB8.

[0041] The end portions of the first to third molded structures MS1, MS2, and MS3, which are in contact with the first interlayer insulating layer ILD1, can have a stepped structure STS_a (see Figure 4 ). The first to eighth separation layers SL1 to SL8 can be formed as a single layer (e.g., a single homogeneous layer). The first separation layer SL1 and the fifth separation layer SL5 can extend in parallel to the second direction Y to penetrate the first interlayer insulating layer ILD1, and can be connected to each other. The second separation layer SL2 and the sixth separation layer SL6 can extend in parallel to the second direction Y to penetrate the first interlayer insulating layer ILD1, and can be connected to each other. The third separation layer SL3 and the seventh separation layer SL7 can extend in parallel to the second direction Y to penetrate the first interlayer insulating layer ILD1, and can be connected to each other. The fourth separation layer SL4 and the eighth separation layer SL8 can extend in parallel to the second direction Y to penetrate the first interlayer insulating layer ILD1, and can be connected to each other. The first to third separation structures SRS1 to SRS3 can have the same stacked structure. The first separation structure SRS1 among the first to third separation structures SRS1 to SRS3 will be described in more detail later as a representative. Figure 7

[0042] The sidewalls of the first to fourth stacked structure blocks STB1 to STB4, which are in contact with the first separation structure SRS1, can be substantially perpendicular to the top surface of the substrate 100, and can be flat surfaces substantially parallel to the third direction Z. The sidewalls of the fifth and sixth stacked structure blocks STB5 and STB6, which are in contact with the second separation structure SRS2, can be substantially perpendicular to the top surface of the substrate 100, and can be flat. The sidewalls of the seventh and eighth stacked structure blocks STB7 and STB8, which are in contact with the third separation structure SRS3, can be substantially perpendicular to the top surface of the substrate 100, and can be flat. It should be appreciated that the geometric shapes described herein such as "flat", "plane", "coplanar", and the like, should not be interpreted as being geometrically perfectly flat, planar, coplanar, and the like, but rather typical deviations of conventional semiconductor manufacturing processes are allowed. The term "substantially" or similar modifiers can be used to emphasize such understanding.

[0043] Referring to Figure 3B , each of the first to eighth stacked structure blocks STB1 to STB8 can include a first end portion EP1, a second end portion EP2, a third end portion EP3, and a fourth end portion EP4. The first end portion EP1 and the third end portion EP3 can be opposite to each other in the second direction Y when viewed in a plan view; and the second end portion EP2 and the fourth end portion EP4 can be opposite to each other in the first direction X when viewed in a plan view. At least one of the second end portion EP2 and the fourth end portion EP4 can be disposed between the first end portion EP1 and the third end portion EP3. ​

[0044] The sidewalls of the first end portions EP1 and the second end portions EP2 of the first stack structure block STB1 to the fourth stack structure block STB4 can be in contact with the first separation structure SRS1. The first end portions EP1 and the second end portions EP2 of the first stack structure block STB1 to the fourth stack structure block STB4 can have a wall structure and be vertical without substantial deviation in the horizontal direction. For example, such first end portions EP1 and second end portions EP2 can be flat and extend vertically from the substrate 100. The sidewalls of the first end portions EP1 of the first stack structure block STB1 to the fourth stack structure block STB4 can be substantially perpendicular to the top surface of the substrate 100 and can be substantially parallel to the third direction Z. The sidewalls of the second end portions EP2 of the first stack structure block STB1 to the fourth stack structure block STB4 can be substantially perpendicular to the top surface of the substrate 100 and can be substantially parallel to the third direction Z. The sidewalls of the third end portions EP3 and the fourth end portions EP4 of the first stack structure block STB1 to the fourth stack structure block STB4 can be in contact with the first interlayer insulating layer ILD1. The third end portions EP3 and the fourth end portions EP4 of the first stack structure block STB1 to the fourth stack structure block STB4 can have a staircase structure.

[0045] The sidewalls of the first end portions EP1 and the second end portions EP2 of the fifth stack structure block STB5 and the sixth stack structure block STB6 can be in contact with the second separation structure SRS2. The first end portions EP1 and the second end portions EP2 of the fifth stack structure block STB5 and the sixth stack structure block STB6 can have a wall structure and be vertical without substantial deviation in the horizontal direction. For example, such first end portions EP1 and second end portions EP2 can be flat and extend vertically from the substrate 100. The sidewalls of the first end portions EP1 of the fifth stack structure block STB5 and the sixth stack structure block STB6 can be substantially perpendicular to the top surface of the substrate 100 and can be substantially parallel to the third direction Z. The sidewalls of the second end portions EP2 of the fifth stack structure block STB5 and the sixth stack structure block STB6 can be substantially perpendicular to the top surface of the substrate 100 and can be substantially parallel to the third direction Z. The sidewalls of the third end portions EP3 and the fourth end portions EP4 of the fifth stack structure block STB5 and the sixth stack structure block STB6 can be in contact with the first interlayer insulating layer ILD1. The third end portions EP3 and the fourth end portions EP4 of the fifth stack structure block STB5 and the sixth stack structure block STB6 can have a staircase structure.

[0046] The sidewalls of the first and second end portions EP1, EP2 of the seventh and eighth stack structure blocks STB7, STB8 can be in contact with the third separation structure SRS3. The first and second end portions EP1, EP2 of the seventh and eighth stack structure blocks STB7, STB8 can have a wall structure and be vertical without substantial deviation in horizontal direction. For example, such first and second end portions EP1, EP2 can be flat and extend vertically from the substrate 100. The sidewalls of the first end portions EP1 of the seventh and eighth stack structure blocks STB7, STB8 can be substantially perpendicular to the top surface of the substrate 100 and can be substantially parallel to the third direction Z. The sidewalls of the second end portions EP2 of the seventh and eighth stack structure blocks STB7, STB8 can be substantially perpendicular to the top surface of the substrate 100 and can be substantially parallel to the third direction Z. The sidewalls of the third and fourth end portions EP3, EP4 of the seventh and eighth stack structure blocks STB7, STB8 can be in contact with the first interlayer insulating layer ILD1. The third and fourth end portions EP3, EP4 of the seventh and eighth stack structure blocks STB7, STB8 can have a staircase structure.

[0047] When viewed in plan view, the first contact plug 610a can be arranged along the circumference of each of the first, second, and third blocks BLK1, BLK2, BLK3. The first contact plug 610a can penetrate the first interlayer insulating layer ILD1. A bottom surface of the first contact plug 610a can be in contact with the substrate 100. The first contact plug 610a can be electrically connected to a transistor of the peripheral circuit structure PRS. The first contact plug 610a will be described later in more detail with reference to Figure 4 and Figure 5 The first contact plug 610a and the second to fifth contact plugs 610b, 610c, 610d, 610e will be described in more detail.

[0048] Each of the first to eighth stack structure blocks STB1-STB8 can comprise stack structures ST arranged in the first direction X and extending in the second direction Y (see Figure 4 The contact structures 400 (see Figure 4 ) are provided between stack structures ST adjacent to each other and between stack structures ST adjacent to each other and the separation structures SRS1, SRS2, or SRS3. The first to fourth stack structure blocks STB1-STB4 will be described in more detail as representatives. Figure 4 to Figure 7

[0049] Referring to Figure 4 to Figure 6 ​A 3D semiconductor memory device can include a lower substrate 200, a peripheral circuit structure PRS, a substrate 100, and first to fourth stack structures ST1a and ST1 to ST4a and ST4. The lower substrate 200 can be or can include a crystalline semiconductor substrate, such as a crystalline silicon substrate, a crystalline silicon germanium substrate, a crystalline germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. A device isolation layer 201 can be provided in the lower substrate 200. The device isolation layer 201 can define an active area of the lower substrate 200. The device isolation layer 201 can be an insulating material (e.g., silicon oxide).

[0050] The peripheral circuit structure PRS can be provided on and / or in the lower substrate 200. The peripheral circuit structure PRS can include transistors TR, a peripheral interlayer insulating layer 210, interconnect conductors 213, and vias 215. The transistors TR can be formed on and / or in the active area of the lower substrate 200. Each transistor TR can include a peripheral gate insulating layer 40, a peripheral gate electrode 50, and a source / drain region 60. The peripheral interlayer insulating layer 210 can be provided on the lower substrate 200. The peripheral interlayer insulating layer 210 can include several different interlayer insulating layers. The peripheral interlayer insulating layer 210 can cover the transistors TR. The interconnect conductors 213 and the vias 215 can be provided in the peripheral interlayer insulating layer 210. The interconnect conductors 213 can be conductive pads and / or wires. Interconnect conductors 213 at different levels can be connected to each other by vias 215 provided between the interconnect conductors 213. Further, the transistors TR can be connected to the interconnect conductors 213 by the vias 215 and provide conductive wiring connections to other transistors TR, to terminals of the semiconductor chip (e.g., to chip pads), and / or to circuits formed on and / or in the substrate 100. It is to be understood that Figure 5 and Figure 6 cross-sectional views provide a simplified representation of such wiring connections (and do not show wiring connections formed from interconnect conductors 213 extending in a direction perpendicular to the plane of the paper along the direction of the arrow Figure 5 and Figure 6 ).

[0051] The substrate 100 can be disposed on the peripheral circuit structure PRS. The substrate 100 can include a cell block region CBR and a peripheral circuit region PR1 and a peripheral circuit region PR2. The cell block region CBR can be spaced apart from each other in a first direction X and a second direction Y, and the peripheral circuit region PR1 and the peripheral circuit region PR2 can define the cell block region CBR. The peripheral circuit region PR1 and the peripheral circuit region PR2 can include a first peripheral circuit region PR1 and a second peripheral circuit region PR2. The first peripheral circuit region PR1 can correspond to a region on which the first separation structure SRS1 is disposed. The second peripheral circuit region PR2 can correspond to a region on which the first interlayer insulation layer ILD1 is disposed. The substrate 100 can be a crystalline semiconductor material or include a crystalline semiconductor material. For example, the substrate 100 can be crystalline silicon (Si), crystalline germanium (Ge), crystalline silicon germanium (SiGe), crystalline gallium arsenide (GaAs), crystalline indium gallium arsenide (InGaAs), crystalline aluminum gallium arsenide (AlGaAs), or a combination thereof. The semiconductor materials of the substrate 100 and the lower substrate 200 can be the same or different from each other.

[0052] Each of the first to fourth stacked structure blocks STB1 to STB4 can be disposed in each of the cell block regions CBR of the substrate 100. The first stacked structure block STB1 can include first stacked structures ST1a and ST1 on a top surface of the substrate 100 arranged in the first direction X and extending in the second direction Y. The second stacked structure block STB2 can include second stacked structures ST2a and ST2 on the top surface of the substrate 100 arranged in the first direction X and extending in the second direction Y. The third stacked structure block STB3 can include third stacked structures ST3a and ST3 on the top surface of the substrate 100 arranged in the first direction X and extending in the second direction Y. The fourth stacked structure block STB4 can include fourth stacked structures ST4a and ST4 on the top surface of the substrate 100 arranged in the first direction X and extending in the second direction Y.

[0053] Each of the first stack structure ST1a and ST1 to the fourth stack structure ST4a and ST4 can include insulating patterns 330 and gate electrodes 320a, 320b, and 320c alternately and repeatedly stacked on the substrate 100. The insulating patterns 330 can be stacked in the third direction Z. The insulating patterns 330 can be silicon oxide or can include, for example, silicon oxide. Each of the gate electrodes 320a, 320b, and 320c can be disposed between the insulating patterns 330 adjacent to each other in the third direction Z. The gate electrodes 320a, 320b, and 320c can include a ground select gate electrode 320a, a cell gate electrode 320b, and a string select gate electrode 320c. The ground select gate electrode 320a can correspond to a lowermost one of the gate electrodes 320a, 320b, and 320c, and the string select gate electrode 320c can correspond to an uppermost one of the gate electrodes 320a, 320b, and 320c. The cell gate electrode 320b can be disposed between the ground select gate electrode 320a and the string select gate electrode 320c. A plurality of string select gate electrodes 320c can also be implemented with the embodiments described herein and can be connected in series (as part of a cell string CSTR) and formed over the cell gate electrode 320b and the ground select gate electrode 320a.

[0054] An end of each of the first and second stack structures ST1a and ST1 to ST4a and ST4 that contacts the first interlayer insulating layer ILD1 can have a stepped structure STS. For example, a height of each of the first and second stack structures ST1a and ST1 to ST4a and ST4 can decrease as a distance of the stack structure from the first separation structure SRS1 in the second direction Y increases. In other words, lengths of the gate electrodes 320a, 320b, and 320c in the second direction Y can sequentially decrease as the vertical distance from the substrate 100 increases. In some embodiments, each of the gate electrodes 320a, 320b, and 320c can have an end in the stepped structure STS of each of the first and second stack structures ST1a and ST1 to ST4a and ST4. The end of each of the ground select gate electrode 320a and the unit gate electrode 320b can correspond to a portion of the gate electrode exposed directly thereon of each of the ground select gate electrode 320a and the unit gate electrode 320b. In some embodiments, another end of each of the first and second stack structures ST1a and ST1 to ST4a and ST4 that contacts the first separation structure SRS1 can have a wall structure and be vertical without substantial deviation in the horizontal direction. For example, the other end can be flat and extend vertically from the substrate 100. The other end of each of the first and second stack structures ST1a and ST1 to ST4a and ST4 can be a portion of the gate electrode exposed directly thereon of each of the first and second stack structures ST1a and ST1 to ST4a and ST4. Figure 3A and Figure 3B The stack structures included in the fifth to eighth stack structure blocks STB5 to STB8 shown in FIGS. 1A to 1C can have the same structure as the first and second stack structures ST1a and ST1 to ST4a and ST4.

[0055] The first interlayer insulating layer ILD1 can be disposed on the second peripheral circuit region PR2 of the substrate 100 and can cover the stepped structures STS of the first and second stack structures ST1a and ST1 to ST4a and ST4. A top surface of the first interlayer insulating layer ILD1 can be located at substantially the same horizontal level as a top surface of the first and second stack structures ST1a and ST1 to ST4a and ST4. For example, the first interlayer insulating layer ILD1 can be a silicon oxide layer.

[0056] Referring to Figure 4 to Figure 7The vertical cell channel structure CCS can penetrate the first stack structures ST1a and ST1 to the fourth stack structures ST4a and ST4 on the top surface of the substrate 100. The vertical cell channel structure CCS can be spaced apart from the staircase structures STS of the first stack structures ST1a and ST1 to the fourth stack structures ST4a and ST4. The vertical cell channel structure CCS can include a vertical channel portion VC, a semiconductor pillar SP, a charge storage structure 340, a gap fill layer 350, and a pad 360. The vertical channel portion VC can penetrate the first stack structures ST1a and ST1 to the fourth stack structures ST4a and ST4. The vertical channel portion VC can be arranged in a zigzag form or linearly along the second direction Y when viewed in a plan view. Each vertical channel portion VC can have a hollow tube shape, a hollow cylinder shape, or a cup shape. In some examples, the vertical channel portion VC can be solid (e.g., a solid pillar), and the gap fill layer 350 can be omitted. Each vertical channel portion VC can be formed as a single layer (e.g., a single homogenous layer) or multiple layers. For example, the vertical channel portion VC can be or can include a single crystalline silicon layer, an organic semiconductor layer, a carbon nanostructure, or a combination thereof.

[0057] The semiconductor pillar SP can be disposed between the substrate 100 and the vertical channel portion VC, respectively. The semiconductor pillar SP can be disposed on the top surface of the substrate 100 and can penetrate the ground select gate electrode 320a. Each semiconductor pillar SP can contact a corresponding vertical channel portion VC. The semiconductor pillar SP can be or can include a semiconductor material having the same conductivity type as that of the substrate 100, or can be or can include an intrinsic semiconductor material. The charge storage structure 340 can be disposed between the vertical channel portion VC and the gate electrode 320b and the gate electrode 320c. The charge storage structure 340 can extend along the outer sidewall of the vertical channel portion VC in the third direction Z. For example, the charge storage structure 340 can surround the outer sidewall of the vertical channel portion VC, respectively. For example, each charge storage structure 340 can be formed as a single layer (e.g., a single homogenous layer) or include multiple layers of at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric layer.

[0058] As Figure 7As shown, each charge storage structure 340 can include a tunnel insulating layer TL, a blocking insulating layer BLL, and a charge storage layer CTL. The tunnel insulating layer TL can be adjacent to each vertical channel portion VC and can surround the outer sidewalls of the vertical channel portion VC. The blocking insulating layer BLL can be adjacent to the gate electrode 320b and the gate electrode 320c. The charge storage layer CTL can be disposed between the tunnel insulating layer TL and the blocking insulating layer BLL. For example, the tunnel insulating layer TL can be a silicon oxide layer and / or a high-k dielectric layer (e.g., aluminum oxide (AI2O3) or hafnium oxide (HfO2)). For example, the blocking insulating layer BLL can be a silicon oxide layer and / or a high-k dielectric layer (e.g., aluminum oxide (AI2O3) or hafnium oxide (HfO2)). For example, the charge storage layer CTL can be a silicon nitride layer.

[0059] The gap fill layers 350 can be disposed in the inner spaces surrounded by the vertical channel portions VC, respectively. For example, each gap fill layer 350 can include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The pad 360 can be disposed on the vertical channel portions VC, the charge storage structures 340, and the gap fill layers 350. The pad 360 can include a conductive material or a semiconductor material doped with a dopant of a conductive type different from a conductive type of the vertical channel portions VC.

[0060] The gate insulating layer 370 can be disposed between each semiconductor pillar SP and the ground select gate electrode 320a. The sidewalls of the gate insulating layer 370 can have curved surfaces that are convex in opposite directions from each other. For example, the gate insulating layer 370 can be a thermal oxide layer.

[0061] The dummy channel structure DVS can penetrate the staircase structure STS of the first stack structures ST1a and ST1 to the fourth stack structures ST4a and ST4 on the top surface of the substrate 100. The dummy channel structure DVS can penetrate the end portions of the gate electrodes 320a, 320b, and 320c. The dummy channel structure DVS can have the same structure as the vertical cell channel structure CCS. The dummy channel structure DVS will be described later with reference to FIG. 6. Figure 13 and Figure 14 The dummy channel structure DVS will be described in more detail.

[0062] The horizontal insulating layer 380 can be disposed between the charge storage structures 340 and the gate electrodes 320b and 320c, between the gate insulating layer 370 and the gate electrode 320a, and can extend onto the top and bottom surfaces of the gate electrodes 320a, 320b, and 320c. For example, the horizontal insulating layer 380 can be a silicon oxide (SiO2) layer and / or a high-k dielectric layer (e.g., aluminum oxide (AI2O3) or hafnium oxide (HfO2)).

[0063] The first separation structure SRS1 can be disposed on the top surface of the substrate 100 between the first stack structure ST1a and the second stack structure ST2a closest to each other in the first direction X. In addition, the first separation structure SRS1 can extend in the first direction X between the first stack structures ST1 and ST1a and the third stack structures ST3 and ST3a facing the first stack structures ST1 and ST1a in the second direction Y. The first separation structure SRS1 can also extend in the first direction X between the second stack structures ST2 and ST2a and the fourth stack structures ST4 and ST4a facing the second stack structures ST2 and ST2a in the second direction Y. In addition, the first separation structure SRS1 can extend in the second direction Y between the third stack structure ST3a and the fourth stack structure ST4a closest to each other in the first direction X. First sidewalls SS1 of the first stack structures ST1a and ST1 to the fourth stack structures ST4a and ST4 parallel to the first direction X can be in contact with the first separation structure SRS1. A top surface of the first separation structure SRS1 can be located at substantially the same level as top surfaces of the first stack structures ST1a and ST1 to the fourth stack structures ST4a and ST4 and a top surface of the first interlayer insulating layer ILD1.

[0064] The first separation structure SRS1 can include a molding structure MS (i.e., a first molding structure MS1 of the molding structures MS of FIG. 1) and first to fourth separation layers SL1, SL2, SL3, and SL4. Figure 3A and Figure 3B The molding structure MS can include first molding layers M1 stacked in a third direction Z and second molding layers M2 disposed between each pair of the first molding layers M1, respectively. Each second molding layer M2 can be disposed between each pair of the first molding layers M1 adjacent to each other in the third direction Z. The second molding layers M2 can be disposed at the same level as the gate electrodes 320a, 320b, and 320c, respectively, and the first molding layers M1 can be disposed at the same level as the insulating patterns 330, respectively. The first molding layers M1 can include a material having etch selectivity with respect to the second molding layers M2. For example, each first molding layer M1 can be a silicon oxide layer, and each second molding layer M2 can be a silicon nitride layer.

[0065] The first separation layer SL1 can extend along the second direction Y between the molded structure MS and the first stack structure ST1a closest to the first separation structure SRS1, and can extend along the first direction X between the molded structure MS and the first sidewall SS1 of the first stack structure ST1a and ST1. The first separation layer SL1 can be in contact with the first sidewall SS1 of the first stack structure ST1a and ST1. The first sidewall SS1 of the first stack structure ST1a and ST1 can be a planar surface substantially perpendicular to the top surface of the substrate 100. The second separation layer SL2 can extend along the second direction Y between the molded structure MS and the second stack structure ST2a closest to the first separation structure SRS1, and can extend along the first direction X between the molded structure MS and the first sidewall SS1 of the second stack structure ST2a and ST2. The second separation layer SL2 can be in contact with the first sidewall SS1 of the second stack structure ST2a and ST2. The first sidewall SS1 of the second stack structure ST2a and ST2 can be a planar surface substantially perpendicular to the top surface of the substrate 100.

[0066] The third separation layer SL3 can extend along the second direction Y between the molded structure MS and the third stack structure ST3a closest to the first separation structure SRS1, and can extend along the first direction X between the molded structure MS and the first sidewall SS1 of the third stack structure ST3a and ST3. The third separation layer SL3 can be in contact with the first sidewall SS1 of the third stack structure ST3a and ST3. The first sidewall SS1 of the third stack structure ST3a and ST3 can be a planar surface substantially perpendicular to the top surface of the substrate 100. The fourth separation layer SL4 can extend along the second direction Y between the molded structure MS and the fourth stack structure ST4a closest to the first separation structure SRS1, and can extend along the first direction X between the molded structure MS and the first sidewall SS1 of the fourth stack structure ST4a and ST4. The fourth separation layer SL4 can be in contact with the first sidewall SS1 of the fourth stack structure ST4a and ST4. The first sidewall SS1 of the fourth stack structure ST4a and ST4 can be a planar surface substantially perpendicular to the top surface of the substrate 100. Each of the first separation layer SL1 to the fourth separation layer SL4 can be formed as a single layer (e.g., a single homogenous layer). Each of the first separation layer SL1 to the fourth separation layer SL4 can be, for example, a silicon oxide layer.

[0067] In some embodiments, the width W1 of the molding structure MS in the first direction X and the width W1’ of the molding structure MS in the second direction Y can be substantially equal to each other and can be substantially equal to the width W2 of each of the first stack structure ST1a and ST1 to the fourth stack structure ST4a and ST4 in the first direction X (W1, W1’ = W2). In certain embodiments, the width W1 of the molding structure MS in the first direction X and the width W1’ of the molding structure MS in the second direction Y can be different from the width W2 of each of the first stack structure ST1a and ST1 to the fourth stack structure ST4a and ST4 in the first direction X (W1, W1’ ≠ W2).

[0068] The second interlayer insulating layer ILD2 can cover the top surfaces of the first stack structure ST1a and ST1 to the fourth stack structure ST4a and ST4, the top surface of the first interlayer insulating layer ILD1, and the top surface of the first separation structure SRS1. For example, the second interlayer insulating layer ILD2 can be / include a silicon oxide layer.

[0069] The first to fourth contact structures 400a, 400b, 400c, and 400d can extend in the third direction Z on the top surface of the substrate 100 to penetrate the second interlayer insulating layer ILD2. The first contact structure 400a can extend in the second direction Y between the first stack structures ST1 and ST1a adjacent to each other and between the first stack structure ST1a and the first separation structure SRS1 adjacent to each other. The second contact structure 400b can extend in the second direction Y between the second stack structures ST2 and ST2a adjacent to each other and between the second stack structure ST2a and the first separation structure SRS1 adjacent to each other. The third contact structure 400c can extend in the second direction Y between the third stack structures ST3 and ST3a adjacent to each other and between the third stack structure ST3a and the first separation structure SRS1 adjacent to each other. The fourth contact structure 400d can extend in the second direction Y between the fourth stack structures ST4 and ST4a adjacent to each other and between the fourth stack structure ST4a and the first separation structure SRS1 adjacent to each other. The first to fourth contact structures 400a, 400b, 400c, and 400d can be in contact with the first separation structure SRS1.

[0070] In some embodiments, the second sidewalls SS2 of the first stack structure ST1a, the second stack structure ST2a, the third stack structure ST3a, and the fourth stack structure ST4a closest to the first separation structure SRS1 can be planar surfaces substantially perpendicular to the top surface of the substrate 100. The second sidewalls SS2 of the first stack structure ST1a to the fourth stack structure ST4a can be parallel to the second direction Y. In some embodiments, the first contact structure 400a to the fourth contact structure 400d respectively disposed between the first separation structure SRS1 and the first stack structure ST1a to the fourth stack structure ST4a can be in contact with the first separation layer SL1 to the fourth separation layer SL4 of the first separation structure SRS1 and can be spaced apart from the molding structure MS of the first separation structure SRS1.

[0071] Each of the first contact structure 400a to the fourth contact structure 400d can include a spacer 420 and a common-source contact 410. For example, the common-source contact 410 can be and / or include at least one of a metallic material (e.g., tungsten, copper, or aluminum) and a transition metal material (e.g., titanium or tantalum). The spacer 420 can surround the common-source contact 410. For example, the spacer 420 can be and / or include an insulating material (e.g., a silicon oxide layer or a silicon nitride layer).

[0072] A common-source region CSR can be disposed in the substrate 100 and can be respectively located below the first contact structure 400a to the fourth contact structure 400d. The common-source region CSR can be electrically connected to the common-source contact 410 of the first contact structure 400a to the fourth contact structure 400d, respectively. The common-source region CSR can have a conductivity type different from a conductivity type of the substrate 100.

[0073] A third interlayer dielectric layer ILD3 can be disposed on the second interlayer dielectric layer ILD2. The third interlayer dielectric layer ILD3 can cover a top surface of the second interlayer dielectric layer ILD2 and a top surface of the first contact structure 400a to the fourth contact structure 400d. For example, the third interlayer dielectric layer ILD3 can be and / or include a silicon oxide layer.

[0074] A channel contact plug CCP can be disposed on the pad 360. The channel contact plug CCP can penetrate the third interlayer dielectric layer ILD3 and the second interlayer dielectric layer ILD2 so as to be connected to the pad 360, respectively. For example, the channel contact plug CCP can include at least one of a conductive metal (e.g., copper or tungsten) and a metal nitride (e.g., TiN, TaN, or WN).

[0075] The cell contact plug 510 can be disposed on the staircase structure STS of the first stack structure ST1a and ST1 to the fourth stack structure ST4a and ST4. For example, the cell contact plug 510 can be disposed on the end portions of the gate electrodes 320a, 320b, and 320c. The cell contact plug 510 can contact and connect to the gate electrodes 320a, 320b, and 320c. The cell contact plug 510 can include at least one of a conductive metal (e.g., copper or tungsten) and a metal nitride (e.g., TiN, TaN, or WN).

[0076] The first peripheral contact plug PCP1 can be disposed in the first separation structure SRS1. For example, the first peripheral contact plug PCP1 can penetrate the third interlayer insulating layer ILD3, the second interlayer insulating layer ILD2, the molding structure MS, and the substrate 100. The first peripheral contact plug PCP1 can extend into the peripheral circuit interlayer insulating layer 210 and contact and connect to the interconnection conductor 213 of the peripheral circuit structure PRS. The first peripheral contact plug PCP1 can be electrically connected to the corresponding transistor TR of the peripheral circuit structure PRS through a wiring formed by the interconnection conductor 213 and the via 215. The second peripheral contact plug PCP2 can be disposed on the second peripheral circuit region PR2 of the substrate 100. For example, the second peripheral contact plug PCP2 can penetrate the third interlayer insulating layer ILD3, the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the substrate 100. The second peripheral contact plug PCP2 can extend into the peripheral circuit interlayer insulating layer 210 and contact and connect to the interconnection conductor 213. The second peripheral contact plug PCP2 can be electrically connected to the corresponding transistor TR of the peripheral circuit structure PRS through a wiring formed by the interconnection conductor 213 and the via 215.

[0077] A spacer (not shown) can be disposed between the substrate 100 and the first peripheral contact plug PCP1 and between the substrate 100 and the second peripheral contact plug PCP2. The first peripheral contact plug PCP1 and the second peripheral contact plug PCP2 can be spaced apart from the substrate 100 by the spacer. For example, the first peripheral contact plug PCP1 and the second peripheral contact plug PCP2 can be electrically insulated from the substrate 100 by the spacer. Each spacer can be an insulating layer surrounding a corresponding one of the first peripheral contact plug PCP1 and the second peripheral contact plug PCP2.

[0078] The second to fifth contact plugs 610b, 610c, 610d, and 610e can be disposed in the first separation structure SRS1. For example, the second to fifth contact plugs 610b, 610c, 610d, and 610e can penetrate the third interlayer insulating layer ILD3, the second interlayer insulating layer ILD2, and the molding structure MS. A bottom surface 611 of the second to fifth contact plugs 610b, 610c, 610d, and 610e can be in contact with the substrate 100. The bottom surface 611 of the second to fifth contact plugs 610b, 610c, 610d, and 610e can be located at substantially the same horizontal level as the top surface of the substrate 100, or can be located below the top surface of the substrate 100 (e.g., at a horizontal level between the top surface and the bottom surface of the substrate 100). The second to fifth contact plugs 610b, 610c, 610d, and 610e can be in contact with and electrically connected to the substrate 100. For example, referring to FIG. 6A, the second to fifth contact plugs 610b, 610c, 610d, and 610e can be in contact with and electrically connected to the substrate 100. Figure 3B and Figure 4 When viewed in a plan view, the second contact plug 610b can be disposed in the molding structure MS along sidewalls of the first and second end portions EP1 and EP2 of the first stack structure block STB1. When viewed in a plan view, the third contact plug 610c can be disposed in the molding structure MS along sidewalls of the first and second end portions EP1 and EP2 of the second stack structure block STB2. When viewed in a plan view, the fourth contact plug 610d can be disposed in the molding structure MS along sidewalls of the first and second end portions EP1 and EP2 of the third stack structure block STB3. When viewed in a plan view, the fifth contact plug 610e can be disposed in the molding structure MS along sidewalls of the first and second end portions EP1 and EP2 of the fourth stack structure block STB4. The second to fifth contact plugs 610b, 610c, 610d, and 610e disposed in the molding structure MS can be spaced apart from each other. The second to fifth contact plugs 610b, 610c, 610d, and 610e can include the same material as the channel contact plug CCP. For example, the contact plugs 610a to 610e can include at least one of a conductive metal (e.g., copper or tungsten) and a metal nitride (e.g., TiN, TaN, or WN).

[0079] The connection lines EC can be disposed on the third interlayer insulating layer ILD3. Each of the connection lines EC can connect a respective one of the second to fifth contact plugs 610b, 610c, 610d, and 610e with a respective one of the first peripheral contact plugs PCP1. Accordingly, the second to fifth contact plugs 610b, 610c, 610d, and 610e can be electrically connected to the transistors TR formed with the lower substrate 200 through the connection lines EC and the first peripheral contact plugs PCP1.

[0080] According to embodiments of the inventive concept, in combination with the first contact plug 610a, the second to fifth contact plugs 610b, 610c, 610d, and 610e can be respectively disposed around the stack structure block STB1, the stack structure block STB2, the stack structure block STB3, and the stack structure block STB4, and thus the resistance of the electrical connection to the substrate 100 can be reduced. As a result, the operating performance of the 3D semiconductor memory device can be improved.

[0081] The interconnection line ICN can be disposed on the third interlayer insulating layer ILD3. The interconnection line ICN can be connected to the cell contact plug 510 and the second peripheral contact plug PCP2. The bit lines BL1 and BL2 can be disposed on the third interlayer insulating layer ILD3. The bit lines BL1 and BL2 can include a first bit line BL1 crossing the first stack structures ST1 and ST1a, a second bit line BL2 crossing the second stack structures ST2 and ST2a, a third bit line (not shown) crossing the third stack structures ST3 and ST3a, and a fourth bit line (not shown) crossing the fourth stack structures ST4 and ST4a. The first to fourth bit lines can extend in the first direction X and can be spaced apart from each other.

[0082] The first bit line BL1 and the second bit line BL2 facing each other in the first direction X can be aligned with each other and can be spaced apart from each other. The first bit line BL1 and the second bit line BL2 can not be electrically connected to each other. The third bit line and the fourth bit line facing each other in the first direction X can be aligned with each other and can be spaced apart from each other. The third bit line and the fourth bit line can not be electrically connected to each other.

[0083] Figure 8 is a cross-sectional view taken along a line I-I' of Figure 4 to illustrate a 3D semiconductor memory device according to some embodiments of the inventive concept.

[0084] Referring to Figure 8 , the vertical channel portion VC and the charge storage structure 340 can extend to and contact a top surface of the substrate 100. In Figure 8 embodiments, the semiconductor pillar SP and the gate insulating layer 370 described with reference to Figure 4 to Figure 7 may be omitted. Figure 8 Other structures of embodiments of the inventive concept can be the same as other structures described with reference to Figure 1 to Figure 7 and / or the same as other structures of any one of alternative embodiments of Figure 1 to Figure 7 .

[0085] Figure 9 is a cross-sectional view taken along a line I-I' of Figure 4 to illustrate a 3D semiconductor memory device according to some embodiments of the inventive concept.Figure 10 is a cross-sectional view taken along the line II-II’ of Figure 4 for illustrating a 3D semiconductor memory device according to some embodiments of inventive concepts.

[0086] With reference to Figure 9 and Figure 10 , the transistor TR can be disposed in and / or on the second peripheral circuit region PR2 of the substrate 100. A top of the transistor TR can be disposed at a horizontal level between the ground select gate electrode 320a and the lowermost unit gate electrode 320b, and the transistor TR can be covered by the insulating pattern 330 on a top surface of the second peripheral circuit region PR2 of the substrate 100. In Figure 9 and Figure 10 , the lower substrate 200 and the peripheral circuit structure PRS formed on the lower substrate 200 can be omitted. The first peripheral contact plug PCP1 can not be disposed in the first separation structure SRS1. The second peripheral contact plug PCP2 can penetrate the third interlayer insulating layer ILD3, the second interlayer insulating layer ILD2, and the first interlayer insulating layer ILD1 and extend to the insulating pattern 330 on the second peripheral circuit region PR2, and can be electrically connected to the source / drain region 60 of the transistor TR disposed in the substrate 100.

[0087] The second to fifth contact plugs 610b, 610c, 610d, and 610e can be disposed in the molded structure MS of the first separation structure SRS1. The second to fifth contact plugs 610b, 610c, 610d, and 610e can penetrate the third interlayer insulating layer ILD3, the second interlayer insulating layer ILD2, and the molded structure MS. The connection line EC can be disposed on the third interlayer insulating layer ILD3. The connection line EC can connect the second peripheral contact plug PCP2 to the second to fifth contact plugs 610b to 610e. The first to fifth contact plugs 610a to 610e can be electrically connected to the transistor TR disposed on the second peripheral circuit region PR2 of the substrate 100. Figure 9 and Figure 10 , other structures of embodiments of Figure 1 to Figure 7 may be the same as other structures described for Figure 1 to Figure 7 and / or the same as other structures of any one of the alternative embodiments of

[0088] Figure 11 is an enlarged view of the portion “A” of Figure 3A . Figure 12 is a cross-sectional view taken along the line I-I’ of Figure 11 for illustrating a 3D semiconductor memory device according to some embodiments of inventive concepts.

[0089] Referring to Figure 11 and Figure 12 , second contact plugs to fifth contact plugs 610b, 610c, 610d, and 610e can be disposed in the first to fourth separation layers SL1, SL2, SL3, and SL4. For example, the second contact plug 610b can be arranged in a row along the first separation layer SL1, and the third contact plug 610c can be arranged in a row along the second separation layer SL2. The fourth contact plug 610d can be arranged in a row along the third separation layer SL3, and the fifth contact plug 610e can be arranged in a row along the fourth separation layer SL4. Figure 11 and Figure 12 , other structures of embodiments of the present application can be the same as other structures described with respect to Figure 1 to Figure 7 and / or the same as other structures of any one of the alternative embodiments of Figure 1 to Figure 7 .

[0090] Figure 13 is an enlarged view of part "A" of Figure 3A . Figure 14 is a cross-sectional view taken along line III-III' of Figure 13 to illustrate a 3D semiconductor memory device according to some embodiments of inventive concepts.

[0091] Referring to Figure 13 and Figure 14 , the through-insulation patterns TIP can penetrate a pair of first stack structures ST1 and ST1a adjacent to each other in the first direction X, a pair of second stack structures ST2 and ST2a adjacent to each other in the first direction X, a pair of third stack structures ST3 and ST3a adjacent to each other in the first direction X, and a pair of fourth stack structures ST4 and ST4a adjacent to each other in the first direction X. The through-insulation patterns TIP can penetrate the substrate 100 and can be in contact with a top surface of the peripheral circuit structure PRS. Each through-insulation pattern TIP can be disposed between a cell contact plug 510 connected to the string selection gate electrode 320c and a vertical channel portion VC when viewed in a plan view. A sidewall of the through-insulation pattern TIP can be inclined with respect to a top surface of the substrate 100. For example, the through-insulation pattern TIP can be a high-density plasma (HDP) oxide layer, a tetraethyl orthosilicate (TEOS) layer, a plasma-enhanced tetraethyl orthosilicate (PE-TEOS) layer, an O3-tetraethyl orthosilicate (O3-TEOS) layer, an undoped silicate glass (USG) layer, a phosphosilicate glass (PSG) layer, a borosilicate glass (BSG) layer, a borophosphosilicate glass (BPSG) layer, a fluorosilicate glass (FSG) layer, a spin-on glass (SOG) layer, a Tonen Silazene (TOSZ) layer, or any combination thereof.

[0092] Although not shown in the accompanying drawings, a dummy channel structure (DVS) may surround a through-insulation pattern TIP in a planar view and may penetrate from the first stacked structures ST1a and ST1 to the fourth stacked structures ST4a and ST4. Each dummy channel structure (DVS) may include a dummy semiconductor pillar SP', a dummy vertical channel portion VC', a dummy charge storage structure 340', a dummy gap fill layer 350', and a dummy pad 360'. The dummy channel structure (DVS) may have the same characteristics as described herein (e.g., as for...). Figure 5 or Figure 8 The vertical channel portion VC, charge storage structure 340, and gap filling layer 350 described herein have the same structure. The dummy channel structure DVS can also have the same structure (e.g., when utilizing...). Figure 5 The structure is the same as that of the semiconductor pillars in the implementation. The dummy channel structure (DVS) may not be connected to any bit line (BL) or may otherwise be connected for input and / or output data. For example, the channel contact plug (CCP) may not be provided on the top surface of the dummy pad 360' of the dummy channel structure (DVS). The dummy pad 360' may be covered by the second interlayer insulating layer (ILD2). The dummy gate insulating layer (370') may be provided between the dummy semiconductor pillar (SP') and the ground select gate electrode (320a).

[0093] The third peripheral contact plug PCP3 can penetrate the insulating pattern TIP and the substrate 100, and can be connected to the interconnect conductor 213 of the peripheral circuit structure PRS. The third peripheral contact plug PCP3 can be connected to the interconnect line ICN disposed on the top surface of the third interlayer insulating layer ILD3. Figure 13 and Figure 14 Other structures of the embodiments can be used with respect to Figure 1 to Figure 7 The other structures described are the same as and / or similar to those described. Figure 1 to Figure 7 The other structures of any of the alternative embodiments are the same.

[0094] Figure 15 yes Figure 3A A magnified view of part of the "A". Figure 16 It is along Figure 15 The line IV-IV' is a cross-sectional view used to illustrate some embodiments of a 3D semiconductor memory device according to the present invention. Figure 17 yes Figure 16 A magnified view of part of the "C".

[0095] Reference Figure 15 to Figure 17The first contact structure 400a between the first stack structure ST1a and the first separation structure SRS1, the second contact structure 400b between the second stack structure ST2a and the first separation structure SRS1, the third contact structure 400c between the third stack structure ST3a and the first separation structure SRS1, and the fourth contact structure 400d between the fourth stack structure ST4a and the first separation structure SRS1 can be in contact with the molded structure MS of the first separation structure SRS1. In Figure 15 to Figure 17 The first to fourth separation layers SL1 to SL4 can be omitted in the first separation structure SRS1 in the present embodiment. The first separation structure SRS1 (i.e., the molded structure MS) can include first molded layers M1 stacked along the third direction Z, second molded layers M2 disposed between the first molded layers M1, and third molded layers M3. The sidewalls of the second molded layers M2 can be laterally recessed from the sidewalls of the first molded layers M1. For example, the width W3 of the second molded layers M2 in the first direction X can be smaller than the width W4 of the first molded layers M1 in the first direction X (W3 < W4).

[0096] The third molded layers M3 can be disposed on both sides of each second molded layer M2 between the first molded layers M1 adjacent to each other in the third direction Z. One sidewall of each third molded layer M3 can be in contact with a corresponding one of the second molded layers M2. The other sidewall of each third molded layer M3 opposite to the one sidewall can be aligned with the sidewalls of the first molded layers M1 and in contact with the contact structure 400a, the contact structure 400b, the contact structure 400c, or the contact structure 400d. Each third molded layer M3 can include an insulating molded layer IML and a metallic molded layer MML. The metallic molded layer MML can be disposed between adjacent (adjacent to each other in the third direction) ones of the first molded layers M1. The insulating molded layer IML can be disposed between the metallic molded layer MML and the second molded layers M2 and can extend onto the top and bottom surfaces of the metallic molded layer MML. The insulating molded layer IML can be formed of the same material as the horizontal insulating layer 380. The metallic molded layer MML can be formed of the same material as the gate electrodes 320a, 320b, and 320c. The first peripheral connection plug PCP1 disposed in the molded structure MS can penetrate the first molded layers M1 and the second molded layers M2 and can be spaced apart from the third molded layers M3. The second to fifth connection plugs 610b, 610c, 610d, and 610e disposed in the molded structure MS can penetrate the first molded layers M1 and the second molded layers M2 and can be spaced apart from the third molded layers M3. Figure 7 The first to fourth separation layers SL1 to SL4 can be omitted in the first separation structure SRS1 in the present embodiment. The first separation structure SRS1 (i.e., the molded structure MS) can include first molded layers M1 stacked along the third direction Z, second molded layers M2 disposed between the first molded layers M1, and third molded layers M3. The sidewalls of the second molded layers M2 can be laterally recessed from the sidewalls of the first molded layers M1. For example, the width W3 of the second molded layers M2 in the first direction X can be smaller than the width W4 of the first molded layers M1 in the first direction X (W3 < W4).

[0096] The third molded layers M3 can be disposed on both sides of each second molded layer M2 between the first molded layers M1 adjacent to each other in the third direction Z. One sidewall of each third molded layer M3 can be in contact with a corresponding one of the second molded layers M2. The other sidewall of each third molded layer M3 opposite to the one sidewall can be aligned with the sidewalls of the first molded layers M1 and in contact with the contact structure 400a, the contact structure 400b, the contact structure 400c, or the contact structure 400d. Each third molded layer M3 can include an insulating molded layer IML and a metallic molded layer MML. The metallic molded layer MML can be disposed between adjacent (adjacent to each other in the third direction) ones of the first molded layers M1. The insulating molded layer IML can be disposed between the metallic molded layer MML and the second molded layers M2 and can extend onto the top and bottom surfaces of the metallic molded layer MML. The insulating molded layer IML can be formed of the same material as the horizontal insulating layer 380. The metallic molded layer MML can be formed of the same material as the gate electrodes 320a, 320b, and 320c. The first peripheral connection plug PCP1 disposed in the molded structure MS can penetrate the first molded layers M1 and the second molded layers M2 and can be spaced apart from the third molded layers M3. The second to fifth connection plugs 610b, 610c, 610d, and 610e disposed in the molded structure MS can penetrate the first molded layers M1 and the second molded layers M2 and can be spaced apart from the third molded layers M3.

[0097] The molding structure MS can be in contact with the first stack structures ST1a and ST1 to the fourth stack structures ST4a and ST4. For example, the first stack structures ST1a and ST1 to the fourth stack structures ST4a and ST4 can be in contact with the first molding layer M1 and the third molding layer M3 of the molding structure MS. The first stack structures ST1a and ST1 to the fourth stack structures ST4a and ST4 can be spaced apart from the second molding layer M2 of the molding structure MS. In some embodiments, the width W1 of the molding structure MS in the first direction X and the width W1’ of the molding structure MS in the second direction Y can be greater than the width W2 of the first stack structures ST1a and ST1 to the fourth stack structures ST4a and ST4 in the first direction X (W1, W1’ > W2). Figure 15 to Figure 17 Other structures of embodiments of the present application can be the same as and / or the same as other structures of any one of alternative embodiments of the present application described in Figure 1 to Figure 7 Figure 1 to Figure 7

[0098] Figure 18 Figure 2 is an enlarged view of the semiconductor chip of Figure 19 is an enlarged view of the portion “D” of Figure 18

[0099] Referring to Figure 18 and Figure 19 Each semiconductor chip USC can include a substrate 100, blocks BLK disposed on a top surface of the substrate 100, and a first interlayer insulating layer ILD1. The blocks BLK can be spaced apart from each other in the second direction Y on the top surface of the substrate 100. The first interlayer insulating layer ILD1 can cover sidewalls of the blocks BLK on the top surface of the substrate 100. Each block BLK can include first stack structure blocks STB1, second stack structure blocks STB2, and a separation structure SRS. The first stack structure blocks STB1 and the second stack structure blocks STB2 can be spaced apart from each other in the first direction X on the top surface of the substrate 100. The first stack structure blocks STB1 of the blocks BLK can be spaced apart from each other in the second direction Y, and the second stack structure blocks STB2 of the blocks BLK can be spaced apart from each other in the second direction Y.

[0100] The separation structure SRS can be disposed between the first stack structure blocks STB1 and the second stack structure blocks STB2. The separation structure SRS can extend in the second direction Y on the top surface of the substrate 100 to penetrate the first interlayer insulating layer ILD1 disposed between the blocks BLK.

[0101] ​​​​The separation structure SRS can include: a molding structure MS, a first separation layer SL1, and a second separation layer SL2. Each molding structure MS can be disposed between a first stack structure block STB1 and a second stack structure block STB2 facing each other in a first direction X. The molding structures MS can be spaced apart from each other in a second direction Y. The first separation layer SL1 can extend between each molding structure MS and each first stack structure block STB1 in the second direction Y. The first separation layer SL1 can extend in the second direction Y and penetrate the first interlayer insulation layer ILD1. The second separation layer SL2 can extend between each molding structure MS and each second stack structure block STB2 in the second direction Y. The second separation layer SL2 can extend in the second direction Y and can penetrate the first interlayer insulation layer ILD1. Two end portions of each molding structure MS in contact with the first interlayer insulation layer ILD1 can have a stepped structure STS_a. The two end portions of each molding structure MS can be opposite each other in the second direction Y.

[0102] Each first stack structure block STB1 can include first stack structures ST1 and ST1a spaced apart from each other in the first direction X, and each second stack structure block STB2 can include second stack structures ST2 and ST2a spaced apart from each other in the first direction X. In some embodiments, sidewalls of the first stack structure block STB1 and the second stack structure block STB2 in contact with the separation structure SRS can be flat surfaces substantially perpendicular to a top surface of the substrate 100.

[0103] Sidewalls SS2 of the first stack structure ST1a and the second stack structure ST2a closest to the separation structure SRS can be flat surfaces substantially perpendicular to a top surface of the substrate 100. The sidewalls SS2 of the first stack structure ST1a and the second stack structure ST2a can be parallel to the second direction Y and can be in contact with a first contact structure 400a disposed between the separation structure SRS and the first stack structure ST1a and a second contact structure 400b disposed between the separation structure SRS and the second stack structure ST2a, respectively.

[0104] In some embodiments, two end portions of each of the first stack structure ST1 and ST1a and the second stack structure ST2 and ST2a that are in contact with the first interlayer insulating layer IDL1 can have a stepped structure STS. The two end portions of each of the first stack structure ST1 and ST1a and the second stack structure ST2 and ST2a can be opposite to each other in the second direction Y. In some embodiments, a width W1 of the molding structure MS in the first direction X can be substantially equal to a width W2 of each of the first stack structure ST1, ST1a and the second stack structure ST2 and ST2a in the first direction X (W1 = W2). In certain embodiments, the width W1 of the molding structure MS in the first direction X can be different from the width W2 of each of the first stack structure ST1, ST1a and the second stack structure ST2 and ST2a in the first direction X (W1 ≠ W2).

[0105] The first contact plug 610a can be arranged along a periphery of each of the blocks BLK when viewed in a plan view. The first contact plug 610a can penetrate the first interlayer insulating layer IDL1. The second contact plug 610b and the third contact plug 610c can be provided in each of the molding structures MS. The second contact plug 610b and the third contact plug 610c can penetrate the molding structure MS. The second contact plug 610b can be arranged along the first separation layer SL1 in each of the molding structures MS, and the third contact plug 610c can be arranged along the second separation layer SL2 in each of the molding structures MS. The second contact plug 610b and the third contact plug 610c can be spaced apart from each other.

[0106] Figure 20 is Figure 18 an enlarged view of a portion "D" of Figure 18 and Figure 19 The same elements or components that are described in the above-described embodiments of the

[0107] Referring to Figure 20 , the first contact structure 400a between the first stack structure ST1a and the separation structure SRS can be in contact with the molding structure MS of the separation structure SRS, and the second contact structure 400b between the second stack structure ST2a and the separation structure SRS can be in contact with the molding structure MS of the separation structure SRS. In other words, the first separation layer SL1 and the second separation layer SL2 can be omitted in the separation structure SRS in the present embodiment.

[0108] The second contact plug 610b can be arranged in the molding structure MS along the first contact structure 400a in contact with the molding structure MS in the second direction Y, and the third contact plug 610c can be arranged in the molding structure MS along the second contact structure 400b in contact with the molding structure MS in the second direction Y.

[0109] In some embodiments, a width W1 of the molding structure MS in the first direction X can be greater than a width W2 of each of the first stack structure ST1, ST1a and the second stack structure ST2 and ST2a in the first direction X (W1>W2). Figure 18 to Figure 20 Other structures of embodiments of the present inventive concept can be the same as other structures described with respect to Figure 1 to Figure 7 any one of alternative embodiments of the present inventive concept. Figure 1 to Figure 7 any one of alternative embodiments of the present inventive concept.

[0110] According to embodiments of the present inventive concept, the first to fifth contact plugs can be arranged to surround the stack structure blocks, respectively, and thus can reduce an electrical resistance of an electrical connection with the substrate. As a result, an operation performance of the 3D semiconductor memory device can be improved.

[0111] Although the present inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present inventive concept. It is therefore intended that such changes and modifications be included within the scope of the application as defined by the appended claims and their equivalents. Accordingly, the above-described embodiments are to be considered in all respects as illustrative and not restrictive. The scope of the present inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and should not be limited or restricted by the foregoing description.

Claims

1. A three-dimensional semiconductor memory device, comprising: a first stack structure block including first stack structures arranged side by side in a first direction on a substrate; a second stack structure block including second stack structures arranged side by side in the first direction on the substrate; a separation structure provided on the substrate and including a molding structure including first molding layers and second molding layers alternately and repeatedly stacked in a vertical direction; and a contact plug penetrating the separation structure, wherein a bottom surface of the contact plug is in contact with the substrate, wherein the first stack structure block has a first sidewall of a first end portion in contact with the separation structure, the second stack structure block has a first sidewall of a first end portion in contact with the separation structure, the first end portion of the first stack structure block and the first end portion of the second stack structure block are flat and extend vertically, and the molding structure is located between the first end portion of the first stack structure block and the first end portion of the second stack structure block, wherein the first stack structure block has a second end portion spaced apart from the separation structure, the second stack structure block has a second end portion spaced apart from the separation structure, and the second end portions of the first stack structure block and the second stack structure block have a stepped structure. The bottom surface of the contact plug is disposed below a top surface of the substrate.

2. The three-dimensional semiconductor memory device of claim 1, wherein, 3. The three-dimensional semiconductor memory device of claim 1, further comprising a plurality of contact plugs penetrating the separation structure and in contact with the substrate, the plurality of contact plugs including the contact plug, the plurality of contact plugs including a first contact plug and a second contact plug, wherein wherein the first contact plug is arranged along the first sidewall of the first stack structure block in contact with the separation structure, and wherein the second contact plug is arranged along the first sidewall of the second stack structure block in contact with the separation structure. The separation structure further includes:

4. The three-dimensional semiconductor memory device of claim 1, wherein, a first separation layer between the first stack structure block and the first molding layers and the second molding layers; a second separation layer between the second stack structure block and the first molding layers and the second molding layers; and a plurality of contact plugs penetrating the separation structure and in contact with the substrate, the plurality of contact plugs including the contact plug, wherein the plurality of contact plugs include a first contact plug and a second contact plug, wherein the first contact plug is arranged along the first separation layer, and wherein the second contact plug is arranged along the second separation layer. The first separation layer and the second separation layer are formed of a same material as a material of the first molding layers or the second molding layers.

5. The three-dimensional semiconductor memory device of claim 4, wherein, 6. The three-dimensional semiconductor memory device of claim 1, the first molding layers are stacked in the vertical direction on a top surface of the substrate, and wherein wherein each of the second molding layers is disposed between a respective pair of adjacent first molding layers among the first molding layers.

7. The three-dimensional semiconductor memory device of claim 1, ​ wherein, a first end portion of the first stack structure block is disposed parallel to the first direction when viewed in a plan view, wherein a second end portion of the first stack structure block is disposed parallel to a second direction different from the first direction when viewed in a plan view, wherein a first end portion of the second stack structure block is disposed parallel to the first direction when viewed in a plan view, wherein a second end portion of the second stack structure block is disposed parallel to the second direction when viewed in a plan view, wherein the three-dimensional semiconductor memory device further includes an interlayer insulating layer, wherein the interlayer insulating layer is in contact with the second end portion of the first stack structure block and the second end portion of the second stack structure block.

8. The three-dimensional semiconductor memory device of claim 1, wherein each of the first stack structures includes a gate electrode, and the three-dimensional semiconductor memory device further includes: a cell contact plug in contact with an end portion of the gate electrode, wherein the contact plug is formed of the same material as that of the cell contact plug.

9. The three-dimensional semiconductor memory device of claim 1, further comprising: a lower substrate disposed below the substrate; a peripheral circuit structure disposed at the lower substrate, the peripheral circuit structure including transistors, interconnection conductors, and vias; and a peripheral contact plug penetrating the separation structure and the substrate and connected to the transistors.

10. A three-dimensional semiconductor memory device, comprising: a first stack structure block including first stack structures arranged side by side in a first direction on a first substrate; a second stack structure block including second stack structures arranged side by side in the first direction on the first substrate; a separation structure disposed on the first substrate between the first stack structure block and the second stack structure block and including a first molding layer and a second molding layer; a first contact plug penetrating the separation structure and the first substrate; a second contact plug penetrating the separation structure and connected to the first substrate; and a connection line connecting the first contact plug and the second contact plug, wherein the separation structure includes: the first molding layer stacked in a vertical direction to a top surface of the first substrate; a pair of the second molding layers spaced apart from each other in a second direction crossing the first direction between first molding layers adjacent in the vertical direction; and a third molding layer disposed between the pair of second molding layers between first molding layers adjacent in the vertical direction, wherein the first molding layer and the second molding layer and the third molding layer include different materials from each other, wherein the first contact plug and the second contact plug penetrate the first molding layer and the third molding layer.

11. The three-dimensional semiconductor memory device of claim 10, further comprising: a second substrate disposed below the first substrate; and a peripheral circuit structure disposed at the second substrate and including transistors, The lower part of the first contact plug is disposed in the peripheral circuit structure and connected to the transistor.

12. The three-dimensional semiconductor memory device of claim 10, wherein, A bottom surface of the second contact plug is in contact with the first substrate.

13. The three-dimensional semiconductor memory device of claim 10, wherein, The first molding layer and the third molding layer include an insulating material, The second molding layer includes a metallic material.

14. The three-dimensional semiconductor memory device of claim 10, wherein, The first molding layer and the second molding layer are alternately and repeatedly stacked on the first substrate, The first molding layer and the second molding layer include different insulating materials from each other.

15. A three-dimensional semiconductor memory device, comprising: a first stack structure block including first stack structures arranged side by side in a first direction on a substrate, wherein the first stack structure block includes a first end portion that is flat and vertically extends above the substrate, the first stack structure block further including a second end portion opposite the first end portion in a second direction perpendicular to the first direction; a second stack structure block including second stack structures arranged side by side in the first direction on the substrate, the second stack structure block including a first end portion that is flat and vertically extends, and a second end portion opposite the first end portion of the second stack structure block in the second direction; a separation structure disposed on the substrate and disposed on a first sidewall of the first end portion of the first stack structure block and between the first end portion of the first stack structure block and the first end portion of the second stack structure block, the separation structure including a molding structure including first molding layers and second molding layers alternately and repeatedly stacked in a vertical direction; and a first contact plug penetrating the separation structure and arranged along the first sidewall of the first end portion of the first stack structure block, wherein the second end portion of the first stack structure block and the second end portion of the second stack structure block have a stepped structure.

16. The three-dimensional semiconductor memory device of claim 15, wherein, the first stack structure block further including a third end portion that is flat and vertically extends above the substrate, wherein, when viewed in a plan view, the first sidewall of the first end portion is parallel to the first direction, and wherein, when viewed in a plan view, a second sidewall of the third end portion is parallel to the second direction.

17. The three-dimensional semiconductor memory device of claim 15, wherein, the separation structure including: a molding structure disposed on the substrate and disposed on the first sidewall of the first end portion of the first stack structure block; and a separation layer disposed between the molding structure and the first stack structure block, wherein the molding structure includes: first molding layers stacked in a direction perpendicular to a top surface of the substrate; and second molding layers disposed between the first molding layers.

18. The three-dimensional semiconductor memory device of claim 15, further comprising: a transistor disposed below the substrate; a second contact plug that penetrates the separation structure and the substrate and is connected to the transistor; and connection lines each connecting a respective one of the first contact plugs and a respective one of the second contact plugs.

19. The three-dimensional semiconductor memory device of claim 15, wherein, The first stack structure block further includes: a third end portion and a fourth end portion disposed between the first end portion of the first stack structure block and the second end portion of the first stack structure block and opposite to each other in the first direction, The three-dimensional semiconductor memory device further includes: an interlayer insulating layer that surrounds a second sidewall of the second end portion of the first stack structure block, a third sidewall of the third end portion, and a fourth sidewall of the fourth end portion; and a second contact plug that penetrates the interlayer insulating layer, wherein the second contact plug is arranged along the second sidewall of the second end portion of the first stack structure block, the third sidewall of the third end portion, and the fourth sidewall of the fourth end portion.

20. The three-dimensional semiconductor memory device of claim 19, wherein, The second end portion of the first stack structure block, the third end portion, and the fourth end portion have a stepped structure.

21. The three-dimensional semiconductor memory device of claim 15, wherein, The first stack structure block further includes: a third end portion and a fourth end portion disposed between the first end portion of the first stack structure block and the second end portion of the first stack structure block and opposite to each other in the first direction, wherein the separation structure extends to a third sidewall of the third end portion, The three-dimensional semiconductor memory device further includes: an interlayer insulating layer that surrounds a second sidewall of the second end portion of the first stack structure block and a fourth sidewall of the fourth end portion; and a second contact plug that penetrates the interlayer insulating layer, wherein the first contact plug is arranged along a first sidewall of the first end portion of the first stack structure block and a third sidewall of the third end portion, and wherein the second contact plug is arranged along a second sidewall of the second end portion of the first stack structure block and a fourth sidewall of the fourth end portion.

22. The three-dimensional semiconductor memory device of claim 15, wherein, The first contact plug is connected to the substrate.

Images