Design Methodology for 3300V 4H-SiC MOSFET

Abstract

The present invention discloses a 3300V 4H-SiC MOSFET design method, which adopts a UMOSFET structure; the structural parameters are optimized as follows: the concentration of the epitaxial layer drift region is 8e 15 cm ‑3 , epitaxial layer thickness 20μm, channel length 2.8μm. This paper designs various structural parameters of MOSFET, ensuring that the power device withstand voltage meets the target of 3300V, and further optimizes the output characteristic to meet the low conduction loss and high frequency characteristics. Simulation data shows that the structural parameters are drift region concentration 8e15cm ‑3 MOSFET cells with a thickness of 25 μm, a trench length of 2.8 μm, and a gate oxide thickness of 500 A can achieve a breakdown voltage of 4310 V and a resistance of 6.1 mΩ·cm 2 The specific on-resistance is 4.81V, the drain current is 110A, and the gate charge is 4.25nC at a drain voltage of 6V.

Description

Technical Field

[0001] The invention relates to a 3300V 4H-SiC MOSFET design method, belonging to the technical field of semiconductors. Background Art

[0002] In the semiconductor industry, silicon substrates are currently the mainstream device on the market. However, due to increasing demand and the inherent limitations of Si materials, Si-based devices are gradually failing to meet these requirements. In 1994, J.W. Palmour et al. first proposed the SiC UMOSFET structure, attracting attention to wide-bandgap semiconductor materials like SiC. Its advantages in bandgap, breakdown field strength, and thermal conductivity make it suitable for a wider range of applications. Consequently, wide-bandgap materials have come into the spotlight.

[0003] SiC, a representative of third-generation semiconductor materials, is the wide-bandgap semiconductor with the most mature crystal growth technology and power semiconductor device manufacturing capabilities. Its bandgap, critical electric field, saturation drift velocity, and thermal conductivity are all significantly greater than those of Si. This means SiC offers superior high-frequency, high-power, and high-temperature capabilities. Furthermore, compared to gallium nitride, only SiC can be thermally grown to form its intrinsic oxide, SiO2, making it suitable for manufacturing any MOSFET device. These advantages have attracted extensive research and significant attention to SiC-based MOSFET devices. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide a 3300V 4H-SiC MOSFET design method.

[0005] In order to solve the above technical problems, the technical solutions adopted by the present invention are as follows:

[0006] A 3300V 4H-SiC MOSFET design method using a UMOSFET structure;

[0007] The structural parameters are optimized as follows: epitaxial layer concentration 8e 15 cm -3 , epitaxial layer thickness is 20μm, and channel length is 2.8μm.

[0008] Furthermore, the gate oxide thickness is The voltage threshold is 4.81V.

[0009] Furthermore, the specific on-resistance is 6.1 mΩ·cm 2 , drain current is 110A, and gate-drain charge is 1.29nC.

[0010] Furthermore, according to formula (1) and the verification of Silvaco simulation software, the thickness of the epitaxial layer is initially set to 20 μm, and the concentration of the epitaxial layer is initially set to 8e 15 cm -3 , the gate oxide thickness is initially set to The channel length was set to 2.5 μm;

[0011] N D =1.10*10 20 *BV -1.27 (1)

[0012] W D =2.62*10 -3 *BV 1.12 (2)

[0013] Where: W D Indicates the thickness of the epitaxial layer; N D represents the doping concentration of the epitaxial layer; BV represents the breakdown voltage;

[0014] Further optimize the channel length and on-resistance.

[0015] Furthermore, a breakdown voltage BV curve corresponding to different epitaxial thicknesses was established, and combined with the relationship between epitaxial layer thickness and on-resistance, the epitaxial layer thickness was analyzed and determined to be 20 μm.

[0016] Furthermore, the withstand voltage value was improved by optimizing and increasing the channel length, and considering the relationship between the withstand voltage value and the on-resistance, the optimized channel length was determined to be 2.8 μm.

[0017] Furthermore, the voltage threshold is controlled by adjusting the gate oxide thickness or the channel concentration. The voltage threshold transfer characteristic curve under different gate oxide thicknesses is obtained through Silvaco simulation, and the gate oxide thickness is determined by Optimized to

[0018] The beneficial effects achieved by the present invention are:

[0019] The present invention designs various structural parameters of MOSFET to ensure that the withstand voltage of the power device meets the target of 3300V, and further optimizes the output characteristic quantity to meet the low conduction loss and high frequency characteristics. Simulation data shows that the structural parameters are drift region concentration 8e15cm -3 MOSFET cells with a thickness of 25μm, a trench length of 2.8μm, and a gate oxide thickness of 500A can achieve a breakdown voltage of 4310V and a resistance of 6.1mΩ·cm 2 The specific on-resistance is 4.81V, the drain current is 110A, the gate-drain charge is 1.29nC, and the gate charge is 4.25nC at a drain voltage of 6V. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 U-MOSFET device cross-section;

[0021] Figure 2 BV curves corresponding to different epitaxial layer thicknesses;

[0022] Figure 3 BV curves corresponding to different epitaxial layer concentrations under 2.5μm trench length;

[0023] Figure 4 BV curves corresponding to different epitaxial layer concentrations under 2.8μm trench length;

[0024] Figure 5(a) Transfer characteristic curves under different gate oxide thicknesses;

[0025] Figure 5(b) Output characteristic curve of

[0026] Figure 5(c) BV characteristic curve;

[0027] Figure 6 Schematic diagram of MOSFET parasitic capacitance;

[0028] Figure 7 Gate charge test circuit;

[0029] Figure 8 Gate charge curve;

[0030] Figure 9 (a) BV curve;

[0031] Figure 9(b) Transfer curve at 0.1V leakage voltage;

[0032] Figure 9(c) Output curve at 20V gate voltage. DETAILED DESCRIPTION

[0033] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.

[0034] 1 3300V SiC MOSFET structure design

[0035] 1.1 Preliminary structure setting

[0036] The 3300V mentioned in this solution refers to the device's withstand voltage. Power devices require termination technology to mitigate premature breakdown caused by electric field concentration. This solution initially designed the withstand voltage of a single cell's planar junction. Generally speaking, a well-designed termination ensures the device's actual withstand voltage reaches over 80% of the cell's ideal planar junction withstand voltage. Therefore, to meet the 3300V withstand voltage requirement, the withstand voltage of a single cell is at least 3300 / 0.8 = 4125V.

[0037] Currently, the most widely researched and commercialized power MOSFETs are of two structures: planar junction and vertical. Although the on-resistance of the planar junction structure is relatively small, the voltage level it can reach is also limited. Therefore, this solution uses the UMOSFET structure for the design of high-voltage MOSFETs. Its cell structure is as follows: Figure 1 As shown, according to the empirical formula (1) and the verification of Silvaco simulation software, the thickness of the epitaxial layer is initially set to 20 μm, and the concentration of the epitaxial layer is initially set to 8e 15 cm -3 , gate oxide thickness The channel length was set to 2.5 μm.

[0038] N D =1.10*10 20 *BV -1.27 (cm -3 ) (1)

[0039] W D =2.62*10 -3 *BV 1.12 (μm) (2)

[0040] Where: W D Indicates the thickness of the epitaxial layer; N D represents the doping concentration of the epitaxial layer; BV represents the breakdown voltage.

[0041] 1.2 Optimization of longitudinal structural parameters

[0042] According to formula (1), BV is proportional to the thickness of the epitaxial layer. The breakdown voltage BV curves corresponding to different epitaxial layer thicknesses are as follows: Figure 2 Data analysis shows that among 11μm, 15μm, 20μm, and 25μm, the BV difference between 20μm and 25μm is not large. However, the thicker the epitaxial layer, the greater the on-resistance. Therefore, choosing 20μm will provide better performance.

[0043] Similarly, BV is inversely proportional to the epitaxial layer concentration. 16 cm -3 , 9e 15 cm -3 , 8e 15 cm-3 , 7.5e 15 cm -3 , 7e 15 cm -3 These quantities were simulated, and the results were as follows Figure 3 ,With the decrease of concentration, the BV value increased significantly, but did not reach 4125V.

[0044] Since BV is proportional to the channel length, appropriately increasing the channel length can improve the withstand voltage capability. The BV curve corresponding to the channel length of 2.8μm is as follows Figure 4 As shown in the figure, it can be clearly seen that the withstand voltage performance has been greatly improved, with the BV value fluctuating around 3000V rising to around 4000V. However, since the withstand voltage value and on-resistance are a pair of conflicting parameters, the impact of on-resistance must also be considered after meeting the BV design requirements.

[0045] The structural parameters and simulation data of the withstand voltage value close to 4150V are plotted in Table 1. Therefore, after comprehensive consideration, the structural parameters selected in this paper are: drift region concentration 8e 15 cm -3 , thickness 20μm, groove length 2.8μm.

[0046] Table 1 Electrical characteristic values ​​under different structural parameters

[0047]

[0048] 2 Output Characteristics Analysis

[0049] 2.1 Static Characteristics Analysis

[0050] According to the previous analysis, the epitaxial layer thickness of 20μm and 8e 15 cm -3 The simulation model uses composite model, mobility model, lifetime model, collision ionization model, etc.

[0051] Threshold voltage is a key parameter in MOS design. Equation (3) proves that the threshold voltage V TH It is related to the well concentration, gate oxide thickness, and temperature. Therefore, the gate oxide thickness T can be adjusted OX Or channel region concentration to control the threshold.

[0052]

[0053] Where q is the electron charge, ε is the dielectric constant of 4H-SiC, k is the Boltzmann constant, and N A is the maximum doping concentration in the channel region, T is the absolute temperature, n i is the intrinsic carrier concentration of the semiconductor, which is positively correlated with T, C OXis the characteristic capacitance of the oxide layer, C OX =ε ox / T OX , where ε ox is the dielectric constant of SiO2.

[0054] Through Silvaco simulation, the transfer curve shown in Figure 5(a) can be obtained. The gate oxide thickness is changed to After that, the voltage threshold dropped from 7V to 4.81V.

[0055] On-resistance is also a key factor affecting performance. When a MOSFET is in the on state, current flows from the source through the channel into the accumulation region, then disperses to the drift region and finally reaches the drain. Therefore, ignoring the ohmic contact resistance, the total resistance of the device can be expressed as:

[0056] R=R S +R CH +R A +R D +R d (4)

[0057] Where: R S 、R d Represents the source and drain resistance; R CH is the channel resistance; R A is the resistance of the accumulation layer; R D is the drift region resistance.

[0058] The channel resistance R CH and drift region resistance R D The sum of these accounts for 70%. Therefore, the general approach to reducing resistance is to reduce the channel length or increase the drift region concentration. The simulation results are shown in Figures 5(b) and 5(c), and Table 2 is calculated.

[0059] Table 2 Characteristic values ​​of the designed structure

[0060] Breakdown voltage BV(V) Drain current ID(A) <![CDATA[Specific on-resistance Ron (mΩ·cm 2 )]]> Threshold Vt(V) 4310 110 6.1 4.81

[0061] 2.2 Dynamic characteristics analysis

[0062] As a switch, the power MOSFET ideally has only two states: on and off. However, in practice, there will be a certain delay in the conversion process, which will produce dynamic losses, which are proportional to the frequency. Figure 6 This is a diagram of the parasitic capacitance of MOSFET. It is the charging and discharging process of these capacitors that causes switching losses. The gate-drain capacitance is called Miller capacitance, so the size of these capacitances has a great impact on power consumption.

[0063] Carry out charge simulation on the previously designed cell, using Figure 7 The driving circuit shown in the simulation results Figure 8 The gate charge curve of the switch is shown in Figure 3. The gate charge values ​​calculated are shown in Table 3.

[0064] Table 3 Gate charge characteristic values

[0065]

[0066] 3 Temperature dependence

[0067] The maximum temperature resistance of Si-based devices can only reach 630K. In comparison, it is found that the maximum temperature resistance of SiC materials can reach 1800K and has a higher thermal conductivity. In the fields of aviation, nuclear energy, power electronics, automotive electronics, petroleum, geothermal energy, etc., devices that can withstand higher temperatures are needed. This means that SiC devices can not only adapt to more high-temperature environments, but their heat dissipation devices will also be simpler.

[0068] Temperature T affects the physical properties of power devices, such as the intrinsic carrier concentration n i , drift region carrier mobility u, depletion layer width W, etc. The calculation formula is:

[0069]

[0070]

[0071]

[0072] Where T is the absolute temperature, q is the electron charge, ε is the dielectric constant of the material, k is the Boltzmann constant, and N A is the maximum doping concentration in the channel region, n i is the intrinsic carrier concentration of the semiconductor.

[0073] It can be seen that as the temperature T increases, the intrinsic carrier concentration n i Rapidly increases, carrier mobility u decreases, and the depletion layer width W increases. The intrinsic carrier concentration and carrier mobility affect the static characteristics of the device, while the depletion layer width changes the size of the characteristic capacitance, thereby affecting the dynamic characteristics.

[0074] Simulations at five temperatures (300K, 350K, 400K, 450K, and 500K) yield the results shown in Figures 9(a), 9(b), and 9(c). The breakdown voltage and threshold drop slightly but remain essentially unchanged, while the on-resistance increases from 0.6Ω to 2.4Ω and the current level decreases to 35A. This demonstrates that, although temperature affects some electrical properties of MOS, SiC devices still have a certain degree of temperature tolerance.

[0075] 4 Conclusion

[0076] This solution designs various structural parameters of MOSFET to ensure that the withstand voltage of the power device meets the target of 3300V, and further optimizes the output characteristic quantity to meet the low conduction loss and high frequency characteristics. Simulation data shows that the structural parameters are drift region concentration 8e15cm -3 , thickness 25μm, trench length 2.8μm, gate oxide thickness The MOSFET unit cell can reach a breakdown voltage of 4310V and a resistance of 6.1mΩ·cm 2 The specific on-resistance is 4.81V, the drain current is 110A, and the gate charge is 4.25nC at a drain voltage of 6V. The high-temperature characteristics of SiC devices were also simulated, verifying that SiC-based devices can withstand high temperatures and still maintain low on-resistance at high temperatures.

[0077] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A 3300V 4H-SiC MOSFET design method, characterized by: Adopt UMOSFET structure; The structural parameters are optimized as follows: epitaxial layer concentration 8e 15 cm -3 , epitaxial layer thickness 20μm, channel length 2.8μm; The gate oxide thickness is The voltage threshold is 4.81V; Specific on-resistance is 6.1mΩ·cm 2 , drain current 110A, gate-drain charge 1.29nC; According to formula (1) and the verification of Silvaco simulation software, the thickness of the epitaxial layer is initially set to 20 μm, and the concentration of the epitaxial layer is initially set to 8e 15 cm -3 , the gate oxide thickness is initially set to The channel length was set to 2.5 μm; N D =1.10*10 20 *BV -1 .27 (1) W D =2.62*10 -3 *BV 1.12 (2) Where: W D Indicates the thickness of the epitaxial layer; N D represents the doping concentration of the epitaxial layer; BV represents the breakdown voltage; Further optimize the channel length and on-resistance; The breakdown voltage (BV) curve corresponding to different epitaxial thicknesses was established, and combined with the relationship between epitaxial layer thickness and on-resistance, the epitaxial layer thickness was determined to be 20 μm. By optimizing and increasing the channel length to improve the withstand voltage, and considering the relationship between the withstand voltage and on-resistance, the optimized channel length was determined to be 2.8μm; The voltage threshold is controlled by adjusting the gate oxide thickness or the channel concentration. The voltage threshold transfer characteristic curve under different gate oxide thicknesses is obtained through Silvaco simulation. The gate oxide thickness is determined by Optimized to

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