An integrated circuit ESD protection circuit

Abstract

The present invention relates to the technical field of integrated circuit (IC: Integrated Circuit) electrostatic discharge (ESD: Electro-Static Discharge) protection design in microelectronics, and provides a high-reliability, low-turn-on voltage, and low-cost ESD protection circuit. The present invention adopts a method of discharging simultaneously by PMOS (positive channel Metal Oxide Semiconductor: positive charge channel metal oxide semiconductor) and NMOS (negative channel Metal Oxide Semiconductor: negative charge channel metal oxide semiconductor). The gate drive signal of the ESD discharge tube is generated by the conduction voltage division of the PMOS device and the NMOS device. The time delay of the drive signal is controlled by R (resistance) C (capacitance), wherein R is implemented by a PMOS device or an NMOS device. A reverse-conducting diode (D) is connected in parallel to the gate of the discharge device PMOS and NMOS to increase the gate reliability. The above design improves the reliability of the ESD protection circuit, reduces the turn-on voltage and reduces the chip cost.

Description

Technical Field

[0001] The present invention relates to an integrated circuit ESD protection circuit, which is suitable for integrated circuit electrostatic discharge protection design, and is particularly suitable for ESD protection design that requires a lower turn-on voltage while achieving high reliability and taking into account area saving and cost reduction. Background Art

[0002] As the manufacturing process of integrated circuits has entered the deep submicron era and the nano era, MOS transistors in integrated circuits all use a lightly doped structure LDD (Lightly Doped Drain); silicide covers the diffusion area of ​​MOS transistors; polycrystalline compound processes are used to reduce the series resistance of gate polycrystalline; and the thickness of the gate oxide layer of MOS transistors is getting thinner and thinner, and the channel length is getting smaller and smaller. These improvements have improved the integration of chips and increased the computing speed of chips, reducing chip power consumption, but for the electrostatic discharge design of deep submicron integrated circuits, it has brought great disadvantages, because the electrostatic environment faced by integrated circuits has not changed, but the process advancement has made the devices more fragile, and their own reliability has been greatly reduced, which can easily cause the reliability of integrated circuit products to decline.

[0003] With the introduction of nanotechnology, the junction breakdown voltage of devices has dropped significantly to less than 10V, and the gate oxide breakdown voltage of devices has dropped even more, below 5V, or even below 3V. Therefore, for the design of power clamp circuits, the start-up voltage needs to be low enough to protect the internal circuits, otherwise it is very likely that the internal circuits have been broken down while the power clamp ESD circuit has not yet started to discharge.

[0004] Traditional ESD clamp circuits such as Figure 3 As shown, NMOS N31 is connected across VCC and VSS to achieve electrostatic protection from VCC to VSS, and the gate of NMOS is grounded through resistor R31. However, the disadvantage is that the start-up voltage is very high, and it may happen that the internal circuit has been broken down while the power clamp ESD circuit has not yet started to discharge.

[0005] Therefore, some people have proposed Figure 4In the power clamp circuit design shown, P41 forms a MOS capacitor, so P41 and R41 form an RC coupling circuit, which generates a certain delay time. During this delay time, the potential of the RC connection point is not "0", that is, the gate of N41 is coupled to a higher voltage, so the turn-on voltage of the original NMOS device can be reduced, thereby achieving the purpose of ESD power clamping to reduce the turn-on voltage, and better protecting the internal circuit. After this delay time, or when the chip is working normally, due to the effect of the resistor, the potential of the RC connection point will be pulled to the "0" potential, and the NMOS device will be turned off to avoid leakage. Therefore, when the circuit is working normally, the circuit will not affect the normal operation of the chip.

[0006] Figure 5 yes Figure 4 The second implementation method of the technology is to connect an inverter in series in the middle, exchange the connection relationship between R and C, connect the resistor R51 to the power supply, and connect the MOS capacitor formed by NMOS N53 to the ground, so as to achieve the following Figure 4 The circuit has the same function.

[0007] However, the discharge device of this technology is an NMOS device. The characteristics of the NMOS device are strong discharge capability, but relatively high turn-on voltage. Although the turn-on voltage can be reduced to a certain extent through RC coupling, for some designs, this turn-on voltage is still relatively high.

[0008] In addition, through this method, the gate of the discharge device NMOS will be coupled to a potential equivalent to or close to the power supply, and such a high potential will damage the NMOS oxide layer, resulting in the NMOS gate potential being too high and causing the gate oxide layer to break down and fail.

[0009] The resistor of the coupling circuit is formed by a polycrystalline (Poly) resistor. Generally, the resistivity of a polycrystalline resistor is relatively low, but the resistor in the coupling circuit is usually relatively large, generally several Kohms or even hundreds of Kohms, so the resistor needs to occupy a larger area.

[0010] Therefore, this method has the disadvantages of high turn-on voltage, easy breakdown failure of the gate oxide layer, and large area. Summary of the invention

[0011] In order to solve the problems of high turn-on voltage, easy breakdown failure of gate oxide layer and large area of ​​the above-mentioned integrated circuit ESD device, the technical method of the present invention is proposed to provide a technical method to achieve lower turn-on voltage, avoid breakdown failure of oxide layer and save area.

[0012] The present invention mainly includes three parts, namely, an RC delay unit, an ESD control unit and an ESD discharge unit.

[0013] The RC delay unit is composed of an equivalent capacitor N11 formed by NMOS and an equivalent resistor P11 formed by PMOS. The RC structure can generate an RC delay time to distinguish ESD discharge from a normal circuit working state. Its time delay signal is output by 101.

[0014] The resistor P11 of the RC delay unit is composed of a PMOS tube, whose gate and drain are short-circuited to form a channel normally-open PMOS tube, which is equivalent to the effect of a resistor. The PMOS resistor formed in this way can greatly save chip layout area compared to the conventional design using polycrystalline resistors.

[0015] The ESD control unit is composed of an inverter and a first voltage divider circuit and a second voltage divider circuit, wherein the inverter is composed of PMOS P12 and NMOS N12, the input stage 102 of the inverter receives the delay signal generated by the previous RC delay circuit, the first voltage divider circuit composed of PMOS P13 and PMOS P14 generates a gate drive signal 104 of the ESD discharge tube P15, and the second voltage divider circuit composed of NMOS N13 and NMOS N14 generates a gate drive signal 105 of the ESD discharge tube N15.

[0016] The third part is an ESD discharge unit, including an NMOS device N15 and a PMOS P15. Under the control of the ESD control unit, in the ESD discharge state, N15 and P15 can be turned on at the same time to provide a discharge path.

[0017] In the ESD discharge unit, the gate of PMOS P15 is connected in parallel with diode D11, and the gate of NMOS N15 is connected in parallel with diode D12. When the gate voltage of N15 and P15 is too high, D11 and D12 can also reverse conduct to clamp the excessively high gate voltage.

[0018] The ESD control unit includes an inverter and a first voltage divider circuit and a second voltage divider circuit, wherein the inverter is composed of a PMOS tube P22 and an NMOS tube N22, the first voltage divider circuit composed of a PMOS tube P23 and a PMOS tube P24 generates a gate drive signal for an ESD discharge tube PMOS tube P25, the output signal of the inverter is used as the gate drive signal for the PMOS tube P24 in the first voltage divider circuit, the second voltage divider circuit composed of an NMOS tube N23 and an NMOS tube N24 generates a gate drive signal for an ESD discharge tube NMOS tube N25, and the time delay signal generated by the RC delay unit is simultaneously used as the gate drive signal for the NMOS tube N23 in the second voltage divider circuit.

[0019] The NMOS tube N25 and the PMOS tube P25 of the ESD discharge unit provide discharge paths at the same time and start discharge at the same time.

[0020] The gate of the PMOS tube P25 is connected in parallel with a diode D21, and the gate of the NMOS tube N25 is connected in parallel with a diode D22. When the gate voltages of the PMOS tube N25 and the NMOS tube P25 are too high, D21 and D22 can also reverse conduct to clamp the excessively high gate voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0022] Figure 1 The integrated circuit ESD protection circuit of the present invention;

[0023] Figure 2 A second embodiment of the integrated circuit ESD protection circuit of the present invention;

[0024] Figure 3 Traditional integrated circuit ESD protection circuit;

[0025] Figure 4 The second structure of the traditional integrated circuit ESD protection circuit;

[0026] Figure 5 The third structure of traditional integrated circuit ESD protection circuit. DETAILED DESCRIPTION

[0027] The specific implementation of the present invention is shown in the attached Figure 1 shown.

[0028] It mainly consists of three parts: RC delay unit, ESD control unit and ESD discharge unit.

[0029] The RC delay unit is composed of an equivalent capacitor N11 composed of NMOS and an equivalent resistor P11 composed of PMOS, wherein the source and substrate of the equivalent resistor P11 are connected to the power supply VCC, and the gate and drain are connected to the output point 101, so the P11 device is in a channel normally open state, forming a PMOS channel resistor. The resistor formed according to this method is smaller in area than the resistor formed by polysilicon, which can save the layout area, thereby reducing the chip cost. The source, drain and substrate of the equivalent capacitor N11 are all connected to the ground VSS, and the gate is connected to the output point 101, so the equivalent capacitor is formed by the gate oxide layer of the NMOS N11. The RC structure can generate an RC delay time. Generally, the equivalent resistance value ranges from 1Kohm to 100Kohm, and the equivalent capacitance value ranges from 2pF to 20pF, so a delay time in the range of 2ns to 2us can be formed to distinguish between ESD discharge and normal circuit working state. The time delay signal is output by 101. When ESD discharges, within the ESD discharge time, 101 outputs a low potential, and when the ESD discharge is completed, or the circuit is working normally, 101 outputs a high potential.

[0030] The resistor P11 of the RC delay unit can also be implemented by a polysilicon resistor, an active area resistor, or a well resistor, but the PMOS channel resistor has the smallest area and the lowest cost. The capacitor N11 of the RC delay unit can also be implemented by a metal-oxide-metal (MOM or MIM) method, but the NMOS gate parasitic capacitor has the smallest area, the simplest process, and the lowest cost.

[0031] The ESD control unit is composed of an inverter and a first voltage divider circuit and a second voltage divider circuit, wherein the inverter is composed of PMOS P12 and NMOS N12, the source and substrate of P12 are connected to the power supply VCC, the drain is connected to the output electrode 103 of the inverter, the source and substrate of N12 are grounded VSS, the drain is the output electrode 103 of the inverter, the gates of P12 and N12 are connected together to form an input stage 102 of the inverter to receive the delayed signal generated by the previous RC delay circuit. The first voltage divider circuit composed of PMOS P13 and PMOS P14 generates a gate drive signal 104 of the ESD discharge tube P15, the source and substrate of P13 are connected to the power supply VCC, the gate is grounded, so P13 also forms an equivalent channel resistance, the source and substrate of P14 are grounded VSS, the gate is connected to the input signal 102 of the inverter, and the drains of P13 and P14 are connected together to generate the gate drive signal 104 of the discharge tube P15. The second voltage divider circuit composed of NMOS N13 and NMOS N14 generates a gate drive signal 105 for the ESD discharge tube N15. The source and substrate of N13 are connected to the power supply VCC, and the gate is connected to the output signal 103 of the inverter. The source and substrate of N14 are grounded to VSS, and its gate is connected to the power supply VCC to form an equivalent channel resistance. The drains of N13 and N14 are connected together to form the gate drive signal 105 for the discharge tube N15.

[0032] In the ESD discharge state, the gate drive signal 104 of P15 outputs an intermediate potential other than the power supply VCC potential, which can drive the subsequent P15 to start discharging, and the gate signal 105 of N15 outputs an intermediate potential other than the ground VSS potential, which can drive the subsequent N15 to start discharging. When the ESD discharge ends or the circuit works normally, the gate drive signal 104 of P15 outputs the power supply VCC potential, which can control the subsequent P15 to turn off, and the gate signal 105 of N15 outputs the ground VSS potential, which can control the subsequent N15 to turn off.

[0033] The method of generating the gate drive signal of the ESD device through the voltage divider circuit of the present invention avoids the gate of the ESD tube P15 being directly charged to the ground VSS potential in the traditional technical method, and avoids the gate of the ESD tube N15 being directly charged to the power supply VCC potential in the traditional technical method, which can effectively reduce the voltage difference between the gate and the source of the ESD tube, and effectively avoid the gate from breaking down and failing under the action of excessively high voltage.

[0034] The channel resistor formed by P13 and N14 of the first voltage divider circuit and the second voltage divider circuit can also be implemented by polysilicon resistors, active area resistors or well resistors. However, the channel resistor has the smallest area and the lowest cost.

[0035] The third part is the ESD discharge unit, including NMOS devices N15 and PMOS P15. Both N15 and P15 are directly connected between the power supply VCC and the ground VSS, and provide a discharge path from the power supply VCC to the ground VSS. Among them, N15 is an NMOS device, which has a relatively strong discharge capability, but a higher turn-on voltage than PMOS, while P15 is a PMOS device. Although its discharge capability is slightly weaker than NMOS, its turn-on voltage is lower than NMOS. Therefore, the combination of N15 and P15 can achieve a higher ESD discharge capability and a lower turn-on voltage. When ESD discharge occurs, the discharge can be started at a lower voltage, avoiding the problem that the internal circuit has failed in the traditional structure, but the ESD device has not yet started to discharge. At the same time, a higher ESD protection capability is also achieved.

[0036] In the ESD discharge unit, the gate of PMOS P15 is connected in parallel with diode D11, and the gate of NMOS N15 is connected in parallel with diode D12. When the gate voltage of N15 and P15 is too high, D1 and D2 can also reverse conduct to clamp the excessively high gate voltage as a supplementary method for controlling the excessively high gate voltage of N15 and P15, effectively avoiding the gate breakdown failure under the action of excessively high voltage.

[0037] A second embodiment of the present invention is as follows Figure 2 As shown, the equivalent capacitor of the RC delay unit is PMOS P21, whose substrate, source and drain are connected to the power supply VCC, the source and substrate of NMOS N21 are grounded VSS, and its gate and drain are connected to the gate of P21 to form the output electrode 201 of the delay unit.

[0038] Since the potential logic and Figure 1 The implementation method is opposite to that of P24, so the gate of P24 is connected to the output terminal 203 of the inverter, and the gate of N23 is connected to the input terminal 202 of the inverter. The other structures are the same as Figure 1 The implementation is similar.

[0039] In the ESD discharge state, the gate drive signal 204 of P25 outputs an intermediate potential other than the power supply VCC potential, which can drive the subsequent P25 to start discharging, and the gate signal 205 of N25 outputs an intermediate potential other than the ground VSS, which can drive the subsequent N25 to start discharging. When the ESD discharge ends or the circuit works normally, the gate drive signal 204 of P25 outputs the power supply VCC potential, which can drive the subsequent P25 to close, and the gate signal 205 of N25 outputs the ground VSS potential, which can drive the subsequent N25 to close.

[0040] Therefore, in the second implementation, N25 and P25 are matched together to achieve both higher ESD discharge capability and lower start-up voltage. When ESD discharge occurs, discharge can be started at a lower voltage, thus avoiding the problem in the traditional structure where the internal circuit has failed but the ESD device has not yet started discharging.

Claims

1. An integrated circuit ESD protection circuit, characterized in that The circuit includes an RC delay unit, an ESD control unit and an ESD discharge unit, wherein the ESD control unit includes an inverter and a first voltage divider circuit and a second voltage divider circuit, the RC delay unit generates a time delay signal and outputs it to the ESD control unit, the time delay signal is used as an input signal of the inverter and the first voltage divider circuit, the output signal of the inverter is used as an input signal of the second voltage divider circuit, and the output signals of the first voltage divider circuit and the second voltage divider circuit drive the ESD device in the ESD discharge unit to start discharging; The inverter is composed of a PMOS tube P12 and an NMOS tube N12, a first voltage-dividing circuit composed of a PMOS tube P13 and a PMOS tube P14 generates a gate drive signal for an ESD discharge tube PMOS tube P15, a time delay signal generated by an RC delay unit is simultaneously used as a gate drive signal for the PMOS tube P14 in the first voltage-dividing circuit, a second voltage-dividing circuit composed of an NMOS tube N13 and an NMOS tube N14 generates a gate drive signal for an ESD discharge tube NMOS tube N15, and an output signal of the inverter is used as a gate drive signal for the NMOS tube N13 in the second voltage-dividing circuit.

2. The circuit according to claim 1, characterized in that The delay unit is composed of an equivalent capacitor N11 and an equivalent resistor P11, wherein the equivalent capacitor N11 is an NMOS device and the equivalent resistor P11 is a PMOS device.

3. The circuit according to claim 2, characterized in that The equivalent resistor P11 is a PMOS tube, whose gate and drain are short-circuited to form a channel normally-open PMOS tube.

4. The circuit according to claim 1, characterized in that The NMOS tube N15 and the PMOS tube P15 of the ESD discharge unit provide discharge paths at the same time and start discharge at the same time.

5. The circuit as claimed in claim 4, characterized in that The gate of the PMOS tube P15 is connected in parallel with a diode D11, and the gate of the NMOS tube N15 is connected in parallel with a diode D12. When the gate voltages of the PMOS tube N15 and the NMOS tube P15 are too high, D11 and D12 can also reverse conduct to clamp the excessively high gate voltage.

6. An integrated circuit ESD protection circuit, characterized in that The circuit includes an RC delay unit, an ESD control unit and an ESD discharge unit, wherein the ESD control unit includes an inverter and a first voltage divider circuit and a second voltage divider circuit, the RC delay unit generates a time delay signal and outputs it to the ESD control unit, the time delay signal is used as an input signal of the inverter and the first voltage divider circuit, the output signal of the inverter is used as an input signal of the second voltage divider circuit, and the output signals of the first voltage divider circuit and the second voltage divider circuit drive the ESD device in the ESD discharge unit to start discharging; The inverter is composed of a PMOS tube P22 and an NMOS tube N22, a first voltage-dividing circuit composed of a PMOS tube P23 and a PMOS tube P24 generates a gate drive signal for an ESD discharge tube PMOS tube P25, an output signal of the inverter is used as a gate drive signal for the PMOS tube P24 in the first voltage-dividing circuit, a second voltage-dividing circuit composed of an NMOS tube N23 and an NMOS tube N24 generates a gate drive signal for an ESD discharge tube NMOS tube N25, and a time delay signal generated by the RC delay unit is simultaneously used as a gate drive signal for the NMOS tube N23 in the second voltage-dividing circuit.

7. The circuit according to claim 6, characterized in that The delay unit is composed of an equivalent capacitor N11 and an equivalent resistor P11, wherein the equivalent capacitor N11 is an NMOS device and the equivalent resistor P11 is a PMOS device.

8. The circuit according to claim 7, characterized in that The equivalent resistor P11 is a PMOS tube, whose gate and drain are short-circuited to form a channel normally-open PMOS tube.

9. The circuit according to claim 6, characterized in that The NMOS tube N25 and the PMOS tube P25 of the ESD discharge unit provide discharge paths at the same time and start discharge at the same time.

10. The circuit according to claim 9, characterized in that The gate of the PMOS tube P25 is connected in parallel with a diode D21, and the gate of the NMOS tube N25 is connected in parallel with a diode D22. When the gate voltages of the PMOS tube N25 and the NMOS tube P25 are too high, D21 and D22 can also reverse conduct to clamp the excessively high gate voltage.

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