Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device according to an exemplary embodiment of the present disclosure includes: an n-type layer disposed in a first surface of a substrate; an n-type layer disposed on the n-type layer; a first electrode disposed on the n-type layer, and a second electrode disposed in a second surface of the substrate, wherein the energy band gap of the n-type layer is greater than the energy band gap of the n-type layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2018 - 0154984, filed with the Korean Intellectual Property Office on December 5, 2018, the entire content of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to semiconductor devices and methods of manufacturing the same. Background Art

[0004] With the recent trend of development of large - size and high - capacity application devices, there is a need for power semiconductor devices having high breakdown voltage, high current capacity, and high - speed switching characteristics.

[0005] A diode is a two - terminal device capable of conducting current in one direction, and the diodes for power semiconductor devices used in switches require high voltage and large current. These diode devices have different electrical characteristics depending on the structure, and appropriate devices are used according to the application fields. However, generally, high current density, low on - voltage, high breakdown voltage, low leakage current, and fast switching speed are required.

[0006] The above information disclosed in the background art section is only for enhancing the understanding of the background of the present invention, and thus it may include information that does not constitute the prior art known to those of ordinary skill in the art in the country. Summary of the Invention

[0007] The present disclosure relates to semiconductor devices having high current density and low on - voltage.

[0008] A semiconductor device according to an exemplary embodiment of the present disclosure includes: an n - type layer disposed in a first surface of a substrate; an n - type layer disposed on the n - type layer; a first electrode disposed on the n - type layer, and a second electrode disposed in a second surface of the substrate, wherein the energy bandgap of the n - type layer is greater than the energy bandgap of the n - type layer.

[0009] A Schottky junction may be formed in a contact surface between the first electrode and the n - type layer.

[0010] The ion doping concentration of the n - type layer may be less than the ion doping concentration of the n - type layer.

[0011] A heterojunction may be formed in a contact surface between the n - type layer and the n - type layer.

[0012] The n - type layer may include silicon carbide, and the n - type layer may include silicon.

[0013] A semiconductor device according to an exemplary embodiment of the present disclosure may further include a low-concentration silicon n-type layer disposed between the n-type layer and the n-type layer, and the ion doping concentration of the low-concentration silicon n-type layer may be less than the ion doping concentration of the n-type layer.

[0014] A heterojunction may be formed in the contact surface between the n-type layer and the low-concentration silicon n-type layer.

[0015] The n-type layer may include silicon carbide, and the n-type layer and the low-concentration silicon n-type layer may include silicon.

[0016] A semiconductor device according to an exemplary embodiment of the present disclosure may further include a low-concentration silicon carbide n-type layer disposed between the n-type layer and the n-type layer, and the ion doping concentration of the low-concentration silicon carbide n-type layer may be less than the ion doping concentration of the n-type layer.

[0017] A heterojunction may be formed in the contact surface between the n-type layer and the low-concentration silicon carbide n-type layer.

[0018] The n-type layer and the low-concentration silicon carbide n-type layer may include silicon carbide, and the low-concentration silicon n-type layer may include silicon.

[0019] The substrate may be an n+-type silicon carbide substrate.

[0020] A method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure includes: forming an n-type layer in a first surface of a substrate; forming an n-type layer on the n-type layer; forming a first electrode on the n-type layer; and forming a second electrode in a second surface of the substrate, wherein the energy band gap of the n-type layer is greater than the energy band gap of the n-type layer.

[0021] The n-type layer may be formed by epitaxial growth on the n-type layer.

[0022] Forming the n-type layer may include forming a silicon n-type layer by epitaxial growth on the n-type layer; and implanting n-type ions into the silicon n-type layer, wherein the silicon n-type layer may include silicon.

[0023] According to an exemplary embodiment of the present disclosure, the semiconductor device may have a high current density and a low on-state voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a cross-sectional view schematically showing an example of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0025] Figure 2 is a view showing Figure 1 the depletion layer distribution and energy band diagram in the on-state of the semiconductor device.

[0026] Figure 3 is a view showing according to Figure 1View of the depletion layer distribution and energy band diagram in the off state of a semiconductor device.

[0027] Figure 4 Is a view schematically showing an example of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0028] Figure 5 And Figure 6 Is a view schematically showing an example of a method of manufacturing a semiconductor device according to another exemplary embodiment of the present disclosure.

[0029] Figure 7 And Figure 8 Is a cross-sectional view schematically showing an example of a semiconductor device according to another exemplary embodiment of the present disclosure. Detailed Description of the Invention

[0030] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. As those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure. Instead, the exemplary embodiments presented herein are provided to make the disclosure thorough and complete, and to fully convey the spirit of the present disclosure to those skilled in the art.

[0031] In the drawings, for clarity, the thicknesses of layers, films, panels, regions, etc. are exaggerated. It should be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or there can also be another layer therebetween.

[0032] Figure 1 Is a cross-sectional view schematically showing an example of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0033] Referring to Figure 1 , the semiconductor device according to this exemplary embodiment includes a substrate 100, an n-type layer 200, an n-type layer 300, a first electrode 400, and a second electrode 500.

[0034] The semiconductor device according to this exemplary embodiment can be a diode. In this case, the first electrode 400 can be an anode, and the second electrode 500 can be a cathode.

[0035] The substrate 100 can be an n+-type silicon carbide (SiC) substrate.

[0036] The n-type layer 200 is disposed in the first surface of the substrate 100, and the n-type layer 300 is disposed on the n-type layer 200. The energy band gap of the n-type layer 200 is greater than that of the n-type layer 300. Here, the n-type layer 200 may include silicon carbide, and the n-type layer 300 may include silicon (Si). The contact surface between the n-type layer 200 and the n-type layer 300 forms a heterojunction.

[0037] In addition, the ion doping concentration of the n-type layer 300 is greater than that of the n-type layer 200.

[0038] On the other hand, in the present exemplary embodiment, the substrate 100 and the n-type layer 200 include silicon carbide, and the n-type layer 300 includes silicon (Si), but is not limited thereto, and may include materials having a relatively large energy band gap for the n-type layer 200 and a relatively small energy band gap for the n-type layer 300. For example, the substrate 100 and the n-type layer 200 may include gallium oxide (Ga2O3), and the n-type layer 300 may include one of germanium (Ge), silicon, gallium nitride (GaN), silicon carbide, and aluminum nitride (AlN).

[0039] The first electrode 400 is disposed on the n-type layer 300 and may include Schottky metal. The first electrode 400 is in contact with the n-type layer 300, thereby forming a Schottky junction at the boundary surface therebetween.

[0040] The second electrode 500 is disposed in the second surface of the substrate 100 and may include ohmic metal. Here, the second surface of the substrate 100 represents the surface opposite to the first surface of the substrate 100.

[0041] In the semiconductor device according to the present exemplary embodiment, since the n-type layer 300 having an energy band gap smaller than that of the n-type layer 200 is disposed on the n-type layer 200, conduction of the semiconductor device is generated at the Schottky junction surface, which is the contact surface between the n-type layer 300 and the first electrode 400. In addition, a maximum electric field causing breakdown of the semiconductor device is formed at the heterojunction surface, which is the contact surface between the n-type layer 200 and the n-type layer 300. Therefore, the current density of the semiconductor device can be improved and the conduction voltage can be reduced.

[0042] Next, refer to Figure 2 and Figure 3 to describe in detail the operation of the semiconductor device according to the present exemplary embodiment.

[0043] Figure 2 is a view showing the depletion layer distribution and energy band diagram of the conduction state of the semiconductor device according to Figure 1 Figure 3 is a view showing according to Figure 1View of the depletion layer distribution and energy band diagram in the off state of the semiconductor device.

[0044] Reference Figure 2 , in the on state of the semiconductor device, depletion layers D1 and D2 are formed near the contact surface between the n-type layer 200 and the n-type layer 300 and below the contact surface between the n-type layer 300 and the first electrode 400.

[0045] In the on state of the semiconductor device, a positive (+) voltage is applied to the first electrode 400 which serves as the anode of the semiconductor device.

[0046] In this case, conduction occurs at the Schottky junction surface which is the contact surface between the n-type layer 300 and the first electrode 400, and without the interference of the energy barrier, electrons in the n-type layer 200 move to the n-type layer 300. Moreover, holes in the n-type layer 300 do not move to the n-type layer 200 through the energy barrier in the heterojunction surface which is the contact surface between the n-type layer 200 and the n-type layer 300.

[0047] Therefore, since the entire current is formed only by the movement of electrons, a fast switching speed can be achieved. Additionally, since conduction occurs at the Schottky junction surface, conduction can be achieved at a low voltage.

[0048] Reference Figure 3 , in the off state of the semiconductor device, a depletion layer D3 is formed in a region other than a part of the n-type layer 200 and the n-type layer 300.

[0049] In the off state of the semiconductor device, a positive (+) voltage is applied to the second electrode 500 which serves as the cathode of the semiconductor device.

[0050] In this case, a large voltage drop occurs in the n-type layer 200 which has an ion doping concentration lower than that of the n-type layer 300, and electrons in the n-type layer 300 do not move to the n-type layer 200 through the energy barrier in the heterojunction surface which is the contact surface between the n-type layer 200 and the n-type layer 300. Furthermore, without the interference of the energy barrier, holes in the n-type layer 300 move to the n-type layer 300. At this time, the number of holes present in the n-type layer 200 is very small, so the off state where the current hardly flows is maintained. In the off state of the semiconductor device, most of the voltage is applied to the n-type layer 200, thereby enabling a high breakdown voltage.

[0051] Next, compare and describe the characteristics of the semiconductor device according to this exemplary embodiment and a general semiconductor device with reference to Table 1.

[0052] Table 1 shows the operation simulation results of the semiconductor device according to this exemplary embodiment and a general semiconductor device.

[0053] Comparative Example 1 is a typical heterojunction diode (HDJ) device, and Comparative Example 2 is a typical Schottky barrier diode (SBD) device.

[0054] Table 1 compares the characteristics of semiconductor devices by making the breakdown voltages of the semiconductor devices according to the exemplary embodiments of Comparative Example 1 and Comparative Example 2 substantially the same.

[0055] (Table 1)

[0056]

[0057] Referring to Table 1, in the case of the semiconductor device according to the present exemplary embodiment and the diode device according to Comparative Example 1, it can be confirmed that the current density increases by about 217.4% and the turn-on voltage decreases by about 81.5%. In the case of the semiconductor device according to the present exemplary embodiment and the diode device according to Comparative Example 2, it can be confirmed that the current density increases by about 496.6% and the turn-on voltage decreases by about 62.9%.

[0058] In addition, in the case of the semiconductor device according to the present exemplary embodiment, it can be confirmed that the device area is reduced by about 68.5% compared to the diode device according to Comparative Example 1, and is reduced by about 83.2% compared to the diode device according to Comparative Example 2. Therefore, for the semiconductor device according to the present exemplary embodiment, the cost of the semiconductor device can be reduced by increasing the number of semiconductor devices per unit wafer and improving the yield.

[0059] Next, refer to Figure 4 and Figure 1 to describe a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0060] Figure 4 is a view schematically showing an example of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0061] Refer to Figure 4 , a substrate 100 is prepared, and an n-type layer 200 and an n-type layer 300 are sequentially formed in a first surface of the substrate 100. Here, the substrate 100 may be an n+-type silicon carbide substrate. The n-type layer 200 may be formed on the substrate 100 by epitaxial growth, and the n-type layer 300 may be formed on the substrate 100 by epitaxial growth on the n-type layer 200. The n-type layer 200 may include silicon carbide, and the n-type layer 300 may include silicon (Si).

[0062] Refer to Figure 1, a first electrode 400 is formed on the n-type layer 300, and a second electrode 500 is formed in the second surface of the substrate 100. Here, the first electrode 400 is in contact with the n-type layer 300, thereby forming a Schottky junction in their contact surface. The first electrode 400 may include Schottky metal, and the second electrode 500 may include ohmic metal.

[0063] On the other hand, the n-type layer 300 may be formed by epitaxial growth and ion implantation. Refer to Figure 5 and Figure 6 for a description thereof.

[0064] Figure 5 and Figure 6 are views schematically showing examples of manufacturing methods of semiconductor devices according to another exemplary embodiment of the present disclosure.

[0065] Refer to Figure 5 , a substrate 100 is prepared, and an n-type layer 200 and an n-type layer 300a are sequentially formed in the first surface of the substrate 100. Here, the substrate 100 may be an n+-type silicon carbide substrate. The n-type layer 200 may be formed on the substrate 100 by epitaxial growth, and the n-type layer 300 may be formed on the substrate 100 by epitaxial growth on the n-type layer 200. The n-type layer 200 may include silicon carbide, and the silicon n-type layer 300a may include silicon (Si).

[0066] Refer to Figure 6 , the n-type layer 300 is formed by implanting n-type ions such as nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb) into the silicon n-type layer 300a.

[0067] Refer to Figure 7 and Figure 8 for a description of a semiconductor device according to another exemplary embodiment of the present disclosure.

[0068] Figure 7 and Figure 8 are cross-sectional views schematically showing examples of semiconductor devices according to another exemplary embodiment of the present disclosure.

[0069] Refer to Figure 7 , except for adding a low-concentration silicon n-type layer 250, the semiconductor device according to the present exemplary embodiment has the same remaining structure as the semiconductor device according to Figure 1 . Therefore, the description of the same structure is omitted.

[0070] The low-concentration silicon n-type layer 250 is disposed between the n-type layer 200 and the n-type layer 300. The ion doping concentration of the low-concentration silicon n-type layer 250 is less than the ion doping concentrations of the n-type layer 200 and the n-type layer 300. The low-concentration silicon n-type layer 250 includes silicon. In the semiconductor device according to the present exemplary embodiment, different from the semiconductor device according to Figure 1 a heterojunction is formed in the contact surface between the low-concentration silicon n-type layer 250 and the n-type layer 200.

[0071] Reference Figure 8 , except for adding the low-concentration silicon carbide n-type layer 270, the remaining structure of the semiconductor device according to the present exemplary embodiment is the same as that of the semiconductor device according to Figure 1 . Therefore, the description of the same structure is omitted.

[0072] The low-concentration silicon carbide n-type layer 270 is disposed between the n-type layer 200 and the n-type layer 300. The ion doping concentration of the low-concentration silicon carbide n-type layer 270 is less than the ion doping concentrations of the n-type layer 200 and the n-type layer 300. The low-concentration silicon carbide n-type layer 270 includes silicon carbide. In the semiconductor device according to the present exemplary embodiment, different from the semiconductor device according to Figure 1 a heterojunction is formed in the contact surface between the low-concentration silicon carbide n-type layer 270 and the n-type layer 300.

[0073] In the semiconductor devices according to Figure 7 and Figure 8 , compared with the semiconductor device according to Figure 1 , the low-concentration silicon n-type layer 250 and the low-concentration silicon carbide n-type layer 270 are added, so that the breakdown voltage is increased compared with the semiconductor device according to Figure 1 .

[0074] Although many exemplary aspects have been discussed above, those skilled in the art will recognize that further modifications, substitutions, additions, and sub-combinations of the disclosed features are still possible. Therefore, the appended claims and the claims introduced hereinafter are intended to be construed to include all such modifications, substitutions, additions, and sub-combinations within their true spirit and scope.

Claims

1. A semiconductor device, comprising: An n-type layer disposed in the first surface of the substrate; An n-type layer disposed on the n-type layer; A first electrode disposed on the n-type layer, and A second electrode disposed in the second surface of the substrate, wherein the energy band gap of the n-type layer is greater than the energy band gap of the n-type layer, wherein the n-type layer includes silicon carbide and the n-type layer includes silicon, wherein the semiconductor device further includes A low-concentration silicon n-type layer disposed between the n-type layer and the n-type layer, and the ion doping concentration of the low-concentration silicon n-type layer is less than the ion doping concentration of the n-type layer, wherein, when the low-concentration silicon n-type layer includes silicon, a heterojunction is formed in the contact surface between the n-type layer and the low-concentration silicon n-type layer; or wherein, when the low-concentration silicon n-type layer includes silicon carbide, a heterojunction is formed in the contact surface between the low-concentration silicon n-type layer and the n-type layer.

2. The semiconductor device according to claim 1, wherein, A Schottky junction is formed in the contact surface between the first electrode and the n-type layer.

3. The semiconductor device according to claim 2, wherein, The ion doping concentration of the n-type layer is less than the ion doping concentration of the n-type layer.

4. The semiconductor device according to claim 1, wherein, The substrate is an n+-type silicon carbide substrate.

5. A method of manufacturing a semiconductor device, comprising: Form an n-type layer in the first surface of the substrate; Form an n-type layer on the n-type layer; Form a first electrode on the n-type layer; And Form a second electrode in the second surface of the substrate, wherein the energy band gap of the n-type layer is greater than the energy band gap of the n-type layer, wherein the n-type layer includes silicon carbide and the n-type layer includes silicon, wherein the method further includes Dispose a low-concentration silicon n-type layer between the n-type layer and the n-type layer, wherein the ion doping concentration of the low-concentration silicon n-type layer is less than the ion doping concentration of the n-type layer, wherein, when the low-concentration silicon n-type layer includes silicon, a heterojunction is formed in the contact surface between the n-type layer and the low-concentration silicon n-type layer; wherein, when the low-concentration silicon n-type layer includes silicon carbide, a heterojunction is formed in the contact surface between the low-concentration silicon n-type layer and the n-type layer.

6. The method according to claim 5, wherein, Form a Schottky junction in the contact surface between the first electrode and the n-type layer.

7. The method according to claim 6, wherein, The ion doping concentration of the n-type layer is less than the ion doping concentration of the n-type layer.

8. The method according to claim 5, wherein, The n-type layer is formed by epitaxial growth on the n-type layer.

9. The method according to claim 5, wherein, Forming the n-type layer includes: Forming a silicon n-type layer by epitaxial growth on the n-type layer; and Injecting n-type ions into the silicon n-type layer, and The silicon n-type layer includes silicon.

10. According to the method of claim 5, wherein, The substrate is an n+-type silicon carbide substrate.

Images