A wideband amplifier and analog filter

Abstract

The embodiment of the present application discloses a kind of wideband amplifier and analog filter, wherein, wideband amplifier, it is arranged in analog filter, analog filter includes multiple bandwidth modes, wideband amplifier includes: gain circuit;Gain circuit includes: first amplification subcircuit and second amplification subcircuit;First amplification subcircuit is used to amplify the input signal and process;Second amplification subcircuit is used to reconfigure according to the bandwidth mode of analog filter, also for amplifying the input signal after amplification processing.The technical scheme provided by the embodiment of the present application can configure amplifier when filter is in different bandwidth mode, while guaranteeing the performance of filter, also realizes power consumption optimization.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, specifically to a broadband amplifier and an analog filter. Background Technology

[0002] With the upgrading of wireless communication systems, the information rate of wireless communication systems is getting higher and higher, which makes the signal bandwidth required by wireless communication systems also larger and larger. At the same time, different communication protocols require different signal bandwidths, which means that the bandwidth of filters in wireless communication systems needs to have multiple different bandwidth modes to adapt to different communication protocols.

[0003] As an important type of filter, analog filters are widely used in wireless communication systems. The most crucial component is the amplifier. To realize the filter's function, the amplifier's bandwidth must be large enough to mitigate the impact of insufficient operational amplifier bandwidth on the filter's functionality and performance. The inventors discovered that the bandwidth of existing amplifiers remains constant. When the amplifier is used in a filter with multiple different bandwidth modes, using the filter in a mode with a smaller bandwidth leads to wasted power consumption. Summary of the Invention

[0004] To address the aforementioned technical problems, embodiments of the present invention provide a broadband amplifier and an analog filter, which can configure the amplifier when the filter is in different bandwidth modes, thereby achieving power consumption optimization.

[0005] To achieve the objective of this invention, an embodiment of this invention provides a broadband amplifier disposed in an analog filter, the analog filter including multiple bandwidth modes, and the broadband amplifier including a gain circuit; the gain circuit including a first amplification sub-circuit and a second amplification sub-circuit.

[0006] The first amplifier sub-circuit is used to amplify the input signal and generate a first signal;

[0007] The second amplification sub-circuit is used to reconfigure according to the bandwidth mode of the analog filter, and also to amplify the first signal to generate the second signal.

[0008] Optionally, the first amplification sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first resistor, a second resistor, a first capacitor, and a second capacitor;

[0009] The control electrode of the first transistor is connected to the first input terminal, its first electrode is connected to the first node, and its second electrode is connected to the second node;

[0010] The control electrode of the second transistor is connected to the second input terminal, its first electrode is connected to the first node, and its second electrode is connected to the third node;

[0011] The control electrode of the third transistor is connected to the fourth node, its first electrode is connected to the second node, and its second electrode is connected to the high-level voltage terminal.

[0012] The control electrode of the fourth transistor is connected to the fourth node, its first electrode is connected to the third node, and its second electrode is connected to the high-level voltage terminal.

[0013] The control electrode of the fifth transistor is connected to the bias voltage terminal, its first electrode is connected to the first node, and its second electrode is connected to the low-level voltage terminal.

[0014] The first terminal of the first capacitor is connected to the second node, and its second terminal is connected to the fourth node.

[0015] The first end of the second capacitor is connected to the fourth node, and its second end is connected to the third node;

[0016] The first end of the first resistor is connected to the second node, and its second end is connected to the fourth node;

[0017] The first end of the second resistor is connected to the fourth node, and its second end is connected to the third node;

[0018] Among them, the first transistor, the second transistor, and the fifth transistor are N-type transistors, and the third transistor and the fourth transistor are P-type transistors.

[0019] Optionally, the second amplification sub-circuit includes: a first reconfigurable amplification sub-circuit and a second reconfigurable amplification sub-circuit;

[0020] The first reconfigurable amplifier sub-circuit includes: M+1 P-type transistors and M switch pairs, each switch pair including: a first switch and a second switch;

[0021] In this configuration, the control electrode of the first transistor is connected to the third node, its first electrode is connected to the high-level voltage terminal, and its second electrode is connected to the second output terminal; the first electrode of the i-th transistor is connected to the high-level voltage terminal, and its second electrode is connected to the second output terminal; in the (i-1)-th switch pair, the first terminal of the first switch is connected to the third node, and its second terminal is connected to the control electrode of the i-th transistor; in the (i-1)-th switch pair, the first terminal of the second switch is connected to the control electrode of the i-th transistor, and its second terminal is connected to the high-level voltage terminal.

[0022] The second reconfigurable amplifier sub-circuit includes: M+1 P-type transistors and M switch pairs, each switch pair including: a first switch and a second switch;

[0023] In this configuration, the control electrode of the first transistor is connected to the second node, its first electrode is connected to the high-level voltage terminal, and its second electrode is connected to the first output terminal; the first electrode of the i-th transistor is connected to the high-level voltage terminal, and its second electrode is connected to the first output terminal; the first terminal of the first switch in the (i-1)-th switch pair is connected to the second node, and its second terminal is connected to the control electrode of the i-th transistor; the first terminal of the second switch in the (i-1)-th switch pair is connected to the control electrode of the i-th transistor, and its second electrode is connected to the high-level voltage terminal; 2≤i≤M+1.

[0024] Optionally, the gain circuit further includes: a first compensation sub-circuit and a second compensation sub-circuit; the first compensation sub-circuit includes: a third resistor and a third capacitor, and the second compensation sub-circuit includes: a fourth resistor and a fourth capacitor;

[0025] The first end of the third resistor is connected to the second node, and its second end is connected to the first end of the third capacitor.

[0026] The second terminal of the third capacitor is connected to the second output terminal;

[0027] The first end of the fourth resistor is connected to the third node, and its second end is connected to the first end of the fourth capacitor.

[0028] The second terminal of the fourth capacitor is connected to the first output terminal.

[0029] Optionally, the broadband amplifier further includes: a feedforward circuit;

[0030] The feedforward circuit is used to reconfigure according to the bandwidth mode of the analog filter, and also to receive the input signal and perform feedforward compensation on the input signal.

[0031] Optionally, the feedforward circuit includes: a first reconfigurable feedforward sub-circuit and a second reconfigurable feedforward sub-circuit;

[0032] The first reconfigurable feedforward subcircuit includes: N+1 N-type transistors and N switch pairs, each switch pair including: a first switch and a second switch;

[0033] In this configuration, the control electrode of the first transistor is connected to the first input terminal, its first electrode is connected to the second output terminal, and its second electrode is connected to the fifth node; the first electrode of the i-th transistor is connected to the second output terminal, and its second electrode is connected to the fifth node; in the (i-1)-th switch pair, the first terminal of the first switch is connected to the first input terminal, and its second terminal is connected to the control electrode of the i-th transistor; in the (i-1)-th switch pair, the first terminal of the second switch is connected to the control electrode of the i-th transistor, and its second electrode is connected to the low-level voltage terminal.

[0034] The second reconfigurable feedforward subcircuit includes: N+1 N-type transistors and N switch pairs, each switch pair including: a first switch and a second switch;

[0035] In this configuration, the control electrode of the first transistor is connected to the second input terminal, its first electrode is connected to the first output terminal, and its second electrode is connected to the fifth node; the first electrode of the i-th transistor is connected to the first output terminal, and its second electrode is connected to the fifth node; in the (i-1)-th switch pair, the first terminal of the first switch is connected to the second input terminal, and its second terminal is connected to the control electrode of the i-th transistor; in the (i-1)-th switch pair, the first terminal of the second switch is connected to the control electrode of the i-th transistor, and its second electrode is connected to the low-level voltage terminal, where 2≤i≤N+1.

[0036] Optionally, the broadband amplifier further includes: a common-mode feedback circuit;

[0037] The common-mode feedback circuit is used to stabilize the second signal.

[0038] Optionally, the common-mode feedback circuit includes: a reconfigurable common-mode feedback sub-circuit, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a fifth capacitor, a sixth capacitor, a fifth resistor, and a sixth resistor; wherein,

[0039] The reconfigurable common-mode feedback sub-circuit is connected to the fifth node, the sixth node, and the low-level voltage terminal, respectively.

[0040] The control electrode of the sixth transistor is connected to the control electrode of the seventh transistor, and its first electrode is connected to the high-level voltage terminal, and its second electrode is connected to the first electrode of the ninth transistor.

[0041] The control electrode of the seventh transistor is connected to the second electrode of the sixth transistor, and its first electrode is connected to the high-level voltage terminal, while its second electrode is connected to the control electrode of the eleventh transistor.

[0042] The control electrode of the eighth transistor is connected to the seventh node, and its first electrode is connected to the second electrode of the seventh transistor, and its second electrode is connected to the first electrode of the tenth transistor.

[0043] The control terminal of the ninth transistor is connected to the reference voltage terminal, and its second terminal is connected to the first terminal of the tenth transistor.

[0044] The control electrode of the tenth transistor is connected to the bias voltage terminal, and its second electrode is connected to the low-level voltage terminal.

[0045] The first terminal of the eleventh transistor is connected to the high-level voltage terminal, and its second terminal is connected to the first terminal of the twelfth transistor.

[0046] The control electrode of the twelfth transistor is connected to the sixth node, its first electrode is connected to the sixth node, and its second electrode is connected to the low-level voltage terminal.

[0047] The first terminal of the fifth capacitor is connected to the first output terminal, and its second terminal is connected to the seventh node.

[0048] The first end of the fifth resistor is connected to the first output terminal, and its second end is connected to the seventh node.

[0049] The first terminal of the sixth capacitor is connected to the second output terminal, and its second terminal is connected to the seventh node.

[0050] The first end of the sixth resistor is connected to the second output end, and its second end is connected to the seventh node;

[0051] The sixth, seventh, and eleventh transistors are P-type transistors, while the eighth, ninth, tenth, and twelfth transistors are N-type transistors.

[0052] Optionally, the reconfigurable common-mode feedback sub-circuit includes: K+1 N-type transistors and K switch pairs, each switch pair including: a first switch and a second switch;

[0053] In this configuration, the control electrode of the first transistor is connected to the sixth node, its first electrode is connected to the fifth node, and its second electrode is connected to the low-level voltage terminal; the first electrode of the i-th transistor is connected to the fifth node, and its second electrode is connected to the low-level voltage terminal; in the (i-1)-th switch pair, the first terminal of the first switch is connected to the sixth node, and its second terminal is connected to the control electrode of the i-th transistor; in the (i-1)-th switch pair, the first terminal of the second switch is connected to the control electrode of the i-th transistor, and its second electrode is connected to the low-level voltage terminal; 2≤i≤K+1.

[0054] Optionally, the number of bandwidth modes of the analog filter is Q, and the minimum number of control bits is Q. min Satisfy the following formula:

[0055]

[0056] Where M, N, K ≥ Q min -1.

[0057] This invention also provides an analog filter for use in a wireless communication system, comprising the aforementioned broadband amplifier.

[0058] Specifically, the wireless communication system includes 2G, 3G, 4G or 5G communication systems, and this embodiment of the invention does not limit it in any way.

[0059] Optionally, the broadband amplifier includes: a first broadband amplifier and a second broadband amplifier connected in series.

[0060] This invention provides a broadband amplifier and an analog filter. The broadband amplifier is disposed within the analog filter, which includes multiple bandwidth modes. The broadband amplifier includes a gain circuit, which further includes a first amplification sub-circuit and a second amplification sub-circuit. The first amplification sub-circuit amplifies the input signal. The second amplification sub-circuit is used to reconfigure the amplifier according to the bandwidth mode of the analog filter and also amplifies the amplified input signal. The technical solution provided by this invention enables the amplifier to be configured when the filter is in different bandwidth modes, achieving power consumption optimization while ensuring filter performance.

[0061] Of course, implementing any product or method of the present invention does not necessarily require achieving all the advantages described above simultaneously. Other features and advantages of the invention will be set forth in the following description and will be apparent in part from the description and embodiments, or may be learned by practicing the invention. The objects and other advantages of the embodiments of the invention can be realized and obtained through the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0062] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of the present invention and do not constitute a limitation on the technical solutions of the present invention.

[0063] Figure 1 This is a schematic diagram of the structure of a broadband amplifier provided in an embodiment of the present invention;

[0064] Figure 2 Equivalent circuit of the gain circuit provided in the embodiments of the present invention Figure 1 ;

[0065] Figure 3A The equivalent circuit diagram of the first reconfigurable amplifier sub-circuit provided in the embodiment of the present invention;

[0066] Figure 3B The equivalent circuit diagram of the second reconfigurable amplifier sub-circuit provided in the embodiment of the present invention;

[0067] Figure 4 Equivalent circuit of the gain circuit provided in the embodiments of the present invention Figure 2 ;

[0068] Figure 5 Equivalent circuit diagram of the feedforward circuit provided in the embodiments of the present invention;

[0069] Figure 6AEquivalent circuit diagram of the first reconfigurable feedforward sub-circuit provided in the embodiments of the present invention;

[0070] Figure 6B The equivalent circuit diagram of the second reconfigurable feedforward sub-circuit provided in the embodiments of the present invention;

[0071] Figure 7 The equivalent circuit diagram of the broadband amplifier provided in the embodiment of the present invention;

[0072] Figure 8 The equivalent circuit diagram of the reconfigurable common-mode feedback sub-circuit provided in the embodiments of the present invention;

[0073] Figure 9 The equivalent circuit diagram of the analog filter provided in the embodiment of the present invention. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

[0075] The steps illustrated in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in a different order than that presented here.

[0076] Unless otherwise defined, the technical or scientific terms used in the embodiments of this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0077] Those skilled in the art will understand that the transistors used in all embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Preferably, the thin-film transistors used in the embodiments of this invention can be oxide semiconductor transistors. Since the source and drain of the transistors used here are symmetrical, their source and drain can be interchanged. In the embodiments of this invention, to distinguish the two electrodes of the transistor other than the control electrode, one electrode is called the first electrode and the other electrode is called the second electrode. The first electrode can be the source or the drain, and the second electrode can be the drain or the source. In addition, the control electrode of the transistor is called the control electrode.

[0078] Example 1

[0079] This invention provides a broadband amplifier. Figure 1 This is a schematic diagram of the structure of a broadband amplifier provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the broadband amplifier provided in this embodiment of the invention includes a gain circuit.

[0080] To achieve the objective of this invention, an embodiment of this invention provides a broadband amplifier disposed within an analog filter. The analog filter includes multiple bandwidth modes, and the broadband amplifier includes a gain circuit. The gain circuit includes a first amplification sub-circuit and a second amplification sub-circuit.

[0081] The first amplification sub-circuit is used to amplify the input signal to generate a first signal; the second amplification sub-circuit is used to reconfigure the bandwidth mode of the analog filter and also to amplify the first signal to generate a second signal.

[0082] Specifically, the bandwidths corresponding to the bandwidth modes of the analog filter are not the same. The embodiments of the present invention do not specifically limit the number of bandwidth modes included in the analog filter, but determine it according to actual needs.

[0083] Specifically, the broadband amplifier provided in this embodiment of the invention is applicable to wireless communication systems such as 2G, 3G, 4G, and 5G, and this embodiment of the invention does not impose any limitations on it.

[0084] The broadband amplifier provided in this embodiment of the invention is configured in an analog filter. The analog filter includes multiple bandwidth modes, and the broadband amplifier includes a gain circuit. The gain circuit includes a first amplification sub-circuit and a second amplification sub-circuit. The first amplification sub-circuit is used to amplify the input signal. The second amplification sub-circuit is used to reconfigure the amplifier according to the bandwidth mode of the analog filter and also to amplify the amplified input signal. The technical solution provided in this embodiment of the invention can configure the amplifier when the filter is in different bandwidth modes, achieving power consumption optimization while ensuring filter performance.

[0085] Optionally, Figure 2 Equivalent circuit of the gain circuit provided in the embodiments of the present invention Figure 1 ,like Figure 2 As shown, the first amplification sub-circuit provided in this embodiment of the invention includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2.

[0086] Specifically, the control electrode of the first transistor M1 is connected to the first input terminal VI1, its first electrode is connected to the first node N1, and its second electrode is connected to the second node N2; the control electrode of the second transistor M2 is connected to the second input terminal VI2, its first electrode is connected to the first node N1, and its second electrode is connected to the third node N3; the control electrode of the third transistor M3 is connected to the fourth node N4, its first electrode is connected to the second node N2, and its second electrode is connected to the high-level voltage terminal VDD; the control electrode of the fourth transistor M4 is connected to the fourth node N4, its first electrode is connected to the third node N3, and its second electrode is connected to the high-level voltage terminal VDD. The voltage level terminal VDD is connected; the control terminal of the fifth transistor M5 is connected to the bias voltage terminal VBIAS, its first terminal is connected to the first node N1, and its second terminal is connected to the low-level voltage terminal VSS; the first terminal of the first capacitor C1 is connected to the second node N2, and its second terminal is connected to the fourth node N4; the first terminal of the second capacitor C2 is connected to the fourth node N4, and its second terminal is connected to the third node N3; the first terminal of the first resistor R1 is connected to the second node N2, and its second terminal is connected to the fourth node N4; the first terminal of the second resistor R2 is connected to the fourth node N4, and its second terminal is connected to the third node N3.

[0087] Specifically, the first amplification sub-circuit is a common-source differential amplifier. The input signals from the first input terminal VI1 and the second input terminal VI2 are amplified by the first amplification sub-circuit and output to the second node N2 and the third node N3, respectively.

[0088] Optionally, the first transistor M1 and the second transistor M2 are a differential input pair, and both are N-type transistors.

[0089] Optionally, the third transistor M3 and the fourth transistor M4 are load transistors, and both are P-type transistors.

[0090] Optionally, the fifth transistor M5 is a tail current transistor and is an N-type transistor.

[0091] Optionally, such as Figure 2 As shown, the second amplification sub-circuit provided in this embodiment of the invention includes: a first reconfigurable amplification sub-circuit MPX1 and a second reconfigurable amplification sub-circuit MPX2.

[0092] Specifically, the first reconfigurable amplifier sub-circuit MPX1 and the second reconfigurable amplifier sub-circuit MPX2 are single-stage common-source amplifiers.

[0093] The signals of the second node N2 and the third node N3 are used as input signals of the second amplification sub-circuit and amplified. The amplified output signal is used as the output of the entire broadband amplifier. Specifically, the signal of the second node N2 is used as the input signal of the second reconfigurable amplification sub-circuit MPX2, and the signal of the third node N3 is used as the input signal of the first reconfigurable amplification sub-circuit MPX1.

[0094] in, Figure 3A The equivalent circuit diagram of the first reconfigurable amplifier sub-circuit provided in the embodiments of the present invention is as follows: Figure 3A As shown, the first reconfigurable amplifier sub-circuit MPX1 includes: M+1 P-type transistors and M switch pairs, each switch pair including: a first switch and a second switch; wherein, the M+1 P-type transistors are: MPX0, MPX1, MPX2, ..., MPX... M The M switch pairs are: SP1 and SPB1, SP2 and SPB2, ..., SP M and SPB M SP j SPB is the first switch of the j-th switch pair. j Let M be the second switch of the j-th switch pair, where 1 ≤ j ≤ M.

[0095] Among them, the control terminal of MPX0 is connected to the third node N3, its first terminal is connected to the high-level voltage terminal VDD, and its second terminal is connected to the second output terminal VO2; MPX i-1 The first terminal is connected to the high-level voltage terminal VDD, and its second terminal is connected to the second output terminal VO2; the first switch SP in the (i-1)th switch pair i-1 The first end is connected to the third node N3, and its second end is connected to MPX. i-1 The control electrode connection is the second switch SPB in the (i-1)th switch pair. i-1 The first end with MPX i-1 The control electrode is connected, and its second electrode is connected to the high-level voltage terminal VDD, 2≤i≤M+1.

[0096] like Figure 3A As shown, MPX0, MPX1, MPX2, ..., MPX M The first terminal of each is connected to the high-level voltage terminal VDD, and the second terminal is connected to the second output terminal. Among them, MPX0 is always on, and MPX1, MPX2, ..., MPX... M The conduction is selected by M pairs of switches.

[0097] Optionally, MPX0, MPX1, MPX2, ..., MPX M The lengths of the trenches are the same, and their widths vary proportionally.

[0098] Preferably, in order to ensure that the amplifier can be adapted to the number of bandwidth modes of the analog filter, the width ratio of the transistors in the embodiments of the present invention satisfies: MPX1:MPX2:...:MPX M =1:2:...:2 M-1 .

[0099] Specifically, SP j and SPB j These are inverse switch pairs, namely SP1 and SPB1, SP2 and SPB2, ..., SP M and SPB M It is a pair of switches controlled by M sets of reciprocating signals, which can control MPX1, MPX2, ..., MPX M Is it in an on or off state when SP j On and SPB j When open, the switch pair is connected in parallel with the first transistor MPX0, and when SP... j Disconnect and SPB j When the switch is on, it turns off the corresponding transistor, and no current flows through it.

[0100] Specifically, SP1 and SPB1 control the state of MPX1. When the first switch SP1 is on, the second switch SPB1 is off, and the signal from the third node N2 is connected to the control electrode of MPX1, putting it in the on state and in parallel with MPX0. When the first switch SP1 is off and the second switch SPB1 is on, the control electrode of MPX1 is pulled to VDD, thus putting it in the off state. The principle is the same as the first switch controlling the state of MPX1 through SP1 and SPB1. SP2 and SPB2, ..., SP... M and SPB M Control MPX2, ..., MPX M The switching on and off of the amplifier enables a reconfigurable design for the second amplifier.

[0101] Figure 3B The equivalent circuit diagram of the second reconfigurable amplifier sub-circuit provided in the embodiments of the present invention is as follows: Figure 3B As shown, the second reconfigurable amplifier sub-circuit MPX2 includes: M+1 P-type transistors and M switch pairs, each switch pair including: a first switch and a second switch; wherein, the M+1 P-type transistors are: MPX0, MPX1, MPX2, ..., MPX M The M switch pairs are: SP1 and SPB1, SP2 and SPB2, ..., SP M and SPBM SP j SPB is the first switch of the j-th switch pair. j Let M be the second switch of the j-th switch pair, where 1 ≤ j ≤ M.

[0102] Among them, the control electrode of MPX0 is connected to the second node N2, its first electrode is connected to the high-level voltage terminal VDD, and its second electrode is connected to the first output terminal VO1; the i-th transistor MPX i-1 The first terminal is connected to the high-level voltage terminal VDD, and its second terminal is connected to the first output terminal VO1; the first switch SP in the (i-1)th switch pair i-1 The first end is connected to the second node N2, and its second end is connected to MPX. i-1 The control electrode connection is the second switch SPB in the (i-1)th switch pair. i-1 The first terminal and the i-th transistor MPX i-1 The control electrode is connected, and its second electrode is connected to the high-level voltage terminal VDD, 2≤i≤M+1.

[0103] like Figure 3B As shown, each transistor is MPX0, MPX1, MPX2, ..., MPX M The first terminal of each transistor is connected to the high-level voltage terminal VDD, and the second terminal is connected to the first output terminal. The first transistor MPX0 is always on, and the transistors MPX1, MPX2, ..., MPX... M The conduction is selected by M pairs of switches.

[0104] Optionally, MPX0, MPX1, MPX2, ..., MPX M The lengths of the trenches are the same, and their widths vary proportionally.

[0105] Preferably, in order to ensure that the amplifier can be adapted to the number of bandwidth modes of the analog filter, the width ratio of the transistors in the embodiments of the present invention satisfies: MPX1:MPX2:...:MPX M =1:2:...:2 M-1 .

[0106] Specifically, SP j and SPB j These are inverse switch pairs, namely SP1 and SPB1, SP2 and SPB2, ..., SP M and SPB M It is a pair of switches controlled by M sets of reciprocating signals, which can control MPX1, MPX2, ..., MPX M Is it in an on or off state when SP j On and SPB j When open, the switch pair is connected in parallel with the corresponding transistor and MPX0. When SPj Disconnect and SPB j When the switch is on, it turns off the corresponding transistor, and no current flows through it.

[0107] Specifically, SP1 and SPB1 control the state of the second transistor MPX1. When the first switch SP1 is on, the second switch SPB1 is off, and the signal from the third node N2 is connected to the control electrode of MPX1, putting it in the on state and in parallel with MPX0. When the first switch SP1 is off and the second switch SPB1 is on, the control electrode of MPX1 is pulled to VDD, thus putting it in the off state. The principle is the same as the first switch controlling the state of MPX1 through SP1 and SPB1. SP2 and SPB2, ..., SP... M and SPB M Control MPX2, ..., MPX M The switching on and off of the amplifier enables a reconfigurable design for the second amplifier.

[0108] According to the bandwidth mode of the analog filter, the number of transistors connected in the second amplification sub-circuit is changed, thereby realizing the reconfigurability of the second sub-circuit.

[0109] Optionally, Figure 4 Equivalent circuit of the gain circuit provided in the embodiments of the present invention Figure 2 ,like Figure 4 As shown, the gain circuit provided in this embodiment of the invention further includes: a first compensation sub-circuit and a second compensation sub-circuit; the first compensation sub-circuit includes: a third resistor R3 and a third capacitor C3, and the second compensation sub-circuit includes: a fourth resistor R4 and a fourth capacitor C4.

[0110] Among them, the first end of the third resistor R3 is connected to the second node N2, and its second end is connected to the first end of the third capacitor C3; the second end of the third capacitor C3 is connected to the second output terminal VO2; the first end of the fourth resistor R4 is connected to the third node N3, and its second end is connected to the first end of the fourth capacitor C4; the second end of the fourth capacitor C4 is connected to the first output terminal VO1.

[0111] Optionally, the resistance values ​​of the third resistor R3 and the fourth resistor R4 are fixed.

[0112] Optionally, the third capacitor C3 and the fourth capacitor C4 can be variable capacitors or Miller capacitors.

[0113] In this embodiment of the invention, the first and second compensating sub-circuits in the gain circuit can compensate for the loop zeros and poles of the broadband amplifier, ensuring the stability of the broadband amplifier under different bandwidth modes.

[0114] Optionally, Figure 5The equivalent circuit diagram of the feedforward circuit provided in the embodiments of the present invention is as follows: Figure 5 As shown, the broadband amplifier provided in this embodiment of the invention further includes a feedforward circuit, wherein the feedforward circuit is used to reconfigure according to the bandwidth mode of the analog filter, and is also used to receive the input signal and perform feedforward compensation on the input signal.

[0115] Specifically, the feedforward circuit and the second amplifier sub-circuit share a single current, which can increase the gain-bandwidth product of the entire broadband amplifier without increasing additional power consumption. At the same time, the feedforward circuit also increases the bandwidth and gain of the broadband amplifier.

[0116] The feedforward circuit includes: a first reconfigurable feedforward sub-circuit and a second reconfigurable feedforward sub-circuit.

[0117] in, Figure 6A An equivalent circuit diagram of the first reconfigurable feedforward sub-circuit provided in an embodiment of the present invention is shown below. Figure 6A As shown, the first reconfigurable feedforward subcircuit includes: N+1 N-type transistors and N switch pairs, each switch pair including: a first switch and a second switch; wherein, the N+1 N-type transistors are: MNX0, MNX1, MNX2, ..., MNX N The N switch pairs are: SN1 and SNB1, SN2 and SNB2, ..., SN N and SNB N SN j SNB is the first switch of the j-th switch pair. j Let be the second switch of the j-th switch pair, where 1 ≤ j ≤ N.

[0118] Among them, the control terminal of MNX0 is connected to the first input terminal VI1, its first terminal is connected to the second output terminal VO2, and its second terminal is connected to the fifth node N5; MNX i-1 The first terminal is connected to the second output terminal VO2, and its second terminal is connected to the fifth node N5; the (i-1)th switch pair SN i-1 and SNB i-1 The first switch SN in i-1 The first end is connected to the first input terminal VI1, and the second end is connected to MNX. i-1 The control electrode connection is the second switch SNB in ​​the (i-1)th switch pair. i-1 The first end with MNX i-1 The control electrode is connected, and its second electrode is connected to the low-level voltage terminal VSS; 2≤i≤N+1.

[0119] like Figure 6A As shown, MNX0, MNX1, MNX2, ..., MNX NThe first terminal of each terminal is connected to the second output terminal VO2, and the second terminal is connected to the fifth node N5. MNX0 is always on, and MNX1, MNX2, ..., MNX... N It is selected to conduct through N pairs of switches.

[0120] Optionally, MNX0, MNX1, MNX2, ..., MNX N The lengths of the trenches are the same, and their widths vary proportionally.

[0121] Preferably, in order to ensure that the amplifier can be adapted to the number of bandwidth modes of the analog filter, the width ratio of the transistors in the embodiments of the present invention satisfies: MNX1:MNX2:...:MNX N =1:2:...:2 N-1 .

[0122] Specifically, SN j and SNB j These are inverse switch pairs, namely SN1 and SNB1, SN2 and SNB2, ..., SN N and SNB N It is a pair of switches controlled by M sets of reciprocating signals, which can control MNX1, MNX2, ..., MNX N Is it in an on or off state when SN j On and SNB j When disconnected, the switch pair is connected in parallel with the corresponding transistor MNX0, when SN j Disconnect and SNB j When the switch is on, it turns off the corresponding transistor, and no current flows through it.

[0123] Specifically, SN1 and SNB1 control the state of MNX1. When the first switch SN1 is on, the second switch SNB1 is off, and the signal at the first input terminal VI1 is connected to the control electrode of MNX1, making it in the on state and connected in parallel with MNX0. When the first switch SN1 is off and the second switch SNB1 is on, the control electrode of MNX1 is pulled to VSS, thus being in the off state. The principle is the same as the first switch controlling the state of MNX1 through SN1 and SNB1. SN2 and SNB2, ..., SN... N and SNB N Control MNX2, ..., MNX N The switching on and off of the feedforward circuit enables a reconfigurable design.

[0124] in, Figure 6B An equivalent circuit diagram of the second reconfigurable feedforward sub-circuit provided in an embodiment of the present invention is shown below. Figure 6BAs shown, the second reconfigurable feedforward subcircuit includes: N+1 N-type transistors and N switch pairs, each switch pair including: a first switch and a second switch; wherein, the N+1 N-type transistors are: MNX0, MNX1, MNX2, ..., MNX N The N switch pairs are: SN1 and SNB1, SN2 and SNB2, ..., SN N and SNB N SN j SNB is the first switch of the j-th switch pair. j Let be the second switch of the j-th switch pair, where 1 ≤ j ≤ N.

[0125] Among them, the control terminal of MNX0 is connected to the second input terminal VI2, its first terminal is connected to the first output terminal VO1, and its second terminal is connected to the fifth node N5; MNX i-1 The first pole is connected to the first output terminal VO1, and its second pole is connected to the fifth node N5; the (i-1)th switch pair SN i-1 and SNB i-1 The first switch SN in i-1 The first terminal is connected to the second input terminal VI2, and the second terminal is connected to MNX. i-1 The control electrode connection is the second switch SNB in ​​the (i-1)th switch pair. i-1 The first end with MNX i-1 The control electrode is connected, and its second electrode is connected to the low-level voltage terminal VSS; 2≤i≤N+1.

[0126] like Figure 6B As shown, MNX0, MNX1, MNX2, ..., MNX N The first terminal of each terminal is connected to the first output terminal VO1, and the second terminal is connected to the fifth node N5. MNX0 is always on, and MNX1, MNX2, ..., MNX... N It is selected to conduct through N pairs of switches.

[0127] Optionally, MNX0, MNX1, MNX2, ..., MNX N The lengths of the trenches are the same, and their widths vary proportionally.

[0128] Preferably, in order to ensure that the amplifier can be adapted to the number of bandwidth modes of the analog filter, the width ratio of the transistors in the embodiments of the present invention satisfies: MNX1:MNX2:...:MNX N =1:2:...:2 N-1 .

[0129] Specifically, SN j and SNB jThese are inverse switch pairs, namely SN1 and SNB1, SN2 and SNB2, ..., SN M and SNB N It is a pair of switches controlled by M sets of reciprocating signals, which can control MNX1, MNX2, ..., MNX N Is it in an on or off state when SN j On and SNB j When disconnected, the switch pair is connected in parallel with the corresponding transistor MNX0, when SN j Disconnect and SNB j When the switch is on, it turns off the corresponding transistor, and no current flows through it.

[0130] Specifically, SN1 and SNB1 control the state of MNX1. When the first switch SN1 is on, the second switch SNB1 is off, and the signal at the second input terminal VI2 is connected to the control electrode of MNX1, putting it in the on state and in parallel with MNX0. When the first switch SN1 is off and the second switch SNB1 is on, the control electrode of MNX1 is pulled to VSS, thus putting it in the off state. The principle is the same as the first switch controlling the state of MNX1 through SN1 and SNB1. SN2 and SNB2, ..., SN... N and SNB N Control MNX2, ..., MNX N The switching on and off of the feedforward circuit enables a reconfigurable design.

[0131] According to the bandwidth mode of the analog filter, the number of transistors connected in the feedforward circuit is changed, thereby realizing the reconfigurability of the feedforward circuit.

[0132] Optionally, Figure 7 The equivalent circuit diagram of the broadband amplifier provided in the embodiments of the present invention is as follows: Figure 7 As shown, the broadband amplifier provided in this embodiment of the invention further includes: a common-mode feedback circuit, wherein the common-mode feedback circuit is used to stabilize the second signal.

[0133] like Figure 7 As shown, the common-mode feedback circuit includes: a reconfigurable common-mode feedback sub-circuit MFBX, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a fifth capacitor C5, a sixth capacitor C6, a fifth resistor R5, and a sixth resistor R6.

[0134] Specifically, the reconfigurable common-mode feedback sub-circuit is connected to the fifth node N5, the sixth node N6, and the low-level voltage terminal VSS, respectively; the control electrode of the sixth transistor M6 is connected to the control electrode of the seventh transistor M7, its first electrode is connected to the high-level voltage terminal VDD, and its second electrode is connected to the first electrode of the ninth transistor M9; the control electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6, its first electrode is connected to the high-level voltage terminal VDD, and its second electrode is connected to the control electrode of the eleventh transistor M11; the control electrode of the eighth transistor M8 is connected to the seventh node N7, its first electrode is connected to the second electrode of the seventh transistor M7, and its second electrode is connected to the first electrode of the tenth transistor M10; the control electrode of the ninth transistor M9 is connected to the reference voltage terminal VREF, and its second electrode is connected to the first electrode of the tenth transistor M10; the tenth transistor M... The control terminal of transistor M10 is connected to the bias voltage terminal VBIAS, and its second terminal is connected to the low-level voltage terminal VSS; the first terminal of the eleventh transistor M11 is connected to the high-level voltage terminal VDD, and its second terminal is connected to the first terminal of the twelfth transistor M12; the control terminal of the twelfth transistor M12 is connected to the sixth node N6, its first terminal is connected to the sixth node N6, and its second terminal is connected to the low-level voltage terminal VSS; the first terminal of the fifth capacitor C5 is connected to the first output terminal VO1, and its second terminal is connected to the seventh node N7; the first terminal of the fifth resistor R5 is connected to the first output terminal VO1, and its second terminal is connected to the seventh node N7; the first terminal of the sixth capacitor C6 is connected to the second output terminal VO2, and its second terminal is connected to the seventh node N7; the first terminal of the sixth resistor R6 is connected to the second output terminal VO2, and its second terminal is connected to the seventh node N7.

[0135] Optionally, the sixth transistor M6 and the seventh transistor M7 are load transistors, and both are P-type transistors.

[0136] Optionally, the eighth transistor M8 and the ninth transistor M9 are a differential input pair, and both are N-type transistors.

[0137] Optionally, the tenth transistor M10 is a tail current transistor and is an N-type transistor.

[0138] Optionally, the eleventh transistor M11 is a P-type transistor.

[0139] Optionally, the twelfth transistor M12 is an N-type transistor.

[0140] It should be noted that the common-mode feedback circuit provided in this embodiment of the invention is essentially a differential-to-single-ended amplifier with dual-ended input and dual-ended output.

[0141] Specifically, Figure 8 The equivalent circuit diagram of the reconfigurable common-mode feedback sub-circuit provided in the embodiments of the present invention is as follows: Figure 8As shown, the reconfigurable common-mode feedback sub-circuit MFBX includes: K+1 N-type transistors and K switch pairs, each switch pair including: a first switch and a second switch; wherein, the K+1 N-type transistors are: MFBX0, MFBX1, MFBX2, ..., MFBX K The K switch pairs are: SF1 and SFB1, SF2 and SFB2, ..., SF K and SFB K SN j SFB is the first switch of the j-th switch pair. j Let K be the second switch of the j-th switch pair, where 1 ≤ j ≤ K.

[0142] In this configuration, the control terminal of MFBX0 is connected to the sixth node N6, its first terminal is connected to the fifth node N5, and its second terminal is connected to the low-level voltage terminal VSS; MFBX i-1 The first pole is connected to the fifth node N5, and its second pole is connected to the low-level voltage terminal VSS; the (i-1)th switch pair SF i-1 and SFB i-1 The first switch SF in i-1 The first end is connected to the sixth node N6, and its second end is connected to MFBX. i-1 The control electrode connection is the second switch SFB in the (i-1)th switch pair. i-1 The first end with MFBX i-1 The control electrode is connected, and its second electrode is connected to the low-level voltage terminal VSS; 2≤i≤K+1.

[0143] like Figure 8 As shown, MFBX0, MFBX1, MFBX2, ..., MFBX K The first terminal of each is connected to the fifth node N5, and the second terminal is connected to the low-level voltage terminal VSS. MFBX0 is always on, and MFBX1, MFBX2, ..., MFBX... K The conduction is selected by K pairs of switches.

[0144] Optionally, MFBX0, MFBX1, MFBX2, ..., MFBX K The lengths of the trenches are the same, and their widths vary proportionally.

[0145] Preferably, in order to ensure that the amplifier can be adapted to the number of bandwidth modes of the analog filter, the width ratio of the transistors in this embodiment of the invention satisfies: MFBX1, MFBX2, ..., MFBX K =1:2:...:2 K-1 .

[0146] Specifically, SF j and SFB jThese are reciprocal switch pairs, namely SF1 and SFB1, SF2 and SFB2, ..., SF K and SFB K It is a pair of switches controlled by K sets of reciprocating signals, which can control MFBX1, MFBX2, ..., MFBX K Is it in a conducting or turning-off state when SF j Conductivity and SFB j When open, the switch pair is connected in parallel with the corresponding transistor and MFBX0. When SF j Disconnect and SFB j When the switch is on, it turns off the corresponding transistor, and no current flows through it.

[0147] Specifically, SF1 and SFB1 control the state of MFBX1. When the first switch SF1 is on, the second switch SFB1 is off, and the signal from the sixth node is connected to the control electrode of MFBX1, putting it in the on state and in parallel with MFBX0. When the first switch SF1 is off and the second switch SFB1 is on, the control electrode of MFBX1 is pulled to VSS, thus putting it in the off state. The principle is the same as the first switch controlling the state of MFBX1 through SF1 and SFB1. SF2 and SFB2, ..., SF... K and SFB K Control MFBX2, ..., MFBX K The switching on and off of the common-mode feedback circuit enables a reconfigurable design.

[0148] According to the bandwidth mode of the analog filter, the number of transistors turned on in the common-mode feedback circuit is changed, thereby realizing the reconfigurability of the analog feedback circuit.

[0149] The broadband amplifier provided in this embodiment of the invention includes: a first reconfigurable amplification sub-circuit, a second reconfigurable amplification sub-circuit, a first reconfigurable feedforward sub-circuit, a second reconfigurable feedforward sub-circuit, and a reconfigurable common-mode feedback sub-circuit. The reconfigurable sub-circuit has a simple and clear structure, and can reconfigure the broadband amplifier according to different analog filter bandwidth modes while implementing a multimode broadband filter, thereby ensuring the performance of the analog filter in different bandwidth modes and optimizing the power consumption of the analog filter.

[0150] Specifically, the number of bandwidth modes of the analog filter is Q, and the minimum number of control bits is Q. min Satisfy the following formula:

[0151]

[0152] Specifically, the number of transistors in the first reconfigurable amplifier sub-circuit and the second reconfigurable amplifier sub-circuit is greater than or equal to the minimum number of control bits, the number of transistors in the first reconfigurable feedforward sub-circuit and the second reconfigurable feedforward sub-circuit is greater than or equal to the minimum number of control bits, and the number of transistors in the reconfigurable common-mode feedback sub-circuit is greater than or equal to the minimum number of control bits.

[0153] Example 2

[0154] Based on the inventive concept of the above embodiments, this invention also provides an analog filter for use in a wireless communication system, including a broadband amplifier.

[0155] The broadband amplifier is the broadband amplifier provided in Embodiment 1, and its implementation principle and effect are similar, so it will not be described again here.

[0156] Specifically, such as Figure 9 This is a schematic diagram of the structure of an analog filter provided in an embodiment of the present invention, as shown below. Figure 9 As shown, the broadband amplifier includes: a first broadband amplifier opa1 and a second broadband amplifier opa2.

[0157] Among them, the first broadband amplifier opa1 and the second broadband amplifier opa2 are the broadband amplifiers provided in Embodiment 1.

[0158] like Figure 9 As shown, the analog filter also includes: resistor R7 (seventh resistor), resistor R8 (eighth resistor), resistor R9 (ninth resistor), resistor R10 (tenth resistor), resistor R11 (eleventh resistor), resistor R12 (twelfth resistor), resistor R13 (thirteenth resistor), resistor R14 (fourteenth resistor), capacitor C7 (seventh capacitor), capacitor C8 (eighth capacitor), capacitor C9 (ninth capacitor), and capacitor C10 (tenth capacitor).

[0159] Specifically, the first terminal of the seventh resistor R7 is connected to the first input terminal of the first broadband amplifier OPA1, and its second terminal is connected to the second output terminal VO2 of the second broadband amplifier OPA2. The first terminal of the eighth resistor R8 is connected to the second input terminal of the first broadband amplifier OPA1, and its second terminal is connected to the first output terminal VO1 of the second broadband amplifier OPA2. The first terminal of the ninth resistor R9 is connected to the first input terminal INPUT1, and its second terminal is connected to the first input terminal of the first broadband amplifier OPA1. The first terminal of the tenth resistor R10 is connected to the second input terminal INPUT2, and its second terminal is connected to the second input terminal of the first broadband amplifier OPA1. The first terminal of the eleventh resistor R11 is connected to the first input terminal of the first broadband amplifier OPA1, and its second terminal is connected to the first output terminal of the first broadband amplifier OPA1. The first terminal of the twelfth resistor R12 is connected to the second input terminal of the first broadband amplifier OPA1, and its second terminal is connected to the second output terminal of the first broadband amplifier OPA1. The first end of resistor R13 (the thirteenth resistor) is connected to the first output terminal of the first broadband amplifier OPA1, and its second end is connected to the first input terminal of the second broadband amplifier OPA2. The first end of resistor R14 (the fourteenth resistor) is connected to the second output terminal of the first broadband amplifier OPA1, and its second end is connected to the second input terminal of the second broadband amplifier OPA2. The first end of capacitor C7 (the seventh capacitor) is connected to the first input terminal of the first broadband amplifier OPA1, and its second end is connected to the first output terminal of the first broadband amplifier OPA1. The first end of capacitor C8 (the eighth capacitor) is connected to the second input terminal of the first broadband amplifier OPA1, and its second end is connected to the second output terminal of the first broadband amplifier OPA1. The first end of capacitor C9 (the ninth capacitor) is connected to the first input terminal of the second broadband amplifier OPA2, and its second end is connected to the first output terminal of the second broadband amplifier OPA2. The first end of capacitor C10 (the tenth capacitor) is connected to the second input terminal of the second broadband amplifier OPA2, and its second end is connected to the second output terminal of the second broadband amplifier OPA2.

[0160] Optionally, the seventh resistor R7 and the eighth resistor R8 have the same resistance value, and both are resistors with fixed resistance values.

[0161] Optionally, the ninth resistor R9 and the tenth resistor R10 are variable resistors.

[0162] Optionally, the eleventh resistor R11 and the twelfth resistor R12 are variable resistors.

[0163] Optionally, the thirteenth resistor R13 and the fourteenth resistor R14 have the same resistance value, and both are resistors with fixed resistance values.

[0164] Optionally, the seventh capacitor C7 and the eighth capacitor C8 are variable capacitors.

[0165] Optionally, the ninth capacitor C9 and the tenth capacitor C10 are variable capacitors.

[0166] It should be noted that the seventh resistor R7, the eighth resistor R8, the thirteenth resistor R13, the fourteenth resistor R14, the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, and the tenth capacitor C10 in the analog filter provided in this embodiment of the invention jointly determine the cutoff frequency of the analog filter. The bandwidth variation of the analog filter disclosed in this embodiment of the invention is achieved by changing the switching mode of the capacitance values ​​of the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, and the tenth capacitor C10.

[0167] In the analog filter provided in this embodiment of the invention, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, and the tenth resistor R10 together determine the gain of the analog filter. Specifically, in this embodiment of the invention, the resistance values ​​of the seventh resistor R7 and the eighth resistor R8 are fixed, and the gain of the analog filter can be adjusted by changing the resistance values ​​of the ninth resistor R9 and the tenth resistor R10.

[0168] In the analog filter provided in this embodiment of the invention, the seventh resistor R7, the eighth resistor R8, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, and the fourteenth resistor R14 collectively determine the quality factor of the analog filter, thereby affecting the in-band flatness and out-of-band rejection of the analog filter. Since the resistance values ​​of the seventh resistor R7, the eighth resistor R8, the thirteenth resistor R13, and the fourteenth resistor R14 in this embodiment of the invention are fixed, independently adjusting the bandwidth and gain of the analog filter will not affect the quality factor of the filter.

[0169] Furthermore, the configuration of the bandwidth mode of the analog filter provided in this embodiment of the invention includes the following steps:

[0170] Step S1: Configure the capacitors of the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, and the tenth capacitor C10 according to the required bandwidth mode. Repeat this operation until the gain at the corresponding cutoff frequency is 3dB less than the power gain at DC.

[0171] It should be noted that step S1 can be completed manually or automatically.

[0172] Step S2: Configure the resistances of the eleventh resistor R11 and the twelfth resistor R12 according to the required in-band flatness, and repeat this operation until the flatness meets the requirements.

[0173] Step S3: Repeat steps one and two until both bandwidth and in-band flatness meet the requirements.

[0174] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A broadband amplifier, characterized in that, The analog filter includes multiple bandwidth modes, and the broadband amplifier includes a gain circuit; the gain circuit includes a first amplification sub-circuit and a second amplification sub-circuit. The first amplifier sub-circuit is used to amplify the input signal and generate a first signal; The second amplification sub-circuit is used to reconfigure according to the bandwidth mode of the analog filter, and also to amplify the first signal to generate the second signal; The broadband amplifier also includes: a feedforward circuit; The feedforward circuit is used to reconfigure according to the bandwidth mode of the analog filter, and also to receive the input signal and perform feedforward compensation on the input signal. The feedforward circuit includes: a first reconfigurable feedforward sub-circuit and a second reconfigurable feedforward circuit; The first reconfigurable feedforward subcircuit includes: N+1 N-type transistors and N switch pairs, each switch pair including: a first switch and a second switch; In this configuration, the control electrode of the first transistor is connected to the first input terminal, its first electrode is connected to the second output terminal, and its second electrode is connected to the fifth node; the first electrode of the i-th transistor is connected to the second output terminal, and its second electrode is connected to the fifth node; in the (i-1)-th switch pair, the first terminal of the first switch is connected to the first input terminal, and its second terminal is connected to the control electrode of the i-th transistor; in the (i-1)-th switch pair, the first terminal of the second switch is connected to the control electrode of the i-th transistor, and its second electrode is connected to the low-level voltage terminal. The second reconfigurable feedforward subcircuit includes: N+1 N-type transistors and N switch pairs, each switch pair including: a first switch and a second switch; In this configuration, the control electrode of the first transistor is connected to the second input terminal, its first electrode is connected to the first output terminal, and its second electrode is connected to the fifth node; the first electrode of the i-th transistor is connected to the first output terminal, and its second electrode is connected to the fifth node; in the (i-1)-th switch pair, the first terminal of the first switch is connected to the second input terminal, and its second terminal is connected to the control electrode of the i-th transistor; in the (i-1)-th switch pair, the first terminal of the second switch is connected to the control electrode of the i-th transistor, and its second electrode is connected to the low-level voltage terminal, where 2≤i≤N+1.

2. The broadband amplifier according to claim 1, characterized in that, The first amplification sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first resistor, a second resistor, a first capacitor, and a second capacitor; The control electrode of the first transistor is connected to the first input terminal, its first electrode is connected to the first node, and its second electrode is connected to the second node; The control electrode of the second transistor is connected to the second input terminal, its first electrode is connected to the first node, and its second electrode is connected to the third node; The control electrode of the third transistor is connected to the fourth node, its first electrode is connected to the second node, and its second electrode is connected to the high-level voltage terminal. The control electrode of the fourth transistor is connected to the fourth node, its first electrode is connected to the third node, and its second electrode is connected to the high-level voltage terminal. The control electrode of the fifth transistor is connected to the bias voltage terminal, its first electrode is connected to the first node, and its second electrode is connected to the low-level voltage terminal. The first end of the first capacitor is connected to the second node, and its second end is connected to the fourth node. The first end of the second capacitor is connected to the fourth node, and its second end is connected to the third node; The first end of the first resistor is connected to the second node, and its second end is connected to the fourth node; The first end of the second resistor is connected to the fourth node, and its second end is connected to the third node; Among them, the first transistor, the second transistor, and the fifth transistor are N-type transistors, and the third transistor and the fourth transistor are P-type transistors.

3. The broadband amplifier according to claim 2, characterized in that, The second amplifier sub-circuit includes: a first reconfigurable amplifier sub-circuit and a second reconfigurable amplifier sub-circuit; The first reconfigurable amplifier sub-circuit includes: M+1 P-type transistors and M switch pairs, each switch pair including: a first switch and a second switch; In this configuration, the control electrode of the first transistor is connected to the third node, its first electrode is connected to the high-level voltage terminal, and its second electrode is connected to the second output terminal; the first electrode of the i-th transistor is connected to the high-level voltage terminal, and its second electrode is connected to the second output terminal; in the (i-1)-th switch pair, the first terminal of the first switch is connected to the third node, and its second terminal is connected to the control electrode of the i-th transistor; in the (i-1)-th switch pair, the first terminal of the second switch is connected to the control electrode of the i-th transistor, and its second terminal is connected to the high-level voltage terminal. The second reconfigurable amplifier sub-circuit includes: M+1 P-type transistors and M switch pairs, each switch pair including: a first switch and a second switch; In this configuration, the control electrode of the first transistor is connected to the second node, its first electrode is connected to the high-level voltage terminal, and its second electrode is connected to the first output terminal; the first electrode of the i-th transistor is connected to the high-level voltage terminal, and its second electrode is connected to the first output terminal; the first terminal of the first switch in the (i-1)-th switch pair is connected to the second node, and its second terminal is connected to the control electrode of the i-th transistor; the first terminal of the second switch in the (i-1)-th switch pair is connected to the control electrode of the i-th transistor, and its second electrode is connected to the high-level voltage terminal; 2≤i≤M+1.

4. The broadband amplifier according to claim 3, characterized in that, The gain circuit further includes: a first compensation sub-circuit and a second compensation sub-circuit; the first compensation sub-circuit includes: a third resistor and a third capacitor, and the second compensation sub-circuit includes: a fourth resistor and a fourth capacitor; The first end of the third resistor is connected to the second node, and its second end is connected to the first end of the third capacitor. The second terminal of the third capacitor is connected to the second output terminal; The first end of the fourth resistor is connected to the third node, and its second end is connected to the first end of the fourth capacitor. The second terminal of the fourth capacitor is connected to the first output terminal.

5. The broadband amplifier according to claim 1, characterized in that, The broadband amplifier further includes: a common-mode feedback circuit; The common-mode feedback circuit is used to stabilize the second signal.

6. The broadband amplifier according to claim 5, characterized in that, The common-mode feedback circuit includes: a reconfigurable common-mode feedback sub-circuit, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a fifth capacitor, a sixth capacitor, a fifth resistor, and a sixth resistor; wherein, The reconfigurable common-mode feedback sub-circuit is connected to the fifth node, the sixth node, and the low-level voltage terminal, respectively. The control electrode of the sixth transistor is connected to the control electrode of the seventh transistor, and its first electrode is connected to the high-level voltage terminal, and its second electrode is connected to the first electrode of the ninth transistor. The control electrode of the seventh transistor is connected to the second electrode of the sixth transistor, and its first electrode is connected to the high-level voltage terminal, while its second electrode is connected to the control electrode of the eleventh transistor. The control electrode of the eighth transistor is connected to the seventh node, and its first electrode is connected to the second electrode of the seventh transistor, and its second electrode is connected to the first electrode of the tenth transistor. The control terminal of the ninth transistor is connected to the reference voltage terminal, and its second terminal is connected to the first terminal of the tenth transistor. The control electrode of the tenth transistor is connected to the bias voltage terminal, and its second electrode is connected to the low-level voltage terminal. The first terminal of the eleventh transistor is connected to the high-level voltage terminal, and its second terminal is connected to the first terminal of the twelfth transistor. The control electrode of the twelfth transistor is connected to the sixth node, its first electrode is connected to the sixth node, and its second electrode is connected to the low-level voltage terminal. The first terminal of the fifth capacitor is connected to the first output terminal, and its second terminal is connected to the seventh node. The first end of the fifth resistor is connected to the first output terminal, and its second end is connected to the seventh node. The first terminal of the sixth capacitor is connected to the second output terminal, and its second terminal is connected to the seventh node. The first end of the sixth resistor is connected to the second output end, and its second end is connected to the seventh node; The sixth, seventh, and eleventh transistors are P-type transistors, while the eighth, ninth, tenth, and twelfth transistors are N-type transistors.

7. The broadband amplifier according to claim 6, characterized in that, The reconfigurable common-mode feedback sub-circuit includes: K+1 N-type transistors and K switch pairs, each switch pair including: a first switch and a second switch; In this configuration, the control electrode of the first transistor is connected to the sixth node, its first electrode is connected to the fifth node, and its second electrode is connected to the low-level voltage terminal; the first electrode of the i-th transistor is connected to the fifth node, and its second electrode is connected to the low-level voltage terminal; in the (i-1)-th switch pair, the first terminal of the first switch is connected to the sixth node, and its second terminal is connected to the control electrode of the i-th transistor; in the (i-1)-th switch pair, the first terminal of the second switch is connected to the control electrode of the i-th transistor, and its second electrode is connected to the low-level voltage terminal; 2≤i≤K+1.

8. The broadband amplifier according to claim 7, characterized in that, The analog filter has Q bandwidth modes and a minimum number of control bits Q. min Satisfy the following formula: Where M, N, K ≥ Q min -1.

9. An analog filter, characterized in that, Applied to wireless communication systems, including: a broadband amplifier as described in any one of claims 1 to 8.

10. The analog filter according to claim 9, characterized in that, The broadband amplifier includes a first broadband amplifier and a second broadband amplifier connected in series.

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