Generation of Pulse Width Modulation (PWM) Pulses

Abstract

The present application discloses the generation of pulse width modulation (PWM) pulses. A circuit includes: a basic pulse generator (310) for generating a first pulse width modulation (PWM) pulse, a first clock generation circuit for generating a first frequency and M clocks that are phase-shifted relative to each other, and a second clock generation circuit (302) for receiving the M clocks and generating N clocks each at a second lower frequency, and the M clocks are phase-shifted relative to each other. Each of a plurality of flip-flops (302) includes: a clock input for receiving a different one of the N clocks; a data input that is coupled to receive the first PWM pulse; and a flip-flop output. A selection circuit (340) includes a plurality of inputs and a selection circuit output. Each of the plurality of inputs is coupled to a corresponding flip-flop output. The selection circuit (340) provides a selected one of the flip-flop outputs as the selection circuit output in response to a control signal.

Description

Background Art

[0001] Many applications use Pulse Width Modulation (PWM) signals. For example, a buck converter regulator uses a PWM signal to control the duty cycle, for which the high-side and low-side power transistors are turned on and off to produce the required level of the output voltage. For each rising edge and each falling edge of a given PWM pulse when it occurs, certain applications benefit from relatively high-resolution control. Summary of the Invention

[0002] In some embodiments, a circuit includes: a basic pulse generator for generating a first Pulse Width Modulation (PWM) pulse; a first clock generation circuit for generating M clocks having a first frequency and phase-shifted relative to each other; and a second clock generation circuit for receiving the M clocks and generating N clocks at a second lower frequency. The M clocks are phase-shifted relative to each other. Each of a plurality of flip-flops includes: a clock input for receiving a different one of the N clocks; a data input for receiving the first PWM pulse; and a flip-flop output. A selection circuit includes a plurality of inputs and a selection circuit output. Each of the plurality of inputs is coupled to a corresponding flip-flop output. The selection circuit provides a selected one of the flip-flop outputs as the selection circuit output in response to a control signal to form an output PWM pulse. Description of the Drawings

[0003] For a detailed description of various examples, reference will now be made to the drawings, in which:

[0004] Figure 1 Illustrates a system including a Pulse Width Modulation (PWM) pulse generator according to an example.

[0005] Figure 2 Includes an example of a phase-locked loop that can be used in Figure 1 the system.

[0006] Figure 3 is Figure 1 a schematic diagram of a PWM pulse generator.

[0007] Figure 4 is a schematic diagram of a circuit for generating a larger number of phase-delayed clocks based on a smaller number of input clocks.

[0008] Figure 5 is a timing diagram illustrating the timing relationship between one of the input clocks and the larger number of phase-delayed clocks generated using that input clock.

[0009] Figure 6 is a timing diagram illustrating the timing relationship between the input clocks and the larger number of phase-delayed clocks generated using each of the input clocks.

[0010] Figure 7 Shows how the width of the output pulse can be reduced relative to the width of the basic pulse.

[0011] Figure 8 Shows how the width of the output pulse can be extended relative to the width of the basic pulse. DETAILED DESCRIPTION

[0012] This disclosure describes an example in which a first set of clocks is used to generate a second set of clocks. Each of the first set of clocks has the same frequency, but the first set of clocks is phase-shifted relative to each other. The number of the second set of clocks is greater than the number of the first set of clocks. Each of the second set of clocks also has a common frequency, but the second set of clocks is phase-shifted relative to each other. The frequency of the second set of clocks is less than the frequency of the first set of clocks. The phase shift between the clocks in the second set is less than the phase shift between the clocks in the first set. A basic PWM generator generates basic PWM pulses. A circuit is described below that receives the basic PWM pulses and uses one or more of the second set of clock bases to generate output PWM pulses, the width of which (a) is the same as the basic PWM pulses, (b) is narrower than the width of the basic PWM pulses, or (c) is wider than the width of the basic PWM pulses. A central processing unit (CPU) core can specify when the rising edge and / or falling edge of the output PWM pulses should occur, thereby determining the width of the output PWM pulses.

[0013] Figure 1 Shows system 100 according to the disclosed example. In Figure 1 the example, system 100 includes a system-on-chip (SoC) that includes a semiconductor substrate 101 on which a CPU core 102, a PWM pulse generator 110, a phase-locked loop (PLL) 112, a direct memory access (DMA) controller 120, a memory 130, and one or more input / output (I / O) devices 140 are formed. The memory 130 (or a memory external to the semiconductor substrate 101) includes firmware (F / W) 132 that includes instructions executable by the CPU core 102. The CPU core 102 can be a single core or can include multiple CPU cores 102. If there are multiple CPU cores 102, each core can execute some or all of the firmware 132. That is, the firmware 132 can be fully executed by each of the multiple cores or distributed across the multiple cores. The DMA controller 120 can implement block transfer of data from a region of memory starting at, for example, one address to a different region of memory starting at a different address. The CPU core 102 programs the DMA controller 120 to initiate the data transfer, but the DMA controller causes the data transfer to occur without further participation of the CPU core 102. Each I / O device can include a port (e.g., Ethernet) or other type of peripheral device.

[0014] The PWM pulse generator 110 is programmed by the CPU core 102 to generate a series of PWM output pulses (PWM output 113). The CPU core 102 provides one or more configuration parameters to the PWM pulse generator 110. The configuration parameters indicate the frequency of the PWM pulses and the width of each pulse. As described below, the PWM pulse generator 110 uses a plurality of clock signals 114 from the PLL 112 to generate the requested PWM pulses. The clock signals 114 from the PLL 112 represent the first set of clock signals described above. The second set of clocks is generated internally within the PWM pulse generator 110. The frequency of the clocks 114 is generally substantially higher than the frequency of the second set of clocks. Although in Figure 1 the example of Figure 1 the PLL 112 is used to generate the higher frequency clocks 114 for use by the PWM pulse generator 110, in other examples other higher frequency clock sources may be used.

[0015] Figure 2 An example of the PLL 112 is shown. The PLL 112 includes a phase and frequency detector (PFD) 202, a charge pump and loop filter 204, a voltage controlled oscillator (VCO) 206, and a frequency divider 210. The VCO 206 generates an output clock (CLK_OUT), which in addition to being the output clock from the PLL, is also provided back to the input of the PFD 202. A reference clock (REF_CLOCK) is also provided to the PFD 202 through the frequency divider 210 (in this example). If the frequency of CLK_OUT is greater than REF_CLOCK (e.g., CLK_OUT is ten times the frequency of REF_CLOCK), then the frequency divider 210 is included to divide CLK_OUT to produce a feedback clock (FB_CLK) having the same frequency as REF_CLOCK. If the frequency of CLK_OUT is the same as the frequency of REF_CLOCK, the frequency divider is not used. The PFD 202 generates an error signal (ERR) 203, which encodes whether FB_CLK leads or lags REF_CLOCK. The charge pump and filter 204 includes a charge pump and a low pass filter, and generates a filtered voltage for the VCO 206 to cause the VCO 206 to slightly adjust the phase or frequency of CLK_OUT. The feedback control of the PLL 112 keeps CLK_OUT in phase lock with REF_CLOCK.

[0016] In this example, VCO 206 includes a ring oscillator 208 to generate CLK_OUT. The ring oscillator 208 includes an odd number of inverters connected in series in a ring configuration. In this example, the ring oscillator 208 includes three inverters 208a, 208b, and 208c, but may include 5, 7, 9, etc. inverters in other embodiments. The oscillation frequency of the output of each inverter 208a-c is a function of the number of inverters in the ring and the propagation delay through each inverter. The outputs of each of the inverters 208a, 208b, and 208c are tapped to provide VCO clock output signals. The output of inverter 208a is labeled VCO_CLK_1. The output of inverter 208b is labeled VCO_CLK_2. The output of inverter 208c is labeled VCO_CLK_3. These three clocks have equal frequencies, but are phase-shifted from each other due to the propagation delay of each inverter. That is, the time delay of VCO_CLK_2 relative to VCO_CLK_1 is an amount of time equal to the propagation delay through inverter 208a. Similarly, the time delay of VCO_CLK_3 relative to VCO_CLK_2 is an amount of time equal to the propagation delay through inverter 208b, and the time delay of VCO_CLK_1 relative to VCO_CLK_3 is an amount of time equal to the propagation delay through inverter 208c.

[0017] Figure 3 FIG. shows an example block diagram of PWM pulse generator 110. In this example, PWM pulse generator 110 includes a phase-shifted clock generator 302, a basic pulse generator 310, a plurality of flip-flops 320, and a selection circuit 340. As shown at 301, the phase-shifted clock generator 302 receives M VCO clocks and generates N clocks 303 based on these M clocks, denoted as CLK_1, CLK_2, …, CLK_N. N is greater than M, and in one example, N is at least twice M. In Figure 3 the example, M is 3 and includes the clocks VCO_CLK_1, VCO_CLK_2, and VCO_CLK_3. In one example, N is 24, meaning the phase-shifted clock generator 302 generates 24 output clocks based on 3 input clocks. Each of the N clocks CLK_1-N has the same frequency among the N clocks CLK_1-N, but is lower than the frequencies of the clocks VCO_CLK_1, VCO_CLK_2, and VCO_CLK_3. The N clocks 303 are phase-shifted relative to each other. In one example, the frequency of each of the N clocks 303 is less than half the frequency of the VCO clocks 301. In one example, the frequency of each of the N clocks 303 is one-fourth the frequency of each of the VCO clocks 301. An example implementation of the phase-shifted clock generator 302 is shown in Figure 4 and described below.

[0018] Still referring to Figure 3 ,the basic pulse generator 310 can be configured by, for example, the CPU core 102 to generate pulses on the output line 311 to a plurality of flip - flops 320. The CPU core 102 can program the basic pulse generator 310 with respect to the pulse frequency and its duty cycle on the line 311. In one embodiment, the CPU core 102 can write to one or more registers to configure the basic pulse generator 310.

[0019] The flip - flops 320 include flip - flops 320a, 320b, …, 320N, with one flip - flop 320 for each of CLK_1 - N. The output line 311 from the basic pulse generator 310 is coupled to the data input (D) input of each of the flip - flops 320. Each clock CLK_1 - N is coupled to the clock input of the corresponding flip - flop 320. For example, CLK_1 is coupled to the clock input of flip - flop 320a, CLK_2 is coupled to the clock input of flip - flop 320b, and so on.

[0020] The selection circuit 340 includes a multiplexer 342 and a multiplexer 345. The Q outputs of the flip - flops 320 are provided to the inputs of the multiplexer 342. The output of the multiplexer 342 is coupled to one input of the multiplexer 345, and the output line 311 (on which the basic pulse from the basic generator 310 is provided) is coupled to the other input of the multiplexer 345. In this embodiment, the control signals CTL1 and CTL2 generated by the basic pulse generator 310 are provided to the control inputs of the multiplexers 342 and 345 respectively. By controlling the multiplexers 342 and 345, the output of any flip - flop 320 can be routed through the multiplexer as the PWM output 113. Alternatively, when the basic pulse generated by the basic pulse generator 310 bypasses the multiplexer 342 and the flip - flops 320, the basic pulse generated by the basic pulse generator 310 can be provided through the multiplexer 345.

[0021] Figure 4 An example of an embodiment of the phase - shift clock generator 302 is shown. The example embodiment includes circuits 410a, 410b, and 410c - each circuit 410a - c receives one of the VCO clocks 301. VCO_CLK_1 is provided to circuit 410a. VCO_CLK_2 is provided to circuit 410b. VCO_CLK_3 is provided to circuit 410c. In this example, the circuits 410 - c are generally identical to each other, and thus only circuit 410a is shown in detail for convenience. Circuit 410a includes flip - flops 420, 422, 430, and 432 and inverters 425, 440, 442, 446, and 448.

[0022] The Q output of flip-flop 420 is coupled to the D input of flip-flop 422, and the Q' output (logical inverse of the Q output) of flip-flop 422 is coupled to the D input of flip-flop 420. Each of flip-flops 420 and 422 is clocked by VCO_CLK_1. The combination of flip-flops 420 and 422 represents a frequency divider that divides the frequency of the input clock VCO_CLK_1 by a factor of 4. That is, the frequency of each of the output clocks A, B, A', and B' is one-fourth of the frequency of VCO_CLK_1. Flip-flops 430 and 432 are configured similarly and also represent a frequency divider (factor 4 in this example). Inverter 425 inverts VCO_CLK_1, and the complement of VCO_CLK_1 is thus used to clock flip-flops 430 and 432.

[0023] Based on one clock input VCO_CLK_1, eight output clocks A, B, C, D and their complements A′, B′, C′, and D′ are generated. Figure 5 An example of a timing diagram showing the input clock VCO_CLK_1 and the eight output clocks A-D and A′-D′ is shown. The A clock is taken from the Q output of flip-flop 420. Inverter 440 generates the complement of A. The B clock is tapped from the Q output of flip-flop 422 and is phase-delayed by one VCO_CLK_1 period with respect to the A clock. Inverter 442 generates the complement of B. The C and D clocks are taken from the Q outputs of flip-flops 430 and 432, respectively. Inverters 446 and 448 are used to generate the complements of C and D, respectively.

[0024] As in Figure 5As can be seen, the eight output clocks A - B and A' - D' have the same frequency, which is one - quarter of the frequency of VCO_CLK_1. In addition, each of the eight output clocks A - B and A' - D' is phase - delayed relative to each other. The other two circuits 410b and 410c operate in the same manner as circuit 410a, but are based on different input clocks (VCO_CLK_2 and VCL_CLK_3). Since VCO_CLK2 and VCO_CLK 3 are phase - delayed relative to each other and relative to VCO_CLK_1, each of the eight output clocks A - D and A' - D' from circuits 410b and 410c is also phase - delayed relative to its corresponding clock in the other circuits. That is, the output clock A from each of circuits 410a - c is phase - delayed relative to each of the other A output clocks. In addition, the output clock B from each of circuits 410a - c is phase - delayed relative to each of the other B output clocks, and so on. Since each circuit 410 - c generates 8 output clocks A - D and A' - D' from a single input clock, the set of circuits 410a - 410c generates 24 output clocks based on the three input clocks VCO_CLK_1, VCO_CLK_2, and VCO_CLK_3.

[0025] Figure 6 FIG. shows an example timing diagram that illustrates the three input clocks (VCO_CLK_1, VCO_CLK_2, VCO_CLK_3) of the phase - shift clock generator 302 and the corresponding 24 output clocks CLK_1, CLK_2, …, CLK_24. The phase delay between the clocks generated by the phase - shift clock generator 302 is relatively small (15 degrees in this example), and as described below, fine control of the position of the edges of the PWM output 113 can be obtained by using any one of the 24 clocks.

[0026] Return reference Figure 3 , the CPU core 102 provides one or more configuration parameters to the basic pulse generator 310 so that PWM pulses are generated for the PWM output 113 with a specific pulse width. The basic pulse generator 310 generates a basic pulse on line 311, the width of which can be different from the width specified by the CPU core 102. For example, the width of the basic pulse can be 100 picoseconds, but the CPU core 102 can request a pulse width of 110 picoseconds. The flip - flop 320 and the selection circuit 340 are used to generate the PWM output 113 with the necessary pulse width (e.g., 110 picoseconds). The requested pulse width can be less than or greater than the pulse width generated by the basic pulse generator 310. The basic pulse generator 301 can be configured by the CPU core 102 to generate basic pulses with a certain pulse - width range on line 311.

[0027] In a case where the CPU core 102 requests that the PWM output 113 have a pulse width smaller than the basic pulse width on line 311, the basic pulse generator 310 asserts the control signals CTL1 and CTL2 to operate the multiplexers 342 and 345 so that the rising edge of the PWM output 113 is delayed with respect to the rising edge of the basic pulse. Figure 7 Illustrates the basic pulse and the PWM output 113 pulse. The rising edge 710 of the PWM output pulse is time-delayed (TD1) with respect to the rising edge 705 of the basic pulse, but the falling edges 715 and 720 are phase-aligned as shown. The delay of the rising edge 710 can be achieved by selecting the output of a specific flip-flop 320 via the multiplexer 342, and the output of the specific flip-flop 320 is time-delayed by the target time delay amount TD1. The D input of each of the flip-flops 320 receives the basic pulse from line 311, but each flip-flop is clocked by a different one of the 24 phase-delayed clocks CLK_1 to CLK_24. The basic pulse generator 310 asserts CTL1 to select the Q output of the flip-flop 320 corresponding to TD1. For example, if TD1 is 100 picoseconds and the time delay from one clock to the next in the clock 303 is 10 picoseconds, then CTL1 is asserted to select the output of the flip-flop 320 corresponding to CLK_10. CTL2 is also asserted to pass through the output of the multiplexer 342 to the PWM output 113. The basic pulse generator 310 determines the flip-flop 320 for generating the corresponding PWM edge based on the programmed pulse width from the CPU core 102. The basic pulse generator may include, for example, a mapping between the pulse width and the flip-flop 320.

[0028] Once the rising edge of the corresponding clock (e.g., CLK_10) appears, the output of the flip-flop will transition to the logic high state (since the D input is high), thus forming the rising edge of the PWM output 113. Once the rising edge of the PWM output 113 is generated using the correct flip-flop 320, the basic pulse generator 310 then changes CTL2 so that the multiplexer 345 selects the signal on line 311 as the output from the multiplexer 345. In this way, the falling edge 715 of the basic pulse serves as the falling edge 720 of the PWM output 113, as Figure 7 shown.

[0029] In a case where the CPU core 102 requests that the PWM output 113 have a width larger than the width of the basic pulse on line 311, the basic pulse generator 310 asserts the control signals CTL1 and CTL2 to operate the multiplexers 342 and 345, thereby using the rising edge of the PWM output 113 as the rising edge of the PWM output 113, but delaying the falling edge. Figure 8Describe the basic pulse and the PWM output pulse. The rising edge 810 of the PWM output pulse serves as the rising edge 810 of the PWM output 113. That is, the rising edges 805 and 810 are phase-aligned. However, the falling edge 820 of the basic pulse is time-delayed (TD2) relative to the falling edge 815 of the basic pulse. The phase alignment of the rising edge 810 of the PWM output 113 with the rising edge 805 of the basic pulse is achieved by the multiplexer 345 selecting the basic pulse on the BYPASS line 327. Once the rising edge 805 appears, the basic pulse generator 310 reconfigures the multiplexer to select the flip-flop 320 corresponding to the desired TD2 time delay.

[0030] In the disclosed example, the higher-frequency clock 301 is taken from the ring oscillator 208 of the voltage-controlled oscillator 206 of the PLL. By its nature, the PLL maintains frequency and phase lock relative to the reference clock, and does so regardless of process, voltage, and temperature (PVT) variations. Thus, since the disclosed example uses the clock from the PLL as the higher-frequency clock (from which a greater number of lower-frequency clocks 303 are generated), the higher-frequency clock 301 does not drift due to the effects of process, voltage, and temperature. Thus, the examples described herein achieve a resolution for the edges of the pulses for the PWM output 113 that varies relatively little (if at all) with changes in process, voltage, and temperature. Additionally, some systems (e.g., systems based on the use of delay lines) require calibration to account for changes in the phase shift between clocks due to changes in operating conditions (which in turn translates to the delay inserted in the PWM pulses). For example, delay line systems require periodic calibration of the delay as operating conditions change. However, in the disclosed example, since the phase shift between the clocks does not change due to the use of the clock from the PLL, no calibration is required during operation, thus saving application runtime. Also, only a small portion of the logic (e.g., the counter) is clocked at a relatively high frequency; the remaining logic is clocked at a lower frequency and thus consumes less power than if more logic were clocked at a higher frequency. Additionally, since the time positions of the rising and / or falling edges of the output PWM pulse can be configured relative to the basic PWM pulse by clocking the flip-flops 320 separately, the basic PWM pulse does not need to be passed through a delay line to delay the rising / falling edges of the pulse, and thus no delay line is required.

[0031] In this specification, the term "couple / couples" means a direct or indirect wired or wireless connection. Thus, if a first device is coupled to a second device, that connection may be a direct connection or an indirect connection through other devices and connections. Recitation of "based on" means "at least partially based on". Thus, if X is based on Y, X may be a function of Y and any number of other factors.

[0032] Within the scope of the claims, modifications may be made in the described embodiments, and other embodiments are possible.

Claims

1. A circuit, comprising: a basic pulse generator for generating a first pulse width modulation pulse, i.e., a first PWM pulse; a first clock generation circuit for generating M clocks having a first frequency and phase-shifted relative to each other; a second clock generation circuit for receiving the M clocks and generating N clocks each having a second frequency lower than the first frequency, and the N clocks being phase-shifted relative to each other, wherein N is greater than M; a plurality of flip-flops, each of the flip-flops comprising: a clock input coupled to receive a different one of the N clocks; a data input coupled to receive the first PWM pulse; and a flip-flop output; and a selection circuit comprising a plurality of inputs and a selection circuit output, each of the plurality of inputs being coupled to a corresponding flip-flop output, the selection circuit providing a selected one of the flip-flop outputs as the selection circuit output in response to a control signal; wherein the M and the N are integers.

2. The circuit according to claim 1, wherein one of the inputs of the selection circuit is coupled to receive the first PWM pulse.

3. The circuit according to claim 1, wherein the selection circuit comprises a first multiplexer and a second multiplexer, the first multiplexer comprising the plurality of inputs coupled to the corresponding flip-flop outputs, the first multiplexer comprising a first multiplexer output coupled to an input of the second multiplexer, and the second multiplexer comprising another input coupled to receive the first PWM pulse.

4. The circuit according to claim 3, wherein the basic pulse generator receives one or more configuration parameters for specifying the timing of the rising edge and the falling edge of the selection circuit output.

5. The circuit according to claim 4, wherein in response to the one or more configuration parameters, the basic pulse generator asserts a control signal to the first multiplexer and the second multiplexer to select: as the rising edge of the selection circuit output, an output from one of the plurality of flip-flops or the rising edge of the first PWM pulse; and as the falling edge of the selection circuit output, the falling edge of the first PWM pulse or an output from one of the plurality of flip-flops.

6. The circuit according to claim 1, wherein the first clock generation circuit comprises a voltage-controlled oscillator.

7. The circuit according to claim 6, wherein the voltage-controlled oscillator comprises a ring oscillator for generating the M clock signals.

8. The circuit according to claim 1, wherein the second clock generation circuit comprises a plurality of frequency dividers.

9. The circuit according to claim 1, wherein N is at least twice M.

10. The circuit according to claim 1, wherein the second frequency is less than half of the first frequency.

11. A system-on-chip, i.e., SoC, comprising: a semiconductor substrate; a central processing unit core, i.e., a CPU core, disposed on the semiconductor substrate; and A pulse width modulation generator, i.e., a PWM generator, disposed on the semiconductor substrate, the PWM generator being configured to: Receive configuration parameters from the CPU core to generate pulses with a specified pulse width; Generate M clocks from N input clocks, where M is greater than N, and each of the M clocks has a frequency lower than that of each of the N input clocks, and the M clocks are phase-shifted relative to each other; Generate a plurality of phase-shifted signals, each of the phase-shifted signals being generated using a different one of the M clocks; And Assert a control signal to select at least one of the generated phase-shifted signals to generate an output pulse with the specified pulse width; Wherein, M and N are integers.

12. The SoC according to claim 11, Wherein, The PWM generator includes a plurality of flip-flops for generating the plurality of phase-shifted signals, each of the plurality of flip-flops being coupled to receive a different one of the M clocks as a clock input.

13. The SoC according to claim 11, Wherein, The PWM generator includes: A basic pulse generator for generating a basic pulse; A selection circuit for selecting one of the phase-shifted signals or the basic pulse as the output from the PWM generator based on the control signal.

14. The SoC according to claim 11, Wherein, N is 3 and M is 24.

15. The SoC according to claim 11, Wherein, The PWM generator includes a plurality of frequency dividers and inverters to generate the M clocks from the N input clocks.

16. The SoC according to claim 11 further includes a ring oscillator for generating the N input clocks.

17. A circuit, Comprising: A basic pulse generator for generating a first pulse width modulation pulse, i.e., a first PWM pulse; A ring oscillator for generating M clocks with a first frequency and phase-shifted relative to each other; A second clock generation circuit for receiving the M clocks and generating N clocks each having a second frequency lower than the first frequency, and the N clocks are phase-shifted relative to each other, where N is greater than M; A plurality of flip-flops, each of the flip-flops including: a clock input coupled to receive a different one of the N clocks; a data input coupled to receive the first PWM pulse; and a flip-flop output; and A first multiplexer including a plurality of inputs, each of the plurality of inputs being coupled to a corresponding flip-flop output; and A second multiplexer coupled to receive the output from the first multiplexer and the first PWM pulse; Wherein, the basic pulse generator asserts a control signal to the first multiplexer and the second multiplexer; Wherein, M and N are integers.

18. The circuit according to claim 17, Wherein, The basic pulse generator is configured to receive one or more configuration parameters for specifying the timing of the rising edge and the falling edge of the output from the second multiplexer.

19. The circuit according to claim 17, wherein, the second clock generation circuit includes a plurality of frequency dividers.

20. The circuit according to claim 19, wherein based on the division factor of the frequency divider, the second frequency of the N clocks is a fraction of the first frequency of the M clocks.

21. A method, comprising: generating a first pulse width modulation pulse, i.e., a first PWM pulse; generating M clocks having a first frequency and phase-shifted relative to each other; using the M clocks to generate N clocks each having a second frequency lower than the first frequency and the N clocks being phase-shifted relative to each other, wherein N is greater than M; selecting, by a selection circuit, an output of one of a plurality of flip-flops, each flip-flop including a clock input coupled to receive a different one of the N clocks and including a data input coupled to receive the first PWM pulse; wherein, M and N are integers.

22. The method according to claim 21, further comprising: receiving one or more configuration parameters that specify timings of rising edges and falling edges of the output of the selection circuit.

23. The method according to claim 21, wherein, N is at least twice M, and the second frequency is less than half of the first frequency.

Images