Connection structure and forming method thereof

Abstract

A connection structure for a semiconductor package is provided, the connection structure comprising: a first passivation layer having an opening; a first conductive pattern penetrating the first passivation layer and protruding upward from the first passivation layer; a second passivation layer covering the first conductive pattern on the first passivation layer; a second conductive pattern electrically connected to the first conductive pattern on the second passivation layer; a third passivation layer covering the second conductive pattern on the second passivation layer; and an external terminal in the opening electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0155947 filed in the Korean Intellectual Property Office on December 6, 2018, the disclosure of which is incorporated herein by reference. Technical Field

[0003] Example embodiments of the inventive concepts relate to a connection structure for a semiconductor package and a method of forming the same. Background Art

[0004] With the continuous development of semiconductor technology, semiconductor chips are becoming more and more miniaturized. In contrast, various functions are integrated into a single semiconductor chip. Therefore, the semiconductor chip has a large number of input / output pads on a small area.

[0005] As a result, improved semiconductor chip packages are contemplated. Summary of the invention

[0006] Example embodiments of the inventive concepts provide a connection structure having improved structural stability for a semiconductor package and a method of forming the same.

[0007] Example embodiments also provide a connection structure having enhanced electrical characteristics for a semiconductor package and a method of forming the same.

[0008] Example embodiments also provide a connection structure having no pattern abnormality for a semiconductor package and a method of forming the same.

[0009] According to an aspect of an example embodiment, there is provided a connection structure that may include: a first passivation layer having an opening; a first conductive pattern penetrating the first passivation layer and protruding upward from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern. The first conductive pattern may be thicker than the second conductive pattern.

[0010] According to an aspect of an example embodiment, there is provided a connection structure, which may include: a carrier substrate; a first passivation layer, a second passivation layer, and a third passivation layer sequentially disposed on the carrier substrate; a first conductive pattern penetrating the first passivation layer and protruding upward from the first passivation layer; and a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern. The first conductive pattern may be thicker than the second conductive pattern.

[0011] According to an aspect of an example embodiment, a method for forming a connection structure is provided, the method may include: forming a first passivation layer having a plurality of first openings on a carrier substrate; forming a plurality of first conductive patterns, the plurality of first conductive patterns filling the first openings and protruding upward from the first passivation layer; forming a second passivation layer on the first passivation layer, the second passivation layer having a plurality of second openings exposing the first conductive patterns; forming a plurality of second conductive patterns on the second passivation layer, the plurality of second conductive patterns filling the second openings and being electrically connected to the first conductive patterns; and forming a third passivation layer on the second passivation layer to cover the second conductive patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figures 1A to 1G Illustrated is a cross-sectional view illustrating a method of forming a connection structure of a semiconductor package according to example embodiments.

[0013] Figure 1H The diagram shows a method according to an example embodiment Figure 1G An enlarged cross-sectional view of a portion of.

[0014] FIG. 2A to FIG. 2C FIG. 2 is a diagram showing a method for semiconductor packaging according to example embodiments. Figure 1G A cross-sectional view of an example of a connection structure is shown.

[0015] FIG. 3A to FIG. 3D Illustrated is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0016] 4A to 4F The diagram shows a method according to an example embodiment Figure 3D A cross-sectional view of an example of a semiconductor package is shown. DETAILED DESCRIPTION

[0017] A connection structure of a semiconductor package and a method of forming the same according to example embodiments of the inventive concept will be described below with reference to the accompanying drawings.

[0018] Advantages and aspects of the inventive concept will be apparent from the appended claims and the description discussed with reference to the drawings. The inventive concept is clearly required and particularly pointed out in the claims. However, the inventive concept can be best understood by referring to the description in conjunction with the drawings. In the description, the same reference numerals represent the same parts throughout the drawings.

[0019] It should be understood that when an element or layer is referred to as being "above," "over," "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly above, over, on, directly connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly above," "over," "on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. Throughout the drawings, the same reference numerals represent the same elements.

[0020] For ease of description, spatially relative terms such as "under", "below", "below", "above", "on", "on", etc. may be used herein to describe the relationship of an element or feature to other elements or features as shown in the drawings. It should be understood that the spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the drawings. For example, if the device in the drawings is turned over, the elements described as being "under" or "below" other elements or features will be oriented "above" the other elements or features. Therefore, the term "below" can include both above and below orientations. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptors used in this article can be interpreted accordingly.

[0021] Figures 1A to 1G Illustrated is a cross-sectional view illustrating a method of forming a connection structure of a semiconductor package according to example embodiments. Figure 1H The diagram shows Figure 1G An enlarged cross-sectional view of a portion of.

[0022] refer to Figure 1A , a carrier substrate 100 may be provided. The carrier substrate 100 may be a rigid substrate including a conductive material, a semiconductor material, or a dielectric material. For example, the carrier substrate 100 may be a bare silicon wafer or a glass substrate. The lower passivation layer 105 may be formed on the carrier substrate 100.

[0023] The lower passivation layer 105 may include a dielectric material. For example, the lower passivation layer 105 may be formed by depositing silicon oxide, silicon nitride, or a polymer. A dielectric material may be deposited on the lower passivation layer 105 and then patterned to form a first passivation layer 110 having one or more first openings 111 .

[0024] The first passivation layer 110 may include a material that is the same as or similar to that of the lower passivation layer 105. For example, the first passivation layer 110 may include silicon oxide, silicon nitride, or a polymer. Each first opening 111 may partially expose the lower passivation layer 105. When viewed in a plan view, each first opening 111 may have a circular shape, an elliptical shape, a rectangular shape, a polygonal shape, or an arbitrary shape.

[0025] An adhesive layer 101 may also be provided between the carrier substrate 100 and the lower passivation layer 105. The adhesive layer 101 may be a photosensitive adhesive. In the following description, the adhesive layer 101 will be omitted for the sake of brevity.

[0026] refer to Figure 1B , a first seed layer 112a having a relatively small thickness and a first conductive layer 114a having a relatively large thickness may be disposed on the carrier substrate 100. The first seed layer 112a may cover the first passivation layer 110, and also cover the lower passivation layer 105 partially exposed through the first opening 111. The first conductive layer 114a may have a thickness sufficient to cover the first seed layer 112a and fill the first opening 111.

[0027] The first seed layer 112a may be formed by plating or depositing a metal or its alloy such as copper (Cu), titanium (Ti), a combination thereof, or an alloy thereof, which is the same as or similar to the first conductive layer 114a. The first seed layer 112a may be formed by an electroplating process using the first seed layer 112a. The first conductive layer 114a may include, for example, copper (Cu), aluminum (Al), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), a combination thereof, or an alloy thereof.

[0028] refer to Figure 1C , the first seed layer 112a and the first conductive layer 114a may be converted into the first seed pattern 112 and the first conductive pattern 114, respectively. For example, the first seed layer 112a may be patterned to form the first seed patterns 112 separated from each other. Likewise, the first conductive layer 114a may be patterned to form the first conductive patterns 114 separated from each other. The first seed layer 112a and the first conductive layer 114a may be patterned simultaneously. The first conductive pattern 114 may fill the corresponding first opening 111 and partially protrude upward from the first passivation layer 110. The first seed pattern 112 may be disposed below the corresponding first conductive pattern 114. For example, the first seed pattern 112 may cover the bottom surface of the corresponding first conductive pattern 114.

[0029] When viewed in cross section, each first conductive pattern 114 may have a "T" shape. When viewed in cross section, each first seed pattern 112 may have a curved shape extending along a bottom surface of the corresponding first conductive pattern 114. When viewed in a plan view, each of the first seed pattern 112 and the first conductive pattern 114 may have a circular shape, an elliptical shape, a rectangular shape, a polygonal shape, or an arbitrary shape.

[0030] refer to Figure 1D , a second passivation layer 120 may be formed to cover the first passivation layer 110. For example, a dielectric material may be deposited on the first passivation layer 110 and then patterned to form a second passivation layer 120 having one or more second openings 121. The second passivation layer 120 may include a material that is the same as or similar to that of the first passivation layer 110. For example, the second passivation layer 120 may include silicon oxide, silicon nitride, or a polymer. Each second opening 121 may partially expose the first conductive pattern 114 therebelow. When viewed in a plan view, each second opening 121 may have a circular shape, an elliptical shape, a rectangular shape, a polygonal shape, or an arbitrary shape.

[0031] refer to Figure 1E , a second seed layer 122a having a relatively small thickness and a second conductive layer 124a having a relatively large thickness may be disposed on the second passivation layer 120. The second seed layer 122a may cover the second passivation layer 120, and also cover the first conductive pattern 114 partially exposed through the second opening 121. The second conductive layer 124a may have a thickness sufficient to cover the second seed layer 122a and fill the second opening 121.

[0032] The formation of the second seed layer 122a and the second conductive layer 124a can be similar to the above reference Figure 1B The first seed layer 112a and the first conductive layer 114a are formed in the same or similar manner. For example, the second seed layer 122a may be formed by plating or depositing a metal or its alloy such as copper (Cu), titanium (Ti), a combination thereof, or an alloy thereof. The second conductive layer 124a may be formed by an electroplating process, wherein the second seed layer 122a is plated with a metal such as copper (Cu) or its alloy.

[0033] refer to Figure 1F, the second seed layer 122a and the second conductive layer 124a may be patterned simultaneously. Therefore, the second seed layer 122a may be formed into second seed patterns 122 separated from each other. Similarly, the second conductive layer 124a may be formed into second conductive patterns 124 separated from each other. The second conductive patterns 124 may fill the corresponding second openings 121 and be electrically connected to the corresponding first conductive patterns 114. The second seed pattern 122 may be disposed below the corresponding second conductive pattern 124.

[0034] Each second conductive pattern 124 may have a line portion extending horizontally on the second passivation layer 120 and a via portion vertically penetrating the second passivation layer 120. Each second seed pattern 122 may have a curved shape extending along a bottom surface of the corresponding second conductive pattern 124 when viewed in cross section.

[0035] refer to Figure 1G , you can execute the same as above reference Figures 1A to 1C or Figures 1D to 1F The same or similar process as described above is used to form a third passivation layer 130, a third seed pattern 132, and a third conductive pattern 134 on the second passivation layer 120. The third conductive pattern 134 may be electrically connected to the corresponding second conductive pattern 124. A fourth passivation layer 140, a fourth seed pattern 142, and a fourth conductive pattern 144 may be formed on the third passivation layer 130. The fourth conductive pattern 144 may be electrically connected to the corresponding third conductive pattern 134.

[0036] The first connection structure 11 may be provided by the above process. The first connection structure 11 may be formed at a wafer level or a chip level. For example, when the carrier substrate 100 is a bare silicon wafer or a glass substrate having a size (e.g., diameter) that is the same as or similar to that of the bare silicon wafer, a slicing process may be further performed to separate the wafer-level carrier substrate 100 into a plurality of chip-level first connection structures 11.

[0037] Because the first connection structure 11 includes the rigid carrier substrate 100, the first connection structure 11 can have mechanical and structural stability. Therefore, the first connection structure 11 can be prevented from warping and / or damage, and can also be easily handled in subsequent processes. The first connection structure 11 can be processed in subsequent processes and then used as a packaging substrate for a semiconductor package or an insert substrate for any other semiconductor device. FIG. 3A to FIG. 3D and 4A to 4F Discuss these uses.

[0038] For the first connection structure 11, the first conductive pattern 114 may be used as an under-bump metal (UBM) to which a terminal such as a solder ball will be attached. In contrast, each of the second conductive pattern 124 and the third conductive pattern 134 may be used as a redistribution layer electrically connected to the first conductive pattern 114. The fourth conductive pattern 144 may be electrically connected to the first conductive pattern 114 through the second conductive pattern 124 and the third conductive pattern 134, and the fourth conductive pattern 144 may be used as a connection pad to which a terminal such as a solder ball or a solder bump will be attached. For another example, the fourth conductive pattern 144 may be used as a redistribution layer.

[0039] In some embodiments, the third conductive pattern 134 and / or the fourth conductive pattern 144 may not be formed. For example, the first connection structure 11 may include the first conductive pattern 114 used as an under bump metal (UBM) and the second conductive pattern 124 used as a redistribution layer, but includes neither the third conductive pattern 134 nor the fourth conductive pattern 144. For another example, the first connection structure 11 may include the first conductive pattern 114 used as an under bump metal (UBM), the second conductive pattern 124 used as a redistribution layer, and the fourth conductive pattern 144 used as a connection pad, but does not include the third conductive pattern 134. In other embodiments, the first connection structure 11 may further include a conductive pattern used as a redistribution layer between the third conductive pattern 134 and the fourth conductive pattern 144.

[0040] Each of the first conductive pattern 114, the second conductive pattern 124, the third conductive pattern 134, and the fourth conductive pattern 144 may have a head portion horizontally extending on a corresponding passivation layer among the first passivation layer 110, the second passivation layer 120, the third passivation layer 130, and the fourth passivation layer 140, and a tail portion vertically penetrating a corresponding passivation layer among the first passivation layer 110, the second passivation layer 120, the third passivation layer 130, and the fourth passivation layer 140. The head portion and the tail portion of the first conductive pattern 114 may be integrally merged to form a single under-bump metal (UBM). Differently, the tail portion of each of the second conductive pattern 124, the third conductive pattern 134, and the fourth conductive pattern 144 may be used as a via. The head portion of each of the second conductive pattern 124 and the third conductive pattern 134 may be a redistribution layer, and the head portion of the fourth conductive pattern 144 may be a connection pad.

[0041] refer to Figure 1H , the thickness of the first conductive pattern 114 may be greater than the thickness of the second conductive pattern 124, the third conductive pattern 134, and the fourth conductive pattern 144. For ease of description, the first seed pattern 112 may be a constituent element included in the first conductive pattern 114. This description also applies to the second conductive pattern 124, the third conductive pattern 134, and the fourth conductive pattern 144.

[0042] The first thickness T1 of the first conductive pattern 114 may be greater than the second thickness T2 of the second conductive pattern 124, the third thickness T3 of the third conductive pattern 134, and the fourth thickness T4 of the fourth conductive pattern 144, respectively. The second thickness T2, the third thickness T3, and the fourth thickness T4 may be the same or similar to each other. Alternatively, the second thickness T2 and the third thickness T3 may be the same or similar to each other, and the fourth thickness T4 may be greater than or less than each of the second thickness T2 and the third thickness T3. The first thickness T1 may indicate the total thickness of the first conductive pattern 114, and each of the second thickness T2, the third thickness T3, and the fourth thickness T4 may indicate the thickness of the substantial portion (i.e., the head portion of the corresponding conductive pattern in the second conductive pattern 124, the third conductive pattern 134, and the fourth conductive pattern 144).

[0043] The first passivation layer 110, the second passivation layer 120, the third passivation layer 130, and the fourth passivation layer 140 may have different thicknesses from each other. For example, the first thickness Tp1 of the first passivation layer 110 may be the same or similar to the third thickness Tp3 of the third passivation layer 130 and the fourth thickness Tp4 of the fourth passivation layer 140. Alternatively, the first thickness Tp1 may be greater than or less than each of the third thickness T3 and the fourth thickness T4. The second thickness Tp2 of the second passivation layer 120 may be greater than each of the first thickness T1, the third thickness T3, and the fourth thickness T4. Alternatively, the first passivation layer 110, the second passivation layer 120, the third passivation layer 130, and the fourth passivation layer 140 may have the same or similar thicknesses.

[0044] Return to reference Figure 1G , as referenced above Figures 1A to 1D As described above, the first conductive pattern 114 may be formed after forming the first passivation layer 110, and then the second passivation layer 120 may be formed on the first passivation layer 110 to cover the first conductive pattern 114. Although the first conductive pattern 114 is thicker than the second conductive pattern 124, the third conductive pattern 134, and the fourth conductive pattern 144 (as described above with reference to Figure 1H However, since the first passivation layer 110 is pre-formed to surround the tail portion of the first conductive pattern 114, the second passivation layer 120 may be formed to cover only the head portion of the first conductive pattern 114, in which case the thickness of the head portion is less than the first thickness T1 of the first conductive pattern 114. As a result, the second passivation layer 120 may be formed to be flat without undulations (or a wavy shape), which will be discussed below.

[0045] Different from the above, when a specific passivation layer is formed to cover the first conductive pattern 114 after forming a relatively thick first conductive pattern 114 on the carrier substrate 100 or on the lower passivation layer 105, it is possible that the specific passivation layer has undulations between adjacent first conductive patterns 114. In the case where the second conductive pattern 124 is formed on the specific passivation layer, the second conductive pattern 124 may be bent along the undulations of the specific passivation layer. The specific passivation layer having undulations may bring pattern abnormalities to the second conductive pattern 124 formed on the specific passivation layer, and may also cause pattern abnormalities of any other conductive pattern formed on the second conductive pattern 124. Such pattern abnormalities of conductive patterns may cause electrical short circuits or open circuits between conductive patterns.

[0046] According to example embodiments, since the first passivation layer 110 is formed before the first conductive pattern 114, and then the second passivation layer 120 is formed to cover the first conductive pattern 114, the second passivation layer 120 may have a flat shape without ups and downs. Therefore, the conductive pattern may be prevented from having problems such as pattern abnormality caused by ups and downs of the passivation layer.

[0047] FIG. 2A to FIG. 2C FIG. 2 is a diagram showing a method for semiconductor packaging according to example embodiments. Figure 1G A cross-sectional view of an example of a connection structure is shown.

[0048] refer to Figure 2A , the second connection structure 12 may be provided to further include at least one first dummy pattern 114d and / or at least one second dummy pattern 124d. For example, one or more first dummy patterns 114d may be formed simultaneously with the first conductive pattern 114. Similarly, one or more second dummy patterns 124d may be formed simultaneously with the second conductive pattern 124. Although not shown, a third dummy pattern may also be formed on the third passivation layer 130.

[0049] Each first dummy pattern 114d may be disposed on the first passivation layer 110 between adjacent first conductive patterns 114. The first seed pattern 112 may be disposed between the first passivation layer 110 and the first dummy pattern 114d. The first dummy pattern 114d may prevent the second passivation layer 120 from having undulations between the first conductive patterns 114. When viewed in a plan view, each first dummy pattern 114d may have a rectangular shape, a polygonal shape, a circular shape, an elliptical shape, or an arbitrary shape.

[0050] Each second dummy pattern 124d may be disposed on the second passivation layer 120 between adjacent second conductive patterns 124. The second seed pattern 122 may be disposed between the second passivation layer 120 and the second dummy pattern 124d. The second dummy pattern 124d may prevent the third passivation layer 130 from having undulations between the second conductive patterns 124. When viewed in a plan view, each second dummy pattern 124d may have a rectangular shape, a polygonal shape, a circular shape, an elliptical shape, or an arbitrary shape.

[0051] refer to Figure 2B , a third connection structure 13 may be provided to further include a first additional pattern 114g, a second additional pattern 124g, a third additional pattern 134g, and a fourth additional pattern 144g. For example, one or more first additional patterns 114g may be formed simultaneously with the first conductive pattern 114. Each first additional pattern 114g may be disposed on the first passivation layer 110 between adjacent first conductive patterns 114. The first seed pattern 112 may be disposed between the first passivation layer 110 and the first additional pattern 114g. The position of the first additional pattern 114g may not be limited to between the first conductive patterns 114.

[0052] Similarly, the second additional pattern 124g, the third additional pattern 134g, and the fourth additional pattern 144g electrically connected to the first additional pattern 114g may be provided on the second passivation layer 120, the third passivation layer 130, and the fourth passivation layer 140, respectively. The second additional pattern 124g, the third additional pattern 134g, and the fourth additional pattern 144g may be formed simultaneously with the second conductive pattern 124, the third conductive pattern 134, and the fourth conductive pattern 144, respectively. The first additional pattern 114g, the second additional pattern 124g, the third additional pattern 134g, and the fourth additional pattern 144g may be used as conductive patterns for power transmission or for electrical grounding. The first additional pattern 114g, the second additional pattern 124g, and the third additional pattern 134g may prevent pattern abnormalities such as undulations from occurring when the second passivation layer 120, the third passivation layer 130, and the fourth passivation layer 140 are formed.

[0053] The planar shapes of the first additional pattern 114g, the second additional pattern 124g, the third additional pattern 134g, and the fourth additional pattern 144g may be respectively the same as or similar to the planar shapes of the first conductive pattern 114, the second conductive pattern 124, the third conductive pattern 134, and the fourth conductive pattern 144. For example, when viewed in a plan view, the shape (e.g., a circular shape) of the first additional pattern 114g may be the same as or similar to the shape of the first conductive pattern 114.

[0054] refer to Figure 2C, a fourth connection structure 14 without a lower passivation layer 105 may be provided. For example, the first passivation layer 110 may be directly formed on the carrier substrate 100, or an adhesive layer (see 101 of FIG. 1 ) may be provided to form the first passivation layer 110 on the carrier substrate 100. Optionally, a first dummy pattern 114d and a second dummy pattern 124d may also be formed. Instead of the first dummy pattern 114d and the second dummy pattern 124d, Figure 2B As shown, first to fourth additional patterns 114g to 144g are formed.

[0055] FIG. 3A to FIG. 3D Illustrated is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0056] refer to Figure 3A , the semiconductor chip 200 may be disposed on the first connection structure 11. The semiconductor chip 200 may include a memory circuit, a logic circuit, or a combination thereof. The semiconductor chip 200 may include a chip pad 210 corresponding to the fourth conductive pattern 114. A connection terminal 220 such as a solder ball may be disposed between the chip pad 210 and the fourth conductive pattern 144. The semiconductor chip 200 may be electrically connected to the first connection structure 11 through the connection terminal 220.

[0057] refer to Figure 3B , a mold layer 240 may be formed on the first connection structure 11 to cover the semiconductor chip 200. The mold layer 240 may include an epoxy molding compound (EMC). Optionally, before forming the mold layer 240, an underfill layer 230 may be formed between the first connection structure 11 and the semiconductor chip 200. The underfill layer 230 may include a material that is the same as or similar to that of the mold layer 240.

[0058] refer to Figure 3C , the carrier substrate 100 can be removed. When there is a Figure 1A When the adhesive layer 101 shown in the figure is formed, the adhesive layer 101 can be irradiated with laser or ultraviolet light to separate the carrier substrate 100 from the lower passivation layer 105. A patterning process can be performed on the lower passivation layer 105 exposed due to the separation of the carrier substrate 100, so that the opening 106 can be formed to expose the first conductive pattern 114. For example, the opening 106 can be formed by performing an etching process on the lower passivation layer 105. Therefore, the opening 106 can establish a position where an external terminal will be formed as described below (see Figure 3D An etching process may be optionally performed to remove a portion of the first seed pattern 112 exposed through the opening 106.

[0059] refer to Figure 3D, the external terminal 108 may be formed to be electrically connected to the first conductive pattern 114. For example, solder may be provided and reflowed to form the external terminal 108 such as a solder ball corresponding to the first conductive pattern 114. Thus, the semiconductor package 1 may be manufactured to include the semiconductor chip 200 mounted on the first connection structure 11. The first connection structure 11 may be used as a package substrate of the semiconductor package 1.

[0060] As referenced above Figure 3C As described above, the portion of the first seed crystal pattern 112 exposed by the opening 106 may be removed. Therefore, the first seed crystal pattern 112 may not be disposed between the first conductive pattern 114 and the external terminal 108. In this case, an intermetallic compound may not be generated at the interface between the first conductive pattern 114 and the external terminal 108. Additionally or alternatively, the solder used to form the external terminal 108 may have improved wettability to the first conductive pattern 114. Partially removing the first seed crystal pattern 112 may not be a necessary process, and thus may be omitted if unnecessary.

[0061] 4A to 4F The diagram shows a Figure 3D A cross-sectional view of an example of a semiconductor package is shown.

[0062] refer to Figure 4A The semiconductor package 2 may be provided to include a semiconductor chip 200 mounted on a first connection structure 11 serving as a package substrate. The portion of the first seed pattern 112 exposed through the opening 106 may not be removed. Therefore, the first seed pattern 112 may be interposed between the first conductive pattern 114 and the external terminal 108.

[0063] The first connection structure 11 may be replaced by one of the second connection structure 12, the third connection structure 13 and the fourth connection structure 14, as shown below. FIG. 4B to FIG. 4E The detailed description can be as follows.

[0064] refer to Figure 4B , the semiconductor package 3 may be configured to include a semiconductor chip 200 mounted on a second connection structure 12 serving as a package substrate. Figure 2A As described above, the second connection structure 12 may include one or more first dummy patterns 114d formed on the first passivation layer 110 between adjacent first conductive patterns 114, and one or more second dummy patterns 124d formed on the second passivation layer 120 between adjacent second conductive patterns 124. The first dummy pattern 114d and the second dummy pattern 124d may be electrically isolated and thus may not participate in the electrical connection between the second connection structure 12 and the semiconductor chip 200. As described above with reference to Figure 2AAs described above, the first dummy pattern 114 d and the second dummy pattern 124 d may prevent pattern abnormalities such as undulations from occurring when the second passivation layer 120 and the third passivation layer 130 are formed.

[0065] refer to Figure 4C , the semiconductor package 4 may be configured to include a semiconductor chip 200 mounted on a third connection structure 13 serving as a package substrate. Figure 2B As described above, the third connection structure 13 may include a first additional pattern 114g, a second additional pattern 124g, a third additional pattern 134g, and a fourth additional pattern 144g, respectively formed on the first passivation layer 110, the second passivation layer 120, the third passivation layer 130, and the fourth passivation layer 140. The first additional pattern 114g, the second additional pattern 124g, the third additional pattern 134g, and the fourth additional pattern 144g may be used as conductive patterns required to supply power to the semiconductor chip 200 or to electrically ground the semiconductor chip 200. As described above with reference to Figure 2B As described above, the first additional pattern 114 g , the second additional pattern 124 g , and the third additional pattern 134 g may prevent pattern abnormalities such as undulations from occurring when forming the second passivation layer 120 , the third passivation layer 130 , and the fourth passivation layer 140 .

[0066] refer to Figure 4D , the semiconductor package 5 may be configured to include a semiconductor chip 200 mounted on a third connection structure 14 serving as a package substrate. Figure 2C As described above, the fourth connection structure 14 may include a first dummy pattern 114d formed on the first passivation layer 110 and / or a second dummy pattern 124d formed on the second passivation layer 120. Alternatively, instead of the first dummy pattern 114d and the second dummy pattern 124d, the semiconductor package 5 may include first to fourth additional patterns 114g to 144g formed on the first to fourth passivation layers 110 to 140, respectively, as shown in FIG. Figure 2B shown.

[0067] refer to Figure 4E , the semiconductor package 6 can be connected with Figure 4D The semiconductor package 5 shown is configured the same or similarly. Unlike the semiconductor package 5, the first passivation layer 110 may be partially etched and thinned. For example, the first passivation layer 110 may be subjected to an etching process to remove surface damage or foreign matter from the first passivation layer 110, which surface damage or foreign matter may be in the Figure 2C The fourth connection structure 14 is generated when the carrier substrate 100 is separated from the first passivation layer 110. Additionally or alternatively, an etching process may be performed to reduce the thickness of the first passivation layer 110.

[0068] When the thickness of the first passivation layer 110 is reduced, the first conductive pattern 114 may protrude outward from the thinned first passivation layer 110. The protrusion of the first conductive pattern 114 may increase the contact area between the first conductive pattern 114 and the external terminal 108. The increased contact area may reduce the contact resistance between the first conductive pattern 114 and the external terminal 108.

[0069] refer to Figure 4F The semiconductor package 7 may be configured to include a semiconductor chip 200 and a semiconductor package 30 mounted on a first connection structure 11 serving as a package substrate. The semiconductor package 7 may have a package-in-package configuration in which the semiconductor package 30 is mounted on a first connection structure 11 serving as a package substrate. Figure 3D The first connection structure 11 can be replaced by FIG. 4B to FIG. 4E One of the second connecting structure 12, the third connecting structure 13 and the fourth connecting structure 14 is shown.

[0070] The semiconductor package 30 may include one or more semiconductor chips 320 and 330 mounted on a package substrate 300, bonding wires 350 electrically connecting the semiconductor chips 320 and 330 to the package substrate 300, and a mold layer 340 encapsulating the semiconductor chips 320 and 330. The semiconductor package 30 may be disposed within the mold layer 240 encapsulating the semiconductor chip 200.

[0071] Some of the fourth conductive patterns 144 may be used for electrical connection between the first connection structure 11 and the semiconductor chip 200. Other fourth conductive patterns 144 may be used for electrical connection between the first connection structure 11 and the semiconductor package 30. For example, the first connection structure 11 and the semiconductor chip 200 may be electrically connected to each other through connection terminals 220 such as solder balls between the chip pad 210 of the semiconductor chip 200 and some of the fourth conductive patterns 144. The first connection structure 11 and the semiconductor package 30 may be electrically connected to each other through connection terminals 360 such as solder balls between the package substrate 300 and other fourth conductive patterns 144.

[0072] The package substrate 300 may include an inner pattern 302 to which a bonding wire 350 and a connection terminal 360 are electrically connected. The inner pattern 302 may be configured identically or similarly to the first connection structure 11. For example, the inner pattern 302 may include a lower conductive pattern 314 coupled to the connection terminal 360, an upper conductive pattern 334 coupled to the bonding wire 350, and an intermediate conductive pattern 324 electrically connecting the lower conductive pattern 314 and the upper conductive pattern 334 to each other.

[0073] The lower conductive pattern 314 may correspond to the first conductive pattern 114, the upper conductive pattern 334 may correspond to the fourth conductive pattern 144, and the middle conductive pattern 324 may correspond to the second conductive pattern 124 or the third conductive pattern 134. The formation of the package substrate 300 may be the same as or similar to the formation of the first connection structure 11.

[0074] The package substrate 300 including the internal pattern 302 may be used as an interposer or a double-layer redistribution layer. The first connection structure 11 may be replaced by FIG. 4B to FIG. 4E One of the second connecting structure 12, the third connecting structure 13 and the fourth connecting structure 14 is shown.

[0075] According to the present invention, pattern anomalies may not occur on a conductive pattern such as a relatively thick passivation layer between under-bump metals and on a specific pattern formed on the passivation layer. Therefore, the passivation layer or the specific pattern may not have pattern anomalies that may cause electrical failures (e.g., electrical short circuits or open circuits). In summary, the connection structure and the semiconductor package including the connection structure can improve structural stability and electrical characteristics.

[0076] This detailed description of the inventive concept should not be interpreted as being limited to the embodiments set forth herein, and the inventive concept is intended to cover various combinations, modifications and variations of the above embodiments without departing from the spirit and scope of the invention. The appended claims should be interpreted to include other embodiments.

Claims

1. A connection structure, comprising: A first passivation layer having a first opening; a first conductive pattern penetrating the first passivation layer and protruding upward from the first passivation layer; a second passivation layer, on the first passivation layer, having a second opening and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer, on the second passivation layer and covering the second conductive pattern; as well as an external terminal in the first opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern, and The second conductive pattern includes: a redistribution layer portion extending horizontally on the second passivation layer; and a via portion vertically penetrating the second passivation layer to fill the second opening and connected to the first conductive pattern, and the redistribution layer portion extends horizontally on the via portion and across the via portion.

2. The connection structure according to claim 1, wherein: The first conductive pattern comprises: a head portion extending horizontally on the first passivation layer and connected to the second conductive pattern; and The tail portion vertically penetrates the first passivation layer and is connected to the external terminal.

3. The connection structure according to claim 1, wherein: The second passivation layer is the thickest passivation layer among the first to third passivation layers.

4. The connection structure according to claim 1, further comprising: The third conductive pattern is on the third passivation layer and is electrically connected to the second conductive pattern.

5. The connection structure according to claim 1, further comprising: An additional pattern is formed on at least one of the first passivation layer and the second passivation layer.

6. The connection structure according to claim 5, wherein: At least one of the first conductive pattern and the second conductive pattern is provided in plural numbers, and The additional pattern is formed between a plurality of first conductive patterns or between a plurality of second conductive patterns.

7. The connection structure according to claim 5, wherein: The additional pattern is one of the following: an electrically isolated dummy pattern on at least one of the first passivation layer and the second passivation layer; and Conductive patterns used for power transmission or for electrical grounding. 8 . The connection structure according to claim 1 , further comprising a first seed pattern on a bottom surface of the first conductive pattern, the bottom surface of the first conductive pattern facing the external terminal.

9. The connection structure according to claim 8, wherein: The first seed pattern is not disposed at an interface between the first conductive pattern and the external terminal. 10 . The connection structure according to claim 1 , further comprising a second seed pattern on a bottom surface of the second conductive pattern, the bottom surface of the second conductive pattern facing the first conductive pattern.

11. A connection structure comprising: A carrier substrate; A first passivation layer, a second passivation layer and a third passivation layer are sequentially arranged on the carrier substrate; a first conductive pattern penetrating the first passivation layer and protruding upward from the first passivation layer; as well as a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern, and The second conductive pattern includes: a redistribution layer portion extending horizontally on the second passivation layer; and a via portion vertically penetrating the second passivation layer to fill a second opening set in the second passivation layer and connected to the first conductive pattern, and the redistribution layer portion extends horizontally on the via portion and across the via portion.

12. The connection structure according to claim 11, wherein: The first conductive pattern has a T-shape, and the T-shape includes: a head portion extending horizontally on the first passivation layer; and The tail portion vertically penetrates the first passivation layer.

13. The connection structure according to claim 11, further comprising: The third conductive pattern is on the third passivation layer and is electrically connected to the second conductive pattern.

14. The connection structure according to claim 13, wherein: The third conductive pattern is a connection pad, and the connection pad includes: a pad portion extending horizontally on the third passivation layer; and The via portion vertically penetrates the third passivation layer.

15. The connection structure according to claim 11, further comprising: an additional pattern, on at least one of the first passivation layer and the second passivation layer, Wherein, the additional pattern is one of the following: an electrically isolated dummy pattern on at least one of the first passivation layer and the second passivation layer; and Conductive patterns used for power transmission or for electrical grounding.

16. The connection structure according to claim 15, wherein: At least one of the first conductive pattern and the second conductive pattern is provided in plural numbers, and The additional pattern is formed between a plurality of first conductive patterns or between a plurality of second conductive patterns.

17. The connection structure according to claim 11, further comprising: a first seed crystal pattern on a bottom surface of the first conductive pattern, the bottom surface of the first conductive pattern facing the carrier substrate; as well as A second seed pattern on a bottom surface of the second conductive pattern, the bottom surface of the second conductive pattern facing the first conductive pattern.

18. The connection structure according to claim 11, wherein: The second passivation layer is the thickest passivation layer among the first to third passivation layers.

19. A method of forming a connection structure, the method comprising: forming a first passivation layer having a plurality of first openings on the carrier substrate; forming a plurality of first conductive patterns filling the plurality of first openings and protruding upward from the first passivation layer; forming a second passivation layer on the first passivation layer, the second passivation layer having a plurality of second openings exposing the plurality of first conductive patterns; forming a plurality of second conductive patterns on the second passivation layer, the plurality of second conductive patterns filling the plurality of second openings and being electrically connected to the plurality of first conductive patterns; as well as forming a third passivation layer covering the plurality of second conductive patterns on the second passivation layer, Among them, each of the multiple second conductive patterns includes: a redistribution layer portion extending horizontally on the second passivation layer; and a via portion vertically penetrating the second passivation layer to fill the second opening and connected to the first conductive pattern, and the redistribution layer portion extends horizontally on the via portion and across the via portion.

20. The method according to claim 19, wherein: After forming the first passivation layer, the plurality of first conductive patterns are formed.

21. The method according to claim 19, wherein: Forming the plurality of first conductive patterns comprises: forming a first seed layer on the first passivation layer; forming a first conductive layer on the first seed layer; and The first conductive layer and the first seed layer are patterned to transform the first conductive layer into the plurality of first conductive patterns, and simultaneously transform the first seed layer into a plurality of first seed patterns corresponding to the plurality of first conductive patterns.

22. The method according to claim 19, wherein: Forming the plurality of second conductive patterns comprises: forming a second seed layer on the second passivation layer; forming a second conductive layer on the second seed layer; and The second conductive layer and the second seed layer are patterned to transform the second conductive layer into the plurality of second conductive patterns and simultaneously transform the second seed layer into a plurality of second seed patterns corresponding to the plurality of second conductive patterns.

23. The method of claim 19, further comprising: A plurality of third conductive patterns electrically connected to the plurality of second conductive patterns are formed on the third passivation layer.

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