Vertical memory devices

Abstract

A vertical memory device is disclosed. The vertical memory device includes gate electrodes and channels located on a substrate. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to the upper surface of the substrate. The channels extend through the gate electrodes and include a first portion, a second portion, and a third portion. The second portion is formed on and connected to the first portion and has sidewalls inclined relative to the upper surface of the substrate, thereby having a width that gradually decreases from the bottom to the top of the second portion. The third portion is formed on and connected to the second portion.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2018-0157921, filed on December 10, 2018, with the Korean Intellectual Property Office (KIPO), the contents of which are fully incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a vertical memory device. Background Technology

[0003] In VNAND flash memory devices, as the number of gate electrodes stacked vertically increases, the vias extending through the mold cannot be formed in a single process, and each of the mold and vias requires two processes. However, when performing multi-processing, the sacrificial layer filling the lower vias cannot be completely removed, leaving residue in the lower vias, or the sacrificial layer may have a large thickness, causing the substrate on which the VNAND flash memory device can be formed to warp. Summary of the Invention

[0004] An example embodiment provides a vertical memory device with improved characteristics.

[0005] According to an example embodiment, the disclosure relates to a vertical memory device comprising: gate electrodes stacked on a substrate, the gate electrodes being spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate; a communication extending through the gate electrodes, the communication including a first portion, a second portion, and a third portion, the second portion being located on and connected to the first portion, the second portion having sidewalls inclined relative to the upper surface of the substrate such that the second portion has a width that gradually decreases from the bottom to the top of the second portion, and the third portion being located on and connected to the second portion.

[0006] According to an example embodiment, the disclosure relates to a vertical memory device comprising: gate electrodes stacked on a substrate, the gate electrodes being spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate; and a channel extending through the gate electrodes, the channel including a first portion, a second portion, and a third portion, the first portion having a width that gradually increases from the bottom to the top of the first portion, the second portion being located on and connected to the first portion, the second portion having a width that gradually decreases from the bottom to the top of the second portion, and the third portion being located on and connected to the second portion, the third portion having a width that gradually increases from the bottom to the top of the third portion.

[0007] According to an example embodiment, the disclosure relates to a vertical memory device comprising: gate electrodes stacked on a substrate, the gate electrodes being spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate; and a channel extending through the gate electrodes, the channel including a first portion, a protrusion, and a second portion, the first portion having a width that gradually increases from the bottom to the top of the first portion, the protrusion projecting upward from the upper surface of the first portion, and the second portion being located on and connected to the first portion, the second portion having a width that gradually increases from the bottom to the top of the second portion, wherein the width of the lower portion of the second portion is smaller than the width of the upper portion of the first portion. Attached Figure Description

[0008] Figure 1 , Figure 2A and Figure 2B These are plan views and cross-sectional views of a vertical memory device according to an example embodiment;

[0009] Figures 3 to 14 These are plan views and cross-sectional views illustrating a method of manufacturing a vertical memory device according to an example embodiment;

[0010] Figures 15A to 15E and Figure 16 This is a cross-sectional view showing a vertical memory device according to an example embodiment;

[0011] Figure 17A and Figure 17B This is a cross-sectional view showing a vertical memory device according to an example embodiment;

[0012] Figures 18 to 20 This is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to an example embodiment;

[0013] Figure 21 This is a cross-sectional view showing a vertical memory device according to an example embodiment;

[0014] Figures 22 to 23 This is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to an example embodiment; and

[0015] Figure 24 This is a cross-sectional view showing a vertical memory device according to an example embodiment. Detailed Implementation

[0016] The above and other aspects and features of the vertical memory device and its manufacturing method according to exemplary embodiments will become readily understood from the following detailed description with reference to the accompanying drawings.

[0017] Figure 1 , Figure 2A and Figure 2BThese are plan views and cross-sectional views illustrating a vertical memory device according to an example embodiment. Specifically, Figure 1 It's a floor plan. Figure 2A It is along Figure 1 The sectional view taken by line AA′. Figure 2B yes Figure 2A An enlarged sectional view of region X.

[0018] In the following text, a direction substantially perpendicular to the upper surface of the substrate can be defined as a first direction, and two directions substantially parallel to the upper surface of the substrate and intersecting each other can be defined as a second direction and a third direction, respectively. In the example embodiment, the second direction and the third direction can be substantially perpendicular to each other.

[0019] Reference Figure 1 , Figure 2A and Figure 2B The vertical memory device may include a gate electrode structure, an insulating pattern structure, a connection pattern 155, and a second structure extending through them on a substrate 100. The vertical memory device may also include a first impurity region 102 and a second impurity region 104, a second barrier layer 290, a second spacer 320, a common source line (CSL) 330, a contact plug 350, a bit line 370, and first to third insulating intermediate layers 260, 340, and 360.

[0020] The substrate 100 may include silicon, germanium, silicon-germanium, or III-V compounds such as GaP, GaAs, and GaSb. In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0021] The first impurity region 102 may be formed on the upper part of the substrate 100. The first impurity region 102 may include carbon or n-type or p-type impurities.

[0022] The gate electrode structure may include multiple gate electrodes spaced apart from each other in a first direction and located at multiple levels (or horizontal planes). Furthermore, the gate electrode structure may extend in a second direction, and multiple gate electrode structures may be formed in a third direction. For example, gate electrode structures that may all extend along the second direction at the same level may be divided in the third direction by an opening 270 extending longitudinally along the second direction. A component, layer, or portion of a component or layer described as extending "longitudinally" in a specific direction has a length in that specific direction and a width perpendicular to that direction, wherein the length is greater than the width.

[0023] In an example embodiment, a CSL 330 extending longitudinally in a second direction may be formed in an opening 270, and a second spacer 320 may be formed in each of the opposing sidewalls of the CSL 330 in a third direction. A second impurity region 104 may be formed adjacent to the lower surface of the CSL 330 at the upper portion of the substrate 100.

[0024] CSL 330 may include metals, metal nitrides and / or metal silicides, the second spacer 320 may include oxides, such as silicon oxide, and the second impurity region 104 may include n-type impurities, such as phosphorus, arsenic, etc.

[0025] Each gate electrode structure may include at least one first gate electrode 302, a plurality of second gate electrodes 304, and at least one third gate electrode 306 sequentially stacked in a first direction. The plurality of second gate electrodes 304 may be formed above at least one first gate electrode 302 and below at least one third gate electrode 306.

[0026] In the example embodiment, the first gate electrode 302 can be used as a ground select line (GSL), each second gate electrode 304 can be used as a word line, and the third gate electrode 306 can be used as a string select line (SSL).

[0027] Figure 2A The diagram shows a first gate electrode 302 formed at one horizontal level, second gate electrodes 304 formed at nine horizontal levels, and third gate electrodes 306 formed at two horizontal levels. However, the inventive concept is not limited to this. For example, each of the first gate electrode 302 and the third gate electrode 306 may be formed at one or more horizontal levels, and the second gate electrode 304 may be formed at multiple horizontal levels. Specifically, the second gate electrode 304 may be formed at far more than nine horizontal levels, and some of the second gate electrodes 304 adjacent to the first gate electrode 302 and / or the third gate electrode 306 may be used as dummy word lines.

[0028] Each of the first to third gate electrodes 302, 304 and 306 may include a gate conductive pattern extending in a second direction and a gate barrier pattern covering a portion of the upper surface, lower surface and sidewall of the gate conductive pattern.

[0029] The gate conductive pattern can include low-resistance metals, such as tungsten, titanium, tantalum, platinum, etc., and the gate barrier pattern can include metal nitrides, such as titanium nitride, tantalum nitride, etc.

[0030] The insulating pattern structure may include a plurality of insulating patterns 115 stacked at multiple horizontal locations in a first direction. Individual insulating patterns in the insulating patterns 115 may be formed between the upper surface of the first impurity region 102 at the upper part of the substrate 100 and the first gate electrode 302, between adjacent gate electrodes along the first direction from the first gate electrode to the third gate electrodes 302, 304 and 306, and on the third gate electrode 306.

[0031] In an example embodiment, each insulating pattern 115 at corresponding multiple levels may extend in a second direction, and the multiple insulating patterns 115 may be separated from each other in a third direction through openings 270. The insulating patterns 115 may include oxides, such as silicon oxide.

[0032] In an example embodiment, the connection pattern 155 may be formed between two insulating patterns 115 at an intermediate level. For example, the lower surface of the connection pattern 155 may contact the upper surface of the lower one of the two insulating patterns 115, and the upper surface of the connection pattern 155 may contact the lower surface of the upper one of the two insulating patterns 115. In some embodiments, the thickness of the lower one of the two insulating patterns 115 may be greater than the thickness of the upper one of the two insulating patterns 115. The connection pattern 155 may include a material with low gap-filling properties or low step coverage properties, such as tetraethyl orthosilicate (TEOS), high-density plasma (HDP) oxide, etc.

[0033] The second structure may include a first structure and a pad (or solder pad) 250 sequentially stacked on a first impurity region 102 of a substrate 100, and may extend through the gate electrode structure, the connection pattern 155 and the insulating pattern structure in a first direction.

[0034] The first structure may include a channel 235 extending from the upper surface of the first impurity region 102 along a first direction, a charge storage structure 220 covering the outer wall of the channel 235, and a filling pattern 240 filling the internal space defined by the channel 235.

[0035] In an example embodiment, the channel 235 may have a hollow cylindrical shape or a cup shape, and the filling pattern 240 may fill the internal space formed by the channel 235. For example, the lower surface and sidewalls of the filling pattern 240 may be covered by the channel 235.

[0036] The channel 235 may include, for example, crystalline silicon, and the filling pattern 240 may include oxides, such as silicon oxide.

[0037] In an example embodiment, a plurality of channels 235 may be formed in each of the second and third directions to define a channel array.

[0038] In an example embodiment, the charge storage structure 220 covering the outer wall of the channel 235 may have a cup-shaped form with an open central bottom. The charge storage structure 220 may include a tunnel insulation pattern 210, a charge storage pattern 200, and a first barrier pattern 190 sequentially stacked in a horizontal direction from the outer wall of the channel 235. For example, the tunnel insulation pattern 210 may be formed on the outer wall of the channel 235, the charge storage pattern 200 may be formed on the outer wall of the tunnel insulation pattern 210, and the first barrier pattern 190 may be formed on the outer wall of the charge storage pattern 200.

[0039] As used herein, the term “bottom” when used in conjunction with a structure, pattern and / or layer can refer to the portion of the structure, pattern and / or layer closest to the substrate 100, and the term “top” can refer to the portion of the structure, pattern and / or layer furthest from the substrate 100.

[0040] The tunnel insulating pattern 210 and the first barrier pattern 190 may include oxides, such as silicon oxide. The charge storage pattern 200 may include nitrides, such as silicon nitride.

[0041] The first structure may have a cylindrical shape extending in a first direction from the upper surface of the first impurity region 102 at the upper part of the substrate 100, and the second structure including the first structure and the pad 250 may also have a cylindrical shape. For example, each of the first and second structures will have a circular shape when viewed from above. The pad 250 may comprise crystalline silicon doped with impurities.

[0042] In an example embodiment, the channel 235 in the second structure may include a first portion 235a, a second portion 235b, and a third portion 235c that are in contact with each other, each of which may have sidewalls inclined relative to the upper surface of the substrate 100. The first portion 235a, the second portion 235b, and the third portion 235c may be materially continuous with each other. As used herein, the terms "material continuity" and "continuity in material" may refer to structures, patterns, and / or layers that are formed simultaneously and are made of the same material without any interruption in the continuity of the material forming them. As an example, a structure, pattern, and / or layer that is "materially continuous" or "continuous in material" may be a homogeneous, monolithic (single) structure.

[0043] In an example embodiment, the first portion 235a of the channel 235 may have a first width W1 that gradually increases upward in a first direction, the second portion 235b of the channel 235 may have a second width W2 that gradually decreases upward in the first direction, and the third portion 235c of the channel 235 may have a third width W3 that gradually increases upward in the first direction. When viewed in cross-section, each of the first width W1, the second width W2, and the third width W3 may be the distance between the outer walls of the first portion 235a, the second portion 235b, and the third portion 235c, respectively. For example, the first width W1, the second width W2, and the third width W3 may correspond to the diameters of the respective first portion 235a, the second portion 235b, and the third portion 235c. In some embodiments, the maximum value of the first width W1 may be equal to the maximum value of the second width W2, and the minimum value of the third width W3 may be equal to the minimum value of the second width W2.

[0044] In an example embodiment, the sidewalls of each of the first to third portions 235a, 235b and 235c of the channel 235 may have a constant slope relative to the upper surface of the substrate 100.

[0045] In an example embodiment, the upper portion of the first portion 235a of the channel 235 may be covered by an insulating pattern 115, and the lower portions of the second portion 235b and the third portion 235c of the channel 235 may be covered by a connecting pattern 155.

[0046] A contact plug 350 may be formed on the upper surface of the pad 250, and a bit line 370 may be formed on the upper surface of the contact plug 350. The contact plug 350 may extend through the first insulating intermediate layer 260 and the second insulating intermediate layer 340 to contact the upper surface of the pad 250, and the bit line 370 may extend through the third insulating intermediate layer 360 to contact the upper surface of the contact plug 350.

[0047] The contact plug 350 and bit line 370 may include metals (e.g., copper, aluminum, tungsten, titanium, tantalum, etc.) and / or metal nitrides (e.g., titanium nitride, tantalum nitride, tungsten nitride, etc.), and the first to third insulating intermediate layers 260, 340 and 360 may include oxides, such as silicon oxide.

[0048] The second barrier layer 290 may be formed on the upper and lower surfaces and a portion of the sidewalls of each of the gate electrodes 302, 304 and 306, as well as on the sidewalls of each insulating pattern 115. The second barrier layer 290 may contact the sidewalls of the charge storage structure 220.

[0049] Figures 3 to 14 These are plan views and cross-sectional views illustrating a method of manufacturing a vertical memory device according to an exemplary embodiment. Specifically, Figure 4 , Figure 7 and Figure 11 It's a floor plan. Figure 3 , Figures 5 to 6 , Figures 8 to 10 and Figures 12 to 14 These are sectional views taken along line AA′ of the corresponding plan view.

[0050] Reference Figure 3 A first impurity region 102 can be formed at the upper part of the substrate 100, and an insulating layer 110 and a first sacrificial layer 120 can be alternately and repeatedly formed on the first impurity region 102 to form a lower mold.

[0051] The first impurity region 102 can be formed by doping carbon or n-type or p-type impurities into the upper part of the substrate 100.

[0052] Figure 3 The diagram shows a lower mold comprising insulating layers 110 at seven levels and first sacrificial layers 120 at six levels; however, the inventive concept is not limited thereto. The uppermost of the insulating layers 110 may have a greater thickness than the insulating layers 110 at the lower levels.

[0053] The insulating layer 110 and the first sacrificial layer 120 can be formed by processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD). The insulating layer 110 may include oxides, such as silicon oxide, and the first sacrificial layer 120 may include nitrides, such as silicon nitride.

[0054] Reference Figure 4 and Figure 5 The first channel hole 130 can be formed through the lower mold to expose the first impurity region 102 at the upper part of the substrate 100, and a first barrier pattern 140 can be formed on the sidewall and bottom of the first channel hole 130.

[0055] For example, a photoresist pattern (not shown) can be formed on the uppermost one of the insulating layers 110 of the lower mold, and the photoresist pattern can be used as an etching mask to etch the insulating layer 110 and the first sacrificial layer 120 of the lower mold to form a first channel hole 130 exposing the upper surface of the first impurity region 102. In an example embodiment, a plurality of first channel holes 130 can be formed in each of the second and third directions.

[0056] In addition, the first barrier layer can be formed on the sidewalls and bottom of the first channel hole 130 and on the upper surface of the uppermost one of the insulating layers 110. A portion of the upper surface of the uppermost one of the insulating layers can be removed by an anisotropic etching process to form the first barrier pattern 140.

[0057] In an example embodiment, the first impurity region 102 can serve as an etch stop layer during the etching process for forming the first channel via 130. For example, impurities can be implanted into the upper portion of the silicon-complementing substrate 100 to increase etch selectivity relative to the insulating layer 110 and the first sacrificial layer 120 comprising, for example, silicon oxide and silicon nitride. Therefore, during the etching process for forming the first channel via 130, a groove may not be formed on the substrate 100, and the first channel via 130 may have a uniform depth.

[0058] However, in some cases, the process of forming the first impurity region 102 may not be performed and may be skipped.

[0059] In the example embodiment, due to the general characteristics of the etching process, the width of each first channel hole 130 can gradually decrease from its top to its bottom. For example, the sidewalls of each first channel hole 130 may not be substantially perpendicular to the upper surface of the substrate 100, but rather inclined relative to the upper surface of the substrate 100. Therefore, the bottom of each first channel hole 130 may have a fourth width W4 in a horizontal direction substantially parallel to the upper surface of the substrate 100, and the top of each first channel hole 130 may have a fifth width W5 in a horizontal direction greater than the fourth width W4. The bottom of the first channel hole 130 may be the portion of the first channel hole 130 closest to the substrate 100, and the top of the first channel hole 130 may be the portion of the first channel hole 130 furthest from the substrate 100.

[0060] In an example embodiment, the first barrier pattern 140 may include a metal nitride, such as titanium nitride. In another example embodiment, the first barrier pattern 140 may include a nitride (such as silicon nitride) or polysilicon.

[0061] Reference Figure 6 A connecting layer 150 can be formed on the uppermost one of the insulating layers 110 of the lower mold, and the upper part of the connecting layer 150 can be planarized.

[0062] In an example embodiment, the interconnect layer 150 may include a material with low gap-filling properties or low step coverage properties, such as TEOS, HDP oxide, etc. Therefore, the first channel via 130 may not be filled with the interconnect layer 150, but a space may be formed in the first channel via 130 for connection thereto. For example, a space may be formed above the first channel via 130, such that the space is formed in the lower portion of the interconnect layer 150. The interconnect layer 150 may not be formed in the first channel via 130 and may not include, for example, crystalline silicon, so the substrate 100 will not warp due to the interconnect layer 150.

[0063] In the following text, each first channel hole 130 and the space thereon may be referred to as the first gap 160.

[0064] In an example embodiment, the upper surface of the first gap 160, which is higher than the upper surface of the uppermost one of the insulating layers 110, may be inclined relative to the upper surface of the substrate 100, so that the upper part of the first gap 160 may have a conical shape.

[0065] Reference Figure 7 and Figure 8 The insulating layer 110 and the first sacrificial layer 120 can be stacked alternately and repeatedly on the connecting layer 150 to form a first upper mold, and a second channel hole 170 can be formed through the first upper mold and the connecting layer 150 to expose the first gap 160.

[0066] Specifically, a photoresist pattern (not shown) can be formed on the uppermost one of the insulating layers 110 of the first upper mold. The photoresist pattern can be used as an etching mask to etch the insulating layer 110, the first sacrificial layer 120, and the connecting layer 150 of the first upper mold to form a second channel hole 170 exposing the first gap 160. Since a plurality of first channel holes 130 are formed in each of the second and third directions, a plurality of second channel holes 170 can also be formed in each of the second and third directions.

[0067] The first barrier pattern 140 can be formed on the sidewall of the first channel hole 130, so that the insulating layer 110 and the first sacrificial layer 120 of the lower mold will not be damaged during the etching process of the upper mold. However, the connecting layer 150 cannot be formed in the first channel hole 130, so the possibility of damage to the insulating layer 110 and the first sacrificial layer 120 of the lower mold during the etching process is low. Therefore, in some embodiments, the first barrier pattern 140 may not be formed on the sidewall and bottom of the first channel hole 130.

[0068] Furthermore, the connector layer 150 is not formed in the first channel hole 130, so the additional etching process for removing the connector layer 150 can be omitted. Therefore, the barrier pattern used to protect the insulating layer 110 and the first sacrificial layer 120 of the first upper mold during the etching process can be omitted on the sidewall of the second channel hole 170.

[0069] Similar to the first channel hole 130, due to the general characteristics of the etching process, the second channel hole 170 can also have a width that gradually decreases from its top to its bottom. The sidewalls of the second channel hole 170 may not be substantially perpendicular to the upper surface of the substrate 100, but rather inclined relative to the upper surface of the substrate 100. Therefore, the bottom of the second channel hole 170 can have a sixth width W6 in the horizontal direction, and the top of the second channel hole 170 can have a seventh width W7 in the horizontal direction that is greater than the sixth width W6. In the example embodiment, the seventh width W7 can be substantially equal to the fifth width W5, therefore the sixth width W6 can be less than the fifth width W5.

[0070] In the following text, the first gap 160 and the second channel hole 170 connected thereto may be referred to as the third channel hole 180.

[0071] Reference Figure 9 After removing the first barrier pattern 140 to expose the upper surface of the first impurity region 102, a charge storage structure 220 can be formed on the sidewall of the third channel hole 180 and a portion of the exposed upper surface of the first impurity region 102. A channel layer 230 can be formed on the uppermost of the charge storage structure 220, the portion of the exposed upper surface of the first impurity region 102, and the insulating layer 110 of the first upper mold.

[0072] For example, a charge storage structure layer and a second sacrificial layer may be sequentially formed on the sidewall of the third channel hole 180, the exposed upper surface of the first impurity region 102, and the uppermost surface of the insulating layer 110 of the first upper mold. Then, a first spacer layer (not shown) may be formed on the second sacrificial layer, and the first spacer layer may be anisotropically etched to form the first spacer (not shown) only on the sidewall of the third channel hole 180.

[0073] The first spacer can be used as an etching mask to etch the second sacrificial layer and the charge storage structure layer to form a second sacrificial pattern (not shown) and a charge storage structure 220 with cup-shaped bottoms that are open on the upper surface of the first impurity region 102. The exposed upper portion of the first impurity region 102 can also be partially removed.

[0074] After removing the first spacer and the second sacrificial pattern, a channel layer 230 can be formed on the uppermost of the first impurity region 102, the charge storage structure 220, and the insulating layer 110 of the first upper mold.

[0075] In an example embodiment, the charge storage structure 220 may include a first barrier pattern 190, a charge storage pattern 200, and a tunnel insulating pattern 210 stacked sequentially. For example, the first barrier pattern 190, the charge storage pattern 200, and the tunnel insulating pattern 210 may each include silicon oxide, silicon nitride, and silicon oxide, respectively. The second sacrificial layer may include, for example, polysilicon, and the first spacer may include, for example, silicon oxide or silicon nitride.

[0076] The channel layer 230 may comprise polycrystalline silicon or amorphous silicon. When the channel layer 230 comprises amorphous silicon, it can be converted into crystalline silicon by heat generated during the processes that form other layers. Alternatively, a laser epitaxial growth (LEG) process or a solid-state epitaxial growth (SPE) process may be further performed, allowing the amorphous silicon to be converted into crystalline silicon.

[0077] Reference Figure 10 A filler layer can be formed on the channel layer 230 to fill the remaining portion of the third channel hole 180, and the filler layer and the channel layer 230 can be planarized until the upper surface of the uppermost one of the insulating layers 110 of the first upper mold is exposed, thereby forming a filler pattern 240 that fills the remaining portion of the third channel hole 180 and converting the channel layer 230 into a channel 235.

[0078] Therefore, the charge storage structure 220, the channel 235, and the filling pattern 240 can be sequentially stacked on the first impurity region 102 in the third channel aperture 180.

[0079] A first structure having a columnar shape can be formed by a channel 235 with an open bottom and a cup-shaped channel 235, a charge storage structure 220 covering the outer wall of the channel 235, and a filling pattern 240 filling the internal space formed by the inner wall of the channel 235.

[0080] The upper part of the first structure can be removed to form a groove, and a pad 250 can be formed to fill the groove.

[0081] In an example embodiment, pad 250 may include doped polycrystalline silicon or amorphous silicon, and when pad 250 includes amorphous silicon, a crystallization process may be further performed on it.

[0082] In the following text, the first structure and the pad 250 thereon may be referred to as the second structure.

[0083] Reference Figure 11 and Figure 12A first insulating intermediate layer 260 may be formed on the uppermost layer of insulating layer 110 and on pad 250, and an opening 270 may be formed through the first insulating intermediate layer 260, insulating layer 110, first sacrificial layer 120 and first impurity region 102. During the formation of opening 270, a portion of the substrate 100 located below the first impurity region 102 may also be partially removed.

[0084] In an example embodiment, the opening 270 may extend longitudinally in the second direction, and a plurality of openings 270 may be formed in the third direction.

[0085] When the opening 270 is formed, the insulating layer 110 can be transformed into an insulating pattern 115 that extends in the second direction, the first sacrificial layer 120 can be transformed into a first sacrificial pattern (not shown) that extends in the second direction, and the connecting layer 150 can be transformed into a connecting pattern 155 that extends in the second direction.

[0086] The first sacrificial pattern exposed by the opening 270 can be removed to form a second gap 280 between adjacent insulating patterns in the insulating pattern 115 at a corresponding level. A portion of the outer wall of the first blocking pattern 190 can be exposed by the second gap 280.

[0087] In an example embodiment, the first sacrificial pattern exposed by the opening 270 can be removed by a wet etching process using a solution comprising phosphoric acid or sulfuric acid.

[0088] Reference Figure 13 A second barrier layer 290 may be formed on the exposed outer wall of the first barrier pattern 190, the inner wall of the second gap 280, the surface of the insulating pattern 115, the upper surface of the substrate 100, and the upper surface of the first insulating intermediate layer 260. A gate electrode may be formed on the second barrier layer 290 to at least partially fill the second gap 280.

[0089] A gate electrode can be formed by forming a gate electrode layer on the second barrier layer 290 to fully fill the second gap 280, and by partially removing the gate electrode layer. In an example embodiment, the gate electrode layer can be partially removed by a wet etching process.

[0090] In an example embodiment, the second barrier layer 290 may include a metal oxide, such as aluminum oxide, hafnium oxide, zirconium oxide, etc. The gate electrode may include a gate conductive pattern and a gate barrier pattern covering the lower surface, upper surface, and sidewalls of the gate conductive pattern. The gate conductive pattern may include a low-resistance metal, such as tungsten, titanium, tantalum, etc., and the gate barrier pattern may include a metal nitride, such as titanium nitride, tantalum nitride, etc.

[0091] The gate electrode can extend in the second direction, and multiple gate electrodes can be formed in the third direction. For example, gate electrodes that can all extend in the second direction can be separated from each other by an opening 270 extending in the second direction.

[0092] In an example embodiment, gate electrodes may be formed at multiple levels spaced apart from each other along a first direction, and the gate electrodes at the multiple levels may form a gate electrode structure. The gate electrode structure may include at least one first gate electrode 302, a plurality of second gate electrodes 304, and at least one third gate electrode 306. The number of levels at which the first to third gate electrodes 302, 304, and 306 are formed may vary depending on the number of levels of the first sacrificial layer 120.

[0093] Figure 13 As shown, the first gate electrode 302 is formed at one horizontal position, the second gate electrode 304 is formed at nine horizontal positions, and the third gate electrode 306 is formed at two horizontal positions. However, the inventive concept is not limited to this.

[0094] In the example embodiment, the first gate electrode 302 can be used as a ground select line (GSL), the second gate electrode 304 can be used as a word line, and the third gate electrode 306 can be used as a string select line (SSL). Some of the second gate electrodes 304 adjacent to the first gate electrode 302 and / or the third gate electrode 306 can be used as dummy word lines.

[0095] Reference Figure 14 Impurities can be injected into the upper part of the substrate 100 through the portion of the second barrier layer 290 located at the bottom of the opening 270 to form a second impurity region 104. In an example embodiment, the impurities may include n-type impurities, such as phosphorus, arsenic, etc.

[0096] A second spacer layer can be formed on the second barrier layer 290, and the second spacer layer can be anisotropically etched to form a second spacer 320 on the sidewall of the opening 270, thereby exposing a portion of the second barrier layer 290 located on the second impurity region 104.

[0097] The portion of the second barrier layer 290 not covered by the second spacer 320 can be etched, and the portion of the second barrier layer 290 located on the upper surface of the first insulating intermediate layer 260 can also be removed. During the etching process, the portion of the second impurity region 104 located on the upper part of the substrate 100 can also be partially removed.

[0098] A conductive layer can be formed on the upper surface of the second impurity region 104, the second spacer 320, and the first insulating intermediate layer 260 to fill the remaining portion of the opening 270, and the conductive layer can be planarized until the upper surface of the first insulating intermediate layer 260 is exposed, thereby forming a common source line (CSL) 330.

[0099] In the example embodiment, CSL 330 may extend in a first direction and may also extend in a second direction. The lower surface of CSL 330 may be covered by the second impurity region 104.

[0100] Refer again Figure 1 , Figure 2A and Figure 2B After a second insulating intermediate layer 340 is formed on the first insulating intermediate layer 260, CSL 330, second spacer 320, and second barrier layer 290, a contact plug 350 can be formed through the first insulating intermediate layer 260 and the second insulating intermediate layer 340 to contact the upper surface of the pad 250. A third insulating intermediate layer 360 can be formed on the second insulating intermediate layer 340 and the contact plug 350, and a bit line 370 can be formed through the third insulating intermediate layer 360 to contact the upper surface of the contact plug 350.

[0101] In the example embodiment, bit line 370 may extend vertically upward in a third direction, and multiple bit lines 370 may be formed in a second direction.

[0102] The above process can be used to manufacture vertical memory devices.

[0103] As explained above, a first impurity region 102 can be formed on the upper part of the substrate 100. An insulating layer 110 and a first sacrificial layer 120 can be alternately and repeatedly stacked at multiple horizontal levels to form a lower mold. A first channel hole 130 can be formed through the lower mold to expose the first impurity region 102. The first impurity region 102 can serve as an etch stop layer, thus the first channel hole 130 can have a uniform depth.

[0104] A connection layer 150 with low gap-filling properties (e.g., TEOS) can be formed on the lower mold, so that the connection layer 150 is not formed in the first channel hole 130. Therefore, for example, a crystalline silicon layer is not formed in the first channel hole 130, thus preventing warping of the substrate 100.

[0105] The insulating layer 110 and the first sacrificial layer 120 can be alternately and repeatedly stacked at multiple horizontal levels on the connecting layer 150 to form a first upper mold. A second channel hole 170 can be formed through the first upper mold to expose the first channel hole 130. The connecting layer 150 is not formed in the first channel hole 130, therefore a barrier pattern for preventing damage to the first upper mold during the removal of the connecting layer 150 does not need to be formed on the sidewall of the second channel hole 170. Thus, the profile of the channel 235 on the sidewall of the third channel hole 180, which includes the first channel hole 130 and the second channel hole 170, can be prevented from being degraded due to the barrier pattern.

[0106] Figures 15A to 15E and Figure 16 This is a cross-sectional view showing a vertical memory device according to an example embodiment. Figures 15A to 15E and Figure 16 Each picture in the book is Figure 2A An enlarged sectional view of region X.

[0107] In addition to the shape of the channels and / or connection patterns, the vertical memory device can be... Figure 1 and Figure 2A The vertical memory devices are substantially the same or similar. Therefore, the same reference numerals denote the same elements, and their detailed descriptions are omitted here.

[0108] Reference Figure 15A and Figure 15B The sidewall of the second portion 235b of the channel 235 may have a slope relative to the upper surface of the base 100 that varies depending on its position.

[0109] For example, Figure 15A The sidewall of the second portion 235b of the channel 235 shown in the figure may have a slope that gradually decreases from its bottom to its top relative to the upper surface of the base 100. Figure 15B The sidewall of the second portion 235b of the channel 235 shown in the figure may have a slope that gradually increases from the bottom to the top relative to the upper surface of the base 100.

[0110] Figure 15A and 15B The shape of the second part 235b shown in the figure can be seen by referring to Figure 6 The shape of the space on the first channel hole 130 is determined during the formation of the shown connecting layer 150.

[0111] Reference Figure 15C The channel 235 may include only the first part 235a and the third part 235c, and may not include the second part 235b.

[0112] During the formation of the connecting layer 150, when the connecting layer 150 does not fill the first channel hole 130 but fills the space on the first channel hole 130, the channel 235, which includes only the first portion 235a and the third portion 235c, can be implemented.

[0113] Reference Figure 15D and Figure 15E The connecting pattern 155 may also be formed at the upper part of the first channel hole 130, and may therefore include a first protrusion 155a, the first protrusion 155a having a lower surface that is lower than the upper surface of the insulating pattern 115 below the connecting pattern 155.

[0114] exist Figure 15D In the middle, the first protrusion 155a of the connecting pattern 155 may be adjacent to and surround the second part 235b and the third part 235c of the channel 235.

[0115] exist Figure 15E In this case, the channel 235 may not include the second portion 235b, so the first protrusion 155a of the connecting pattern 155 may be adjacent to and surround the third portion 235c of the channel 235.

[0116] exist Figure 15D and Figure 15E In the charge storage structure 220, the first blocking pattern 190 may further include a second protrusion 190a, which may protrude upward from a portion of the first portion 235a of the channel 235 to cover the outer wall of the first protrusion 155a of the connecting pattern 155. For example, the second protrusion 190a of the first blocking pattern 190 of the charge storage structure 220 may protrude upward and not contact the outer wall of the channel 235.

[0117] Reference Figure 16 The second part 235b of the channel 235, located between its first part 235a and third part 235c, may be asymmetrical with respect to the vertical line.

[0118] An asymmetric second portion 235b of the channel 235 can be formed during the formation of the second channel hole 170 when the second channel hole 170 is not well aligned with the first channel hole 130 but is offset.

[0119] Figure 17A This is a cross-sectional view showing a vertical memory device according to an example embodiment. Figure 17B yes Figure 17A An enlarged sectional view of region X.

[0120] In addition to the shape of the channel, charge storage structure, and connection pattern, this vertical memory device can be coupled with... Figure 1 and Figures 2A to 2B The vertical memory devices are substantially the same or similar. Therefore, the same reference numerals denote the same elements, and their detailed descriptions are omitted here.

[0121] Reference Figure 17A and Figure 17B The channel 235 may include a first portion 235a, a third portion 235c, and a third protrusion 235d. For example, with Figure 1 and Figures 2A to 2B The channel 235 shown is different; the channel 235 may not include the second portion 235b, but may include the third protrusion 235d. The first portion 235a, the third portion 235c, and the third protrusion 235d may be materially continuous with each other.

[0122] In an example embodiment, the third protrusion 235d of the channel 235 may protrude upward from the upper surface of the first portion 235a of the channel 235, and the upper surface of the third protrusion 235d may be lower than the upper surface of the insulating pattern 115 below the connecting pattern 155. In an example embodiment, the width of the lower portion of the third portion 235c of the channel 235 may be smaller than the width of the upper portion of the first portion 235a.

[0123] In an example embodiment, the vertical memory device may include a first charge storage structure 222 and a second charge storage structure 224 stacked sequentially. The first charge storage structure 222 may include a tunnel insulation pattern 210, a charge storage pattern 200 and a first lower barrier pattern 192 stacked sequentially from the lower outer sidewall of the channel 235 in a horizontal direction substantially parallel to the upper surface of the substrate 100. The second charge storage structure 224 may include a tunnel insulation pattern 210, a charge storage pattern 200 and a first upper barrier pattern 194 stacked sequentially from the upper outer sidewall of the channel 235 in a horizontal direction.

[0124] For example, the tunnel insulation pattern 210 and the charge storage pattern 200 can be continuously formed in the first direction to cover the outer wall of the trench 235, and the first blocking pattern can be divided into a first lower blocking pattern 192 and a first upper blocking pattern 194, which can be disconnected from and separated from each other.

[0125] In an example embodiment, the first lower blocking pattern 192 may cover the outer sidewall of the third protrusion 235d of the channel 235, and the upper surface of the first lower blocking pattern 192 may be substantially coplanar with the upper surface of the insulating pattern 115 below the connecting pattern 155. The lower surface of the first upper blocking pattern 194 may be lower than the upper surface of the insulating pattern 115 below the connecting pattern 155.

[0126] The connecting pattern 155 may not be formed in the first channel hole 130; however, the connecting pattern 155 may completely fill the space on the first channel hole 130 (see...). Figure 6 ).

[0127] Figures 18 to 20 This is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to an example embodiment. The method may include, with reference to... Figures 3 to 14 as well as Figure 1 and Figures 2A to 2B The processes shown are substantially the same or similar, and their detailed descriptions are omitted here.

[0128] Reference Figure 18 It can be executed and referenced. Figures 3 to 6 The processes shown are basically the same or similar.

[0129] However, the first barrier pattern 140 may include polysilicon or silicon nitride instead of metal nitride.

[0130] Furthermore, the connecting layer 150 can fill the upper part of the first channel hole 130, so the upper surface of the first gap 160 can be lower than the upper surface of the first channel hole 130.

[0131] Reference Figure 19 It can be executed and referenced. Figure 7 and Figure 8 The processes shown are basically the same or similar.

[0132] However, the second channel hole 170 may not be connected to the first gap 160. For example, the second channel hole 170 may be formed as a portion extending through the connecting layer 150 into the first channel hole 130, and may not expose the first gap 160 below it.

[0133] After forming the second channel hole 170, a second barrier pattern 145 may be further formed on the sidewall of the second channel hole 170. The second barrier pattern 145 may include a material substantially the same as that of the first barrier pattern 140, such as polysilicon or silicon nitride.

[0134] Reference Figure 20 The portion of the connecting layer 150 exposed by the second channel hole 170 in the first channel hole 130 can be removed to form the third channel hole 180, and an oxidation process can be performed on the first barrier pattern 140 and the second barrier pattern 145.

[0135] Therefore, the first barrier pattern 140 and the second barrier pattern 145 may include oxides and may be converted into a first lower barrier pattern 192 and a first upper barrier pattern 194, respectively.

[0136] Executable and referenced Figure 9 The processes shown are substantially the same or similar, so that charge storage patterns 200 and tunnel insulating patterns 210 can be sequentially stacked on the sidewalls of the first lower barrier pattern 192, the sidewalls of the first upper barrier pattern 194, and a portion of the first impurity region 102, and a channel layer 230 can be formed on the uppermost of the tunnel insulating pattern 210, the portion of the first impurity region 102, and the insulating layer 110 of the first upper mold.

[0137] Reference Figure 17A and Figure 17B It can be executed and referenced. Figures 10 to 14 as well as Figure 1 and Figures 2A to 2B The processes shown are essentially the same or similar, thus completing the manufacture of the vertical memory device.

[0138] Figure 21 This is a cross-sectional view illustrating a vertical memory device according to an example embodiment. Apart from the shapes of the channels, charge storage structures, and connection patterns, this vertical memory device can be compared with a reference... Figure 1 and Figures 2A to 2B The vertical memory devices shown are substantially the same or similar. Therefore, the same reference numerals denote the same elements, and their detailed descriptions are omitted here.

[0139] Reference Figure 21 , Figure 1 and Figures 2A to 2B The channel 235 includes first to third portions 235a, 235b and 235c stacked sequentially along a first direction, while Figure 21 The channel 235 may also include a fourth portion 235e and a fifth portion 235f sequentially stacked on the third portion 235c. The first portion 235a, the second portion 235b, the third portion 235c, the fourth portion 235e, and the fifth portion 235f may be materially continuous with each other.

[0140] The fourth portion 235e and the fifth portion 235f of the channel 235 may have shapes similar to those of the second portion 235b and the third portion 235c, respectively. For example, the fourth portion 235e of the channel 235 may have a width that gradually decreases from its bottom to its top, and the fifth portion 235f of the channel 235 may have a width that gradually increases from its bottom to its top. Furthermore, the lower portions of the fourth portion 235e and the fifth portion 235f of the channel 235 may be surrounded by a connecting pattern 155.

[0141] Figure 21The diagram shows a channel 235 comprising a first portion 235a, a third portion 235c, and a fifth portion 235f, each having a width that gradually increases from its bottom to its top, and a second portion 235b and a fourth portion 235e, each having a width that gradually decreases from its bottom to its top. However, the inventive concept is not limited to this. For example, the channel 235 may include multiple portions, each having a width that gradually increases from its bottom to its top, and multiple portions, each having a width that gradually decreases from its bottom to its top.

[0142] Figure 22 and Figure 23 This is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to an example embodiment. The method may include, with reference to... Figures 3 to 14 as well as Figure 1 and Figures 2A to 2B The processes shown are substantially the same or similar, and their detailed descriptions are omitted here.

[0143] Reference Figure 22 It can be executed and referenced. Figures 3 to 8 The process shown is substantially the same or similar, and a third barrier pattern 147 can be formed on the sidewalls and bottom of the first gap 160 having the first barrier pattern 140 and on the sidewalls of the second channel hole 170.

[0144] The third barrier pattern 147 may include a material substantially the same as that of the first barrier pattern 140.

[0145] Executable and referenced Figures 6 to 8 The processes shown are substantially the same or similar, so that a second upper mold can be formed on a first upper mold, and a fourth channel hole can be formed through the second upper mold to expose the second channel hole 170.

[0146] In the following text, the first gap 160, the second channel hole 170 and the fourth channel hole, which are sequentially stacked and connected to each other in the first direction, may be referred to as the fifth channel hole 480.

[0147] Reference Figure 23 It can be executed and referenced. Figure 9 The processes shown are substantially the same or similar, thereby removing the first barrier pattern 140 and the third barrier pattern 147, and forming the charge storage structure 220 and the channel layer 230.

[0148] Refer again Figure 21 It can be executed and referenced. Figures 10 to 14 as well as Figure 1 and Figures 2A to 2B The processes shown are essentially the same or similar, thus completing the manufacture of the vertical memory device.

[0149] Figure 24 This is a cross-sectional view illustrating a vertical memory device according to an example embodiment. Besides the components, this vertical memory device can be compared with reference to... Figure 1 and Figures 2A to 2B The vertical memory devices shown are substantially the same or similar. Therefore, the same reference numerals denote the same elements, and their detailed descriptions are omitted here.

[0150] Reference Figure 24 The channel connection pattern 510 and the support layer 500 can be sequentially stacked between the upper surface of the substrate 100 and the lowermost one of the insulating patterns 115 of the lower mold, and can avoid forming the first impurity region 102.

[0151] The channel connection pattern 510 can directly contact the lower outer wall of the channel 235 to connect the channels 235 to each other. The charge storage structure 220 may not be formed on the lower outer wall of each channel 235, and the charge storage structure 220 may be divided into an upper part covering most of the outer wall of the channel 235 and a lower part covering the lower outer wall and bottom of the channel 235 located on the substrate 100.

[0152] The channel connection pattern 510 may include, for example, polysilicon doped with n-type impurities, and the support layer 500 may include undoped polysilicon or polysilicon doped with n-type impurities.

[0153] While exemplary embodiments have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A vertical memory device, the vertical memory device comprising: Gate electrodes, stacked on a substrate, are spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate; as well as A channel extending through the gate electrode, the channel comprising: The first part, wherein the first part has a first width at the top of the first part, the first width being the distance between the outer walls of the top of the first part; The second portion, located on and connected to the first portion, has sidewalls inclined relative to the upper surface of the base, such that the second portion has a second width that gradually decreases from the bottom to the top of the second portion and is the distance between the outer sidewalls of the second portion; and A third portion, located on and connected to the second portion, wherein the third portion has a third width at its bottom, the third width being the distance between the outer walls of the bottom of the third portion. Wherein, the first width at the top of the first portion is the same as the second width at the bottom of the second portion, and the second width at the top of the second portion is the same as the third width at the bottom of the third portion. The vertical memory device further includes a charge storage structure covering the outer wall of the channel. A portion of the charge storage structure protrudes upward, overlaps with the channel in a horizontal direction parallel to the upper surface of the substrate, and does not contact the outer wall of the channel.

2. The vertical memory device according to claim 1, wherein, The sidewall of the second portion of the channel has a constant slope relative to the upper surface of the substrate.

3. The vertical memory device according to claim 1, wherein, The sidewall of the second portion of the channel has a varying slope relative to the upper surface of the substrate.

4. The vertical memory device according to claim 1, wherein, Each of the first and third portions of the channel has a sidewall that is inclined relative to the upper surface of the substrate, the width of the sidewall of the first portion of the channel gradually increases from the bottom to the top of the first portion and is the distance between the outer sidewalls of the first portion, and the width of the sidewall of the third portion of the channel gradually increases from the bottom to the top of the third portion and is the distance between the outer sidewalls of the third portion.

5. The vertical memory device according to claim 1, wherein, The lower part of the third portion and the second portion of the channel are surrounded by a connecting pattern, and the upper part of the first portion of the channel is surrounded by an insulating pattern.

6. The vertical memory device according to claim 5, wherein, The connection pattern includes tetraethyl orthosilicate or high-density plasma oxide.

7. The vertical memory device according to claim 5, wherein, A portion of the lower surface of the connecting pattern is lower than the upper surface of the insulating pattern.

8. The vertical memory device according to claim 7, wherein, A portion of the lower surface of the connecting pattern is adjacent to the lower portion of the third portion of the channel and the second portion.

9. The vertical memory device according to claim 1, wherein, The trench also includes: A fourth portion, located on and connected to the third portion, having sidewalls inclined relative to the upper surface of the base, such that the fourth portion has a width that gradually decreases from the bottom to the top of the fourth portion and is the distance between the outer sidewalls of the fourth portion; and The fifth part is located on and connected to the fourth part.

10. The vertical memory device according to claim 9, wherein, The fifth portion has sidewalls that are inclined relative to the upper surface of the base, such that the fifth portion has a width that gradually increases from the bottom of the fifth portion toward the top and is the distance between the outer sidewalls of the fifth portion.

11. The vertical memory device according to claim 1, in, The channel has a cup-shaped form.

12. A vertical memory device, the vertical memory device comprising: Gate electrodes, stacked on a substrate, are spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate; as well as A channel extending through the gate electrode, the channel comprising: The first part has a first width that gradually increases from the bottom of the first part toward the top and is the distance between the outer walls of the first part; The second part, located on and connected to the first part, has a second width that gradually decreases from the bottom to the top of the second part and is the distance between the outer walls of the second part; and The third part, located on and connected to the second part, has a third width that gradually increases from the bottom to the top of the third part and is the distance between the outer walls of the third part. Wherein, the first width at the top of the first portion is the same as the second width at the bottom of the second portion, and the second width at the top of the second portion is the same as the third width at the bottom of the third portion. The vertical memory device further includes a charge storage structure covering the outer wall of the channel. A portion of the charge storage structure protrudes upward, overlaps with the channel in a horizontal direction parallel to the upper surface of the substrate, and does not contact the outer wall of the channel.

13. The vertical memory device according to claim 12, wherein, The lower portion of the third part of the channel and the second part are surrounded by a connecting pattern, and the upper portion of the first part of the channel is surrounded by an insulating pattern.

14. The vertical memory device according to claim 13, wherein, The connection pattern includes tetraethyl orthosilicate or high-density plasma oxide.

15. The vertical memory device according to claim 12, wherein, The trench also includes: A fourth portion, located on and connected to the third portion, the fourth portion having a width that gradually decreases from the bottom to the top of the fourth portion and is the width of the distance between the outer walls of the fourth portion; and The fifth part, located on and connected to the fourth part, has a width that gradually increases from the bottom to the top of the fifth part and is the distance between the outer walls of the fifth part.

16. A vertical memory device, the vertical memory device comprising: Gate electrodes, stacked on a substrate, are spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate; as well as A channel extending through the gate electrode, the channel comprising: The first part has a width that gradually increases from the bottom of the first part toward the top and is the distance between the outer walls of the first part; A protrusion that projects upward from the upper surface of the first portion; and The second part is located on and connected to the first part, and overlaps the protrusion in the horizontal direction. The second part has a width that gradually increases from the bottom to the top of the second part and is the distance between the outer walls of the second part, wherein the width of the lower part of the second part is smaller than the width of the upper part of the first part.

17. The vertical memory device of claim 16, further comprising a charge storage structure covering the outer wall of the channel.

18. The vertical memory device according to claim 17, wherein, The charge storage structure includes tunnel insulation patterns, charge storage patterns, and barrier patterns sequentially stacked along a horizontal direction parallel to the upper surface of the substrate from the outer sidewall of the trench. The blocking pattern includes: The lower portion covers the first portion of the channel and the protrusion; and The upper part covers the outer wall of the second portion of the channel.

19. The vertical memory device according to claim 18, in, Each of the tunnel insulation pattern and the charge storage pattern is continuously formed on the outer wall of the trench, and The lower and upper parts of the blocking pattern are disconnected and separated from each other.

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