Non-volatile memory device and operation method thereof

Abstract

A nonvolatile memory device and an operation method thereof are disclosed. An operation method of a nonvolatile memory device includes: receiving a first DQ signal representing a first data bit from an external device through a first DQ line, and receiving a second DQ signal representing a second data bit from an external device through a second DQ line; and programming a first memory cell corresponding to the first DQ line and a second memory cell corresponding to the second DQ line, so that the first memory cell has any one of an erased state and a first programming state based on the first DQ signal, and the second memory cell has any one of an erased state and a second programming state based on the second DQ signal. The lower limit value of the threshold voltage distribution corresponding to the second programming state is higher than the lower limit value of the threshold voltage distribution corresponding to the first programming state.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2018-0163035 filed on December 17, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the inventive concepts described herein relate to a semiconductor memory, and more particularly, to a nonvolatile memory device and an operating method thereof. Background Art

[0003] Semiconductor memory devices are classified into volatile memory devices (such as static random access memory (SRAM) or dynamic random access memory (DRAM)) or non-volatile memory devices (such as flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM)), wherein in volatile memory devices, stored data disappears when power is turned off, while in non-volatile memory devices, stored data is retained even when power is turned off.

[0004] The flash memory device is configured to store data by changing the threshold voltage of the memory cell. In the case where the difference between the threshold voltages of the memory cells for determining data is small, the error of the data read from the memory cells increases. Summary of the invention

[0005] Embodiments of the inventive concept provide a nonvolatile memory device having improved performance and improved reliability by differently setting error margins of memory cells included in the nonvolatile memory device based on signal lines, and an operating method thereof.

[0006] According to an example embodiment, an operation method of a nonvolatile memory device includes: receiving a first DQ signal representing a first data bit from an external device through a first DQ line, and receiving a second DQ signal representing a second data bit from an external device through a second DQ line; and programming a first memory cell corresponding to the first DQ line and a second memory cell corresponding to the second DQ line so that the first memory cell has any one of an erased state and a first programmed state based on the first DQ signal, and the second memory cell has any one of an erased state and a second programmed state based on the second DQ signal. A lower limit value of a threshold voltage distribution corresponding to the second programmed state is higher than a lower limit value of a threshold voltage distribution corresponding to the first programmed state.

[0007] According to example embodiments, a nonvolatile memory device includes: a first memory cell connected to a first word line and a first bit line; a second memory cell connected to the first word line and the second bit line; an input / output circuit that outputs a first data bit corresponding to a first DQ signal received on a first DQ line from an external device through a first data line, and outputs a second data bit corresponding to a second DQ signal received on a second DQ line from the external device through a second data line; a first page buffer connected to the first bit line and the first data line, and stores a first latch value based on the first data bit received through the first data line and a first DQ identifier of the first DQ line; and a second page buffer connected to the second bit line and the second data line, and stores a second latch value based on the second data bit received through the second data line and the second DQ identifier of the second DQ line.

[0008] According to an example embodiment, an operating method of a nonvolatile memory device includes: receiving a first DQ signal representing first data from an external device through a first DQ line, receiving a second DQ signal representing second data from the external device through a second DQ line; and programming a plurality of first memory cells corresponding to the first DQ line based on the first data, respectively, and programming a plurality of second memory cells corresponding to the second DQ line based on the second data, respectively. The error margins of the plurality of second memory cells are greater than the error margins of the plurality of first memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the inventive concept will become apparent by describing in detail example embodiments of the inventive concept with reference to the attached drawings.

[0010] Figure 1 is a block diagram illustrating a storage device according to an embodiment of the inventive concept.

[0011] Figure 2 It is shown Figure 1 A flowchart of a method for operating a non-volatile memory device.

[0012] Figure 3 It is shown Figure 1 A block diagram of a non-volatile memory device.

[0013] Figure 4 It is shown in detail Figure 3 A diagram of a partial configuration of a nonvolatile memory device.

[0014] Figure 5 is shown for describing Figure 4 Graph showing threshold voltage distribution of memory cells in a programming operation of a nonvolatile memory device.

[0015] Figure 6 It is used to describe in detail Figure 4 Flowchart of a programming operation of a nonvolatile memory device.

[0016] Fig. 7A and Figure 7B It is used to describe in detail Figure 6 An exemplary diagram of a flowchart of FIG.

[0017] Figure 8 It is shown Figure 4 Schematic diagram of values ​​of a set of data latches in a nonvolatile memory device according to bits received through each DQ line.

[0018] Fig. 9 It shows that according to Figure 8 Graph showing threshold voltage distribution of memory cells programmed by a page buffer setting method.

[0019] Fig.10 It is shown Figure 1 A block diagram of an exemplary non-volatile memory device.

[0020] Fig.11 is shown according to some examples Figure 2 Flowchart of the operation of a nonvolatile memory device.

[0021] Fig.12 Is used to describe Fig.11 An illustration of the operation of a flowchart.

[0022] Fig.13A and Fig. 13B It shows that according to Fig.11 A flow chart of a distribution diagram of threshold voltage distributions of memory cells programmed by a programmable logic circuit.

[0023] Fig.14 is shown according to some examples Figure 2 Flowchart of the operation of a nonvolatile memory device.

[0024] Fig.15 and Fig.16 Is used to describe Fig.14 An illustration of the operation of a flowchart.

[0025] Fig.17 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the inventive concept.

[0026] Fig.18 It is shown Fig.17 Flowchart of a DQ mapping operation of a nonvolatile memory device.

[0027] Fig.19A and Fig.19B Is used to describe Fig.18FIG. 1 is a flowchart of a DQ mapping operation.

[0028] FIG. 20A to FIG. 20D is a block diagram illustrating a memory device to which a nonvolatile memory module according to an embodiment of the inventive concept is applied.

[0029] Fig.21 is a block diagram illustrating a mobile system to which a nonvolatile memory device according to an embodiment of the inventive concept is applied. DETAILED DESCRIPTION

[0030] Below, embodiments of the inventive concept may be described in detail and clearly to the extent that a person having ordinary skill in the art can easily implement the inventive concept.

[0031] Figure 1 is a block diagram showing a storage device according to an embodiment of the inventive concept. Figure 1 , the memory device 10 may include a memory controller 11 and a nonvolatile memory device 100 .

[0032] The memory controller 11 may be configured to control the nonvolatile memory device 100. For example, the memory controller 11 may provide a control signal CTRL to the nonvolatile memory device 100, and may exchange data with the nonvolatile memory device 100 through a plurality of signal lines (hereinafter referred to as “DQ lines”) DQ1 to DQn.

[0033] In response to the control signal CTRL from the memory controller 11, the nonvolatile memory device 100 may store data provided through the plurality of DQ lines DQ1 to DQn, or may output data through the plurality of DQ lines DQ1 to DQn. In an example embodiment, the nonvolatile memory device 100 may be, for example, a NAND flash memory device in the form of a semiconductor chip formed on a die from a wafer, a stack of such semiconductor chips, or a semiconductor package including one or more semiconductor chips formed on a package substrate, may receive information (such as a command, an address, etc.) through the plurality of DQ lines DQ1 to DQn, and may identify the type of the signal (e.g., a command, an address, data, etc.) received through the plurality of DQ lines DQ1 to DQn based on the control signal CTRL. However, the inventive concept is not limited thereto.

[0034] In an example embodiment, the nonvolatile memory device 100 according to an embodiment of the inventive concept may perform a programming operation so that a plurality of DQ lines DQ1 to DQn have different error margins. For example, the nonvolatile memory device 100 may program first data received through the first DQ line DQ1 to have a first error margin, and may program second data received through the second DQ line DQ2 to have a second error margin different from the first error margin. The nonvolatile memory device 100 and an operating method thereof according to an embodiment of the inventive concept will be described with reference to the accompanying drawings.

[0035] Figure 2 It is shown Figure 1 Flow chart of a method for operating a nonvolatile memory device. Figure 1 and Figure 2 In operation S101, the nonvolatile memory device 100 may receive data from the plurality of DQ lines DQ1 to DQn. For example, in order to store data in the nonvolatile memory device 100, the memory controller 11 may transmit the data to the nonvolatile memory device 100 through the plurality of DQ lines DQ1 to DQn. The nonvolatile memory device 100 may identify the data received through the plurality of DQ lines DQ1 to DQn based on a control signal CTRL (e.g., a data strobe signal DQS).

[0036] In operation S102, the nonvolatile memory device 100 may perform a programming operation based on the received data and the DQ identifier DQID for each DQ line. For example, the nonvolatile memory device 100 may perform a programming operation on the received first data based on the DQ identifier (e.g., DQID1) for the first DQ line DQ1 and the first data received through the first DQ line DQ1, and may perform a programming operation on the received second data based on the DQ identifier (e.g., DQID2) for the second DQ line DQ2 and the second data received through the second DQ line DQ2. These DQ identifiers correspond to and include data associated with their respective DQ lines, and may optionally be referred to as DQ line codes. In this case, even if the first data and the second data have the same bit value, the error margins of the first data and the second data may be different. Alternatively, even if the first data and the second data have the same bit value, the threshold voltage distribution (or programming state) of the memory cell in which the first data is stored may be different from the threshold voltage distribution (or programming state) of the memory cell in which the second data is stored.

[0037] For example, according to an embodiment of the inventive concept, the nonvolatile memory device 100 may perform a program operation based on received data and the DQ identifier DQID, and thus, error margins of the plurality of DQ lines DQ1 to DQn may be different.

[0038] Figure 3 It is shown Figure 1 A block diagram of a nonvolatile memory device is shown. Figure 1 and Figure 3 , the nonvolatile memory device 100 may include a memory cell array 110 , an address decoder 120 , a page buffer circuit 130 , an input / output circuit (I / O circuit) 140 , and a control logic circuit 150 .

[0039] The memory cell array 110 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings, each of the plurality of cell strings including a plurality of cell transistors connected in series between a bit line and a common source line. The plurality of cell transistors may be connected to a string selection line SSL, a word line WL, and a ground selection line GSL. Each of the plurality of cell transistors (e.g., memory cells) may be configured to store at least 1 bit of data by a programming operation of the nonvolatile memory device 100. In an example embodiment, each of the plurality of memory cells may be programmed to have a different error margin for each corresponding DQ line.

[0040] The address decoder 120 may be connected to the memory cell array 110 through the string selection lines SSL, the word lines WL, and the ground selection lines GSL. The address decoder 120 may decode the address ADDR received from the memory controller 11, and may individually control the voltages of the string selection lines SSL, the word lines WL, and the ground selection lines GSL based on the decoded addresses.

[0041] The page buffer circuit 130 may be connected to the memory cell array 110 through a plurality of bit lines BL. The page buffer circuit 130 may be configured to temporarily store data read from the memory cell array 110 or data provided from the input / output circuit 140. Figure 3 , but the page buffer circuit 130 may include a plurality of page buffers respectively corresponding to the plurality of bit lines BL. Each of the plurality of page buffers may include a data latch or a cache latch configured to temporarily store data.

[0042] The input / output circuit 140 may be connected to the page buffer circuit 130 through a plurality of data lines DL. The plurality of data lines DL may be respectively connected to the plurality of page buffers, or may respectively correspond to the plurality of page buffers. The input / output circuit 140 may exchange data with the memory controller 11 through a plurality of DQ lines DQ. In an example embodiment, the input / output circuit 140 may provide data received from any one of the plurality of DQ lines DQ1 to DQn to one or more of the plurality of data lines DL. For example, one of the plurality of DQ lines DQ1 to DQn may correspond to one or more of the plurality of data lines DL.

[0043] The control logic circuit 150 may control the overall operation of the nonvolatile memory device 100. For example, the control logic circuit 150 may control the address decoder 120, the page buffer circuit 130, and the input / output circuit 140 in response to a control signal CTRL from the memory controller 11.

[0044] Figure 4 It is shown in detail Figure 3 For the sake of simplicity and ease of description, the following is a diagram of a partial configuration of a non-volatile memory device. Figure 4 In the embodiment of the present invention, a part of the configuration of the nonvolatile memory device 100 is omitted. Below, in order to easily describe the embodiment of the inventive concept, it is assumed that the nonvolatile memory device 100 exchanges data with the memory controller 11 through the first DQ line DQ1 to the fourth DQ line DQ4. However, the inventive concept is not limited thereto. For example, the number of DQ lines may be changed variously.

[0045] Reference Figure 1 , Figure 3 and Figure 4 , the memory cell array 110 may include a plurality of memory cells MC1 to MC4. The plurality of memory cells MC1 to MC4 may be connected to one word line WL. Each of the plurality of memory cells MC1 to MC4 may be connected to a corresponding bit line. In an example embodiment, the plurality of bit lines may be divided into first to fourth bit line groups BLG1 to BLG4.

[0046] The page buffer circuit 130 may include a plurality of page buffers PB11 to PB4d. Each of the plurality of page buffers PB11 to PB4d may be connected to a corresponding bit line. For example, the bit lines of the first bit line group BLG1 may be connected to the page buffers PB11 to PB1a, respectively. The bit lines of the second bit line group BLG2 may be connected to the page buffers PB21 to PB2b, respectively. The bit lines of the third bit line group BLG3 may be connected to the page buffers PB31 to PB3c, respectively. The bit lines of the fourth bit line group BLG4 may be connected to the page buffers PB41 to PB4d, respectively.

[0047] Each of the page buffers PB11 to PB4d may temporarily store data to be stored in a memory cell connected to a corresponding bit line. For example, the page buffers PB11 to PB1a connected to the first bit line group BLG1 may temporarily store data to be stored in the first memory cell MC1 connected to the first bit line group BLG1. Similarly, the page buffers PB21 to PB2b connected to the second bit line group BLG2 may temporarily store data to be stored in the second memory cell MC2 connected to the second bit line group BLG2, the page buffers PB31 to PB3c connected to the third bit line group BLG3 may temporarily store data to be stored in the third memory cell MC3 connected to the third bit line group BLG3, and the page buffers PB41 to PB4d connected to the fourth bit line group BLG4 may temporarily store data to be stored in the fourth memory cell MC4 connected to the fourth bit line group BLG4.

[0048] The input / output circuit 140 may provide data received through the first to fourth DQ lines DQ1 to DQ4 to corresponding page buffers PB11 to PB4d through corresponding data lines. For example, the input / output circuit 140 may provide data received through the first DQ line DQ1 to page buffers PB11 to PB1a associated with the first data line group DLG1, and may provide data received through the second DQ line DQ2 to page buffers PB21 to PB2b associated with the second data line group DLG2. Similarly, the input / output circuit 140 may provide data received through the third DQ line DQ3 to page buffers PB31 to PB3c associated with the third data line group DLG3, and may provide data received through the fourth DQ line DQ4 to page buffers PB41 to PB4d associated with the fourth data line group DLG4.

[0049] As described above, the first to fourth DQ lines DQ1 to DQ4 may correspond to the first to fourth data line groups DLG1 to DLG4, respectively, the first to fourth data line groups DLG1 to DLG4 may be respectively connected to page buffers PB11 to PB1a, PB21 to PB2b, PB31 to PB3c and PB41 to PB4d connected to the first to fourth bit line groups BLG1 to BLG4, and the first to fourth bit line groups BLG1 to BLG4 may be respectively connected to the first to fourth memory cells MC1 to MC4.

[0050] Below, for the convenience of description, expressions such as “data line corresponding to a specific DQ line”, “page buffer corresponding to a specific DQ line”, “bit line corresponding to a specific DQ line”, “memory cell corresponding to a specific DQ line”, etc. may be used, and the meaning of such expressions may be determined based on the connection relationship between the components disclosed in the specification.

[0051] Figure 5 is shown for describing Figure 4 FIG. 1 is a diagram showing a threshold voltage distribution of a memory cell in a programming operation of a nonvolatile memory device. Figure 4 and Figure 5 , the nonvolatile memory device 100 may perform a program operation on data received from the first to fourth DQ lines DQ1 to DQ4 so as to have different error margins.

[0052] For example, data received through the first DQ line DQ1 may be stored in the first memory cell MC1 corresponding to the first DQ line DQ1, data received through the second DQ line DQ2 may be stored in the second memory cell MC2 corresponding to the second DQ line DQ2, data received through the third DQ line DQ3 may be stored in the third memory cell MC3 corresponding to the third DQ line DQ3, and data received through the fourth DQ line DQ4 may be stored in the fourth memory cell MC4 corresponding to the fourth DQ line DQ4.

[0053] In this case, each of the first to fourth memory cells MC1 to MC4 may be configured to store one bit. Figure 5 As shown in , the first memory cell MC1 can be programmed to have any one of the erased state "E" and the first programming state P1 based on the data received through the first DQ line DQ1, the second memory cell MC2 can be programmed to have any one of the erased state "E" and the second programming state P2 based on the data received through the second DQ line DQ2, the third memory cell MC3 can be programmed to have any one of the erased state "E" and the third programming state P3 based on the data received through the third DQ line DQ3, and the fourth memory cell MC4 can be programmed to have any one of the erased state "E" and the fourth programming state P4 based on the data received through the fourth DQ line DQ4.

[0054] For example, each of the first to fourth memory cells MC1 to MC4 may store one bit and may have different error margins based on corresponding DQ lines. Figure 5 As shown in , the first memory cell MC1 corresponding to the first DQ line DQ1 may have a first error margin EM1, and the second memory cell MC2 corresponding to the second DQ line DQ2 may have a second error margin EM2. Similarly, the third memory cell MC3 corresponding to the third DQ line DQ3 may have a third error margin EM3, and the fourth memory cell MC4 corresponding to the fourth DQ line DQ4 may have a fourth error margin EM4.

[0055] In one example embodiment, the error margin may indicate a difference between a lower limit value of a programming state (e.g., P1, P2, P3, or P4) and a read voltage VRD. In the case where the error margin is larger, the probability that an error exists in the result of a read operation using the read voltage VRD is lower. Figure 5 As shown in the example of , in some embodiments, different programming states P1, P2, P3, and P4 representing the same data state of different memory cells have different, non-overlapping threshold voltage distributions. In addition, the lower limit value of the threshold voltage distribution corresponding to a particular programming state is lower than the lower limit value of the threshold voltage distribution corresponding to a higher-level programming state. For example, the lower limit value of the threshold voltage distribution corresponding to the programming state "P1" is higher than the lower limit value (and upper limit value) of the threshold voltage distribution corresponding to the erased state "E", the lower limit value of the threshold voltage distribution corresponding to the programming state "P2" is higher than the lower limit value (and upper limit value) of the threshold voltage distribution corresponding to the programming state "P1", and so on.

[0056] For example, the nonvolatile memory device 100 according to an embodiment of the inventive concept can improve the reliability of data output through a specific DQ line by programming memory cells so as to have a different error margin for each DQ line. In this case, since the burden caused by a separate error correction operation is reduced, a nonvolatile memory device with improved performance and improved reliability is provided.

[0057] Figure 6 It is used to describe in detail Figure 4 Flowchart of a programming operation of a non-volatile memory device. In an example embodiment, it is assumed that a data bit "1" corresponds to a programming state of a memory cell and a data bit "0" corresponds to an erased state of the memory cell. However, the inventive concept is not limited thereto. For example, according to the bit ordering of the programming state of the memory cell, the above correspondence may be interchangeable.

[0058] Reference Figure 1 , Figure 4 and Figure 5 , in operation S110 , a variable “i” is set to “1.” The variable “i” is a simple reference symbol used to describe data sequentially received through one DQ line and is not intended to limit the inventive concept.

[0059] In operation S120, the nonvolatile memory device 100 may receive the i-th bit through one DQ line. For example, the nonvolatile memory device 100 may receive the i-th bit from the memory controller 11 through one DQ line. Although described herein as the i-th bit, the "bit" received on the data line is actually a data signal or DQ signal representing the bit. For example, the data signal will have a specific voltage representing the bit, for example, a high voltage representing a first bit or a first data state (such as "1") and a low voltage representing a second bit or a second data state (such as "0").

[0060] In operation S130 , the nonvolatile memory device 100 may determine whether the value of the received DQ signal corresponds to a bit value of “1”.

[0061] When the value of the received bit is '1', the nonvolatile memory device 100 sets the page buffer to a value corresponding to the DQ identifier DQID in operation S140 .

[0062] When the value of the received bit is '0', the nonvolatile memory device 100 sets the page buffer to a value corresponding to the erase state in operation S150.

[0063] In operation S160, it is determined whether the variable "i" is a maximum value. For example, it is determined whether all bits are received through one DQ line. When the variable "i" is not a maximum value, in operation S170, the variable "i" may be increased by "1" and operation S120 is performed.

[0064] When the variable 'i' is a maximum value (ie, when all bits are received through one DQ line), in operation S180, the nonvolatile memory device 100 may perform a program operation based on the set page buffer.

[0065] In one example embodiment, referring to Figure 6 The flowchart of FIG. 1 describes the operation of programming data received through one DQ line, but the inventive concept is not limited thereto. Figure 6 After setting a plurality of page buffers based on data received through a plurality of DQ lines as described in the flowchart, the nonvolatile memory device 100 may perform a program operation in units of word lines.

[0066] Fig. 7A and Figure 7B It is used to describe in detail Figure 6 For the sake of simplicity, in Figure 7B Some components are omitted.

[0067] Reference Figure 4 , Fig. 7A and Figure 7B, the nonvolatile memory device 100 may sequentially receive bits B21 to B24 through the second DQ line DQ2, and may sequentially receive bits B31 to B34 through the third DQ line DQ3. Fig. 7A As shown in , the nonvolatile memory device 100 can receive bits B21 to B24 synchronized with the data selection signal DQS through the second DQ line DQ2, and can receive bits B31 to B34 synchronized with the data selection signal DQS through the third DQ line DQ3 (e.g., will be received at the same time as the rising edge or falling edge of the data selection signal).

[0068] Page buffers PB21, PB22, PB23, and PB24 corresponding to the second DQ line DQ2 may be respectively or sequentially set based on bits B21 to B24 received through the second DQ line DQ2, and page buffers PB31, PB32, PB33, and PB34 corresponding to the third DQ line DQ3 may be respectively or sequentially set based on bits B31 to B34 received through the third DQ line DQ3. The relationship between the page buffers PB21, PB22, PB23, PB24, PB31, PB32, PB33, and PB34, the bit line groups BLG2 and BLG3, and the DQ lines DQ2 and DQ3 is described above, and thus additional description will be omitted to avoid redundancy.

[0069] For example, each of the page buffers PB21, PB22, PB23, PB24, PB31, PB32, PB33, and PB34 may include first to third data latches DL1, DL2, and DL3. Each of the first to third data latches DL1, DL2, and DL3 may be configured to store or latch a bit value "1" or a bit value "0".

[0070] In an example embodiment, assuming that the DQ identifier DQID of the second DQ line DQ2 is "101", the DQ identifier DQID of the third DQ line DQ3 is, for example, "111" having a value different from that of the DQ identifier DQID of the second DQ line DQ2, and the value corresponding to the erase state is "000". However, the inventive concept is not limited thereto. For example, the DQ identifier may be variously changed or modified according to a programming method, a bit order, etc. of the nonvolatile memory device 100.

[0071] When bits B22 and B23 received through the second DQ line DQ2 and bits B32 and B33 received through the third DQ line DQ3 are both "0", page buffers PB22, PB23, PB32, and PB33 corresponding to bits B22, B23, B32, and B33, respectively, may be set to values ​​corresponding to the erase state. For example, all first to third data latches DL1, DL2, and DL3 of each of the page buffers PB22, PB23, PB32, and PB33 may be set to a value of "0".

[0072] When bits B21 and B24 received through the second DQ line DQ2 are both "1", page buffers PB21 and PB24 corresponding to bits B21 and B24 may be set to values ​​corresponding to the DQ identifier. For example, first to third data latches DL1, DL2, and DL3 of each of page buffers PB21 and PB24 may be set to values ​​"1", "0", and "1", respectively.

[0073] When bits B31 and B34 received through the third DQ line DQ3 are both "1", page buffers PB31 and PB34 corresponding to bits B31 and B34 may be set to values ​​corresponding to the DQ identifier. For example, first to third data latches DL1, DL2, and DL3 of each of page buffers PB31 and PB34 may be set to values ​​"1", "1", and "1", respectively.

[0074] As reference Figure 7B As described above, even if the same bit value is received through different DQ lines, different values ​​can be set to the page buffer based on the DQ identifier. The error margin of the memory cell can be set differently for each DQ line by setting the page buffer in the above manner.

[0075] Figure 8 is a diagram showing a method according to an example embodiment Figure 4 Schematic diagram of values ​​of a set of data latches in a nonvolatile memory device according to bits received through each DQ line. Fig. 9 It shows that according to Figure 8 Graph showing threshold voltage distribution of memory cells programmed by a page buffer setting method.

[0076] Reference Figure 2 and Figure 8 , for each of the first to fourth DQ lines DQ1 to DQ4 , when a bit value “0” is received, all of the first to third data latches DL1 to DL3 of the page buffer corresponding to each DQ line are set to “0”.

[0077] For each of the first to fourth DQ lines DQ1 to DQ4, when a bit value "1" is received, the first to third data latches DL1 to DL3 of the page buffer corresponding to each DQ line are set to the value of the DQ identifier corresponding to the corresponding DQ line. For example, the DQ identifier DQID1 of the first DQ line DQ1 may be "100", the DQ identifier DQID2 of the second DQ line DQ2 may be "101", the DQ identifier DQID3 of the third DQ line DQ3 may be "111", and the DQ identifier DQID4 of the fourth DQ line DQ4 may be "110". However, the inventive concept is not limited thereto. For example, the DQ identifier may be changed differently.

[0078] When a bit value "1" is received through the first DQ line DQ1, the first to third data latches DL1 to DL3 of the page buffer corresponding to the first DQ line DQ1 may be set to values ​​"1", "0", and "0", respectively. When a bit value "1" is received through the second DQ line DQ2, the first to third data latches DL1 to DL3 of the page buffer corresponding to the second DQ line DQ2 may be set to values ​​"1", "0", and "1", respectively. When a bit value "1" is received through the third DQ line DQ3, the first to third data latches DL1 to DL3 of the page buffer corresponding to the third DQ line DQ3 may be set to values ​​"1", "1", and "1", respectively. When a bit value "1" is received through the fourth DQ line DQ4, the first to third data latches DL1 to DL3 of the page buffer corresponding to the fourth DQ line DQ4 may be set to values ​​"1", "1", and "0", respectively.

[0079] In such Figure 8 After the plurality of page buffers are included in the page buffer circuit 130 as shown in the configuration shown in FIG, the nonvolatile memory device 100 may perform a programming operation based on the page buffers thus configured. Fig. 9 According to the threshold voltage distribution diagram of FIG. 1 , a plurality of memory cells connected to one word line WL may be programmed to have an erase state “E” and any one of first to fourth program states P1 to P4.

[0080] For example, a memory cell corresponding to a page buffer in which all of the first to third data latches DL1 to DL3 are set to “0” may have an erase state “E”; a memory cell corresponding to a page buffer in which the first to third data latches DL1 to DL3 are respectively set to “1”, “0” and “0” may have a first programming state “P1”; a memory cell corresponding to a page buffer in which the first to third data latches DL1 to DL3 are respectively set to “1”, “0” and “1” may have a second programming state “P2”; a memory cell corresponding to a page buffer in which the first to third data latches DL1 to DL3 are respectively set to “1”, “1” and “1” may have a third programming state “P3”; and a memory cell corresponding to a page buffer in which the first to third data latches DL1 to DL3 are respectively set to “1”, “1” and “0” may have a fourth programming state “P4”.

[0081] In an example embodiment, as described above, the values ​​set to the first to third data latches DL1 to DL3 may be based on the DQ identifier DQID (however, there is an exceptional state (ie, erase state 'E') in which all of the first to third data latches DL1 to DL3 are set to '0').

[0082] As described above, in the case where the memory cells connected to one word line WL are programmed, the memory cells corresponding to the first DQ line DQ1 (ie, Figure 4 The first memory cell MC1 of the first programming state may have any one of the erase state “E” and the first programming state P1, and the memory cell corresponding to the second DQ line DQ2 (ie, Figure 4 The second memory cell MC2 of the third DQ line may have any one of the erase state “E” and the second program state P2, and the memory cell corresponding to the third DQ line DQ3 (ie, Figure 4 The third memory cell MC3 of the fourth DQ line may have any one of the erase state “E” and the third program state P3, and the memory cell corresponding to the fourth DQ line DQ4 (ie, Figure 4 The fourth memory cell MC4) may have any one of the erased state "E" and the fourth programmed state P4. Therefore, the memory cell can be programmed to have different error margins based on the DQ line. In this example, although a single bit having only one of the two bit values ​​is being stored in the memory cell connected to one word line WL, the memory cell may be in the erased state "E" representing the first bit value (e.g., "0") or in one of four different programmed states P1, P2, P3, and P4, wherein each of the programmed states P1, P2, P3, and P4 represents a second bit value (e.g., "1").

[0083] In an example embodiment, in a programming operation of a memory cell, a first programming state P1 may be verified based on a first verification voltage Vvfy1, a second programming state P2 may be verified based on a second verification voltage Vvfy2 higher than the first verification voltage Vvfy1, a third programming state P3 may be verified based on a third verification voltage Vvfy3 higher than the second verification voltage Vvfy2, and a fourth programming state P4 may be verified based on a fourth verification voltage Vvfy4 higher than the third verification voltage Vvfy3.

[0084] In one example embodiment, the same read voltage VRD may be used to read Fig. 9 . For example, in the nonvolatile memory device 100, the state of the memory cell may be determined while the read voltage VRD is applied to the word line WL. In this case, a memory cell having a threshold voltage (Vth) higher than the read voltage VRD may be determined to store a bit value "1"; a memory cell having a threshold voltage lower than the read voltage VRD may be determined to store a bit value "0".

[0085] Fig.10 It is shown Figure 1 A block diagram of a nonvolatile memory device is shown. Fig.10 , the nonvolatile memory device 100-1 may include a memory cell array 110-1, an address decoder 120-1, a page buffer circuit 130-1, an input / output circuit 140-1, and a control logic circuit 150-1. The memory cell array 110-1, the address decoder 120-1, the page buffer circuit 130-1, the input / output circuit 140-1, and the control logic circuit 150-1 are described above, and thus additional description will be omitted to avoid redundancy.

[0086] Fig.10 The input / output circuit 140-1 may divide the DQ lines into a plurality of DQ line groups DQG1 to DQGn for management. The DQ lines of the respective DQ line groups DQG1 to DQGn may correspond to different DQ identifiers DQID1 to DQIDn, respectively. For example, the DQ lines of the first DQ line group DQG1 may correspond to the first DQ identifier DQID1; the DQ lines of the second DQ line group DQG2 may correspond to the second DQ identifier DQID2; and the DQ lines of the nth DQ line group DQGn may correspond to the nth DQ identifier DQIDn.

[0087] In an example embodiment, as described above, when a bit value "1" is received through a DQ line, the nonvolatile memory device 100-1 may set the page buffer to the value of a DQ identifier corresponding to the DQ line. For example, when a bit value "1" is received through a DQ line included in the first DQ line group DQG1, the nonvolatile memory device 100-1 may set the value of the first DQ identifier DQID1 to the page buffer corresponding to the first DQ line group DQG1.

[0088] As described above, the nonvolatile memory device 100-1 can manage a plurality of DQ lines in units of DQ line groups and can give different DQ identifiers based on DQ line groups. In this way, memory cells of respective DQ line groups can have different error margins.

[0089] Fig.11 is shown according to some examples Figure 2 Flowchart of the operation of a nonvolatile memory device. Fig.12 Is used to describe Fig.11 An illustration of the operation of a flowchart. Fig.13A and Fig. 13B It shows that according to Fig.11 A flow chart of a distribution diagram of threshold voltage distributions of memory cells programmed by a programmable logic circuit.

[0090] In one example embodiment, reference will be made to Figures 1 to 10 An embodiment is described in which the memory cells have different error margins based on the DQ lines but store 1-bit data in the same manner. However, the inventive concept is not limited thereto. For example, each or a portion of the memory cells may be configured to store 2-bit data based on the DQ lines.

[0091] For example, refer to Figure 2 , Fig.11 and Fig.12In operation S210, the nonvolatile memory device 100 may determine a programming type (PGM type) based on the DQ identifier DQID. For example, the nonvolatile memory device 100 may determine a programming type (such as a single-level cell ("SLC") programming mode or a multi-level cell ("MLC") programming mode (which may store multiple bits per cell - for example, a triple-level cell ("TLC") programming mode)) for a memory cell corresponding to the DQ identifier DQID. Cells programmed to store different amounts of bits may generally be referred to herein as "m"-bit cells (or storing "m" bits) or "n"-bit cells (or storing "n" bits). In an example embodiment, the programming type may be determined based on the number of bits stored per cell. For example, in a case where the SLC programming mode is determined as the programming type associated with the first DQ line DQ1, the memory cell corresponding to the first DQ line DQ1 may be programmed in the SLC programming mode of storing one bit per cell. In a case where the MLC programming mode is determined as the programming type associated with the second DQ line DQ2 , memory cells corresponding to the second DQ line DQ2 may be programmed in the MLC programming mode of storing two (or more) bits per cell.

[0092] Then, the nonvolatile memory device 100 may perform operations S220 and S230. Operations S220 and S230 are similar to Figure 6 Operation S110 is similar to operation S120 , and thus additional description will be omitted to avoid redundancy.

[0093] In operation S240, the nonvolatile memory device 100 may set a page buffer based on the received i-th bit and the programming type. Figures 1 to 10 Different from the embodiment of the present invention, the third data latch DL3 of each of the page buffers PB21, PB22, PB23, PB24, PB31 and PB32 may be used as a flag latch for storing information about the programming type. For example, it is assumed that the memory cells MC21, MC22, MC23 and MC24 corresponding to the second DQ line DQ2 are programmed in the SLC programming mode, and the memory cells MC31 and MC32 corresponding to the third DQ line DQ3 are programmed in the MLC programming mode. In this case, the third latch DL3 of the page buffers PB21, PB22, PB23 and PB24 corresponding to the second DQ line DQ2 may be set to "0", and the third latch DL3 of the page buffers PB31 and PB32 corresponding to the third DQ line DQ3 may be set to "1". That is, the information of the relevant programming type may be stored in the third data latch DL3 of the page buffers PB21, PB22, PB23, PB24, PB31 and PB32.

[0094] In an example embodiment, Fig.12As shown in , bits B21, B22, B23, and B24 having a value of "1001" may be sequentially received through the second DQ line DQ2. In this case, the bits B21, B22, B23, and B24 received through the second DQ line DQ2 may be set to the first data latches DL1 of the page buffers PB21, PB22, PB23, and PB24, respectively. In this case, since the memory cells MC21, MC22, MC23, and MC24 corresponding to the second DQ line DQ2 are programmed in an SLC programming manner, the second data latches DL2 of the page buffers PB21, PB22, PB23, and PB24 may not be individually set or may be ignored.

[0095] Bits B31, B32, B33, and B34 having a value of "1001" may be sequentially received through the third DQ line DQ3. In this case, bits B31, B32, B33, and B34 received through the third DQ line DQ3 may be set to first data latches DL1 and second data latches DL2 of page buffers PB31 and PB32. For example, bits B31 and B32 may be set to first data latches DL1 and second data latches DL2 of page buffer PB31, respectively, and bits B33 and B34 may be set to first data latches DL1 and second data latches DL2 of page buffer PB32, respectively.

[0096] Then, the nonvolatile memory device 100 may perform operations S250 and S260. Operations S250 and S260 may be performed in conjunction with Figure 6 Operation S160 is similar to operation S170 , and thus additional description will be omitted to avoid redundancy.

[0097] In operation S270, the nonvolatile memory device 100 performs a programming operation based on the set page buffer. For example, the nonvolatile memory device 100 may determine a programming type based on the third data latch DL3 of the page buffer including information about the programming type, and may program memory cells based on values ​​stored in the first and second data latches DL1 and DL2 of the page buffer according to the determined programming type.

[0098] For example, with reference Fig.12The memory cells (e.g., MC21, MC22, MC23, and MC24) corresponding to the described second DQ line DQ2 may be SLC-programmed to have any one of the erased state "E" and the first SLC program state SP1. For example, the memory cells (e.g., MC21 and MC24) corresponding to the following page buffers (e.g., PB21 and PB24) may be SLC-programmed to have the first SLC program state SP1, wherein, in the page buffers, the third data latch DL3 including information about the programming type is set to "0" and the first data latch DL1 is set to "1". Alternatively, the memory cells (e.g., MC22 and MC23) corresponding to the following page buffers (e.g., PB22 and PB23) may be SLC-programmed to have the erased state "E", wherein, in the page buffers, the third data latch DL3 is set to "0" and the first data latch DL1 is set to "0".

[0099] The memory cells (e.g., MC31 and MC32) corresponding to the third DQ line DQ3 can be programmed by MLC to have one of the erased state E and the first to third MLC programming states MP1 to MP3. In this example, the memory cells corresponding to the following page buffer (not shown) can be programmed by MLC to have the erased state "E", wherein in the page buffer, the third data latch DL3 including information about the programming type is set to "1" and the first data latch DL1 and the second data latch DL2 are set to "0". Alternatively, the memory cells (e.g., MC32) corresponding to the following page buffer (e.g., PB32) can be programmed by MLC to have the first MLC programming state MP1, wherein in the page buffer, the third data latch DL3 is set to "1", the first data latch DL1 is set to "0" and the second data latch DL2 is set to "1". In addition, a memory cell corresponding to a page buffer (not shown) in which the third data latch DL3 is set to "1" and the first data latch DL1 and the second data latch DL2 are set to "1" can be MLC programmed to have a second MLC programming state MP2. A memory cell (e.g., MC31) corresponding to a page buffer (e.g., PB31) in which the third data latch DL3 is set to "1", the first data latch DL1 is set to "1" and the second data latch DL2 is set to "0" can be MLC programmed to have a third MLC programming state MP3.

[0100] In the above embodiments, the SLC programming mode and the 2-bit per cell MLC programming mode are described for the second DQ line DQ2 and the third DQ line DQ3, but the inventive concept is not limited thereto. Fig. 13B As shown in , the memory cells can be programmed in a TLC programming manner or a QLC programming manner based on the DQ identifier of the DQ line. In the case where the memory cells corresponding to a specific DQ line (or a specific DQ identifier) ​​are TLC programmed, the memory cells can be programmed to have Fig. 13B The erase state 'E' shown in FIG. 1 and any one of the first to seventh TLC program states TP1 to TP7. In this case, each memory cell can store 3 bits of information.

[0101] In the case where a memory cell corresponding to a specific DQ line (or a specific DQ identifier) ​​is QLC programmed, the memory cell may be programmed to have Fig. 13B The erase state "E" shown in FIG. 1 and any one of the first to fifteenth QLC program states QP1 to QP15. In this case, each memory cell can store 4 bits of information.

[0102] In an example embodiment, in the case where each of the specific memory cells corresponding to the specific DQ line stores n-bit data, each of the page buffers respectively corresponding to the specific memory cells may include (n+1) or more data latches (e.g., "n" data latches configured to store "n" bits respectively and other data latches configured to store information about programming type). Therefore, in some cases such as the first group of memory cells programmed to store n-bit data and the second group of memory cells programmed to store m-bit data (where m is greater than n) described above, the first page buffer corresponding to the first group of memory cells includes at least (n+1) data latches, and the second page buffer corresponding to the second group of memory cells includes at least (m+1) data latches.

[0103] like Fig.13A and Fig. 13B As shown in , when the number of bits stored per cell decreases, the error margin of the memory cell (e.g., the difference between the lower limit value of a programming state (e.g., P1, P2, P3, or P4) and a read voltage VRD lower than the programming state) can increase. For example, the nonvolatile memory device 100 according to an embodiment of the inventive concept can allow memory cells to have different error margins based on DQ lines or DQ identifiers by applying different programming methods to the memory cells based on the DQ lines or DQ identifiers.

[0104] As based on Figures 6 to 9 and Figures 11 to 13BAs can be seen from the comparison, in different embodiments, the same page buffer circuit can be used for a group of memory cells connected to a single word line to allow the group of memory cells to be accessed using different access schemes. For example, in one scheme, different memory cells connected to the same word line are programmed to store the same number of bits of data (e.g., single bits), but have different respective error margins. In another scheme, memory cells connected to the same word line are programmed to store different numbers of bits of data (e.g., some memory cells store single bits of data and some memory cells store multiple bits of data). In both cases, the DQ identifier or DQ line code associated with the memory cell can be used to determine the error margin between different programming states of a group of memory cells including the memory cell. It should be noted that the error margin can represent the minimum width or minimum threshold difference between two adjacent programming states of a group of memory cells.

[0105] Fig.14 is shown according to some examples Figure 2 Flowchart of the operation of a nonvolatile memory device. Fig.15 and Fig.16 Is used to describe Fig.14 Flowchart of the operation of FIG. Figure 2 and Figures 14 to 16 , the nonvolatile memory device 100 may perform operations S310 to S330. Operations S310 to S330 are similar to Fig.11 Operations S210 to S230 are similar, and thus additional description will be omitted to avoid redundancy.

[0106] In operation S340, the nonvolatile memory device 100 may set a page buffer based on the programming type, the i-th bit, and the value of the variable "i". Fig.15 As shown in , the nonvolatile memory device 100 can receive bits B31, B32, B33, and B34 through the third DQ line DQ3. The programming mode associated with the memory cells MC31, MC32, MC33, and MC34 corresponding to the third DQ line DQ3 can be determined as the MLC programming mode. In this way, as in the above description, the third data latches DL3 of the page buffers PB31, PB32, PB33, and PB34 corresponding to the third DQ line DQ3 can be set to "1".

[0107] In this case, the values ​​of the page buffers PB31, PB32, PB33, and PB34 may be set according to the values ​​of the received bits and the order of each received bit. Fig.12 In the described embodiment, a combination of two bits is provided to one page buffer for an MLC programming operation.

[0108] On the contrary, Fig.15 In the embodiment of the present invention, the first data latches DL1 and the second data latches DL2 of the page buffers PB31, PB32, PB33 and PB34 may be set according to a bit received through the third DQ line DQ3 and the order of the received bits. For example, in the case where the bit B31 first received through the third DQ line DQ3 is "1", the first data latch DL1 and the second data latch DL2 of the page buffer PB31 may be set to "1" and "0", respectively, so that the memory cell MC31 corresponding to the page buffer PB31 has Fig.16 . In the case where the next received bit B32 through the third DQ line DQ3 is "1", the first data latch DL1 and the second data latch DL2 of the page buffer PB32 may be set to "1" and "1", respectively, so that the memory cell MC32 corresponding to the page buffer PB32 has Fig.16 In the case where the bit B33 then received through the third DQ line DQ3 is "1", the first data latch DL1 and the second data latch DL2 of the page buffer PB33 may be set to "0" and "1", respectively, so that the memory cell MC33 corresponding to the page buffer PB33 has Fig.16 3. In the case where the last bit B34 received through the third DQ line DQ3 is "0", the first data latch DL1 and the second data latch DL2 of the page buffer PB34 may be set to "0" and "0", respectively, so that the memory cell MC34 corresponding to the page buffer PB34 has Fig.16 The erased state “E” is shown in FIG.

[0109] As described above, the nonvolatile memory device 100 may set a page buffer based on a value of one bit received, an order in which the one bit is received, and a program type.

[0110] Then, the nonvolatile memory device 100 may perform operations S350 to S370. Operations S350 to S370 are similar to Fig.11 Operations S250 to S270 are similar, and thus additional description will be omitted to avoid redundancy.

[0111] In one example embodiment, according to Fig.14 The memory cell corresponding to the third DQ line DQ3 among the memory cells programmed by the flowchart of Fig.16. For example, the memory cell corresponding to the third DQ line DQ3 may have any one of the erased state "E" and the first MLC programming state MP1 to the third MLC programming state MP3. However, the (3n-2)th memory cell ("n" is a natural number equal to or greater than 1) among the plurality of memory cells corresponding to the third DQ line DQ3 may have any one of the erased state "E" and the first MLC programming state MP1; the (3n-1)th memory cell among the plurality of memory cells corresponding to the third DQ line DQ3 may have any one of the erased state "E" and the second MLC programming state MP2; and the 3nth memory cell among the plurality of memory cells corresponding to the third DQ line DQ3 may have any one of the erased state "E" and the third MLC programming state MP3.

[0112] The above order of the memory cells is exemplary, and the inventive concept is not limited thereto. In addition, the order of the memory cells may be a physical order or a logical order.

[0113] In the above embodiments of the inventive concept, the detailed description of the configuration of the page buffer, the number of data latches, the number of bits stored per cell, and the corresponding relationship between the data latch value and the threshold voltage distribution may be a simple example, and the inventive concept is not limited thereto. The above embodiments may be variously changed or modified by ordinary persons without departing from the technical concept of the inventive concept.

[0114] As described above, according to an embodiment of the inventive concept, a nonvolatile memory device can differently set the error margin of a memory cell in various ways based on a DQ line (or a DQ identifier). In this case, since the probability of an error occurring in data output through a specific DQ line is reduced, the burden associated with error correction can be reduced. Therefore, a nonvolatile memory device with improved reliability and improved performance and an operating method thereof are provided.

[0115] Fig.17 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the inventive concept. Fig.17 , the nonvolatile memory device 200 may include a memory cell array 210, an address decoder 220, a page buffer circuit 230, an input / output circuit 240, and a control logic circuit 250. In an example embodiment, as shown in FIG. Figures 1 to 16 As stated, Fig.17 The nonvolatile memory device 200 may perform a programming operation so that memory cells corresponding to DQ lines have different error margins. Figures 1 to 15 The memory cell array 210 , the address decoder 220 , the page buffer circuit 230 , and the control logic circuit 250 are described, and thus additional description will be omitted to avoid redundancy.

[0116] Fig.17 The input / output circuit 240 may include a DQ remapping controller 241. The DQ remapping controller 241 may be configured to control a mapping relationship or a corresponding relationship between the DQ line DQ and the data line DL. Figure 4 As described above, the first to fourth DQ lines DQ1 to DQ4 may correspond to data line groups DLG1 to DLG4, respectively. Data received through the fourth DQ line DQ4 may be stored in a fourth memory cell MC4 corresponding to the fourth data line group DLG4. In this case, as described above, since the fourth memory cell MC4 is programmed to have a relatively high threshold voltage, the fourth memory cell MC4 may experience a large amount of degradation compared to other memory cells (e.g., MC1, MC2, and MC3). In this case, the reliability of the data stored in the memory cell may be reduced.

[0117] As described above, in order to compensate for the degradation difference of the memory cells, the DQ remapping controller 241 may adjust the mapping relationship or correspondence relationship between the DQ lines DQ and the data lines DL periodically or when a specific condition is satisfied. In this way, the degradation difference of the memory cells may be compensated.

[0118] Fig.18 It is shown Fig.17 Flowchart of a DQ mapping operation of a nonvolatile memory device. Fig.19A and Fig.19B Is used to describe Fig.18 FIG. 1 is a flowchart of a DQ mapping operation.

[0119] Reference Fig.17 and Fig.18 In operation S410, the nonvolatile memory device 200 may determine a cell condition. In an example embodiment, the cell condition may indicate various factors capable of determining a degree of degradation of a memory cell. For example, the cell condition may include various information such as P / E cycle information of the nonvolatile memory device 200, information about the number of errors of data read from a memory cell of the nonvolatile memory device 200, and temperature information of the nonvolatile memory device 200.

[0120] In operation S420, the nonvolatile memory device 200 may determine whether the determined cell condition satisfies a specific condition. For example, the nonvolatile memory device 200 may determine whether the P / E cycle count reaches a specific count. Alternatively, the nonvolatile memory device 200 may determine whether the number of errors included in the data read from the memory cell is not less than a specific value.

[0121] When the cell condition does not satisfy the specific condition, the nonvolatile memory device 200 may not perform a separate operation. When the cell condition satisfies the specific condition, the nonvolatile memory device 200 may remap the correspondence between the DQ line DQ and the data line DL in operation S430.

[0122] For example, refer to Fig.19A and Fig.19B The nonvolatile memory device 200 may include a memory cell array 210, a page buffer circuit 230, and a DQ remapping controller 241. The page buffer circuit 230 may include a plurality of page buffers PB1 to PB4. Fig.19A and Fig.19B The components and connection relationships between the components are shown in the figure, so additional description will be omitted to avoid redundancy.

[0123] As reference Fig.19A As described, the first to fourth DQ lines DQ1 to DQ4 may correspond to the first to fourth data line groups DLG1 to DLG4, respectively. That is, the data received through the first DQ line DQ1 is provided to the first page buffer PB1 connected to the first data line group DLG1; the data received through the second DQ line DQ2 is provided to the second page buffer PB2 connected to the second data line group DLG2; the data received through the third DQ line DQ3 is provided to the third page buffer PB3 connected to the third data line group DLG3; and the data received through the fourth DQ line DQ4 is provided to the fourth page buffer PB4 connected to the fourth data line group DLG4. The data stored or latched in the first to fourth page buffers PB1 to PB4 may be stored in corresponding memory cells of the memory cell array 210.

[0124] Here, when the cell conditions of the memory cells of the memory cell array 210 satisfy specific conditions (for example, when the P / E cycle count reaches a reference value), the DQ remapping controller 241 can adjust the correspondence between the first DQ line DQ1 to the fourth DQ line DQ4 and the first data line group DLG1 to the fourth data line group DLG4.

[0125] For example, the remapping operation can be performed by the DQ remapping controller 241 so that the first DQ line DQ1 corresponds to the fourth data line group DLG4, the second DQ line DQ2 corresponds to the first data line group DLG1, the third DQ line DQ3 corresponds to the second data line group DLG2, and the fourth DQ line DQ4 corresponds to the third data line group DLG3.

[0126] For example, after the DQ remapping operation is performed, the data received through the first DQ line DQ1 may be provided to the fourth page buffer PB4 connected to the fourth data line group DLG4; the data received through the second DQ line DQ2 may be provided to the first page buffer PB1 connected to the first data line group DLG1; the data received through the third DQ line DQ3 may be provided to the second page buffer PB2 connected to the second data line group DLG2; and, the data received through the fourth DQ line DQ4 may be provided to the third page buffer PB3 connected to the third data line group DLG3.

[0127] Assuming that the memory cell corresponding to the fourth DQ line DQ4 has the largest error margin and the memory cell corresponding to the first DQ line DQ1 has the smallest error margin, the degradation of the memory cell corresponding to the fourth page buffer PB4 before the DQ remapping operation may be relatively large, and the degradation of the memory cell corresponding to the fourth page buffer PB4 after the DQ remapping operation may be relatively reduced. Therefore, since the degradation degrees of all memory cells of the nonvolatile memory device 200 are balanced, the reliability of the nonvolatile memory device 200 is improved.

[0128] exist Fig.19A In the embodiment of FIG. 1 , a description is given of the correspondence between the DQ line and the data line group controlled by the DQ remapping controller 241, but the inventive concept is not limited thereto. Fig.19B As shown in , the DQ remapping operation can be performed in units of data lines.

[0129] For example, Fig.19B As shown in , before the DQ remapping operation, the first DQ line DQ1 may correspond to the data line connected to the first page buffer PB1; however, after the DQ remapping operation of the DQ remapping controller 241, the first DQ line DQ1 may correspond to the data line connected to a portion of the first page buffer PB1 and the data line connected to a portion of the second page buffer PB2. That is, the DQ remapping controller 241 may perform the DQ remapping operation in units of data lines.

[0130] The embodiments of the inventive concept described above are simple examples to easily describe the technical idea of ​​the inventive concept, and the inventive concept is not limited thereto.

[0131] FIG. 20A to FIG. 20D is a block diagram showing a storage device to which a nonvolatile memory module according to an embodiment of the inventive concept is applied. Fig. 20A , the storage device 1000a may include a storage controller 1100a and a nonvolatile memory device 1200a.

[0132] The storage controller 1100a may exchange data with the nonvolatile memory device 1200a. The nonvolatile memory device 1200a may include a multiply-accumulate (MAC) unit 1210a. The MAC unit 1210a may be configured to perform a MAC operation on data stored in the nonvolatile memory device 1200a. For example, the MAC operation may include a computing operation (such as machine learning or artificial intelligence) used in various applications. The nonvolatile memory device 1200a may store weight information for various applications, the MAC unit 1210a may perform a MAC operation on the weight information, and may provide the result of the MAC operation to the storage controller 1100a.

[0133] The nonvolatile memory device 1200a may be a reference Figures 1 to 19B The nonvolatile memory device described herein may be or may operate similarly to the nonvolatile memory device described herein. For example, a DQ line of the nonvolatile memory device 1200a may be connected to the MAC unit 1210, and the MAC unit 1210a may perform a MAC operation on weight information received through the DQ line.

[0134] In this case, as described above, because the nonvolatile memory device 1200a can set the error margin of the memory cell differently based on the DQ line, the data corresponding to a specific DQ line among the data input to the MAC unit 1210 can have a higher reliability than the data corresponding to any other DQ line. For example, a group of data received through the DQ line during one cycle can be a bit vector. In the event that an error occurs in the most significant bit (MSB) of the bit vector, the error present in the result value of the MAC unit 1210a can be larger than in the event that an error occurs in other bits (e.g., the least significant bit (LSB)). For example, since the nonvolatile memory device 1200a makes the error margin of the DQ line corresponding to the MSB of the bit vector large, the reliability of the calculation of the MAC unit 1210a can be improved.

[0135] Reference Fig. 20B , the storage device 1000b may include a storage controller 1100b and a non-volatile memory device 1200b. The storage controller 1100b may include a MAC unit 1110b. The non-volatile memory device 1200b may be a reference Figures 1 to 19B The nonvolatile memory device described herein may be Figures 1 to 19B Operate according to the described operation method.

[0136] In addition to the MAC unit 1110b included in the memory controller 1100b, Fig. 20B The storage device 1000b and Fig. 20A The present invention is similar to the storage device 1000a, and thus additional description will be omitted to avoid redundancy.

[0137] Reference Fig. 20C The storage device 1000c may include a storage controller 1100c, a nonvolatile memory device 1200c, and a controller 1300c. The controller 1300c may include a MAC unit 1310c. The nonvolatile memory device 1200c may be a reference Figures 1 to 19B The nonvolatile memory device described herein may be Figures 1 to 19B Operate according to the described operation method.

[0138] In addition to the MAC unit 1310c included in the separate controller 1300c, Fig. 20C The memory device 1000c is similar to the memory devices 1000a and 1000b, and thus additional description will be omitted to avoid redundancy.

[0139] Reference Fig.20D The storage device 1000d may include a storage controller 1100d, a first nonvolatile memory device 1200d, a controller 1300d, and a second nonvolatile memory device 1400d. The controller 1300d may include a MAC unit 1310d.

[0140] The first nonvolatile memory device 1200d may be a reference Figures 1 to 19B The nonvolatile memory device described herein may be Figures 1 to 19B Operate according to the described operation method.

[0141] The storage controller 1100d may be configured to communicate with the controller 1300d or the second nonvolatile memory device 1400d based on an operation situation. For example, the second nonvolatile memory device 1400d may be a high-capacity storage medium configured to store user data. In response to a request from an external device (e.g., a host or an application processor (AP)), the storage controller 1100d may read data stored in the second nonvolatile memory device 1400d, or may store data in the second nonvolatile memory device 1400d.

[0142] The storage controller 1100d may control the controller 1300d to perform a specific function (eg, an artificial intelligence function), and the controller 1300d may be configured to perform a specific function under the control of the storage controller 1100d.

[0143] As described above, according to an embodiment of the inventive concept, a nonvolatile memory device can set the error margin of a memory cell differently based on a DQ line. In this case, the reliability of data exchanged through a specific DQ line can be increased. For example, in a MAC operation, in the case where a specific bit error has an impact on a computing operation, a nonvolatile memory device according to an embodiment of the inventive concept can provide improved reliability and improved performance.

[0144] Fig.21 is a block diagram illustrating a mobile system to which a nonvolatile memory device according to an embodiment of the inventive concept is applied. Fig.21 , the mobile system 2000 may include an application processor 2100, a network module 2200, a system memory 2300, a storage device 2400, an image sensor 2500, a display device 2600, and a user input / output device 2700. In an example embodiment, the mobile system 2000 may be a portable computing system such as a smart phone, a tablet personal computer (PC), or a notebook computer.

[0145] The application processor 2100 (e.g., an application processor (AP)) may control the overall operation of the mobile system 2000. The network module 2200 may provide wireless or wired communication with an external device (e.g., a base station, a server, or any other mobile device). The system memory 2300 may be used as a working memory or a buffer memory of the mobile system 2000. In an example embodiment, the system memory 2300 may be a memory (e.g., DRAM) supporting high-speed operation.

[0146] The storage device 2400 may be used as a high-capacity storage medium for storing various information used in the mobile system 2000. In an example embodiment, the storage device 2400 may be a reference Figures 1 to 19B The nonvolatile memory device described herein may be based on reference Figures 1 to 19B The described method is performed.

[0147] The display device 2600 may be a device that displays information processed by the application processor 2100 to a user. The image sensor 2500 may be a device that collects image information associated with an external object. The user input / output device 2700 may be a device that receives a command from a user or provides information, such as a microphone, a speaker, a keyboard, or a touch screen display.

[0148] According to an embodiment of the inventive concept, a nonvolatile memory device can differently set an error margin of a memory cell based on a DQ line. Therefore, a nonvolatile memory device having improved reliability and improved performance and an operating method thereof are provided.

[0149] While the inventive concepts have been described with reference to example embodiments of the inventive concepts, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the invention as defined in the claims.

[0150] Ordinal numbers such as "first", "second", "third", etc. may simply be used as labels for specific elements, steps, etc. to distinguish such elements, steps, etc. from each other. Terms that are not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, a term referenced with a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0151] It should be understood that when an element is referred to as being "connected" or "coupled" to or with another element, it can be directly connected or coupled to the other element or intervening elements may be present. Circuit components that are described as being connected to other components associated with the circuit diagram are in electrical communication with those other components.

Claims

1. A method for operating a non-volatile memory device, the method comprising: receiving a first DQ signal representing a first data bit from an external device through a first DQ line, and receiving a second DQ signal representing a second data bit from an external device through a second DQ line; as well as programming a first memory cell corresponding to a first DQ line and a second memory cell corresponding to a second DQ line so that the first memory cell has any one of an erased state and a first programmed state based on a first DQ signal and the second memory cell has any one of an erased state and a second programmed state based on a second DQ signal, The lower limit value of the threshold voltage distribution corresponding to the second programming state is higher than the lower limit value of the threshold voltage distribution corresponding to the first programming state. wherein the first memory cell and the second memory cell are connected to the same word line, The programming step includes: storing a first data bit in a first memory cell, storing a second data bit in a second memory cell, When the first data bit and the second data bit are the same, a first programming state of a first memory cell storing the first data bit is different from a second programming state of a second memory cell storing the second data bit.

2. The operating method according to claim 1, wherein: Each of the first memory cell and the second memory cell stores 1-bit data.

3. The operating method according to claim 2, wherein: The erased state for each of the first memory cell and the second memory cell represents the same data state for both memory cells, and both the first programmed state for the first memory cell and the second programmed state for the second memory cell represent the same data state for both memory cells.

4. The operating method according to claim 1, wherein: The programming steps include: When the first DQ signal representing the first data bit has a first value, setting the first page buffer corresponding to the first memory cell to a value corresponding to the erase state, and when the first DQ signal representing the first data bit has a second value, setting the first page buffer to a value corresponding to the first DQ identifier for the first DQ line; When a second DQ signal representing a second data bit has a first value, setting a second page buffer corresponding to a second memory cell to a value corresponding to an erase state, and when a second DQ signal representing a second data bit has a second value, setting the second page buffer to a value corresponding to a second DQ identifier for a second DQ line, wherein the first DQ identifier has a different value than the second DQ identifier; and The first memory cell and the second memory cell are programmed based on the set first page buffer and the set second page buffer, respectively.

5. The operating method according to claim 4, wherein: The first page buffer is connected to a first bit line connected to the first memory cell, and the second page buffer is connected to a second bit line connected to the second memory cell.

6. The operating method according to claim 1, further comprising: programming a first memory cell corresponding to a first DQ line to have a first programmed state; as well as programming a second memory cell corresponding to a second DQ line to have a second programmed state, wherein the first programmed state and the second programmed state have non-overlapping threshold voltage distributions, and Therein, both the first programmed state for the first memory cell and the second programmed state for the second memory cell represent the same data state for both memory cells.

7. The operating method according to claim 1, wherein: The programming steps include: When the first DQ signal representing the first data bit has a first value, the first page buffer corresponding to the first memory cell is set to a value corresponding to the first value and a value corresponding to the first programming mode, and when the first DQ signal representing the first data bit has a second value, the first page buffer is set to a value corresponding to the second value and a value corresponding to the first programming mode; When the second DQ signal indicating the second data bit has a first value, setting the second page buffer corresponding to the second memory cell to a value corresponding to the first value and a value corresponding to the second programming mode, and when the second DQ signal indicating the second data bit has a second value, setting the second page buffer to a value corresponding to the second value and a value corresponding to the second programming mode; and The first memory cell and the second memory cell are programmed based on the set first page buffer and the set second page buffer, respectively.

8. The operating method according to claim 7, wherein: The first programming mode indicates a programming mode for storing n bits per cell, and the second programming mode indicates a programming mode for storing m bits per cell, wherein n is a natural number equal to or greater than 1, and m is a natural number greater than n.

9. The operating method according to claim 8, wherein: The first page buffer includes at least n+1 data latches, and the second page buffer includes at least m+1 data latches.

10. The operating method according to claim 1, wherein: The first DQ signal and the second DQ signal are received at the same time as a rising edge or a falling edge of a data strobe signal from an external device.

11. The operating method according to claim 1, further comprising: receiving a third data bit via the first DQ line and receiving a fourth data bit via the second DQ line; determining a cell condition of the first memory cell and the second memory cell; as well as programming the first memory cell and the second memory cell based on the cell condition, the third data bit, and the fourth data bit, wherein, when the cell condition does not satisfy the reference condition, programming the first memory cell and the second memory cell so that the first memory cell has any one of an erased state and a first programmed state based on a third data bit, and the second memory cell has any one of an erased state and a second programmed state based on a fourth data bit; and Wherein, when the cell condition meets the reference condition, the first memory cell and the second memory cell are programmed so that the second memory cell has any one of an erased state and a first programmed state based on a third data bit, and the first memory cell has any one of an erased state and a second programmed state based on a fourth data bit.

12. A non-volatile memory device comprising: a first memory cell connected to a first word line and a first bit line; a second memory cell connected to the first word line and the second bit line; an input / output circuit configured to output a first data bit corresponding to a first DQ signal received from an external device on the first DQ line through a first data line, and to output a second data bit corresponding to a second DQ signal received from an external device on a second DQ line through a second data line; a first page buffer connected to the first bit line and the first data line and configured to store a first latch value based on a first data bit received via the first data line and a first DQ identifier for the first DQ line; as well as a second page buffer connected to the second bit line and the second data line and configured to store a second latch value based on a second data bit received through the second data line and a second DQ identifier for the second DQ line, wherein the first memory cell programmed based on the first latch value has any one of an erased state and a first programmed state, wherein a second memory cell programmed based on the second latch value has any one of an erased state and a second programmed state, The lower limit value of the threshold voltage distribution corresponding to the second programming state is higher than the lower limit value of the threshold voltage distribution corresponding to the first programming state. wherein the first data bit is stored in a first memory unit, the second data bit is stored in a second memory unit, and When the first data bit and the second data bit are the same, a first programming state of a first memory cell storing the first data bit is different from a second programming state of a second memory cell storing the second data bit.

13. The nonvolatile memory device according to claim 12, wherein: The first page buffer includes a plurality of first data latches configured to store first latch values, and The second page buffer includes a plurality of second data latches configured to store second latch values.

14. The nonvolatile memory device according to claim 12, further comprising: an address decoder configured to control the first word line based on an address received from an external device; as well as The control logic circuit is configured to control the address decoder, the input / output circuit, the first page buffer and the second page buffer so that the first memory cell and the second memory cell are programmed based on the first latch value and the second latch value, respectively.

15. The non-volatile memory device according to claim 14, in, Both the first programmed state for the first memory cell and the second programmed state for the second memory cell represent the same data state for both memory cells.

16. The nonvolatile memory device according to claim 15, wherein: When the first data bit is a first value, the first latch value corresponds to an erased state, wherein, when the first data bit is the second value, the first latch value corresponds to the first DQ identifier, wherein, when the second data bit is the first value, the second latch value corresponds to an erased state, Wherein, when the second data bit is a second value, the second latch value corresponds to a second DQ identifier.

17. The nonvolatile memory device according to claim 15, wherein: A first program state of the first memory cell is verified based on a first verification voltage, and a second program state of the second memory cell is verified based on a second verification voltage higher than the first verification voltage.

18. The nonvolatile memory device according to claim 15, wherein: Each of the first memory cell programmed based on the first latch value and the second memory cell programmed based on the second latch value is read by a first read voltage.

19. The nonvolatile memory device according to claim 12, wherein: The input / output circuit includes: a DQ remapping controller configured to manage a correspondence between the first DQ line and the second DQ line and the first data line and the second data line, and When the cell conditions of the first memory cell and the second memory cell meet the reference conditions, the DQ remapping controller performs a DQ remapping operation so that a first additional data bit corresponding to a first additional DQ signal received on the first DQ line is output through the second data line, and a second additional data bit corresponding to a second additional DQ signal received on the second DQ line is output through the first data line.

20. An operating method of a non-volatile memory device, the operating method comprising: receiving a first DQ signal representing first data from an external device through a first DQ line, and receiving a second DQ signal representing second data from an external device through a second DQ line; as well as programming a plurality of first memory cells corresponding to the first DQ line respectively based on the first data, and programming a plurality of second memory cells corresponding to the second DQ line respectively based on the second data, wherein the error margin of the plurality of second memory cells is greater than the error margin of the plurality of first memory cells, wherein the plurality of first memory cells and the plurality of second memory cells are connected to the same word line, The first data and the second data have the same bit value. The error margin indicates a difference between a lower limit value of a programming state and a read voltage.

21. The operating method according to claim 20, in, By applying the same read voltage to the word line, first data stored in the plurality of first memory cells and second data stored in the plurality of second memory cells are read.

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