Semiconductor devices

Abstract

The present invention provides a semiconductor device that can improve the di / dt controllability with respect to the collector-emitter current during conduction and can suppress oscillation. The semiconductor device (20) is an IGBT with a trench gate structure, has an accumulation region (33) directly below the p-type base region (32), and has a gate trench (36a) and a dummy trench (36b) as trenches (36) constituting the trench gate structure. The interval (mesa width) (w1) of the trenches (36) is 0.7 μm to 2 μm. A first gate electrode (38a) at the gate potential is provided inside the gate trench (36a) with a first gate insulating film (37a) therebetween. A second gate electrode (38b) at the emitter potential is provided inside the dummy trench (36b) with a second gate insulating film (37b) therebetween. The ratio of the number of gate trenches (36a) to the total number of trenches (36) is 60% or more and 84% or less.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] In the past, it was known that in IGBT (Insulated Gate Bipolar Transistor) and RC-IGBT (Reverse Conducting IGBT), a trench gate structure was used in which the electrodes were buried in the trenches formed in the semiconductor substrate via an insulating film, and all the electrodes in the trenches in the active area (hereinafter referred to as gate trenches) were connected to the gate pad (hereinafter referred to as gate ratio 100%).

[0003] In addition, it is known that in n - In the case of an n-channel IGBT, a charge (carrier) accumulation region is provided near the pn junction of the internal base region and the drift region for accumulating charges that become minority carriers when the device is turned on (for example, refer to the following patent document 1 (paragraphs 0161 and 0166, Figures 24 to 28).). In the case of an n-channel IGBT, the carrier accumulation region (hereinafter referred to as the accumulation region) is a region of conductivity type and n-type. - The drift region of the same type and the impurity concentration is n - In the n-type region with a high drift region, the minority carriers are holes.

[0004] By providing the accumulation region, the IE (Injection Enhanced) effect is enhanced and the conduction loss is reduced.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent No. 5025071 Summary of the invention

[0008] Technical issues

[0009] The present invention aims to solve the above-mentioned problems of the prior art and to provide a semiconductor device capable of improving di / dt controllability of collector-emitter current during on-time and suppressing oscillation.

[0010] Technical Solution

[0011] In order to solve the above-mentioned problems and achieve the purpose of the present invention, the semiconductor device of the present invention has the following characteristics. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate. A second semiconductor region of a second conductivity type is provided inside the semiconductor substrate at a position closer to the front side of the semiconductor substrate than the first semiconductor region. A third semiconductor region of a first conductivity type is provided inside the first semiconductor region between the first semiconductor region and the second semiconductor region in contact with the first semiconductor region and the second semiconductor region. The impurity concentration of the third semiconductor region is higher than that of the first semiconductor region. A fourth semiconductor region of a first conductivity type is selectively provided inside the second semiconductor region. A fifth semiconductor region of a second conductivity type is provided inside the semiconductor substrate at a position closer to the back side of the semiconductor substrate than the first semiconductor region in contact with the first semiconductor region.

[0012] The groove contacts the fourth semiconductor region and the second semiconductor region and reaches the first semiconductor region. The first electrode is arranged inside the groove through an insulating film. The second electrode is electrically connected to the second semiconductor region and the fourth semiconductor region. The third electrode is electrically connected to the fifth semiconductor region. The groove is arranged in plurality at predetermined intervals. The groove includes a gate groove and a dummy groove. The first electrode includes a gate electrode of a gate potential and a dummy gate electrode electrically connected to the second electrode. The gate groove has the gate electrode inside. The dummy groove has the dummy gate electrode inside. The predetermined interval is 0.7 μm to 2 μm. The ratio of the number of the gate grooves to the total number of the grooves is greater than 60% and less than 84%.

[0013] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the impurity concentration of the third semiconductor region is 2×10 14 / cm 3 Above and 5×10 16 / cm 3 the following.

[0014] In addition, the semiconductor device of the present invention is characterized in that, in the above invention, the ratio of the number of the gate trenches to the total number of the trenches is 75% or more. The third semiconductor region includes a first third semiconductor region and a second third semiconductor region having a lower impurity concentration than the first third semiconductor region. The first third semiconductor region is arranged between the gate trench and the dummy trench. The second third semiconductor region is arranged between at least one set of adjacent gate trenches.

[0015] In the semiconductor device of the present invention, the ratio of the number of the gate trenches to the total number of the trenches is 75% or more. The third semiconductor region is not arranged between at least one set of adjacent gate trenches between adjacent dummy trenches.

[0016] Furthermore, in the semiconductor device of the present invention, in the above invention, the third semiconductor region is provided between the depth of the second semiconductor region and the depth of the trench.

[0017] In addition, the semiconductor device of the present invention is characterized in that, in the above invention, the semiconductor substrate has a first element region and a second element region. A first element is arranged in the first element region. A second element is arranged in the second element region in a manner adjacent to the first element region. The first element includes the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, the gate trench, the dummy trench, the gate electrode, the dummy gate electrode, the second electrode, and the third electrode. The second element includes the first semiconductor region, the second semiconductor region, the third semiconductor region, the dummy trench, the dummy gate electrode, the second electrode, the third electrode, and a sixth semiconductor region of the first conductivity type. The sixth semiconductor region is provided in a manner contacting the first semiconductor region at a position closer to the back side of the semiconductor substrate than the first semiconductor region inside the semiconductor substrate. The sixth semiconductor region is electrically connected to the third electrode. The impurity concentration of the sixth semiconductor region is higher than that of the first semiconductor region.

[0018] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, it also has a seventh semiconductor region of the first conductivity type, and the seventh semiconductor region of the first conductivity type is arranged inside the first semiconductor region and between the first semiconductor region and the fifth semiconductor region in a manner of contacting the first semiconductor region, and has an impurity concentration higher than that of the first semiconductor region.

[0019] Technical Effects

[0020] According to the semiconductor device of the present invention, it is possible to improve the di / dt controllability of the collector-emitter current during on-time and suppress oscillation. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a plan view showing the layout of the semiconductor device according to the embodiment as viewed from the front side of the semiconductor substrate.

[0022] Figure 2 It is shown in an enlarged manner Figure 1 A top view of the portion enclosed by the rectangular frame A1.

[0023] Figure 3 It is shown in an enlarged manner Figure 2 A top view of the portion enclosed by the rectangular frame A2.

[0024] Figure 4 It is shown Figure 3 A cross-sectional view of the cross-sectional structure at the cutoff line B1-B1'.

[0025] Figure 5 It is shown Figure 3 A cross-sectional view of the cross-sectional structure at the cutoff line B2-B2'.

[0026] Figure 6 It is shown Figure 2 A cross-sectional view of the cross-sectional structure at the cut-off line C1-C1'.

[0027] Figure 7 It is shown Figure 2 A cross-sectional view of the cross-sectional structure at the cutoff line C2-C2'.

[0028] Figure 8 3D is a perspective view showing the minority carrier density distribution of Reference Example 1.

[0029] Fig. 9 This is a perspective view showing the minority carrier density distribution of Example 1.

[0030] Fig.10 This is a characteristic diagram showing the hole density distribution of Example 1.

[0031] Fig.11 This is a graph showing the integrated value of the hole density in Example 1.

[0032] Fig.12 3 is a characteristic diagram showing the relationship between the ratio of the trench gate and the hole density in Example 1.

[0033] Fig.13 1 is a characteristic diagram showing the relationship between di / dt of the collector-emitter current at the time of on-state and the resistance value of the gate resistor in Examples 1 and 4.

[0034] Fig.14 1 is a characteristic diagram showing the relationship between the conduction loss Eon at the time of conduction and the dV / dt of the collector-emitter voltage at the time of conduction in Example 5.

[0035] Fig.15 This is a cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment.

[0036] Fig.16This is a cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment.

[0037] Fig.17 This is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment.

[0038] Fig.18 3 is a characteristic diagram showing the voltage-current waveform of the conventional example 1.

[0039] Fig.19 It is a perspective view showing the minority carrier density distribution of Conventional Example 1.

[0040] Fig. 20 1 is a characteristic diagram showing the di / dt controllability of the collector-emitter current at the time of conduction in Conventional Example 2.

[0041] Fig.21 3 is a characteristic diagram showing the voltage-current waveform when the conventional example 2 is turned on.

[0042] Fig. 22 3 is a characteristic diagram showing the voltage-current waveform when the conventional example 2 is turned on.

[0043] Explanation of symbols

[0044] 1: Active area

[0045] 2: Edge termination area

[0046] 10: Semiconductor substrate

[0047] 11: Emitter pad

[0048] 12: Gate pad

[0049] 13: Emitter polysilicon layer

[0050] 15: Gate channel

[0051] 20, 20', 30, 80: Semiconductor devices

[0052] 21: Trench gate

[0053] 22: Dummy gate

[0054] 23-25: Countertop area

[0055] 31:n - Drift zone

[0056] 32: p - Base Region

[0057] 33, 33': Accumulation zone

[0058] 34:n + Type Emitter Region

[0059] 35: p + Type contact area

[0060] 36: Groove

[0061] 36a: Gate trench

[0062] 36b: Dummy groove

[0063] 37a, 37b: Gate insulating film

[0064] 38a, 38b: Gate electrodes

[0065] 39: Interlayer insulation film

[0066] 40, 50: contact holes

[0067] 41: Barrier Metal

[0068] 42: Contact plug

[0069] 43: Emitter electrode

[0070] 44:n + Type Buffer

[0071] 45: p + Type collector region

[0072] 46: Collector electrode

[0073] 47:n + Cathode region

[0074] 50: Contact hole

[0075] 51: p + Type Area

[0076] 52: Field oxide film

[0077] 61a:n - The part inside the drift region and directly below the accumulation region

[0078] 61b: Portion of the gate insulating film along the side wall of the gate trench

[0079] 81: IGBT Department

[0080] 82: Diode Department

[0081] d1: The bottom depth of the groove

[0082] d2: p - Depth of base area

[0083] d3:p + Depth of mold area

[0084] t1:n + Type buffer, n - The thickness of the n-type region formed by the sequential stacking of the n-type drift region and the accumulation region

[0085] w1: table width

[0086] X: direction in which the trench extends parallel to the front surface of the semiconductor substrate (first direction)

[0087] Y: A direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction (second direction)

[0088] Z: thickness direction DETAILED DESCRIPTION

[0089] Hereinafter, preferred embodiments of the semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p respectively indicate that electrons or holes are majority carriers. In addition, + and - marked on n and p respectively indicate that the impurity concentration is higher and lower than the impurity concentration of the layer or region not marked with + or -. It should be noted that in the following description of the embodiments and the accompanying drawings, the same symbols are marked for the same configurations, and repeated descriptions are omitted.

[0090] (experiment)

[0091] In the trench gate structure, the IE effect is also enhanced by increasing the channel density by narrowing the interval between the gate trenches. For example, in an IGBT with a gate ratio of 100%, the interval between the configured trenches (hereinafter referred to as the terrace width) is about 2.8 μm or less. The doping amount of ion implantation used to form the accumulation region is 6×10 12 / cm 2 The impurity concentration in the accumulation region is about 5×10 16 / cm 3 about.

[0092] When an IGBT with a gate ratio of 100% is provided with an accumulation region, minority carriers tend to accumulate directly below the accumulation region (on the collector region side) when turned on, and minority carriers in the semiconductor substrate are difficult to be extracted to the emitter electrode. As a result, minority carriers tend to be charged into the parasitic capacitance formed by the gate insulating film between the gate electrode and the semiconductor when turned on.

[0093] If minority carriers are charged into the parasitic capacitance during conduction, the gate voltage (gate-emitter voltage) increases, and the controllability of the collector-emitter current di / dt (current change rate per unit time) based on the gate resistance deteriorates. In addition, if the maximum current value of the collector-emitter current di / dt during conduction is high, the collector-emitter current waveform is prone to oscillation, and the device is prone to shut down at an unexpected time due to malfunction.

[0094] These issues were verified. Fig.18 is a characteristic diagram showing the voltage-current waveform of the prior art example 1. Fig.18 The figure shows that two 16 / cm 3 The operation waveform in the bridge circuit formed by connecting RC-IGBTs (hereinafter referred to as prior art 1) in series with a gate ratio of 100% in the accumulation region. Symbol 102 is the voltage waveform of the collector-emitter voltage VCE(on) when the lower arm (low potential side) RC-IGBT is turned on, and symbol 101 represents the current waveform of the collector-emitter current ICE(on) when the lower arm RC-IGBT is turned on. Symbol 104 is the voltage waveform of the collector-emitter voltage VCE(off) when the upper arm (high potential side) RC-IGBT is turned off, and symbol 103 represents the current waveform of the collector-emitter current ICE(off) when the upper arm RC-IGBT is turned off.

[0095] according to Fig.18 The results shown confirm that in the prior art example 1, when the lower arm RC-IGBT is turned on, the current waveform 101 of the collector-emitter current ICE(on) when the lower arm RC-IGBT is turned on rises, and then the current waveform 101 of the collector-emitter current ICE(on) when the lower arm RC-IGBT is turned on oscillates 101a. In addition, it is confirmed that when the upper arm RC-IGBT is turned off, the current waveform 103 of the collector-emitter current ICE(off) when the upper arm RC-IGBT is turned off is dragged by the collector-emitter current when the lower arm RC-IGBT is turned on and oscillates 103a. The reason why the current waveform of the collector-emitter current ICE of the prior art example 1 oscillates 101a and 103a in this way is verified by simulating the hole density inside the device of the prior art example 1.

[0096] Regarding the conventional example 1, the results of simulating the hole density inside the device at the initial rising stage 101b of the current waveform 101 of the collector-emitter current ICE(on) during the on-time are shown in FIG. Fig.19 .

[0097] Fig.19 is a three-dimensional diagram showing the minority carrier density distribution of the prior art example 1. Fig.19 As shown, it is confirmed that - The portion 118a directly below the accumulation region 113 in the drift region 111 is prone to accumulate holes, and the portion 118b of the gate insulating film 116 along the sidewall of the gate trench 115 is excessively charged with holes. It is presumed that the bridge circuit meets the resonance condition due to the excessive charge, and the current waveforms 101 and 103 of the collector-emitter current ICE oscillate 101a and 103a (see Fig.18 ). On the other hand, in the RC-IGBT with a gate ratio of 100% without the accumulation region 113, no oscillation of the current waveform of the collector-emitter current ICE was confirmed. The reason is presumably because the amount of charge of holes charged into the portion of the gate insulating film 116 along the side wall of the gate trench 115 is low. Symbols 112, 114, and 117 are p - Type base region, p + Type contact area and n + Type emitter region.

[0098] Fig. 20 1 is a characteristic diagram showing the di / dt controllability of the collector-emitter current at the time of conduction by the gate resistance of the conventional example 2. Fig.21 , Fig. 22 3 is a characteristic diagram showing the voltage-current waveform when the conventional example 2 is turned on. Fig. 20 The gate resistance on the horizontal axis and di / dt on the vertical axis are both arbitrary units (au). Fig. 20 In the case of an IGBT having an accumulation region with a gate ratio of 100% (hereinafter referred to as conventional example 2 ( Fig. 20 The figure in the figure is "with accumulation region"), and shows the maximum current value of di / dt when the collector-emitter current of each sample is turned on when two different gate resistors are used. The resistance values ​​of the two different gate resistors are A (arbitrary unit) and 1.7A (arbitrary unit), respectively. Fig. 20 The maximum current values ​​of di / dt of the collector-emitter current at the time of conduction in the conventional example 2 shown are Fig.21 , Fig. 22 The current values ​​of the rising peaks 121a and 121a' of the current waveforms 121 and 121' of the collector-emitter current ICE during the on-time are shown.

[0099] In addition, Fig. 20 FIG. 1 shows an IGBT having a gate ratio of 100% and having no accumulation region (hereinafter referred to as Comparative Example 1). Fig. 20The maximum current value of the collector-emitter current di / dt when the electrode is turned on (the “no accumulation region” in the figure). Fig.21 , Fig. 22 In the example 2 of the related art in which the gate resistor has a resistance value of A (arbitrary unit) and 1.7A (arbitrary unit), the voltage waveforms 123 and 123' of the gate-emitter voltage VGE rise when turned on (parts indicated by symbols 123a and 123a'), and the current values ​​of the peaks 121a and 121a' of the collector-emitter current ICE rise when the current waveforms 121 and 121' are increased. Symbols 122 and 122' are the voltage waveforms of the collector-emitter voltage VCE when turned on.

[0100] according to Fig. 20 The results shown confirm that in the prior art example 2, the maximum current value of the di / dt of the collector-emitter current at the time of conduction is about twice as high as that of the comparative example 1, and the controllability of the di / dt of the collector-emitter current at the time of conduction based on the gate resistance is poor. In addition, in the prior art example 2, it is confirmed that the maximum current value of the di / dt of the collector-emitter current at the time of conduction can be reduced by only about 3% compared with the sample with the gate resistance value set to A (arbitrary unit). It is speculated that in such an IGBT with a gate ratio of 100% having an accumulation region, even if the resistance value of the gate resistance is increased, the di / dt controllability of the collector-emitter current at the time of conduction is deteriorated and it is easily affected by noise, etc.

[0101] The present invention has been completed based on the findings and studies obtained from the experiments.

[0102] (Implementation Method 1)

[0103] The structure of the semiconductor device according to the first embodiment will be described. Figure 1 This is a plan view showing the layout of the semiconductor device according to the first embodiment as viewed from the front side of the semiconductor substrate. Figure 2 It is shown in an enlarged manner Figure 1 A top view of the portion enclosed by the rectangular frame A1. Figure 3 It is shown in an enlarged manner Figure 2 A top view of the portion enclosed by the rectangular frame A2. Figure 4 , Figure 5 are shown separately Figure 3 Cross-sectional view of the cross-sectional structure at the cut-off line B1-B1' and the cut-off line B2-B2'. Figure 6 , Figure 7 are shown separately Figure 2 Cross-sectional view of the cross-sectional structure at the cut-off line C1-C1' and the cut-off line C2-C2'.

[0104] Figure 1 to Figure 7 The semiconductor device 20 of the embodiment 1 shown is an n-channel IGBT monomer having a trench gate structure and an accumulation region (third semiconductor region) 33 in the active region 1 of the semiconductor substrate (semiconductor chip) 10. The trench gate structure is a structure having a MOS gate (hereinafter referred to as a trench gate) 21 with a gate potential and a MOS gate (hereinafter referred to as a dummy gate) 22 with an emitter potential at a predetermined ratio described later. The active region 1 is a region where current flows when the element is in the on state. Figure 1 As shown, the active region 1 has, for example, a substantially rectangular planar shape.

[0105] The edge termination region 2 surrounds the active region 1. The edge termination region 2 is a region between the active region 1 and the end (chip end) of the semiconductor substrate 10, and is a region that relaxes the electric field on the front side of the semiconductor substrate 10 and maintains a withstand voltage (voltage resistance). The withstand voltage refers to the limit voltage that does not cause malfunction or damage to the element. The edge termination region 2 is configured with a field limiting ring (FLR: Field Limiting Ring), a mesa structure, a junction termination extension (JTE: Junction Termination Extension) structure, a field plate and other withstand voltage structures.

[0106] In the active region 1, electrode pads such as an emitter pad 11 and a gate pad 12 are arranged on the front surface of the semiconductor substrate 10 and are separated from each other. The emitter pad 11 covers almost the entire surface of the active region 1 except for the region where the gate pad 12 is arranged. The emitter pad 11 serves as an emitter electrode 43 (see Figures 4 to 7 ) functions. The emitter pad 11 is electrically connected to the dummy gate 22 via the emitter polysilicon (poly-Si) layer 13 (see Figure 2 ).

[0107] The gate pad 12 is connected to the trench gate 21 (see Figure 2 ) is electrically connected. The gate channel 15 is provided in the edge termination region 2 and surrounds the active region 1 in a substantially rectangular shape. The gate channel 15 is formed through a field oxide film 52 (see Figure 7 ) is provided on the front side of the semiconductor substrate 10. Figure 1 , Figure 2 In the figure, the emitter polysilicon layer 13 and the gate channel 15 and other polysilicon layers are indicated by hatching.

[0108] like Figure 2As shown, the trench 36 constituting the trench gate structure is provided in a stripe shape extending in a direction (hereinafter referred to as the first direction) X parallel to the front surface of the semiconductor substrate 10. The ratio of the number (number of roots) of the trenches (gate trenches) 36a constituting the trench gate 21 to the total number (total number of roots) of the trenches 36 is 60% or more and 84% or less. The dummy gate 22 is embedded in the trenches 36 (hereinafter referred to as dummy trenches) 36b other than the gate trenches 36a among all the trenches 36.

[0109] By making the ratio of the number of gate trenches 36a equal to or less than the upper limit, the collector-emitter current waveform does not oscillate during conduction, and the controllability of di / dt of the collector-emitter current based on the gate resistance is improved, as in Comparative Example 1 without the accumulation region 33. By making the ratio of the number of gate trenches 36a equal to or greater than the lower limit, the trade-off relationship between the conduction loss Eon during conduction and the dV / dt (voltage change rate per unit time) of the collector-emitter voltage during conduction can be improved.

[0110] Specifically, in order to satisfy the ratio of the number of the gate trenches 36a described above, the gate trenches 36a and the dummy trenches 36b are alternately arranged in a predetermined number along a direction Y parallel to the front surface of the semiconductor substrate 10 and perpendicular to the first direction X (hereinafter referred to as the second direction). Figure 2 to Figure 7 2 shows a case where one dummy trench 36 b is arranged for every two gate trenches 36 a arranged along the second direction Y. That is, the ratio of the number of gate trenches 36 a to the total number of trenches 36 is approximately 67%. Figure 2 The trench gate 21 and the dummy gate 22 are indicated by bold lines.

[0111] More specifically, although not shown in the figure, when two dummy trenches 36b are arranged for every three gate trenches 36a arranged along the second direction Y, the ratio of the number of gate trenches 36a to the total number of trenches 36 is 60% (=3 / (3+2)×100%). For example, when one dummy trench 36b is arranged for every three gate trenches 36a arranged along the second direction Y, the ratio of the number of gate trenches 36a to the total number of trenches 36 is 75% (=3 / (3+1)×100%).

[0112] For example, when one dummy trench 36b is arranged for every four gate trenches 36a arranged along the second direction Y, the ratio of the number of gate trenches 36a to the total number of trenches 36 is 80% (=4 / (4+1)×100%). For example, when one dummy trench 36b is arranged for every five gate trenches 36a arranged along the second direction Y, the ratio of the number of gate trenches 36a to the total number of trenches 36 is approximately 83% (≈5 / (5+1)×100%).

[0113] The ratio of the number of gate trenches 36 a relative to the total number of trenches 36 is determined by taking the following characteristics into consideration.

[0114] The first characteristic is the trade-off between the on-state voltage and the short-circuit withstand capability. This is because the ratio of the number of gate trenches 36a to the total number of trenches 36 increases. + The type emitter region 34 is implanted into the n - The more the carrier injection amount of the drift region 31 increases, the better the on-state voltage is, but the short-circuit withstand capability decreases. The second characteristic is that the input capacitance (the sum of the gate-emitter capacitance and the gate-collector capacitance) and the feedback capacitance (gate-collector capacitance) increase as the ratio of the number of gate trenches 36a to the total number of trenches 36 increases, and the switching loss increases due to the increase in the Miller period for charging these parasitic capacitances.

[0115] The gate-collector capacitance of the parasitic capacitance of these IGBTs can be reduced by changing n + Type buffer 44, n - The thickness t1 of the n-type region formed by stacking the drift region 31 and the accumulation region 33 in sequence becomes smaller as the thickness t1 of the n-type region becomes thicker. The reason for this is that the thicker the thickness t1 of the n-type region, the greater the difference between the first gate electrode 38a and the p-type region in the thickness direction Z. + If the gate-collector capacitance is reduced, even if the gate-emitter capacitance is increased by increasing the ratio of the number of gate trenches 36a to the total number of trenches 36, the di / dt controllability of the collector-emitter current at turn-on based on the gate resistance can be suppressed from being deteriorated.

[0116] Specifically, although the ratio of the gate trenches 36a to the total number of the trenches 36 varies depending on whether the resistance value of the gate resistor can be adjusted, for example, in the case of a withstand voltage of 600 V, n is set to n. + Type buffer 44, n - The thickness t1 of the n-type region formed by sequentially stacking the n-type drift region 31 and the accumulation region 33 is thin, so the ratio of the gate trench 36a to the total number of the trenches 36 is, for example, 67%. +Type buffer 44, n - The thickness t1 of the n-type region formed by sequentially stacking the n-type drift region 31 and the accumulation region 33 becomes 1.5 to 2 times thicker than that of the 600V withstand voltage level. Therefore, the ratio of the number of gate trenches 36a to the total number of trenches 36 can reach 80%, for example.

[0117] In the case of low withstand voltage, by + Type buffer 44, n - The thickness t1 of the n-type region formed by sequentially stacking the n-type drift region 31 and the accumulation region 33 becomes thinner, thereby increasing the feedback capacitance. Therefore, in order to improve the di / dt controllability of the collector-emitter current based on the gate resistance during conduction, the ratio of the number of gate trenches 36a to the total number of trenches 36 can be reduced to reduce the gate-emitter capacitance. The thickness t1 of the n-type region refers to the thickness of the n-type region from the p - The interface between the base region 32 and the accumulation region 33 is n + Type buffer 44 and p + The distance to the interface of the collector region 45.

[0118] All trenches 36 extend from active region 1 to edge termination region 2 and terminate in edge termination region 2. The end of gate trench 36a is opposite to gate flow channel 15 in thickness direction Z. At the end of gate trench 36a, first gate electrode (gate electrode in first electrode) 38a (refer to Figures 4 to 7 ) is connected to the gate channel 15. The gate trench 36a may have a ring-shaped planar shape in which the ends of the gate trenches 36a adjacent to each other in the second direction Y are connected.

[0119] The end of the dummy trench 36b ends at the active region 1 side relative to the gate flow channel 15. The end of each dummy trench 36b faces different emitter polysilicon layers 13 in the thickness direction Z. At the end of the dummy trench 36b, a second gate electrode (dummy gate electrode in the first electrode) 38b (see Figures 4 to 7 ) is electrically connected to the emitter pad 11 via the emitter polysilicon layer 13. The emitter polysilicon layer 13 is spread along the boundary between the active region 1 and the edge termination region 2, for example, closer to the active region 1 than the gate runner 15.

[0120] like Figure 3 As shown, in the mesa region 23 between adjacent gate trenches 36a and between adjacent gate trenches 36a and dummy trenches 36b (mesa region 24), the mesa regions 23 and 24 are provided with n in the same configuration. + type emitter region (fourth semiconductor region) 34 and p + Type contact area 35. + type emitter region 34 and p+ The type contact regions 35 are arranged along the first direction X in an alternating and repeated manner. Figure 3 Different shadows are used to represent n + type emitter region 34 and p + Type contact area 35.

[0121] n + The emitter region 34 and the p + The contact regions 35 are separated in the first direction X. + The emitter region 34 and the p + Between the type contact regions 35, a p - The p-type base region (second semiconductor region) 32 may not be formed on the front surface of the semiconductor substrate 10. - The base region 32 is exposed, and the n-type base region 32 adjacent to the first direction X is + The p-type emitter region 34 is exposed on the entire front surface of the semiconductor substrate 10. + type contact area 35. In this case, due to p + The contact area between the type contact region 35 and the emitter electrode 43 is increased, so that the n - The function of extracting holes in the drift region 31 to the emitter electrode 43 .

[0122] n + type emitter region 34 and p + The type contact region 35 extends to the side wall of the adjacent trench 36 in the second direction Y. + The type emitter region 34 may not be provided in the mesa region 24 adjacent to the dummy trench 36b. + type emitter region 34 and p + The contact hole 40 extends linearly in the first direction X in each of the mesa regions 23 and 24. Figure 2 In FIG. 1 , the contact hole 40 is a portion surrounded by a U-shaped dotted line.

[0123] Next, the cross-sectional structure of the semiconductor device 20 according to the first embodiment will be described. Figure 4 , Figure 5 As shown, inside the semiconductor substrate 10, n are arranged from the active area 1 to the edge termination area 2. - A p type drift region (first semiconductor region) 31 is provided on the surface layer of the front side of the semiconductor substrate 10 over the entire active region 1. - Type base region 32. p - The base region 32 is n - The interior of the semiconductor substrate 10 is provided with a -The type drift region 31 is located closer to the front side of the semiconductor substrate 10. - Type drift region 31 and p - An accumulation region 33 is provided between the base regions 32 so as to extend over the entire active region 1 .

[0124] The accumulation region 33 is of conductivity type n - The type drift region 31 is the same and the impurity concentration is n - The n-type drift region 31 is a high n-type region. When turned on, minority carriers are accumulated in the accumulation region 33. In the case of an n-channel IGBT, the minority carriers are holes. By accumulating minority carriers in the accumulation region 33 when turned on, the IE (electron injection enhancement) effect is improved and the conduction loss is reduced. In addition, by providing a dummy gate 22, the IE effect can be suppressed from becoming too high due to the accumulation region 33.

[0125] Accumulation area 33 and n - Type drift region 31 and p - In addition, the accumulation region 33 is connected to the p-type base region 32. - Type base region 32 and n - The interface of the drift region 31 is from the collector side (p + Specifically, the accumulation region 33 extends from the p-type collector region 45 side to a deeper position. - The accumulation region 33 may be located from the depth d2 of the base region 32 to the depth d1 of the bottom surface of the trench 36. - The depth d2 of the base region 32 is set to the depth d1 of the bottom surface of the trench 36. - The depth d2 of the base region 32 is configured to the depth d1 of the bottom surface of the trench 36, so that the parasitic capacitance area formed by the first gate insulating film 37a between the first gate electrode 38a and the semiconductor when turned on becomes smaller, so the charge amount of holes charged into the parasitic capacitance can be reduced.

[0126] The impurity concentration of the accumulation region 33 is, for example, 2×10 14 / cm 3 Above and 5×10 16 / cm 3 When the impurity concentration of the accumulation region 33 is higher than the upper limit, the oscillation of the current waveform between the collector and the emitter during conduction cannot be suppressed, which is not preferred. The higher the impurity concentration of the accumulation region 33 is, the easier it is to accumulate minority carriers during conduction, which can reduce the on-resistance. When the impurity concentration of the accumulation region 33 is lower than the lower limit, the IE effect becomes weak and the predetermined characteristics cannot be obtained, which is not preferred.

[0127] In p -Inside the base region 32, n + type emitter region 34 and p + The trench 36 penetrates the semiconductor substrate 10 in the thickness direction Z from the front surface of the semiconductor substrate 10. + Type emitter region 34, p + Type contact area 35 and p - type base region 32 and reaches n - Type drift region 31. In each mesa region 23, 24, in p - Type base region 32 and n - An accumulation region 33 is arranged between the n-type drift regions 31. + Type emitter region 34, p + Type contact area 35, p - The base region 32 and the accumulation region 33 extend to two adjacent trenches 36 sandwiching the mesa regions 23 and 24 in the second direction Y.

[0128] A first gate electrode 38a of gate potential is provided inside a gate trench 36a among the plurality of trenches 36 via a first gate insulating film 37a, and the gate trench 36a, the first gate insulating film 37a, and the first gate electrode 38a constitute a trench gate 21. A second gate electrode 38b of emitter potential is provided inside a dummy trench 36b among the plurality of trenches 36 via a second gate insulating film 37b, and the dummy trench 36b, the second gate insulating film 37b, and the second gate electrode 38b constitute a dummy gate 22.

[0129] The interval (terrace width) w1 of the configuration groove 36 is miniaturized to be narrower, for example, to the extent of 0.7 μm to 2 μm. As a result, since the hole density becomes higher, the IE effect can be improved and the on-resistance can be reduced. The narrower the terrace width w1 is set, the greater the hole density is, so the current waveform of the collector-emitter current becomes easier to oscillate. Therefore, by making the number of gate grooves 36a relative to the total number of grooves 36 the above ratio, the current waveform oscillation of the collector-emitter current can be suppressed.

[0130] The interlayer insulating film 39 is provided on the front surface of the semiconductor substrate 10 and covers the first gate electrode 38a and the second gate electrode 38b. In the interlayer insulating film 39, contact holes 40 are provided in each of the mesa regions 23 and 24, respectively, penetrating the interlayer insulating film 39 in the thickness direction Z and reaching the semiconductor substrate 10. The contact holes 40 are arranged in each of the mesa regions 23 and 24 in a straight line extending in the first direction X, for example, terminating at the boundary between the active region 1 and the edge termination region 2 (see Figure 2 In each of the mesa regions 23 and 24, p is exposed in the contact hole 40. -Type base region 32, n + type emitter region 34 and p + Type contact area 35.

[0131] A barrier metal 41 is provided along the front surface of the semiconductor substrate 10 exposed in the contact hole 40 and the surface of the interlayer insulating film 39. The barrier metal 41 includes a metal that has a high degree of close adhesion to the semiconductor portion (semiconductor substrate 10) and makes ohmic contact with the semiconductor portion. Specifically, the barrier metal 41 can be a laminated film in which, for example, a titanium (Ti) film and a titanium nitride (TiN) film are laminated in sequence. A contact plug 42 is provided on the barrier metal 41 in a manner buried in the contact hole 40.

[0132] The contact plug 42 is made of a metal film of tungsten (W) with high embedding properties. The emitter electrode (second electrode) 43 is provided on the entire front surface of the semiconductor substrate 10 in the active region 1. The emitter electrode 43 is connected to the p-type active region 1 via the contact plug 42 and the barrier metal 41. - Type base region 32, n + type emitter region 34 and p + The emitter electrode 43 is electrically connected to the type contact region 35. The emitter electrode 43 is, for example, an aluminum silicon (Al—Si) electrode. The emitter electrode 43 functions as the emitter pad 11.

[0133] On the back side of the semiconductor substrate 10, n + Type buffer 44 and p + Type collector region (fifth semiconductor region) 45. + Type buffer 44 in n - Type drift region 31 and p + The collector region 45 is arranged to extend from the active region 1 to the edge termination region 2. + The collector region 45 is exposed on the back surface of the semiconductor substrate 10 and is provided in a manner extending from the active region 1 to the edge termination region 2. The collector electrode (third electrode) 46 is connected to the p + The collector region 45 is in contact with the p + The collector region 45 is electrically connected.

[0134] like Figure 6 As shown, in the edge termination region 2, a p + Type area 51. p + The type region 51 is arranged along the boundary between the active region 1 and the edge termination region 2 and surrounds the active region 1. + The depth d3 of the type region 51 may be deeper than the depth d1 of the bottom surface of the trench 36. All trenches 36 extend from the active region 1 to the edge termination region 2 and are located at the p + The internal end of the type region 51. +The region 51 is located further outward (toward the end of the semiconductor substrate 10) so as to be aligned with the p + The mold area 51 is separated in a manner such that a pressure-resistant structure (not shown) is provided.

[0135] In addition, in the edge termination region 2, an emitter polysilicon layer 13 is provided on the front surface of the semiconductor substrate 10 in such a manner as to cover the second gate electrode 38b at the end of the dummy trench 36b. The emitter polysilicon layer 13 is in contact with the second gate electrode 38b at the end of the dummy trench 36b and is electrically connected to the second gate electrode 38b. The emitter polysilicon layer 13 penetrates the interlayer insulating film 39 in the thickness direction Z and reaches the contact hole 50 of the semiconductor substrate 10 and is exposed.

[0136] In the contact hole 50, a barrier metal 41 and a contact plug 42 are provided similarly to the contact hole 40 of the active region 1. The second gate electrode 38b is electrically connected to the emitter electrode 43 via the emitter polysilicon layer 13 and the contact plug 42 and the barrier metal 41 in the contact hole 50. In addition, in the edge termination region 2, a gate runner 15 is provided on the front surface of the semiconductor substrate 10 via a field oxide film 52.

[0137] The gate runner 15 is provided at a position closer to the end of the semiconductor substrate 10 than the emitter polysilicon layer 13 and is separated from the emitter polysilicon layer 13. The gate runner 15 is in contact with the first gate electrode 38a at the end of the gate trench 36a and is electrically connected to the first gate electrode 38a. The end of the first gate electrode 38a may be extended on the field oxide film 52 at the end of the gate trench 36a, and the extended portion of the end of the first gate electrode 38a may be in contact with the gate runner 15.

[0138] As described above, according to Embodiment 1, when conducting, the portion of the accumulation region that faces the dummy gate across the second gate insulating film of the sidewall of the dummy trench is inverted to p-type, and holes in the semiconductor substrate are extracted from the dummy gate to the emitter electrode via the inversion layer. - The hole density in the portion directly below the accumulation region inside the drift region is reduced. Therefore, the amount of charge of holes charged into the parasitic capacitance formed by the first gate insulating film between the first gate electrode and the semiconductor during conduction can be reduced.

[0139] Furthermore, according to the first embodiment, by reducing the amount of charge of holes charged to the parasitic capacitance formed by the first gate insulating film, the increase in gate voltage (gate-emitter voltage) can be eliminated, and the di / dt of the collector-emitter current can be reduced. As a result, the di / dt controllability of the collector-emitter current based on the gate resistance is improved. In addition, since the di / dt of the collector-emitter current is reduced, the oscillation of the collector-emitter current waveform during conduction is suppressed.

[0140] According to Embodiment 1, the improvement of the di / dt controllability of the collector-emitter current at the time of conduction based on the gate resistance and the suppression of the oscillation of the collector-emitter current waveform at the time of conduction can be achieved by making the ratio of the number of gate trenches to the total number of trenches 60% or more and 84% or less. In addition, by increasing the ratio of the number of gate trenches to the total number of trenches, the IE effect can be improved and the channel density can be increased. Therefore, the conduction loss can be reduced.

[0141] (Experiment 1)

[0142] Next, the hole density reduction effect by the dummy trench 22 was verified. Figure 8 3D is a perspective view showing the minority carrier density distribution of Reference Example 1. Fig. 9 is a perspective view showing the minority carrier density distribution of Example 1. The trench gate structure having the trench gate 21 and the dummy gate 22 and the impurity concentration of 5×10 16 / cm 3 The initial rising period (with the same as the rising period) of the collector-emitter current ICE when the two IGBTs (hereinafter referred to as Reference Example 1 and Example 1) in the accumulation region 33 are simulated. Fig.18 The results obtained by measuring the hole density inside the device (inside the semiconductor substrate 10) during the period corresponding to the symbol 101b' are shown in FIG. Figure 8 , Fig. 9 .

[0143] Figure 8 , Fig. 9 Reference Example 1 and Example 1 shown are examples in which the ratio of the number of gate trenches 36 a to the total number of trenches 36 is set to 50% and 60%, respectively. Figure 8 In the reference example 1 shown in the figure, the gate trenches 36a and the dummy trenches 36b are repeatedly arranged alternately along the second direction Y ( Figure 8 , 10 , 11, and 13 are illustrated as “gate ratio 50%, with accumulation region”). Fig. 9 In the first embodiment shown, one dummy trench 36b is arranged for every two gate trenches 36a arranged along the second direction Y ( Figures 9 to 11 (The figure shows "gate ratio 67%, accumulation region present"). The configurations of Reference Example 1 and Example 1 are the same as those of the semiconductor device 20 of the above-described embodiment except for the number of gate trenches 36a.

[0144] according to Figure 8 , Fig. 9 The results shown in FIG. 1 confirm that both Reference Example 1 and Example 1 extract holes from the dummy gate 22, thereby preventing holes from accumulating in the mesa region 24 adjacent to the dummy trench 36b. - The portion 61a of the inner portion of the type drift region 31 and directly below the accumulation region 33 is confirmed. Therefore, it was confirmed that the hole density around the dummy gate 22 can be suppressed by providing the dummy gate 22 in the trench gate IGBT.

[0145] (Experiment 2)

[0146] Next, the results of simulating the hole density of the portion 61b around the first gate insulating film 37a and along the side wall of the gate trench 36a for the above-mentioned Example 1 ("gate ratio 67%, with accumulation region") are shown in FIG. Fig.10 , Fig.11 . Fig.10 This is a characteristic diagram showing the hole density distribution of Example 1. Fig.11 This is a graph showing the integrated value of the hole density in Example 1.

[0147] exist Fig.10 The horizontal axis of represents the depth with the front surface of the semiconductor substrate 10 being the depth=0 μm. Fig.10 The range indicated by the double arrow in FIG. 1 represents the depth of the gate trench 36 a from the front surface of the semiconductor substrate 10 . Fig.11 It is an integrated value of the hole density from the front surface of the semiconductor substrate 10 to the depth of the gate trench 36 a .

[0148] also, Fig.10 , Fig.11 The above-mentioned reference example 1 ("gate ratio 50%, with accumulation region") and conventional example 1 ("gate ratio 100%, with accumulation region") are shown in FIG. Fig.19 ) and Comparative Example 1 ("gate ratio 100%, no accumulation region": structure diagram not shown) also simulated the same position as Example 1 (equivalent to Figure 8 The symbol 61b is equivalent to Fig.19 The result obtained by comparing the hole density of symbol 118b (not shown in Comparative Example 1).

[0149] according to Fig.10 , Fig.11The results shown confirm that Example 1, Reference Example 1, and Comparative Example 1 can reduce the integrated value of the hole density of the portion 61b of the first gate insulating film 37a along the side wall of the gate trench 36a compared to Conventional Example 1. In addition, it is confirmed that in Example 1 and Reference Example 1, the hole density of the portion 61b of the first gate insulating film 37a along the side wall of the gate trench 36a can be made less than the integrated value of the hole density at the same position in Comparative Example 1.

[0150] In Comparative Example 1, since there is no accumulation region, the current waveform of the collector-emitter current ICE does not oscillate during conduction, and the controllability of the collector-emitter current di / dt based on the gate resistance is good. In Example 1 and Reference Example 1, by making the hole density of the portion 61b of the first gate insulating film 37a along the side wall of the gate trench 36a less than the integral value of the hole density at the same position in Comparative Example 1, the same effect as in Comparative Example 1 can be obtained, and the IE effect can be improved by the accumulation region 33.

[0151] (Experiment 3)

[0152] Next, the ratio of the number of gate trenches 36 a to the total number of trenches 36 (hereinafter referred to as the ratio of trench gates 21 ) was verified. Fig.12 3 is a characteristic diagram showing the relationship between the ratio of the trench gate and the hole density in Example 1. Fig.12 Graphs are provided showing data points obtained by simulating the integrated value of the hole density of the portion 61b of the first gate insulating film 37a along the side wall of the gate trench 36a in the above-mentioned Example 1 ("gate ratio 67%, with accumulation region").

[0153] also, Fig.12 The data points obtained by simulating the integral value of the hole density of the gate insulating film 37a, 116 along the side wall 61b, 118b of the gate trench 36a, 115 of the reference example 1 ("gate ratio 50%, with accumulation area") and the conventional example 1 ("gate ratio 100%, with accumulation area") are shown in the figure. Fig.12 The graph in FIG. 2 shows the data points of the integrated value of the hole density when the ratio of the trench gate is 50%, 67%, and 100%. Fig.12 An approximate straight line 71 showing the relationship between the trench gate ratio and the hole density calculated based on these three data points is shown in FIG.

[0154] according to Fig.12The approximate straight line 71 representing the relationship between the ratio of the trench gate and the hole density confirms that in the present invention, the integral value of the hole density of the portion 61b of the first gate insulating film 37a along the side wall of the gate trench 36a becomes larger in proportion to the size of the ratio of the trench gate 21 as the ratio of the trench gate 21 increases. In addition, it is confirmed that when the ratio of the trench gate is 84%, the integral value of the hole density of the portion 61b of the first gate insulating film 37a along the side wall of the gate trench 36a of Example 1 is equal to the integral value of the hole density at the same position of Comparative Example 1 ( Fig.12 The same as the value indicated by straight line 70 in FIG.

[0155] Therefore, it was confirmed that in the present invention, in order to make the integral value of the hole density of the portion 61b of the first gate insulating film 37a along the side wall of the gate trench 36a less than the integral value of the hole density at the same position in Comparative Example 1, it is sufficient to make the ratio of the trench gate 21 Fig.12 The upper limit of the range indicated by the double arrow in FIG. 1 may be 84% or less. Fig.12 The range of the ratio of the trench gate 21 indicated by the double arrow in FIG. 1 is a preferred range of the ratio of the trench gate 21 of the present invention. The ratio of the trench gate 21 is set to

[0156] Fig.12 The reason why the lower limit of the range indicated by the double arrow is 60% or more will be described in Example 5 described later.

[0157] (Experiment 4)

[0158] Next, an approximate curve based on data points obtained by simulation is shown in FIG. 1 for the relationship between the resistance value of the gate resistor and the di / dt of the collector-emitter current during on-state. Fig.13 . Fig.13 1 is a characteristic diagram showing the relationship between di / dt of the collector-emitter current at the time of on-state and the resistance value of the gate resistor in Examples 1 and 4. Fig.13 The horizontal axis is the resistance value of the gate resistor, and the vertical axis is the maximum current value of the di / dt of the collector-emitter current when it is turned on.

[0159] Fig.13 The results of simulations of the above-mentioned Example 1 (gate ratio 67%, with accumulation region), Reference Example 1 (gate ratio 50%, with accumulation region), Comparative Example 1 (gate ratio 100%, without accumulation region) and Conventional Example 1 (gate ratio 100%, with accumulation region) are shown. In addition, Fig.13 2 shows the simulation results of Reference Example 2 and Conventional Example 2, in which only the impurity concentration of the accumulation region 113 is different from that of Reference Example 1 and Conventional Example 1, respectively. The impurity concentration of each accumulation region 33, 113 in Reference Example 2 and Conventional Example 2 is 2×1016 / cm 3 .

[0160] Fig.13 In the notes, Comparative Example 1 is illustrated as "gate ratio 100%, no accumulation region". Existing Examples 1 and 2 are described as "gate ratio 100%, with accumulation region", Reference Examples 1 and 2 are described as "gate ratio 50%, with accumulation region", and Example 1 is described as "gate ratio 67%, with accumulation region".

[0161] according to Fig.13 The results shown confirm that the conventional examples 1 and 2 without the dummy gate have a higher di / dt of the collector-emitter current when turned on, regardless of the resistance value of the gate resistor, compared with the comparative example 1 with the same resistance value of the gate resistor. On the other hand, it is confirmed that the embodiment 1 and the reference examples 1 and 2 with the dummy gate 22 can make the di / dt of the collector-emitter current when turned on equal to or lower than that of the comparative example 1 with the same resistance value of the gate resistor, regardless of the resistance value of the gate resistor Rg. Fig.13 In the figure, a broken line showing the characteristics of Example 1, Reference Examples 1 and 2, and Comparative Example 1 is indicated by reference numeral 72 .

[0162] Therefore, it was confirmed that in Example 1 and Reference Examples 1 and 2, the controllability of di / dt of collector-emitter current at turn-on based on gate resistance was as good as that in Comparative Example 1. In addition, regardless of the resistance value of the gate resistance, Reference Examples 1 and 2 had lower di / dt of collector-emitter current at turn-on than Example 1 under the same conditions of the resistance value of the gate resistance. Therefore, it was confirmed that the controllability of di / dt of collector-emitter current at turn-on based on gate resistance could be improved by reducing the impurity concentration of the accumulation region 33. The effect obtained by reducing the impurity concentration of the accumulation region 33 can also be obtained in Example 1.

[0163] (Experiment 5)

[0164] Next, an approximate curve based on data points obtained by simulation is shown in FIG. 1 for the relationship between the conduction loss Eon during conduction and the collector-emitter voltage dV / dt during conduction. Fig.14 . Fig.14 1 is a characteristic diagram showing the relationship between the conduction loss Eon at the time of conduction and the dV / dt of the collector-emitter voltage at the time of conduction in Example 5. Fig.14 2 shows the results of simulations of Example 5 and the above-mentioned Reference Example 1. Example 5 is an example in which the ratio of the trench gate 21 in Example 1 is set to 60%. Fig.14 The ratio of the trench gate 21 is in the parentheses of the annotation.

[0165] according to Fig.14 The results shown in FIG. 1 confirm that Example 5 (the ratio of the trench gate 21 is 60%) can reduce both the conduction loss Eon and the collector-emitter voltage dV / dt when conducting compared to Reference Example 1 (the ratio of the trench gate 21 is 50%). That is, the larger the ratio of the trench gate 21 (the closer the approximate curve is to Fig.14 The more it moves in the direction indicated by the arrow 73, the more it can reduce the conduction loss Eon and the dV / dt of the collector-emitter voltage during conduction.

[0166] Although not shown in the figure, it was confirmed that when the ratio of the trench gate 21 was set to be greater than 75%, the dV / dt of the collector-emitter voltage during conduction became higher, and the trade-off relationship between the conduction loss Eon during conduction and the dV / dt of the collector-emitter voltage during conduction became worse. Therefore, considering the trade-off relationship between the conduction loss Eon during conduction and the dV / dt of the collector-emitter voltage during conduction, the ratio of the trench gate 21 is preferably 60% or more and 75% or less.

[0167] (Implementation Method 2)

[0168] Next, the structure of the semiconductor device according to the second embodiment will be described. Fig.15 , Fig.16 This is a cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment. Fig.15 , Fig.16 Shown in Figure 3 The cross-sectional structure at a position corresponding to the cut-off line B1-B1'. Figure 3 The cutoff line B2-B2', Figure 2 The truncation line C1-C1' and Figure 2 The cross-sectional structures at the positions corresponding to the truncation line C2-C2' are respectively Figure 5 to Figure 7 The arrangement of the middle accumulation region 33, the gate trench 36a and the dummy trench 36b is set to be similar to Fig.15 , Fig.16 The same structure is obtained.

[0169] Fig.15 The semiconductor device 20' of the second embodiment shown in the figure is different from the semiconductor device 20 of the first embodiment in the following two points. The first difference is that three or more gate trenches 36a are arranged between the dummy trenches 36b adjacent to each other in the second direction Y so as to be adjacent to each other in the second direction Y. That is, Fig.15 In the semiconductor device 20 ′ according to the second embodiment shown, the ratio of the number of gate trenches 36 a to the total number of trenches 36 (gate ratio) is 75% or more.

[0170] The second difference is that the impurity concentration of the accumulation region 33' of one or more mesa regions 23 (hereinafter referred to as the second accumulation region) among the two or more mesa regions 23 adjacent to each other in the second direction Y between the dummy trenches 36b adjacent to each other in the second direction Y is set to be lower than the impurity concentration of the accumulation region 33 of the remaining mesa regions 23 and 24 (hereinafter referred to as the first accumulation region). That is, the impurity concentration of the second accumulation region 33' is lower than the impurity concentration of the first accumulation region 33 and lower than the impurity concentration of the second accumulation region 33. - The impurity concentration of the type drift region 31 is high.

[0171] like Fig.16 As shown, the accumulation region 33 may be arranged in one or more of the two or more mesa regions 23 adjacent to each other in the second direction Y, not between the dummy trenches 36 b adjacent to each other in the second direction Y. That is, Fig.16 The semiconductor device 30 of the second embodiment shown in FIG. Fig.15 The semiconductor device 20 ′ of the second embodiment shown is different in that the second accumulation region 33 ′ is not provided.

[0172] As described above, according to the second embodiment, by partially reducing the impurity concentration of the accumulation region or not providing a part of the accumulation region, the controllability of di / dt of the collector-emitter current at the time of conduction by the gate resistance can be improved similarly to the first embodiment.

[0173] (Implementation 3)

[0174] Next, the structure of the semiconductor device according to the third embodiment will be described. Fig.17 2 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 3. A semiconductor device 80 according to Embodiment 3 is obtained by applying the semiconductor device 20 according to Embodiment 1 to an IGBT portion 81 of an RC-IGBT. In Embodiment 3, a diode connected in reverse parallel to the IGBT is provided in an active region 1 of the same semiconductor substrate 10 as the IGBT having the structure of the semiconductor device 20 according to Embodiment 1.

[0175] Specifically, Fig.17 The semiconductor device 80 of the third embodiment shown in the figure has an IGBT unit 81 and a diode unit 82 in the active region 1 of the semiconductor substrate 10. The IGBT unit 81 is provided with an IGBT. The configuration of the IGBT in the IGBT unit 81 is similar to that of the semiconductor device 20 of the first embodiment (see FIG. 2 ). Figure 3 to Figure 7 The diode unit 82 is provided with a diode connected in reverse parallel to the IGBT of the IGBT unit 81 .

[0176] The diode portion 82 is provided with a dummy trench 36b extending in parallel with the trench gate 21 of the IGBT portion 81 in a stripe shape. In the dummy trench 36b, a second gate electrode 38b of emitter potential is provided via a second gate insulating film 37b as in the first embodiment, and the dummy gate 22 is formed by the dummy trench 36b, the second gate insulating film 37b, and the second gate electrode 38b.

[0177] Since the trench gate structure of the diode part 82 is entirely a dummy gate 22, the di / dt controllability based on the gate resistance is better than that of the IGBT alone. Therefore, in the IGBT 81, the ratio of the number of gate trenches 36a to the total number of trenches 36 can be increased. The ratio of the number of gate trenches 36a in the IGBT part 81 to the total number of trenches 36 is 60% or more and 84% or less.

[0178] In the diode portion 82, a p-type electrode is provided between the dummy trenches 36b adjacent to each other in the second direction Y (the mesa region 25). - The p-type base region 32 and the accumulation region 33. The p-type base region 32 and the accumulation region 33 of the diode portion 82 are - The composition of the base region 32 and the accumulation region 33 is consistent with that of the p-type base region 32 and the accumulation region 33 in the other mesa regions 23 and 24. - The base region 32 and the accumulation region 33 are the same. - The base region 32 functions as an anode region.

[0179] No n is provided in the mesa region 25 of the diode portion 82. + Although not shown in the figure, a p-type emitter region 34 may be provided in the mesa region 25 of the diode portion 82. + The p-type contact area 35. The p-type contact area 35 in the mesa area 25 - The base region 32 and the p-type base region 32 in the other mesa regions 23 and 24 - Similarly, the base region 32 is electrically connected to the emitter electrode 43 via the barrier metal 41 and the contact plug 42. The emitter electrode 43 also serves as an anode electrode.

[0180] On the back side of the semiconductor substrate 10, the diode portion 82 is provided with an n + Type cathode region (sixth semiconductor region) 47. + The cathode region 47 is disposed on the back side of the semiconductor substrate 10 and the n + The p-type buffer 44 is provided between the IGBT portion 81 and is exposed on the back surface of the semiconductor substrate 10. + The collector region 45 and the n + The cathode region 47 is adjacent to the collector electrode 46 in the second direction Y. + The cathode region 47 is in contact with the n +The collector electrode 46 also serves as a cathode electrode.

[0181] Embodiment 2 may be applied to semiconductor device 80 according to Embodiment 3, and the layout of accumulation region 33 may be changed.

[0182] As described above, according to the third embodiment, even when the semiconductor device of the first embodiment is applied to the RC-IGBT, the same effect as that of the first embodiment can be obtained for the IGBT constituting the RC-IGBT. As a result, it is possible to suppress the oscillation of the current waveform of the collector-emitter current ICE of the partial IGBT unit (functional unit of the IGBT) separated from the diode portion in the IGBT portion at the time of conduction.

[0183] As mentioned above, the present invention is not limited to the above-mentioned embodiment, and various changes can be made within the scope not departing from the gist of the present invention. + type emitter region and p + The arrangement of the n-type contact region can be changed in various ways, and there may be a case where the n-type contact region is arranged so as to reach only one side wall of the adjacent trench. + In addition, in each of the above-mentioned embodiments, an IGBT monomer or an RC-IGBT is described, but it is not limited thereto and can also be applied to a semiconductor device having an IGBT portion configured with an IGBT. In addition, the present invention is also applicable even if the conductivity type (n-type, p-type) is reversed.

[0184] Industrial Applicability

[0185] As described above, the semiconductor device of the present invention is useful as a power semiconductor device used in a power conversion device, a power supply device for various industrial machines, and the like.

Claims

1. A semiconductor device, characterized in that: have: A first semiconductor region of a first conductivity type is disposed inside the semiconductor substrate; A second semiconductor region of a second conductivity type provided inside the semiconductor substrate and closer to the front side of the semiconductor substrate than the first semiconductor region; A third semiconductor region of the first conductivity type is provided inside the first semiconductor region in a manner of contacting with the second semiconductor region and has a higher impurity concentration than the first semiconductor region; A fourth semiconductor region of the first conductivity type, selectively disposed inside the second semiconductor region; a fifth semiconductor region of the second conductivity type provided in contact with the first semiconductor region and located within the semiconductor substrate and closer to the back side of the semiconductor substrate than the first semiconductor region; A buffer zone of a first conductivity type, disposed on the back side of the semiconductor substrate; a trench, contacting the fourth semiconductor region and the second semiconductor region and reaching the first semiconductor region; A first electrode is disposed inside the groove via an insulating film; a second electrode electrically connected to the second semiconductor region and the fourth semiconductor region; as well as a third electrode electrically connected to the fifth semiconductor region, The grooves are arranged in plurality at predetermined intervals. The trenches include gate trenches and dummy trenches, The first electrode includes a gate electrode of gate potential and a dummy gate electrode electrically connected to the second electrode, The gate trench has the gate electrode inside. The dummy trench has the dummy gate electrode inside. The predetermined interval is 0.7 μm to 2 μm, The ratio of the number of the gate trenches to the total number of the trenches is greater than or equal to 60% and less than or equal to 84%, The ratio of the number of the gate trenches to the total number of the trenches can be increased as the thickness of the region in which the buffer region, the first semiconductor region, and the third semiconductor region are sequentially stacked becomes thicker.

2. The semiconductor device according to claim 1, wherein: The impurity concentration of the third semiconductor region is 2×10 14 / cm 3 Above and 5×10 16 / cm 3 the following.

3. The semiconductor device according to claim 1, wherein: The ratio of the number of the gate trenches to the total number of the trenches is greater than 75%, The third semiconductor region includes a first third semiconductor region and a second third semiconductor region having a lower impurity concentration than the first third semiconductor region, The first third semiconductor region is arranged between the gate trench and the dummy trench. The second third semiconductor region is arranged between at least one group of adjacent gate trenches.

4. The semiconductor device according to claim 2, wherein: The ratio of the number of the gate trenches to the total number of the trenches is greater than 75%, The third semiconductor region includes a first third semiconductor region and a second third semiconductor region having a lower impurity concentration than the first third semiconductor region, The first third semiconductor region is arranged between the gate trench and the dummy trench. The second third semiconductor region is arranged between at least one group of adjacent gate trenches.

5. The semiconductor device according to claim 1, wherein: The ratio of the number of the gate trenches to the total number of the trenches is greater than 75%, The third semiconductor region is not arranged between adjacent dummy trenches and between at least one group of adjacent gate trenches.

6. The semiconductor device according to claim 2, wherein: The ratio of the number of the gate trenches to the total number of the trenches is greater than 75%, The third semiconductor region is not arranged between adjacent dummy trenches and between at least one group of adjacent gate trenches.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The third semiconductor region is provided from the depth of the second semiconductor region to the depth of the trench.

8. The semiconductor device according to any one of claims 1 to 6, wherein: The semiconductor substrate has: A first device region is configured with a first device; and A second device region is adjacent to the first device region and is provided with a second device. The first element includes the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, the gate trench, the dummy trench, the gate electrode, the dummy gate electrode, the second electrode, and the third electrode. The second element includes the first semiconductor region, the second semiconductor region, the third semiconductor region, the dummy trench, the dummy gate electrode, the second electrode, the third electrode, and a sixth semiconductor region of the first conductivity type. The sixth semiconductor region of the first conductivity type is arranged inside the semiconductor substrate in contact with the first semiconductor region and closer to the back side of the semiconductor substrate than the first semiconductor region, and is electrically connected to the third electrode. The impurity concentration is higher than that of the first semiconductor region.

9. The semiconductor device according to claim 7, wherein: The semiconductor substrate has: A first device region is configured with a first device; and A second device region is adjacent to the first device region and is provided with a second device. The first element includes the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, the gate trench, the dummy trench, the gate electrode, the dummy gate electrode, the second electrode, and the third electrode. The second element includes the first semiconductor region, the second semiconductor region, the third semiconductor region, the dummy trench, the dummy gate electrode, the second electrode, the third electrode, and a sixth semiconductor region of the first conductivity type. The sixth semiconductor region of the first conductivity type is arranged inside the semiconductor substrate in contact with the first semiconductor region and closer to the back side of the semiconductor substrate than the first semiconductor region, and is electrically connected to the third electrode. The impurity concentration is higher than that of the first semiconductor region.

10. The semiconductor device according to any one of claims 1 to 6, wherein: The semiconductor device further includes a first conductivity type seventh semiconductor region, which is provided inside the first semiconductor region so as to be in contact with the fifth semiconductor region and has a higher impurity concentration than the first semiconductor region.

11. The semiconductor device according to claim 7, wherein: The semiconductor device further includes a first conductivity type seventh semiconductor region, which is provided inside the first semiconductor region so as to be in contact with the fifth semiconductor region and has a higher impurity concentration than the first semiconductor region.

12. The semiconductor device according to claim 8, wherein: The semiconductor device further includes a first conductivity type seventh semiconductor region, which is provided inside the first semiconductor region so as to be in contact with the fifth semiconductor region and has a higher impurity concentration than the first semiconductor region.

13. The semiconductor device according to claim 9, wherein: The semiconductor device further includes a first conductivity type seventh semiconductor region, which is provided inside the first semiconductor region so as to be in contact with the fifth semiconductor region and has a higher impurity concentration than the first semiconductor region.

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