A New High-Speed ​​and High-Precision Analog-to-Digital Converter

Abstract

The present invention provides a novel high-speed and high-precision analog-to-digital converter, comprising: a first-order Sigma delta ADC unit, for converting an input analog signal voltage into a high-speed serial data stream and a residual voltage; a low-power cyclic structure analog-to-digital converter unit connected to the first-order Sigma delta ADC unit, for performing secondary quantization on the residual voltage to generate a serial data stream; a digital low-pass filter unit cascaded with the first-order Sigma delta ADC unit, for converting a high-speed serial data stream into a low-speed parallel data stream; a shift register unit cascaded with the low-power cyclic structure analog-to-digital converter unit, for converting the serial data stream generated by the low-power cyclic structure analog-to-digital converter unit into a parallel data stream; a digital correction logic unit connected with the digital low-pass filter unit and the shift register unit, for performing corresponding logic operations on the output results of the two to obtain a final digital conversion result. While obtaining high precision, the conversion speed is improved, and the negative impact of the limited gain of the operational amplifier is eliminated.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to a novel high-speed and high-precision analog-to-digital converter. Background Art

[0002] Analog to Digital Converter (ADC) is generally divided into two categories according to the sampling frequency: traditional Nyquist ADC and oversampling ADC. The sampling frequency of the former is equal to or slightly greater than twice the signal frequency, that is, the Nyquist frequency. The sampling frequency of the latter is much higher than the Nyquist frequency of the signal.

[0003] Sigma delta ADC is a typical oversampling ADC, which uses a sampling frequency higher than the Nyquist frequency for sampling, thus greatly reducing the requirements for its anti-aliasing filter. Due to its high sampling frequency, the passband of the quantization noise becomes larger, but the total amount of noise remains unchanged, which makes the power spectrum density of the quantization noise smaller, thus greatly reducing the impact of the quantization noise introduced into the signal passband on the output signal. At the same time, the Sigma delta modulator has the characteristics of quantization noise shaping, which pushes the low-frequency quantization noise to the high frequency, greatly reducing the quantization noise within the bandwidth of the low-frequency signal, and then the output signal of the Sigma-delta modulator is sent to the digital filter to filter out the high-frequency quantization noise, so that the signal-to-noise ratio is greatly improved, so the Sigma delta ADC can achieve higher accuracy. However, one disadvantage of the Sigma delta ADC is its slow conversion speed. In order to achieve n-bit accuracy for a first-order Sigma delta ADC, it usually requires 2 n sampling clock cycles.

[0004] Cyclic ADC is a common Nyquist ADC. The sampling frequency of Nyquist ADC is equal to or slightly greater than twice the signal frequency, so in general, it has high requirements for anti-aliasing filters, which will increase the difficulty of ADC circuit design, power consumption and area. However, Nyquist ADC generally has a faster conversion speed. In order for Cyclic ADC to achieve m-bit accuracy, it usually requires m sampling clock cycles. However, Cyclic ADC is affected by non-ideal factors such as capacitor matching and limited gain of operational amplifiers. Therefore, this structure cannot achieve very high accuracy.

[0005] The upper limit of the achievable accuracy of an analog-to-digital converter is often constrained by non-ideal factors in the circuit, such as clock jitter, limited op amp DC gain, noise, etc. Eliminating or suppressing non-ideal factors is a problem that must be solved to improve the accuracy of the analog-to-digital converter.

[0006] Therefore, a new high-speed and high-precision analog-to-digital converter is proposed. Summary of the invention

[0007] The present invention provides a novel high-speed and high-precision analog-to-digital converter to solve the above-mentioned technical problems.

[0008] The embodiment of the present invention provides a novel high-speed and high-precision analog-to-digital converter, comprising:

[0009] A first-order Sigma delta ADC unit, used to convert the input analog signal voltage into a high-speed serial data stream and a residual voltage, and output;

[0010] The low-power cycle structure analog-to-digital converter unit is connected to the first-order Sigma delta ADC unit and is used to perform secondary quantization on the residual voltage output by the first-order Sigma delta ADC unit to generate a serial data stream;

[0011] The digital low-pass filter unit is cascaded with the first-order Sigma delta ADC unit, and is used to convert the high-speed serial data stream output by the first-order Sigma delta ADC unit into a low-speed parallel data stream and output it, that is, the high bit of the final digital conversion result;

[0012] The shift register unit is cascaded with the low-power cyclic structure analog-to-digital converter unit, and is used to convert the serial data stream generated by the low-power cyclic structure analog-to-digital converter unit into a parallel data stream and output it, that is, the low bit of the final digital conversion result;

[0013] The digital correction logic unit is connected to the digital low-pass filter unit and the shift register unit, and is used to perform corresponding logic operations on the output results of the digital low-pass filter unit and the shift register unit to obtain a final digital conversion result.

[0014] Preferably, the first-order Sigma delta ADC unit comprises: a switching sequence S1 to S 16 , sampling capacitors C1-C4, integrating capacitors C5-C6, operational amplifier with offset capacitor, comparator unit and feedback voltage unit;

[0015] The low power consumption cycle structure analog-to-digital converter unit comprises: a switch sequence S 17 ~S 24, sampling capacitors C7-C8, integrating capacitors C5-C6, operational amplifier with offset capacitor, comparator unit and feedback voltage unit;

[0016] The first-order Sigma delta ADC unit and the low-power cycle structure analog-to-digital converter unit commonly use integration capacitors C5-C6, an operational amplifier with an offset capacitor, a comparator unit and a feedback voltage unit.

[0017] Preferably, the operational amplifier with offset capacitance comprises: a switching sequence S 25 ~S 30 , offset capacitor C9~C 10 and operational amplifier G;

[0018] The A terminal of the operational amplifier with offset capacitance is connected to the switch S 29 One end of the switch S 25 and one end of the offset capacitor C9, the other end of the offset capacitor C9 is connected to the switch S 28 and the inverting input of the operational amplifier G, the switch S 28 The other end and switch S 29 The other end is connected to the C terminal, and the switch S 30 One end of the switch S 26 One end and the offset capacitor C 10 One end is connected to the B terminal, and the offset capacitor C 10 The other end is connected to the switch S 27 and the non-inverting input of the operational amplifier G, the switch S 27 The other end and switch S 30 The other end is connected to the D terminal, and the switch S 25 The other end and switch S 26 The other end is connected to a fixed level.

[0019] Preferably, the first-order Sigma delta ADC unit is implemented with a fully differential circuit structure;

[0020] The first-order sigma delta ADC unit has a port V in+ and V in- Differential port for analog signal input, port V in+ Connection switch S 14 One end of the switch S 14 The other end of the switch S2 is connected to one end of the sampling capacitor C2, the other end of the switch S2 is connected to a fixed level, and the other end of the sampling capacitor C2 is connected to the switch S 10 and one end of switch S6, switch S 10The other end of switch S6 is connected to the fixed level, and the other end of switch S6 is connected to the A end of the operational amplifier with offset capacitor. in- Connection switch S 15 One end of the switch S 15 The other end of the switch S3 is connected to one end of the sampling capacitor C3, the other end of the switch S3 is connected to a fixed level, and the other end of the sampling capacitor C3 is connected to the switch S 11 and one end of switch S7, switch S 11 The other end of switch S7 is connected to the fixed level, and the other end of switch S7 is connected to the B end of the operational amplifier with offset capacitor. DAC+ and V DAC- The output port of the feedback voltage unit, port V DAC+ Connection switch S 16 One end of the switch S 16 The other end of the switch S4 is connected to one end of the sampling capacitor C4, the other end of the switch S4 is connected to a fixed level, and the other end of the sampling capacitor C4 is connected to the switch S 12 and one end of switch S8, switch S 12 The other end of switch S8 is connected to the fixed level, and the other end of switch S8 is connected to the B end of the operational amplifier with offset capacitor. DAC- Connection switch S 13 One end of the switch S 13 The other end of is connected to one end of switch S1 and one end of sampling capacitor C1, the other end of switch S1 is connected to a fixed level, the other end of sampling capacitor C1 is connected to switch S9 and one end of switch S5, the other end of switch S9 is connected to a fixed level, the other end of switch S5 is connected to terminal A of an operational amplifier with an offset capacitor, both ends of integrating capacitor C5 are connected to terminal C and OUT+ of the operational amplifier with an offset capacitor, both ends of integrating capacitor C6 are connected to terminal D and OUT- of the operational amplifier with an offset capacitor, the output end of the operational amplifier with an offset capacitor is connected to the comparator unit, and the output of the comparator unit is connected to the input of the feedback voltage unit and the digital low-pass filter unit.

[0021] Preferably, the low-power cycle structure analog-to-digital converter unit is implemented with a fully differential circuit structure;

[0022] One end of the sampling capacitor C7 is connected to the switch S 21 and switch S 19 , the other end of the sampling capacitor C7 is connected to the switch S 17 and switch S 23 , switch S 21 The other end of the switch S is connected to a fixed level. 19 The other end of the switch is connected to the A terminal of the operational amplifier with an offset capacitor. 17The other end is connected to the output terminal V of the feedback voltage unit DAC+ , switch S 23 The other end of the sampling capacitor is connected to the OUT+ end of the operational amplifier with the offset capacitor, and one end of the sampling capacitor C8 is connected to the switch S 20 and switch S 22 , the other end of the sampling capacitor C8 is connected to the switch S 18 and switch S 24 , switch S 22 The other end is connected to a fixed level, switch S 20 The other end is connected to the B terminal of the operational amplifier with offset capacitor, and the switch S 18 The other end is connected to the output terminal V of the feedback voltage unit DAC- , switch S 24 The other end of is connected to the OUT- end of the operational amplifier with an offset capacitor, the two ends of the integrating capacitor C5 are connected to the C end and the OUT+ end of the operational amplifier with an offset capacitor, the two ends of the integrating capacitor C6 are connected to the D end and the OUT- end of the operational amplifier with an offset capacitor, the output end of the operational amplifier with an offset capacitor is connected to the comparator unit, and the output of the comparator unit is connected to the shift register unit and the feedback voltage unit.

[0023] Preferably, it also includes: a switch sequence S 31 ~S 34 , the switch S 32 One end of the switch S 31 One end of the switch S 32 The other end of the switch S 29 One end of the switch S 28 One end of the switch S is connected to one end of the integrating capacitor C5. 31 The other end of the switch S is connected to the other end of the integral capacitor C5 and the OUT+ end of the operational amplifier with the offset capacitor. 34 One end of the switch S 33 One end of the switch S 34 The other end of the switch S 30 One end of the switch S 27 One end of the switch S is connected to one end of the integrating capacitor C6. 33 The other end of is connected to the other end of the integrating capacitor C6 and the OUT- terminal of the operational amplifier having the offset capacitor.

[0024] Preferably, the gain coefficient of the first-order Sigma delta ADC unit is 0.5.

[0025] Preferably, the comparator unit is connected to an output end of an operational amplifier having an offset capacitor, and the comparator unit adopts a 1.5-bit comparator.

[0026] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0027] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0029] Figure 1 This is a structural principle diagram of a novel high-speed and high-precision analog-to-digital converter in an embodiment of the present invention;

[0030] Figure 2 is a circuit schematic diagram of a first-order Sigma delta ADC unit in an embodiment of the present invention;

[0031] Figure 3 is a circuit schematic diagram of a low-power cycle structure analog-to-digital converter unit in an embodiment of the present invention;

[0032] Figure 4 is a circuit schematic diagram of an operational amplifier with an offset capacitor in an embodiment of the present invention;

[0033] Figure 5 It is a circuit schematic diagram of a hybrid incremental Sigma delta / Cyclic analog-to-digital converter provided by the present invention;

[0034] Figure 6 The present invention provides a hybrid incremental Sigma delta / Cyclic analog-to-digital converter. DETAILED DESCRIPTION

[0035] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0036] The present invention proposes a novel high-speed and high-precision analog-to-digital converter, wherein a residual voltage and a high-speed serial data stream are obtained by quantization of a first-stage first-order Sigmadelta ADC unit, and a second-stage low-power cyclic structure analog-to-digital converter unit is used to perform a rapid secondary conversion on the residual voltage, thereby obtaining high precision while also greatly improving the conversion speed. In the structure of the high-precision analog-to-digital converter, the limited gain of the operational amplifier also becomes an important factor limiting the improvement of the precision. The use of an operational amplifier with an offset capacitor greatly eliminates the negative impact of the limited gain of the operational amplifier and also reduces the design difficulty of the operational amplifier.

[0037] The embodiment of the present invention provides a novel high-speed and high-precision analog-to-digital converter, such as Figure 1 As shown, including:

[0038] A first-order Sigma delta ADC unit 1 is used to convert an input analog signal voltage into a high-speed serial data stream and a residual voltage, and output the result;

[0039] The low-power cycle structure analog-to-digital converter unit 2 is connected to the first-order Sigma delta ADC unit 1, and is used to perform secondary quantization on the residual voltage output by the first-order Sigma delta ADC unit 1 to generate a serial data stream;

[0040] The digital low-pass filter unit 3 is cascaded with the first-order Sigma delta ADC unit 1, and is used to convert the high-speed serial data stream output by the first-order Sigma delta ADC unit 1 into a low-speed parallel data stream and output it, that is, the high bit of the final digital conversion result;

[0041] The shift register unit 4 is cascaded with the low-power cyclic structure analog-to-digital converter unit 2, and is used to convert the serial data stream generated by the low-power cyclic structure analog-to-digital converter unit 2 into a parallel data stream and output it, that is, the low bit of the final digital conversion result;

[0042] The digital correction logic unit 5 is connected to the digital low-pass filter unit 3 and the shift register unit 4, and is used to perform corresponding logic operations on the output results of the digital low-pass filter unit 3 and the shift register unit 4 to obtain a final digital conversion result.

[0043] Among them, the first-order Sigma delta ADC unit 1 can be represented by 1st-order IncrementalΣ-ΔADC; the low-power cyclic structure analog-to-digital converter unit 2 can be represented by Cyclic ADC; the digital low-pass filter unit 3 can be represented by DigitalLow-pass Filter; the shift register unit 4 can be represented by Shift Register; and the digital correction logic unit 5 can be represented by Digital Correction Logic. For details, see Figure 1 .

[0044] The beneficial effect of the above technical solution is that it is easy to obtain high precision while also improving the conversion speed.

[0045] In one embodiment, Figure 5 As shown,

[0046] The first-order Sigma delta ADC unit 1 includes: switch sequences S1 to S 16 , sampling capacitors C1-C4, integrating capacitors C5-C6, an operational amplifier 6 with an offset capacitor, a comparator unit 7 and a feedback voltage unit 8;

[0047] The low power consumption cycle structure analog-to-digital converter unit 2 comprises: a switch sequence S 17 ~S 24 , sampling capacitors C7-C8, integrating capacitors C5-C6, an operational amplifier 6 with an offset capacitor, a comparator unit 7 and a feedback voltage unit 8;

[0048] The first-order Sigma delta ADC unit 1 and the low-power cycle structure analog-to-digital converter unit 2 commonly use integrating capacitors C5-C6, an operational amplifier 6 with an offset capacitor, a comparator unit 7 and a feedback voltage unit 8.

[0049] The first-order Sigma delta ADC unit and the Cyclic ADC unit have the same circuit structure, an operational amplifier with offset capacitor, an integrating capacitor, a comparator unit, and a feedback voltage unit. In terms of time domain, Figure 6 As shown, the first-order Sigma delta ADC unit and the Cyclic ADC cannot work at the same time. Therefore, the first-order Sigma delta ADC unit and the Cyclic ADC can share the same circuit structure to save chip area and cost.

[0050] The beneficial effect of the above technical solution is that by using the integration capacitor, the operational amplifier with the offset capacitor, the comparator unit and the feedback voltage unit together, it is convenient to effectively save the area of ​​the Sigma delta / Cyclic analog-to-digital converter and save costs.

[0051] In one embodiment, Figure 4 As shown,

[0052] The operational amplifier 6 with offset capacitance comprises: a switching sequence S 25 ~S 30 , offset capacitor C9~C 10 and operational amplifier G9;

[0053] The A terminal of the operational amplifier 6 is connected to the switch S 29 One end of the switch S 25 and one end of the offset capacitor C9, the other end of the offset capacitor C9 is connected to the switch S 28 and the inverting input of operational amplifier G9, switch S 28 The other end and switch S 29 The other end is connected to the C terminal, and the switch S 30 One end of the switch S 26 One end and the offset capacitor C 10 One end is connected to the B terminal, and the offset capacitor C 10 The other end is connected to the switch S 27 and the non-inverting input of operational amplifier G9, switch S 27 The other end and switch S 30 The other end is connected to the D terminal, and the switch S 25 The other end and switch S 26 The other end is connected to a fixed level.

[0054] During the sampling phase of the first-order Sigma Delta ADC unit or the Cyclic ADC unit, the switch S 25 ~S 28 Closed, S 29 ~S 30 When disconnected, the switch S 25 ~S 28 Disconnect, S 29 ~S 30 Closed, greatly eliminating the negative effects of the finite gain of the operational amplifier.

[0055] The beneficial effect of the above technical solution is that the above operational amplifier with offset capacitor has smaller offset voltage and 1 / f noise than the operational amplifier G without offset capacitor, so that the hybrid incremental Sigma delta / Cyclic analog-to-digital converter has higher accuracy.

[0056] In one embodiment, Figure 2 As shown,

[0057] The first-order Sigma delta ADC unit 1 is implemented with a fully differential circuit structure;

[0058] The first-order sigma delta ADC unit 1 has a port V in+ and V in- Differential analog signal input port, port V in+ Connection switch S 14 One end of the switch S 14 The other end of the switch S2 is connected to one end of the sampling capacitor C2, the other end of the switch S2 is connected to a fixed level, and the other end of the sampling capacitor C2 is connected to the switch S 10 and one end of switch S6, switch S 10 The other end of the switch S6 is connected to the fixed level, and the other end of the switch S6 is connected to the A end of the operational amplifier 6 with an offset capacitor. in- Connection switch S 15 One end of the switch S 15 The other end of the switch S3 is connected to one end of the sampling capacitor C3, the other end of the switch S3 is connected to a fixed level, and the other end of the sampling capacitor C3 is connected to the switch S 11 and one end of switch S7, switch S 11 The other end of the switch S7 is connected to the fixed level, and the other end of the switch S7 is connected to the B end of the operational amplifier 6 with an offset capacitor. DAC+ and V DAC- is the output port of the feedback voltage unit 8, port V DAC+ Connection switch S 16 One end of the switch S 16 The other end of the switch S4 is connected to one end of the sampling capacitor C4, the other end of the switch S4 is connected to a fixed level, and the other end of the sampling capacitor C4 is connected to the switch S 12 and one end of switch S8, switch S 12 The other end of the switch S8 is connected to the fixed level, and the other end of the switch S8 is connected to the B end of the operational amplifier 6 with an offset capacitor. DAC- Connection switch S 13 One end of the switch S 13The other end of is connected to one end of switch S1 and one end of sampling capacitor C1, the other end of switch S1 is connected to a fixed level, the other end of sampling capacitor C1 is connected to switch S9 and one end of switch S5, the other end of switch S9 is connected to a fixed level, the other end of switch S5 is connected to the A end of operational amplifier 6 with offset capacitor, the two ends of integrating capacitor C5 are connected to the C end and OUT+ end of operational amplifier 6 with offset capacitor, the two ends of integrating capacitor C6 are connected to the D end and OUT- end of operational amplifier 6 with offset capacitor, the output end of operational amplifier 6 with offset capacitor is connected to comparator unit 7, and the output of comparator unit 7 is connected to feedback voltage unit 8 and the input of digital low-pass filter unit 3.

[0059] The first-order Sigma delta ADC unit is used as the first-level quantization unit for the input analog voltage signal. Each working clock cycle has two working modes, namely sampling mode and integration mode. Switches S1 to S8 are disconnected, and switches S9 to S1 are closed. 16 Closed, the first-order Sigma delta ADC unit enters sampling mode, the comparator unit quantizes the output voltage of the operational amplifier, the quantized value controls the feedback voltage value of the feedback voltage unit, the sampling capacitor samples the input voltage and the feedback voltage at the same time, switches S1~S8 are closed, switches S9~S 16 When the first-order Sigma delta ADC unit is disconnected, it enters the integration mode, and the charge of the sampling capacitor is transferred to the integration capacitor. When it works continuously, the comparator unit will generate serial quantization value data, and the output voltage of the operational amplifier in the last cycle is the residual voltage.

[0060] The beneficial effect of the above technical solution is that through the above circuit, it is convenient to obtain the residual voltage and the high-speed serial data stream.

[0061] In one embodiment, Figure 3 As shown,

[0062] The low-power cycle structure analog-to-digital converter unit 2 is implemented with a fully differential circuit structure;

[0063] One end of the sampling capacitor C7 is connected to the switch S 21 and switch S 19 , the other end of the sampling capacitor C7 is connected to the switch S 17 and switch S 23 , switch S 21 The other end of the switch S is connected to a fixed level. 19 The other end is connected to the A terminal of the operational amplifier 6 with an offset capacitor, and the switch S 17 The other end is connected to the output end V of the feedback voltage unit 8 DAC+ , switch S 23The other end of is connected to the OUT+ end of the operational amplifier 6 with offset capacitor, and one end of the sampling capacitor C8 is connected to the switch S 20 and switch S 22 , the other end of the sampling capacitor C8 is connected to the switch S 18 and switch S 24 , switch S 22 The other end is connected to a fixed level, switch S 20 The other end is connected to the B terminal of the operational amplifier 6 with an offset capacitor, and the switch S 18 The other end is connected to the output end V of the feedback voltage unit 8 DAC- , switch S 24 The other end is connected to the OUT-terminal of the operational amplifier 6 with an offset capacitor, the two ends of the integrating capacitor C5 are connected to the C terminal and the OUT+ terminal of the operational amplifier 6 with an offset capacitor, the two ends of the integrating capacitor C6 are connected to the D terminal and the OUT-terminal of the operational amplifier 6 with an offset capacitor, the output end of the operational amplifier 6 with an offset capacitor is connected to the comparator unit 7, and the output of the comparator unit 7 is connected to the shift register unit 4 and the feedback voltage unit 8.

[0064] The above Cyclic ADC unit is used as a secondary quantization unit for the residual voltage of the first-order Sigma delta ADC unit. Each working clock cycle has two modes, namely, sampling mode and integration mode. The switch S 17 ~S 20 Disconnect, switch S 21 ~S 24 Closed, the Cyclic ADC unit enters the sampling mode, the comparator unit quantizes the output voltage of the operational amplifier, the quantized value controls the feedback voltage value of the feedback voltage unit, and the sampling capacitor samples the output voltage of the operational amplifier at the same time. Switch S 17 ~S 20 Closed, switch S 21 ~S 24 When disconnected, the Cyclic ADC unit enters the integration mode, the feedback voltage is valid, the charge of the sampling capacitor is transferred to the integration capacitor, and when it works continuously, the comparator unit will generate a serial quantization value.

[0065] The beneficial effects of the above technical solution are: the above circuit facilitates secondary quantization, facilitates acquisition of serial quantization values, and improves conversion speed.

[0066] In one embodiment, it also includes: Figure 5 As shown,

[0067] Switching sequence S 31 ~S 34 , the switch S 32 One end of the switch S31 One end of the switch S 32 The other end of the switch S 29 One end of the switch S 28 One end of the switch S is connected to one end of the integrating capacitor C5. 31 The other end of the switch S is connected to the other end of the integral capacitor C5 and the OUT+ end of the operational amplifier 6 having an offset capacitor. 34 One end of the switch S 33 One end of the switch S 34 The other end of the switch S 30 One end of the switch S 27 One end of the switch S is connected to one end of the integrating capacitor C6. 33 The other end of is connected to the other end of the integrating capacitor C6 and the OUT- terminal of the operational amplifier 6 having an offset capacitor.

[0068] The beneficial effect of the above technical solution is that the hybrid incremental Sigma delta / Cyclic analog-to-digital converter contains a switching sequence S 31 ~S 34 Each time the hybrid incremental Sigma delta / Cyclic ADC starts a data conversion, the switch sequence S 31 ~S 34 It will first close to release the charge left in the integrating capacitor during the last conversion process, and then open the switch sequence S 31 ~S 34 , making this conversion more accurate.

[0069] In one embodiment,

[0070] The gain coefficient of the first-order Sigma delta ADC unit 1 is 0.5.

[0071] The beneficial effect of the above technical solution is that by setting a gain coefficient of 0.5, the residual voltage of the first-order Sigmadelta ADC unit is reduced, thereby increasing the circuit's tolerance to the comparator unit offset voltage.

[0072] In one embodiment,

[0073] The comparator unit 7 is connected to the output end of the operational amplifier 6 having an offset capacitor, and the comparator unit 7 is a 1.5-bit comparator.

[0074] By selecting to use a 1.5-bit comparator, that is, using V OUT =V OUT+ -V OUT- With fixed level 0.25V ref and -0.25Vref Comparison is performed, and the output terminals Q1 Q0 of the comparator unit are 11, 01 or 00 in each cycle;

[0075] The feedback voltage unit is connected to the output terminal Q1Q0 of the comparator, and the output Q1Q0 of the comparator unit is used as the input signal so that V DAC =V DAC+ -V DAC- Equal to V ref , 0 or -V ref .

[0076] The beneficial effect of the above technical solution is that it can not only improve the circuit accuracy, but also improve the circuit's tolerance to the comparator unit offset voltage.

[0077] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A new type of high-speed and high-precision analog-to-digital converter, characterized in that: include: A first-order Sigma delta ADC unit (1) is used to convert an input analog signal voltage into a high-speed serial data stream and a residual voltage, and output the result; The low-power cyclic structure analog-to-digital converter unit (2) is connected to the first-order Sigma delta ADC unit (1) and is used to perform secondary quantization on the residual voltage output by the first-order Sigma delta ADC unit (1) to generate a serial data stream; The digital low-pass filter unit (3) is cascaded with the first-order Sigma delta ADC unit (1) and is used to convert the high-speed serial data stream output by the first-order Sigma delta ADC unit (1) into a low-speed parallel data stream and output it, that is, the high bit of the final digital conversion result; The shift register unit (4) is cascaded with the low-power cyclic structure analog-to-digital converter unit (2) and is used to convert the serial data stream generated by the low-power cyclic structure analog-to-digital converter unit (2) into a parallel data stream and output it, that is, the low bit of the final digital conversion result; The digital correction logic unit (5) is connected to the digital low-pass filter unit (3) and the shift register unit (4) and is used to perform corresponding logic operations on the output results of the digital low-pass filter unit (3) and the shift register unit (4) to obtain a final digital conversion result; The first-order Sigma delta ADC unit (1) comprises: a switching sequence , sampling capacitor , integrating capacitor , an operational amplifier (6) having an offset capacitor, a comparator unit (7) and a feedback voltage unit (8); The low power consumption cycle structure analog-to-digital converter unit (2) comprises: a switch sequence , sampling capacitor , integrating capacitor , an operational amplifier (6) having an offset capacitor, a comparator unit (7) and a feedback voltage unit (8); The first-order Sigma delta ADC unit (1) and the low-power cycle structure analog-to-digital converter unit (2) use an integral capacitor together. , an operational amplifier (6) having an offset capacitor, a comparator unit (7) and a feedback voltage unit (8); The low-power cycle structure analog-to-digital converter unit (2) is implemented with a fully differential circuit structure; Among them, the sampling capacitor Connect one end of the switch and switch , sampling capacitor The other end of the switch and switch ,switch The other end of the switch is connected to a fixed level. The other end of the switch is connected to the A terminal of the operational amplifier (6) with an offset capacitor. The other end is connected to the output end of the feedback voltage unit (8) ,switch The other end of the operational amplifier (6) is connected to the Terminal, sampling capacitor Connect one end of the switch and switch , sampling capacitor The other end of the switch and switch ,switch The other end is connected to a fixed level, switch The other end is connected to the B terminal of the operational amplifier (6) with an offset capacitor. The other end is connected to the output end of the feedback voltage unit (8) ,switch The other end of the operational amplifier (6) is connected to the Terminal, integrating capacitor The two ends of are connected to the C terminal of the operational amplifier (6) with offset capacitor and Terminal, integrating capacitor The two ends of are connected to the D terminal of the operational amplifier (6) with offset capacitance and The output end of the operational amplifier (6) having an offset capacitor is connected to the comparator unit (7), and the output of the comparator unit (7) is connected to the shift register unit (4) and the feedback voltage unit (8).

2. The analog-to-digital converter according to claim 1, wherein: The operational amplifier (6) with offset capacitance comprises: a switching sequence , offset capacitance and an operational amplifier G (9); The A terminal of the operational amplifier (6) with offset capacitance is connected to a switch One end of the switch One end and the offset capacitor One end of the offset capacitor The other end of the switch and the inverting input terminal of the operational amplifier G (9), the switch The other end and switch The other end is connected to the C terminal, the switch One end of the switch One end and the offset capacitor One end is connected to the B terminal, the offset capacitor The other end of the switch and the non-inverting input terminal of the operational amplifier G (9), the switch The other end and switch The other end is connected to the D terminal, the switch The other end and switch The other end is connected to a fixed level.

3. The analog-to-digital converter according to claim 1, wherein: The first-order Sigma delta ADC unit (1) is implemented with a fully differential circuit structure; the first-order Sigma delta ADC unit (1) also includes a port and ; The first-order Sigma delta ADC unit (1) has a port and Differential port for analog signal input, port Connect the switch One end of the switch The other end of the switch One end and the sampling capacitor One end of the switch The other end of the sampling capacitor is connected to a fixed level The other end of the switch And switch One end of the switch The other end of the switch is connected to a fixed level. The other end is connected to the A terminal of the operational amplifier (6) with an offset capacitor. Connect the switch One end of the switch The other end of the switch One end and the sampling capacitor One end of the switch The other end of the sampling capacitor is connected to a fixed level The other end of the switch And switch One end of the switch The other end of the switch is connected to a fixed level. The other end is connected to the B terminal of the operational amplifier (6) with an offset capacitor. and is the output port of the feedback voltage unit (8), port Connect the switch One end of the switch The other end of the switch One end and the sampling capacitor One end of the switch The other end of the sampling capacitor is connected to a fixed level. The other end of the switch And switch One end of the switch The other end of the switch is connected to a fixed level. The other end is connected to the B terminal of the operational amplifier (6) with an offset capacitor. Connect the switch One end of the switch The other end of the switch One end and the sampling capacitor One end of the switch The other end of the sampling capacitor is connected to a fixed level The other end of the switch And switch One end of the switch The other end of the switch is connected to a fixed level. The other end is connected to the A terminal of the operational amplifier (6) with an offset capacitor, and the integrating capacitor The two ends of are connected to the C terminal of the operational amplifier (6) with offset capacitor and Terminal, integrating capacitor The two ends of are connected to the D terminal of the operational amplifier (6) with offset capacitance and The output end of the operational amplifier (6) having an offset capacitor is connected to a comparator unit (7), and the output of the comparator unit (7) is connected to an input of a feedback voltage unit (8) and a digital low-pass filter unit (3).

4. The analog-to-digital converter according to claim 2, wherein: The operational amplifier (6) with offset capacitance further comprises: Switching sequence S 31~ S 34 , the switch S 32 One end of the switch S 31 One end of the switch S 32 The other end of the switch S 29 One end of the switch S 28 One end of the switch S is connected to one end of the integrating capacitor C5. 31 The other end of the integrated capacitor C5 and the operational amplifier (6) with offset capacitor Terminal connection, switch S 34 One end of the switch S 33 One end of the switch S 34 The other end of the switch S 30 One end of the switch S 27 One end of the switch S is connected to one end of the integrating capacitor C6. 33 The other end of the integrated capacitor C6 and the operational amplifier (6) with offset capacitor End connection.

5. The analog-to-digital converter according to claim 1, wherein: The gain coefficient of the first-order Sigma delta ADC unit (1) is 0.

5.

6. The analog-to-digital converter according to claim 1, wherein: The comparator unit (7) is connected to the output end of an operational amplifier (6) having an offset capacitor, and the comparator unit (7) adopts a 1.5-bit comparator.

Images