Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device can include a substrate; a bit line structure extending in one direction on the substrate, the bit line structure including a sidewall; a storage node contact on the sidewall of the bit line structure; a first spacer and a second spacer between the sidewall of the bit line structure and the storage node contact, the first spacer separated from the second spacer by a space between the first spacer and the second spacer; an interlayer dielectric layer on the bit line structure, the interlayer dielectric layer including a bottom surface; a spacer cap pattern extending downward from the bottom surface of the interlayer dielectric layer toward the space between the first spacer and the second spacer; and a landing pad structure through the interlayer dielectric layer, the landing pad structure coupled to the storage node contact.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0168250, filed on December 24, 2018, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor memory device and / or a method of manufacturing thereof, and more specifically, to a semiconductor memory device and / or a method of manufacturing thereof comprising a spacer structure having an air gap. Background Technology

[0004] Semiconductor devices are considered a crucial element in the electronics industry due to their small size, versatility, and / or low manufacturing cost. As the electronics industry develops, semiconductor devices are becoming increasingly integrated. For example, the linewidth of patterns in semiconductor devices decreases due to their high integration density. However, the refinement of patterns requires new and / or expensive exposure techniques, making it difficult to achieve highly integrated semiconductor devices. Therefore, various studies have recently been conducted on new integration technologies. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide a semiconductor memory device with improved reliability and a method for manufacturing the same.

[0006] The present invention is not limited to the above-described aspects, and those skilled in the art will clearly understand other aspects not mentioned above through the following description.

[0007] According to some exemplary embodiments of the present invention, a semiconductor memory device may include: a substrate; a bit line structure extending in one direction on the substrate, the bit line structure including sidewalls; a memory node contact located on the sidewall of the bit line structure; a first spacer and a second spacer located between the sidewall of the bit line structure and the memory node contact, the first spacer and the second spacer being separated by a space between the first spacer and the second spacer; an interlayer dielectric layer on the bit line structure, the interlayer dielectric layer including a bottom surface; a spacer capping pattern extending downward from the bottom surface of the interlayer dielectric layer toward the space between the first spacer and the second spacer; and a landing pad structure passing through the interlayer dielectric layer, the landing pad structure being coupled to the memory node contact.

[0008] According to some exemplary embodiments of the present invention, a semiconductor memory device may include: a substrate including a first active region and a second active region, the first active region and the second active region being spaced apart from each other; a bit line structure coupled to the first active region, the bit line structure passing through the substrate, the bit line structure including sidewalls; a spacer structure on the sidewalls of the bit line structure; an interlayer dielectric layer on the bit line structure and the spacer structure; and a landing pad structure passing through the interlayer dielectric layer and electrically connected to the second active region. The landing pad structure includes a protrusion projecting toward the substrate, and the bottom end of the protrusion is located at a level lower than the top end of the spacer structure.

[0009] According to some exemplary embodiments of the present invention, a semiconductor memory device may include: a substrate; a pair of bit line structures on the substrate, the pair of bit line structures extending parallel in one direction; a memory node contact located between the pair of bit line structures; a lower landing pad between the pair of bit line structures, the lower landing pad located on the memory node contact; an interlayer dielectric layer on the pair of bit line structures and the lower landing pad, the interlayer dielectric layer including a bottom surface; and an upper landing pad passing through the interlayer dielectric layer and coupled to the lower landing pad, the bottom end of the upper landing pad being at a level lower than the bottom surface of the interlayer dielectric layer.

[0010] According to some exemplary embodiments of the present invention, a method of manufacturing a semiconductor memory device may include: forming a bit line structure on a substrate; forming a first spacer, a sacrificial spacer, and a second spacer, the first spacer, the sacrificial spacer, and the second spacer sequentially covering the sidewalls of the bit line structure; forming a lower landing pad on a side surface of the second spacer; forming an air gap between the first spacer and the second spacer by removing the sacrificial spacer; forming an interlayer dielectric layer on the bit line structure and the lower landing pad, the interlayer dielectric layer filling the upper portion of the air gap; and forming an upper landing pad through the interlayer dielectric layer, the upper landing pad being coupled to the lower landing pad. Attached Figure Description

[0011] Figure 1A A plan view of a semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown;

[0012] Figure 1B It shows along Figure 1A A sectional view taken by lines A-A' and B-B';

[0013] Figure 1C It shows along Figure 1A A sectional view taken by lines C-C' and D-D';

[0014] Figure 2A and Figure 2B The display shows Figure 1B A magnified view of part A;

[0015] Figure 3A and Figure 3B The display shows Figure 1B A magnified view of part B;

[0016] Figures 4A to 12A A plan view showing a method of manufacturing a semiconductor memory device according to some example embodiments of the concept of the present invention is shown;

[0017] Figures 4B to 12B It shows along Figures 4A to 12A The cross-sectional views taken along lines A-A' and B-B' illustrate a method of manufacturing a semiconductor memory device according to some exemplary embodiments of the concept of the present invention;

[0018] Figures 4C to 12C It shows along Figures 4A to 12A The cross-sectional views taken along lines C-C' and D-D' illustrate a method for manufacturing a semiconductor memory device according to some exemplary embodiments of the invention. Detailed Implementation

[0019] Now, a three-dimensional semiconductor memory device with some exemplary embodiments of the concept according to the present invention will be described in detail below with reference to the accompanying drawings.

[0020] Figure 1A A plan view of a semiconductor memory device showing some example embodiments of the concept according to the present invention is shown. Figure 1B It shows along Figure 1A A sectional view taken from lines A-A' and B-B'. Figure 1C It shows along Figure 1A A sectional view taken from lines C-C' and D-D'. Figure 2A and Figure 2B The display shows Figure 1B A magnified view of part A. Figure 3A and Figure 3B The display shows Figure 1B A magnified view of part B. The semiconductor memory device may be or may include a volatile memory device such as a dynamic random access (DRAM) device; however, the inventive concept is not limited thereto, and the semiconductor memory device may be or may include a non-volatile memory device.

[0021] Reference Figure 1A , Figure 1B and Figure 1CA device isolation layer 101 defining an active region ACT may be disposed in the semiconductor substrate 100. The semiconductor substrate 100 may include one or more of a silicon substrate, a germanium substrate, and a silicon-germanium substrate. The semiconductor substrate 100 may include a silicon-on-insulator (SOI) substrate.

[0022] The active regions ACT can be arranged two-dimensionally along a first direction D1 and a second direction D2. For example, each of the active regions ACT can be rectangular or strip-shaped. When viewed in a plan view, the active regions ACT can be arranged in a zigzag pattern, and the principal axis of the active regions ACT can be in a diagonal direction relative to the first direction D1 and the second direction D2. The angle of the diagonal direction relative to the first direction D1 can be between approximately 55 degrees and approximately 80 degrees, for example, approximately 70 degrees; however, the inventive concept is not limited thereto.

[0023] Word lines WL may be disposed in the semiconductor substrate 100. When viewed in plan view, word lines WL may extend in a first direction D1, passing through the active region ACT and the device isolation layer 101. Word lines WL may be arranged along a second direction D2. A gate dielectric layer 103 may be disposed between one of the word lines WL and the semiconductor substrate 100.

[0024] For example, a gate recess 102 may be disposed in the active region ACT and the device isolation layer 101. A gate dielectric layer 103 may conformally cover the inner sidewall of the gate recess 102. The gate dielectric layer 103 may be formed by an in-situ vapor generation (ISSG) process; however, the inventive concept is not limited thereto. A word line WL may fill the lower portion of the gate recess 102 in which the gate dielectric layer 103 is disposed. The top surface of the word line WL may be lower than the top surface of the semiconductor substrate 100. The word line WL may be formed by a physical vapor deposition (PVD) process and / or a chemical vapor deposition (CVD) process (such as a plasma-enhanced chemical vapor deposition (PECVD) process). The word line WL may have a hard mask pattern 105 on its top surface that fills the remaining portion of the gate recess 102. The top surface of the hard mask pattern 105 may be at substantially the same level as the top surface of the semiconductor substrate 100. The hard mask pattern 105 may include insulating materials, such as nitride (Si3N4) insulating materials and / or oxide (SiO2) insulating materials.

[0025] A first impurity region 1a and a second impurity region 1b, spaced apart from each other, may be provided in the active region ACT. The first impurity region 1a and the second impurity region 1b may have a depth relative to the top surface of the active region ACT. The first impurity region 1a may be arranged on the upper part of the active region ACT between a pair of word lines WL. For example, when viewed in a plan view, the first impurity region 1a may occupy the middle portion of the active region ACT. When viewed in a plan view, the second impurity region 1b may be spaced apart from the first impurity region 1a and arranged at opposite ends of the active region ACT. Dopants with a conductivity type opposite to that of the semiconductor substrate 100 may be implanted into the first impurity region 1a and the second impurity region 1b. For example, if the conductivity type of the semiconductor substrate 100 is p-type, the dopants implanted in the first impurity region 1a and the second impurity region 1b may be n-type, such as phosphorus (P) and / or arsenic (As).

[0026] Bit line structure (BLS) may be disposed on semiconductor substrate 100. Bit line structure BLS may extend in a second direction D2, passing through active region ACT. Bit line structure BLS may intersect and be insulated from word line WL. Bit line structure BLS may include bit line 120 and bit line capping pattern 125 on bit line 120. Bit line capping pattern 125 may include nitride capping material; however, the inventive concept is not limited thereto.

[0027] Bit line 120 may include a doped or undoped polysilicon pattern 121, a silicide pattern 122, and a metal pattern 123 stacked in sequence. Bit line capping pattern 125 may be disposed on metal pattern 123. A first interlayer dielectric layer 110 may be interposed between polysilicon pattern 121 and semiconductor substrate 100, and polysilicon pattern 121 may have a portion contacting a first impurity region 1a (hereinafter referred to as bit line contact pattern DC). For example, bit line 120 may be electrically connected to the first impurity region 1a via bit line contact pattern DC. The bottom surface of bit line contact pattern DC may be lower than the top surface of semiconductor substrate 100 and higher than the top surface of word line WL. For example, bit line contact pattern DC may be partially located in a recess 111 formed in semiconductor substrate 100 and exposing the first impurity region 1a. When viewed in a plan view, recess 111 may be shaped like an ellipse, and its width in the minor axis direction may be greater than the width of bit line structure BLS.

[0028] Bit line contact spacers (DCPs) may fill the remainder of the recess 111 in which bit line contact patterns (DCs) are disposed. For example, the bit line contact spacer (DCP) may cover the opposite sidewalls of the bit line contact pattern (DC). Alternatively, the bit line contact spacer (DCP) may surround the side surfaces of the bit line contact pattern (DC) in the recess 111. The bit line contact spacer (DCP) may comprise a dielectric material having etch selectivity relative to the first interlayer dielectric layer 110. For example, the bit line contact spacer (DCP) may comprise one or more of silicon oxide, silicon nitride, and silicon oxynitride, and may be formed of multiple layers. The top surface of the bit line contact spacer (DCP) may be at substantially the same level as the top surface of the first interlayer dielectric layer 110.

[0029] A dielectric pattern 143, spaced apart from each other in a second direction D2, may be disposed on the first interlayer dielectric layer 110 between the bit line structures BLS. When viewed in a plan view, the dielectric pattern 143 may overlap with the word lines WL, and the top surface of the dielectric pattern 143 is at the same level as the top surface of the bit line structures BLS. In a particular example embodiment, the dielectric pattern 143 may include a dielectric material having etch selectivity relative to the first interlayer dielectric layer 110.

[0030] Storage node contacts 153 may be located on the sidewalls of bit line structures (BLS). Storage node contacts 153 may be arranged between two adjacent bit line structures (BLS). Storage node contacts 153 may be arranged along a first direction D1 and a second direction D2. When viewed in plan view, each of the storage node contacts 153 may be arranged between word lines (WL) and between bit line structures (BLS). Each of the storage node contacts 153 may fill the space defined by the bit line structures (BLS) adjacent to each other in the first direction D1 and the dielectric patterns 143 adjacent to each other in the second direction D2. At least one of the storage node contacts 153 may comprise, for example, doped polysilicon.

[0031] The memory node contact 153 may penetrate the first interlayer dielectric layer 110 and directly contact the second impurity region 1b. For example, at least one of the memory node contacts 153 may have a bottom end that is below the top surface of the semiconductor substrate 100 and above the bottom surface of the bit line contact pattern DC. The bit line contact spacer DCP may insulate the memory node contact 153 from the bit line contact pattern DC. The memory node contact 153 may have a top surface that is below the metal pattern 123 of the bit line structure BLS.

[0032] A spacer structure SS may be located between the storage node contact 153 and the bit line structure BLS. The spacer structure SS may extend along the sidewall of the bit line structure BLS in a second direction D2. The spacer structure SS may include at least one of a first spacer 131, a second spacer 134, an air spacer 136, and a spacer cap pattern 171. The first spacer 131 may be disposed on the sidewall of the bit line structure BLS. The second spacer 134 may be disposed between the first spacer 131 and the storage node contact 153. The air spacer 136 may be defined between the first spacer 131 and the second spacer 134. The spacer cap pattern 171 may be disposed between the first spacer 131 and the second spacer 134, defining the top end of the air spacer 136. For example, the air spacer 136 may be defined between the first spacer 131 and the second spacer 134 and below the spacer cap pattern 171. The tops of spacer cover pattern 171, first spacer 131, and second spacer 134 may be at substantially the same level. The top of air spacer 136 may be substantially lower than the tops of spacer cover pattern 171, first spacer 131, and second spacer 134.

[0033] The second interlayer dielectric layer 170 may be disposed on the bitline structure BLS and the spacer structure SS. The second interlayer dielectric layer 170 may be disposed (e.g., directly on) the top surface of the bitline structure BLS and the top of the spacer structure SS. The second interlayer dielectric layer 170 may include a material with excellent gap-filling properties, for example, formed of a material with excellent gap-filling properties. The second interlayer dielectric layer 170 may include, for example, a silicon nitride layer. The second interlayer dielectric layer 170 and the underlying spacer capping pattern 171 may be connected as a single unit. For example, the spacer capping pattern 171 may extend from the bottom surface of the second interlayer dielectric layer 170 toward the space between the first spacer 131 and the second spacer 134. For example, the spacer capping pattern 171 and the second interlayer dielectric layer 170 may be integrated together.

[0034] The landing pad structure LPS can penetrate the second interlayer dielectric layer 170 and can be electrically connected to the memory node contact 153. The landing pad structure LPS may include a protrusion PP projecting toward the semiconductor substrate 100. The bottom end of the protrusion PP (see...) Figure 2A The TS of the protrusion PP may be located at a lower level than the top level of the spacer structure SS. The bottom end TS of the protrusion PP may vertically overlap with the spacer structure SS. For example, the bottom end TS of the protrusion PP may be located on the spacer cap pattern 171 and in direct contact with the spacer cap pattern 171.

[0035] The landing pad structure LPS may include a lower landing pad LPa and an upper landing pad LPb. The lower landing pad LPa may be arranged between a pair of bit line structures BLS and on the memory node contact 153. The top surface of the lower landing pad LPa may be at substantially the same level as the top surface of the bit line structure BLS and the top of the spacer structure SS.

[0036] The upper landing pad LPb may pass through the second interlayer dielectric layer 170 and be connected to the lower landing pad LPa. For example, the upper landing pad LPb may be located in an isolation trench NSR that exposes a portion of the lower landing pad LPa. The bottom surface of the isolation trench NSR may be at a lower level than the top surface of the lower landing pad LPa. When viewed in a plan view, multiple isolation trench NSRs may be arranged in a zigzag and / or honeycomb pattern. The protrusion PP of the landing pad structure LPS may be part of the upper landing pad LPb. The top surface of the upper landing pad LPb may be at a higher level than the top surface of the bit line structure BLS. The upper landing pad LPb may vertically overlap with the bit line structure BLS and the spacer structure SS. In a particular example embodiment, a data storage pattern, such as a capacitor, may be coupled to the upper landing pad LPb, for example, electrically connected to the upper landing pad LPb.

[0037] A contact silicide pattern 155 may be disposed between the memory node contact 153 and the landing pad structure LPS. The contact silicide pattern 155 may cover the top surface of the memory node contact 153. For example, the contact silicide pattern 155 may include at least one of titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, or molybdenum silicide. In certain example embodiments, the contact silicide pattern 155 may not be provided.

[0038] A barrier pattern 157 may be disposed between the lower landing pad LPa and the spacer structure SS, and between the lower landing pad LPa and the storage node contact 153. The barrier pattern 157 may cover the side and bottom surfaces of the lower landing pad LPa. The barrier pattern 157 may expose the top surface of the lower landing pad LPa. The top edge of the barrier pattern 157 may be at substantially the same level as the top surface of the lower landing pad LPa. The barrier pattern 157 may include a metal nitride layer. For example, the barrier pattern 157 may include at least one of titanium nitride, tantalum nitride, or tungsten nitride.

[0039] Reference Figure 2A and Figure 2B The lower landing pad LPa may have a flat region PS that is substantially parallel to the top surface of the semiconductor substrate 100. The flat region PS may correspond to the top surface of the lower landing pad LPa and be at the same level as the top surface of the bit line structure BLS. The flat region PS may be at the same level as the top of the spacer structure SS. Therefore, the flat region PS of the lower landing pad LPa may be coplanar with the top surface of the bit line structure BLS and the top of the spacer structure SS.

[0040] The upper landing pad LPb may include the aforementioned protrusion PP projecting toward the semiconductor substrate 100. The bottom end TS of the protrusion PP may be located at a lower level than the flat area PS of the lower landing pad LPa. The bottom end TS of the protrusion PP may be located at a higher level than the bottom surface of the lower landing pad LPa. The bottom end TS of the protrusion PP may be spaced apart from the side surface of the lower landing pad LPa.

[0041] In certain example embodiments, such as Figure 2A As shown, the bottom end TS of the protruding PP can be located on the spacer cover pattern 171. The bottom end of the spacer cover pattern 171 can be located at a lower level than the bottom end TS of the protruding PP, so that the protruding PP does not extend into the air spacer 136. For example, the height h1 of the spacer cover pattern 171 can be greater than the vertical distance h3 between the bottom end TS of the protruding PP and the flat area PS. Alternatively, or otherwise, as Figure 2B As shown, the bottom end TS of the protrusion PP can be located on the bit line 120. For example, the bottom end TS of the protrusion PP can be arranged in the bit line capping pattern 125 of the bit line structure BLS.

[0042] The bottom end of the spacer cover pattern 171 and / or the top end of the air spacer 136 may be located at a higher level than the top surface of the metal pattern 123. The height h2 of the air spacer 136 may be greater than the height h1 of the spacer cover pattern 171 (see...). Figure 2A The dielectric constant of the air spacer 136 may be less than that of the spacer cap pattern 171; for example, the air spacer 136 may comprise air, such as clean, dry air, and have a dielectric constant of about 1. Therefore, reduced parasitic capacitance can be provided between the bit line 120 and the memory node contact 153.

[0043] Reference Figure 3A The width of the spacer cap pattern 171, measured in the first direction D1, can increase as the distance from the semiconductor substrate 100 decreases. For example, the bottom end of the spacer cap pattern 171 has a width w2 in the first direction D1, and its top end has a width w1 in the first direction D1 that is smaller than the width w2. The spacer cap pattern 171 may have a width w1 at the bottom level of the second interlayer dielectric layer 170, and a width w2 at the top of the air spacer 136.

[0044] Alternatively, refer to Figure 3B The spacer cover pattern 171 may have a width w3 in the first direction D1, and the width w3 may be uniform regardless of its distance from the semiconductor substrate 100.

[0045] Figures 4A to 12AA plan view is shown illustrating a method of manufacturing a semiconductor memory device according to some example embodiments of the concept of the present invention. Figures 4B to 12B It shows along Figures 4A to 12A A sectional view taken from lines A-A' and B-B'. Figures 4C to 12C It shows along Figures 4A to 12A A sectional view taken from lines C-C' and D-D'.

[0046] Reference Figure 4A , Figure 4B and Figure 4C A device isolation layer 101 may be formed in a semiconductor substrate 100, defining an active region ACT. The device isolation layer 101 may be formed by forming substrate trenches (not shown) in the semiconductor substrate 100 and subsequently filling the substrate trenches with a dielectric material. The device isolation layer 101 may be formed using a shallow trench isolation (STI) process. The active regions ACT defined by the substrate trenches may be arranged two-dimensionally along a first direction D1 and a second direction D2. When viewed in a plan view, the active regions ACT may be arranged in a zigzag pattern.

[0047] Multiple word lines WL extending in a first direction D1 may be provided on the semiconductor substrate 100. For example, the active region ACT and the device isolation layer 101 may be patterned to form a gate recess 102 extending in the first direction D1. A gate dielectric layer 103 may be formed in the gate recess 102. The gate dielectric layer 103 may be formed by an in-situ vapor generation (ISSG) process; however, the inventive concept is not limited thereto. After the gate dielectric layer 103 is formed, the word lines WL may be formed in the gate recess 102. The bottom surface of the gate recess 102 may be higher than the bottom surface of the device isolation layer 101. The top surface of the word lines WL may be lower than the top surface of the device isolation layer 101. A hard mask pattern 105 may be formed in the gate recess 102 in which the word lines WL are arranged.

[0048] After forming word lines WL, a first impurity region 1a and a second impurity region 1b can be formed in the active region ACT on opposite sides of each word line WL. The first impurity region 1a and the second impurity region 1b can be formed by performing an ion implantation process, and the first impurity region 1a and the second impurity region 1b can have a conductivity type opposite to that of the active region ACT. The first impurity region 1a and the second impurity region 1b can be formed simultaneously; however, the inventive concept is not limited thereto.

[0049] The first interlayer dielectric layer 110 may be formed on the entire surface of the semiconductor substrate 100. The first interlayer dielectric layer 110 may include a single dielectric layer or multiple dielectric layers. For example, the first interlayer dielectric layer 110 may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0050] In a particular example embodiment, the semiconductor substrate 100 and the first interlayer dielectric layer 110 may be patterned to form recesses 111 that expose corresponding first impurity regions 1a. For example, each of the recesses 111 may have an ellipse with its major axis in the second direction D2. When viewed in a plan view, the recesses 111 may be arranged in a zigzag and / or honeycomb pattern.

[0051] In a particular example embodiment, when an anisotropic etching process is performed to form the recess 111, the anisotropic etching process may partially etch the first impurity region 1a, the device isolation layer 101 adjacent to the first impurity region 1a, and the hard mask pattern 105. The bottom surface of the recess 111 may be higher than the bottom surface of the first impurity region 1a, and partially expose the device isolation layer 101 and the hard mask pattern 105.

[0052] Reference Figure 5A , Figure 5B and Figure 5C A bit line structure BLS extending in the second direction D2 can be formed on the first interlayer dielectric layer 110 having a recess 111.

[0053] The formation of the bit line structure (BLS) may include: forming a first conductive layer filling the recess 111 on a first interlayer dielectric layer 110; forming a second conductive layer on the first conductive layer; forming a hard mask layer on the second conductive layer; forming a bit line mask pattern on the hard mask layer; and sequentially etching the hard mask layer, the second conductive layer, and the first conductive layer using the bit line mask pattern as an etching mask. The first conductive layer may be formed of a doped semiconductor layer (e.g., a doped polysilicon layer), and the second conductive layer may be formed of a metal layer (e.g., at least one of a tungsten layer, an aluminum layer, a titanium layer, or a tantalum layer). A metal silicide layer may be formed between the first conductive layer and the second conductive layer.

[0054] Because the bit line structure (BLS) is formed as described above, each of the bit line structures (BLS) may include a polysilicon pattern 121, a silicide pattern 122, a metal pattern 123, and a bit line capping pattern 125 stacked in sequence. A portion of the polysilicon pattern 121 may be locally formed in the recess 111, thus constituting a bit line contact pattern DC that directly contacts the first impurity region 1a, for example, it may be included in the bit line contact pattern DC that directly contacts the first impurity region 1a. The polysilicon pattern 121 may have sidewalls spaced apart from the sidewalls of the recess 111.

[0055] Reference Figure 6A , Figure 6B and Figure 6CA first spacer 131, a sacrificial spacer 133, and a second spacer 134 can be formed in sequence to provide a primary spacer structure PSS on the sidewall of the bitline structure BLS. The first spacer 131, the sacrificial spacer 133, and the second spacer 134 can sequentially cover the sidewall of the bitline structure BLS.

[0056] For example, the formation of the first spacer 131 may include: depositing a spacer layer that fills the recess 111 and conformally covers the bit line structure BLS; and anisotropically etching the spacer layer. The spacer layer may include a first nitride layer, an oxide layer, and a second nitride layer stacked in sequence. When the spacer layer is anisotropically etched, the oxide layer may serve as an etch stop layer, and the oxide layer and the second nitride layer may be partially retained in the recess 111 to form a bit line contact spacer DCP. The first spacer 131 may include a lower segment filling the recess 111 and a sidewall segment covering the sidewall of the bit line structure BLS. In a particular example embodiment, the first spacer 131 may extend along the sidewall of the bit line structure BLS in a second direction D2 and may fill the recess 111.

[0057] After the first spacer 131 is formed, a sacrificial layer may be formed to conformally cover the entire surface of the semiconductor substrate 100, and then anisotropically etched to form sacrificial spacers 133 on the sidewalls of the bit line structure BLS. The sacrificial spacer 133 may be formed of a dielectric material, such as a silicon oxide layer, having etch selectivity relative to the first spacer 131. On the first spacer 131, the sacrificial spacer 133 may extend along the sidewalls of the bit line structure BLS in a second direction D2.

[0058] After the sacrificial spacer 133 is formed, the second spacer 134 is formed to conformally cover the bit line structure BLS and the sacrificial spacer 133. The second spacer 134 may be formed of a dielectric material that has etch selectivity relative to the sacrificial spacer 133 and the first interlayer dielectric layer 110. For example, the second spacer 134 may be formed of a silicon nitride layer and / or a silicon oxynitride layer.

[0059] Reference Figure 7A , Figure 7B and Figure 7C The sacrificial pattern 141 and the dielectric pattern 143 may be formed to be alternately arranged between the bit line structure BLS and may extend along the second direction D2. In a particular example embodiment, the dielectric pattern 143 may be formed on the word line WL and the sacrificial pattern 141 may be formed on the second impurity region 1b.

[0060] For example, the formation of the sacrificial pattern 141 and the dielectric pattern 143 may include: forming a sacrificial layer on the second spacer 134 to fill the space between the bit line structures BLS; forming a plurality of mask patterns (not shown) extending parallel to the word line WL in the first direction D1 on the sacrificial layer; using the bit line structures BLS and the mask patterns as etch masks to anisotropically etch the sacrificial layer to form the sacrificial pattern 141 that exposes the upper part of the word line WL; forming a dielectric layer to fill the space between the sacrificial patterns 141 and between the bit line structures BLS; and planarizing the dielectric layer to expose the top surface of the mask patterns.

[0061] When viewed in a plan view, the sacrificial patterns 141 may be spaced apart from each other in the second direction D2 and arranged between word lines WL. The sacrificial patterns 141 may be formed of a material that has etch selectivity relative to the second spacer 134. For example, the sacrificial patterns 141 may be formed of a spin-coated hard mask (SOH) material (such as SOH silicon oxide). The top surface of the bit line structure BLS between the mask patterns may also be etched during the formation of the sacrificial patterns 141.

[0062] The dielectric pattern 143 may fill the empty space defined by the sacrificial pattern 141 and the bit line structure BLS, and may overlap with the word line WL when viewed in a planar view. The dielectric pattern 143 may be formed of a dielectric material having etch selectivity relative to the sacrificial pattern 141, and the dielectric material may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0063] Reference Figure 8A , Figure 8B and Figure 8C After the dielectric pattern 143 is formed, the sacrificial pattern 141 can be removed using an etching formulation that has etch selectivity relative to the dielectric pattern 143 and the second spacer 134. Therefore, the dielectric patterns 143 can be exposed on their sidewalls, and the second spacer 134 can be partially exposed. A contact area can be defined between the sidewalls of the dielectric pattern 143 facing in the second direction D2 and between the second spacer 134 facing in the first direction D1.

[0064] The dielectric pattern 143 and the bit line structure BLS can be used as an etching mask to anisotropically etch the first interlayer dielectric layer 110 and the portion of the semiconductor substrate 100 exposed to the contact region, and thus a contact hole 145 exposing the second impurity region 1b can be formed.

[0065] When the contact hole 145 is formed, the semiconductor substrate 100 and the device isolation layer 101 can be partially etched. The bottom surface of the contact hole 145 may be lower than the top surface of the semiconductor substrate 100 and may expose a portion of the bit line contact spacer DCP that fills the recess 111.

[0066] Reference Figure 9A , Figure 9B and Figure 9C The storage node contact 153 may be formed to fill the lower portion of the contact hole 145. Forming the storage node contact 153 may include: depositing a conductive layer to fill the contact hole 145; planarizing the conductive layer to expose the top surface of the bit line structure BLS and the dielectric pattern 143; and recessing the top surface of the conductive layer. In a particular example embodiment, the top surface of the storage node contact 153 may be lower than the top surface of the bit line capping pattern 125 of the bit line structure BLS. The storage node contact 153 may include one or more of, for example, a doped semiconductor material (e.g., doped silicon), a metallic material (e.g., tungsten, aluminum, titanium, or tantalum), a conductive metal nitride material (e.g., titanium nitride, tantalum nitride, or tungsten nitride), and a metal semiconductor compound (e.g., a metal silicide).

[0067] A contact silicide pattern 155 may be formed on the top surface of the storage node contact 153. The contact silicide pattern 155 may be formed by the reaction of a metallic material with the top surface of the storage node contact 153. For example, the contact silicide pattern 155 may be formed from at least one of titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, or molybdenum silicide. Alternatively, the contact silicide pattern 155 may not be formed.

[0068] The lower landing pad LPa can be formed to fill the upper part of the contact hole 145 and connect to the corresponding storage node contact 153, and the blocking pattern 157 can be formed to surround the side surface and bottom surface of the lower landing pad LPa.

[0069] The formation of the lower landing pad LPa and the barrier pattern 157 may include: conformally depositing a barrier layer on the entire surface of the semiconductor substrate 100; forming a metal layer on the barrier layer to fill the remainder of the contact hole 145; and etching the metal layer to form the lower landing pad LPa arranged along a first direction D1 and a second direction D2. Simultaneously with etching the metal layer, the barrier layer on the bit line structure BLS may also be etched to expose the top surface of the bit line structure BLS. In a particular example embodiment, the barrier layer may not be etched along with the metal layer, but may be left on the bit line structure BLS. Therefore, by referring to... Figures 10A to 10C The planarization process discussed is used to remove the blocking layer on the bit line structure (BLS).

[0070] Reference Figure 10A , Figure 10B and Figure 10CA planarization process can be performed on the semiconductor substrate 100. The planarization process may include a chemical mechanical polishing (CMP) process. The CMP slurry may include abrasive particles, an oxidant, and a pH adjuster to polish a metal layer such as a lower landing pad LPa. The height of each of the bit line structure BLS and the lower landing pad LPa may be reduced due to the planarization process. The sacrificial spacer 133 may have a top surface exposed between the first spacer 131 and the second spacer 134, the width of which in the first direction D1 may increase as the planarization process proceeds. Conversely, as... Figure 10B As shown, the lower landing pad LPa may have a top surface whose width in the first direction D1 can decrease as the planarization process proceeds. For example... Figure 10C As shown, the top surface of the lower landing pad LPa can have a uniform width in the second direction D2. In a particular example embodiment, the top surface of the sacrificial spacer 133 may be covered by the first spacer 131 and / or the second spacer 134 before performing the planarization process. Therefore, the top surface of the sacrificial spacer 133 can be exposed by the planarization process.

[0071] Reference Figure 11A , Figure 11B and Figure 11C The sacrificial spacer 133 can be removed to form an air gap AG between the first spacer 131 and the second spacer 134. Forming the air gap AG may include performing an ashing process on the exposed top surface of the sacrificial spacer 133. Forming the air gap AG may also include providing an etchant to the top surface of the sacrificial spacer 133 to etch it. For example, forming the air gap AG may include etching the sacrificial spacer 133 with a wet etchant chemical such as buffered hydrogen fluoride and / or sulfuric acid; however, the inventive concept is not limited thereto.

[0072] Reference Figure 12A , Figure 12B and Figure 12CA second interlayer dielectric layer 170 may be formed on the entire surface of the semiconductor substrate 100. The second interlayer dielectric layer 170 may cover the top surface of the bit line structure BLS, the lower landing pad LPa, and the dielectric pattern 143. Formation of the second interlayer dielectric layer 170 may include performing a deposition process on the entire surface of the semiconductor substrate 100 to allow the second interlayer dielectric layer 170 to have excellent gap-filling characteristics. For example, the deposition process may include performing atomic layer deposition (ALD) using a precursor including dichlorosilane (DCS, such as SiH2Cl2). Alternatively or additionally, the deposition process may include performing plasma-enhanced chemical vapor deposition (PECVD) using silicon carbonitride (SiCN). Alternatively or additionally, the deposition process may include performing high-density plasma chemical vapor deposition (HDPCVD). While forming the second interlayer dielectric layer 170, a spacer cap pattern 171 extending from the bottom surface of the second interlayer dielectric layer 170 toward the space between the first spacer 131 and the second spacer 134 may also be formed. The spacer cap pattern 171 and the second interlayer dielectric layer 170 can be connected to form a single body.

[0073] When forming the spacer cover pattern 171, an air spacer 136 may be defined between the first spacer 131 and the second spacer 134 and below the spacer cover pattern 171. Therefore, the bit line structure BLS may have a spacer structure SS on its sidewall comprising the first spacer 131, the second spacer 134, the air spacer 136, and the spacer cover pattern 171. The top end of the air spacer 136 and / or the bottom end of the spacer cover pattern 171 may be located at a higher level than the top surface of the metal pattern 123. The vertical height of the air spacer 136 may be greater than the vertical height of the spacer cover pattern 171.

[0074] Return to reference Figure 1A , Figure 1B and Figure 1C This can form the upper landing pad LPb, which passes through the second interlayer dielectric layer 170 and is connected to the lower landing pad LPa.

[0075] For example, the second interlayer dielectric layer 170 may undergo an anisotropic etching process to form an isolation trench NSR that exposes portions of the lower landing pad LPa. When viewed in plan view, the isolation trench NSR may be arranged in a zigzag or honeycomb pattern. The isolation trench NSR exposes not only a portion of the lower landing pad LPa, but also a portion of the bitline capping pattern 125 and a portion of the spacer structure SS. A metal layer (not shown) may be formed to fill the isolation trench NSR, and a planarization process may be performed to form upper landing pads LPb that are node-separated from each other. The top surface of the upper landing pad LPb may be coplanar with the top surface of the second interlayer dielectric layer 170.

[0076] According to some exemplary embodiments of the present invention, semiconductor memory devices with improved reliability and easier manufacturing can be provided.

[0077] Although the inventive concept has been described with reference to some exemplary embodiments shown in the accompanying drawings, those skilled in the art should understand that various changes and modifications can be made without departing from the technical spirit and essential features of the inventive concept. Those skilled in the art should recognize that various substitutions, modifications, and alterations can be made without departing from the scope and spirit of the inventive concept.

Claims

1. A semiconductor memory device, comprising: a substrate; a bit line structure extending in one direction on the substrate, the bit line structure including a sidewall; a storage node contact on the sidewall of the bit line structure; a first spacer and a second spacer between the sidewall of the bit line structure and the storage node contact, the first spacer separated from the second spacer by a space between the first spacer and the second spacer; an interlayer dielectric layer on the bit line structure, the interlayer dielectric layer including a bottom surface; a spacer cap pattern extending downward from the bottom surface of the interlayer dielectric layer toward the space between the first spacer and the second spacer; and a landing pad structure through the interlayer dielectric layer, the landing pad structure coupled to the storage node contact, wherein the landing pad structure includes a flat region parallel to a top surface of the substrate; and the flat region is between the bottom surface of the interlayer dielectric layer and a bottom surface of the landing pad structure.

2. The semiconductor memory device of claim 1, wherein the first spacer and the second spacer define an air spacer therebetween, the air spacer being below the spacer cap pattern. the landing pad structure includes:

3. The semiconductor memory device according to claim 1, wherein, a protrusion protruding toward the substrate, the protrusion contacting the spacer cap pattern.

4. The semiconductor memory device of claim 1, wherein the landing pad structure includes a protrusion protruding toward the substrate; and a bottom end of the protrusion is between the bottom surface of the interlayer dielectric layer and a bottom end of the spacer cap pattern in a vertical direction.

5. The semiconductor memory device of claim 1, wherein the landing pad structure includes a protrusion protruding toward the substrate; and a bottom end of the protrusion is on one of the first spacer, the second spacer, and the spacer cap pattern. the flat region of the landing pad structure is in contact with the bottom surface of the interlayer dielectric layer.

6. The semiconductor memory device of claim 1, wherein, 7. The semiconductor memory device of claim 1, wherein the bit line structure includes a bit line and a bit line cap pattern on the bit line, and the landing pad structure is in contact with the bit line cap pattern. a top surface of the landing pad structure is at the same level as a top surface of the interlayer dielectric layer.

8. The semiconductor memory device of claim 1, wherein, a bottom end of the spacer cap pattern is at a higher level than a top surface of the storage node contact.

9. The semiconductor memory device of claim 1, wherein, a width of the spacer cap pattern increases as a distance from the bottom surface of the interlayer dielectric layer increases.

10. The semiconductor memory device of claim 1, wherein, 11. A semiconductor memory device, comprising: a substrate including a first active region and a second active region, the first active region and the second active region spaced apart from each other; a bit line structure coupled to the first active region, the bit line structure passing through the substrate, the bit line structure including a sidewall; a spacer structure on the sidewall of the bit line structure; an interlayer dielectric layer on the bit line structure and the spacer structure; and a landing pad structure through the interlayer dielectric layer, the landing pad structure coupled to the storage node contact. ​ a landing pad structure that passes through the interlayer dielectric layer and is electrically connected to the second active region, the landing pad structure including a protrusion that protrudes toward the substrate, and a bottom end of the protrusion being at a lower level than a top end of the spacer structure, wherein the landing pad structure includes a flat region that is parallel to a top surface of the substrate; and the flat region is between a bottom surface of the interlayer dielectric layer and a bottom surface of the landing pad structure.

12. The semiconductor memory device of claim 11, wherein the bit line structure includes: a bit line, and a bit line cap pattern on the bit line, and the protrusion is in contact with the bit line cap pattern.

13. The semiconductor memory device of claim 11, wherein, a top surface of the landing pad structure is at a same level as a top surface of the interlayer dielectric layer.

14. The semiconductor memory device of claim 11, wherein, a bottom end of the protrusion is on the spacer structure.

15. A semiconductor memory device, comprising: a substrate; a pair of bit line structures on the substrate, the pair of bit line structures extending in parallel along a direction; a storage node contact between the pair of bit line structures; a lower landing pad between the pair of bit line structures, the lower landing pad being on the storage node contact; an interlayer dielectric layer on the pair of bit line structures and the lower landing pad, the interlayer dielectric layer including a bottom surface; and an upper landing pad that passes through the interlayer dielectric layer and is coupled to the lower landing pad, a bottom end of the upper landing pad being at a lower level than the bottom surface of the interlayer dielectric layer, wherein the lower landing pad includes a flat region that is parallel to a top surface of the substrate; and the flat region is between the bottom surface of the interlayer dielectric layer and a bottom surface of the lower landing pad.

16. The semiconductor memory device of claim 15, further comprising: a barrier pattern between the lower landing pad and the pair of bit line structures; and wherein an uppermost surface of the barrier pattern is at a same level as the bottom surface of the interlayer dielectric layer.

17. The semiconductor memory device of claim 15, wherein, a top surface of the lower landing pad is in contact with the bottom surface of the interlayer dielectric layer.

18. The semiconductor memory device of claim 15, wherein, at least a portion of the upper landing pad vertically overlaps the bit line structure.

19. The semiconductor memory device of claim 15, wherein, a bottom end of the upper landing pad is between the bit line structure and the lower landing pad.

20. A method of manufacturing a semiconductor memory device, the method comprising: forming a bit line structure on a substrate; forming a first spacer, a sacrificial spacer, and a second spacer that cover a sidewall of the bit line structure in order; forming a lower landing pad on a side surface of the second spacer; removing the sacrificial spacer to form an air gap between the first spacer and the second spacer; forming an interlayer dielectric layer on the bit line structure and the lower landing pad, the interlayer dielectric layer filling an upper portion of the air gap; and forming an upper landing pad that passes through the interlayer dielectric layer, the upper landing pad being coupled to the lower landing pad, ​ wherein the lower landing pad includes a flat region parallel to a top surface of the substrate; and the flat region is between a bottom surface of the interlayer dielectric layer and a bottom surface of the lower landing pad.

21. The method of claim 20, further comprising, prior to removing the sacrificial spacers: performing a planarization process on the substrate, the planarization process increasing a width of a top surface of the sacrificial spacers, the top surface exposed by the first spacers and the second spacers.

22. The method of claim 20, wherein, forming the upper landing pad includes: performing an etch process on the interlayer dielectric layer, the etch process forming an isolation trench, a bottom surface of the isolation trench at a lower level than a top surface of the lower landing pad; and forming the upper landing pad in the isolation trench.

Images