Semiconductor device and method of manufacturing the same

Abstract

Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a bottom substrate, a protruding structure on the bottom substrate, a porous film on a side surface and an upper surface of the protruding structure, and an air gap between at least a portion of the side surface of the protruding structure and the porous film.

Description

[0001] Korean Patent Application No. 10-2018-0167539, entitled "Semiconductor Device and Method of Manufacturing Thereof," filed on December 21, 2018, with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0002] The embodiments relate to a semiconductor device and a method of manufacturing the same. Background Technology

[0003] As semiconductor devices become increasingly integrated, the distance between wiring layers becomes narrower. The insulating layers used between these layers can have a high dielectric constant. The capacitance between the wiring layers may increase due to the high dielectric constant of the insulating layers. As capacitance increases, signal delay may occur, and consequently, the characteristics of the semiconductor device may deteriorate. Summary of the Invention

[0004] The embodiments relate to a semiconductor device including a bottom substrate, a protruding structure on the bottom substrate, a side surface of the protruding structure and a porous film on a top surface, and an air gap between at least a portion of the side surface of the protruding structure and the porous film.

[0005] The embodiments also relate to a semiconductor device including a bottom substrate, a protruding structure on the bottom substrate, a porous film extending along a side surface of the protruding structure, and an air gap between the side surface of the protruding structure and an inner surface of the porous film. The upper surface of the bottom substrate may include a first point spaced apart from the side surface of the protruding structure by a first distance and a second point spaced apart from the side surface of the protruding structure by a second distance greater than the first distance, and the height of the air gap at the first point may be greater than the height of the air gap at the second point.

[0006] The embodiments also relate to a semiconductor device including a bottom substrate, a protruding structure on the bottom substrate, a porous film extending along a side surface of the protruding structure, and an air gap between the side surface of the protruding structure and the porous film, the air gap including a first portion having a width that continuously decreases with distance from the upper surface of the bottom substrate. Attached Figure Description

[0007] The features will become clear to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, wherein:

[0008] Figure 1 A cross-sectional view of a semiconductor device according to some example embodiments is shown;

[0009] Figure 2 It shows Figure 1 A diagram illustrating the height difference of the air gap;

[0010] Figure 3 It shows Figure 1 A diagram showing the width difference of the air gap;

[0011] Figures 4 to 7 A diagram is shown for illustration. Figure 1 A diagram illustrating the shape of the air gap;

[0012] Figure 8 A cross-sectional view of a semiconductor device according to some example embodiments is shown;

[0013] Figure 9 A cross-sectional view of a semiconductor device according to some example embodiments is shown;

[0014] Figure 10 A cross-sectional view of a semiconductor device according to some example embodiments is shown;

[0015] Figure 11 A cross-sectional view of a semiconductor device according to some example embodiments is shown;

[0016] Figure 12 A cross-sectional view of a semiconductor device according to some example embodiments is shown;

[0017] Figure 13 A cross-sectional view of a semiconductor device according to some example embodiments is shown;

[0018] Figure 14 A flowchart illustrating a method for manufacturing a semiconductor device according to some example embodiments is shown;

[0019] Figure 15 It shows in detail Figure 14 Flowchart of operation S120;

[0020] Figure 16 It shows in detail Figure 14 The sectional view of operation S110;

[0021] Figure 17 It shows in detail Figure 15 The sectional view of operation S112;

[0022] Figure 18 It shows Figure 17 A magnified view of region R2;

[0023] Figure 19 It shows in detail Figure 15 Sectional views of operations S124 and S126;

[0024] Figure 20 It shows the way Figure 14 A cross-sectional view of the polymer brush film formed by operation S120;

[0025] Figure 21It shows Figure 19 A magnified view of region R3;

[0026] Figure 22 It shows in detail Figure 14 The sectional view of operation S130;

[0027] Figure 23 It shows in detail Figure 14 The sectional view of operation S140;

[0028] Figure 24 It shows the way Figure 14 A cross-sectional view of the air gap formed by the method of manufacturing a semiconductor device. Detailed Implementation

[0029] Exemplary embodiments will now be described more fully with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully impart exemplary implementation methods to those skilled in the art. In the drawings, the dimensions of layers and regions may be exaggerated for clarity. The same reference numerals always refer to the same elements.

[0030] In the following text, reference will be made to Figures 1 to 7 Describes a semiconductor device according to some example embodiments. Figure 1 This is a cross-sectional view used to illustrate a semiconductor device according to some example embodiments. Figure 2 It is used to show Figure 1 A diagram showing the height difference of the air gap. Figure 3 It is used to show Figure 1 A diagram showing the width difference of the air gap. Figures 4 to 7 It is used to show Figure 1 A diagram illustrating the shape of the air gap. It should be noted that... Figures 5 to 7 It is used to show Figure 4 A cross-sectional view of area R1.

[0031] Reference Figure 1 A semiconductor device according to some example embodiments may include a substrate 10, a protrusion structure 20, a porous film 30, an air gap 40, and a dielectric layer 50.

[0032] The substrate 10 may be a silicon substrate, or it may be a substrate made of a material such as silicon germanium (SiGe), indium antimony (InSb), lead telluride (PbTe) compound, indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs), or gallium antimony (GaSb). In another embodiment, the substrate 10 may be formed by growing an epitaxial layer on a bottom substrate.

[0033] The protruding structure 20 may protrude from the substrate 10. The protruding structure 20 may be located on the upper surface 12 of the substrate 10. The protruding structure 20 may include the same material as the substrate 10, or the protruding structure 20 may include a different material from the substrate 10.

[0034] The dielectric layer 50 may be located on the side surface 24 of the protruding structure 20. Therefore, the inner surface 52 of the dielectric layer 50 may face the side surface 24 of the protruding structure 20. For example, the dielectric layer 50 may include one or more of silicon oxide, silicon nitride, or silicon oxynitride.

[0035] The porous membrane 30 may be located on the upper surface 22 and side surface 24 of the protruding structure 20. The porous membrane 30 may have an inner surface 32 and an outer surface 34. The inner surface 32 of the porous membrane 30 may include a portion extending along the upper surface 22 of the protruding structure 20.

[0036] The inner surface 32 of the porous membrane 30 may include a first portion extending along the outer surface 54 of the dielectric layer 50 and a second portion defining an air gap 40. The first portion of the inner surface 32 of the porous membrane 30 may contact (e.g., in direct contact) the outer surface 54 of the dielectric layer 50. The second portion of the inner surface 32 of the porous membrane 30 may contact the outer surface 44 of the air gap 40 formed on the side surface 24 of the protruding structure 20.

[0037] A portion of the porous membrane 30 may be located on the upper surface 12 of the substrate 10. Therefore, a portion of the porous membrane 30 may face a portion of the upper surface 12 of the substrate 10.

[0038] The porous membrane 30 may be an insulating membrane comprising multiple pores. The porous membrane 30 may allow oxygen (O2), carbon dioxide (CO2), and water (H2O) to pass through the multiple pores. The porous membrane 30 may prevent silicon oxide or silicon nitride from passing through the multiple pores. The porous membrane 30 may comprise silicon oxide and / or silicon nitride deposited by an atomic layer deposition (ALD) process. The porous membrane 30 may comprise silicon oxide or silicon nitride deposited by an atomic layer deposition (ALD) process at a temperature above room temperature or ambient temperature and below 400°C.

[0039] An air gap 40 may be defined between at least a portion of the side surface 24 of the protruding structure 20 and the inner surface 32 of the porous membrane 30. The inner surface 42 of the air gap 40 may contact a portion of the outer surface 54 of the dielectric layer 50. The outer surface 44 of the air gap 40 may contact a portion of the inner surface 32 of the porous membrane 30. The lower surface 46 of the air gap 40 may be located on the upper surface 12 of the substrate 10. For example, as... Figure 1As shown, the air gap 40 may, for example, be surrounded by the outer surface 54 of the dielectric layer 50 and the inner surface 32 of the porous film 30, and the lower surface 46 of the air gap 40 may be in direct contact with the upper surface 12 of the substrate 10. The air gap 40 may be filled with air. The air in the air gap 40 may have a low dielectric constant of approximately -1. The air gap 40 between semiconductor elements can reduce the capacitance between semiconductor elements.

[0040] Reference Figure 2 The air gap 40 may have a wedge shape. The upper surface 12 of the substrate 10 may include a virtual first point P1a spaced apart from the protruding structure 20 by a first distance. The upper surface 12 of the substrate 10 may include a virtual second point P1b spaced apart from the protruding structure 20 by a second distance greater than the first distance. The height H1a of the air gap 40 at the first point P1a may be greater than the height H1b of the air gap 40 at the second point P1b.

[0041] Reference Figure 3 The air gap 40 may include a first portion 40a and a second portion 40b. The width of the first portion 40a of the air gap 40 may decrease as it moves away from the upper surface 12 of the substrate 10. The second portion 40b of the air gap 40 may have a constant width regardless of its distance from the substrate.

[0042] Reference Figure 4 In region RI, a portion of the porous membrane 30 may contact a portion of the dielectric layer 50, and the remaining portion of the porous membrane 30 may contact a portion of the air gap 40. The interface between the porous membrane 30 and the dielectric layer 50 may smoothly connect to the interface between the porous membrane 30 and the air gap 40.

[0043] Reference Figure 5 The inner surface of the porous membrane 30 may include a virtual point P in region R1. At point P on the inner surface of the porous membrane 30, the inclination of the inner surface of the porous membrane 30 can be expressed as the angle θ_P formed between the plane S1 parallel to the side surface of the protruding structure 20 and the inner surface S2_P of the porous membrane 30.

[0044] Reference Figure 6 The inner surface of the porous membrane 30 may include the virtual maximum tilt point P in region R1. max It has the gentlest slope. For example, at the point of maximum slope P... max At the location, a plane S1 parallel to the side surface of the protruding structure 20 and an inner surface S2 of the porous membrane 30 are formed. max The angle θ_P between max It can be 90° or smaller.

[0045] Thus, the inner surface of the porous membrane 30 does not include a recessed shape. If the inner surface of the porous membrane 30 includes a recessed shape, then the plane S1 formed parallel to the side surface of the protruding structure 20 and the inner surface S2 of the porous membrane 30 are... max The angle θ_P between max The angle exceeds 90°. Conversely, in semiconductor devices according to some example embodiments, a plane S1 parallel to the side surface of the protruding structure 20 and an inner surface S2 of the porous film 30 are formed. max The angle θ_P between max No more than 90°

[0046] Reference Figure 7 The inner surface of the porous membrane 30 may extend smoothly along the outer surface of the dielectric layer 50 and the outer surface of the air gap 40. The inner surface of the porous membrane 30 may include a virtual moving point P2 that gradually moves away from the outer surface of the dielectric layer 50.

[0047] The moving point P2 can move along the inner surface of the porous membrane 30 from point P2a to point P2b. Point P2a can be located at the contact point between the inner surface of the porous membrane 30 and the outer surface of the dielectric layer 50. Point P2b can be located at the contact point between the inner surface of the porous membrane 30 and the outer surface of the air gap 40.

[0048] As the moving point P2 moves along the inner surface of the porous membrane 30, the angle formed at the moving point P2 between the side surface of the protruding structure 20 and the inner surface of the porous membrane 30 can continuously change. This can be adjusted according to... Figure 5 The angle formed at point P between the side surface of the protruding structure 20 and the inner surface of the porous membrane 30 is obtained in the same way as the angle formed at point P2 between the side surface of the protruding structure 20 and the inner surface of the porous membrane 30.

[0049] Therefore, as the moving point P2 on the inner surface of the porous membrane 30 moves from point P2a on the outer surface of the dielectric layer 50 to point P2b on the outer surface of the air gap 40, the inner surface of the porous membrane 30 can be smoothly extended.

[0050] If the angle formed between the side surface of the protruding structure 20 and the inner surface of the porous membrane 30 varies discontinuously along the inner surface of the porous membrane 30 (i.e., if the inner surface of the porous membrane 30 includes points of discontinuity), the porous membrane 30 cannot extend smoothly, and at the points where the angle between the side surface of the protruding structure 20 and the inner surface of the porous membrane 30 varies discontinuously, the inner surface of the porous membrane 30 may include unsmooth edges. Conversely, in a semiconductor device according to some example embodiments, the inner surface of the porous membrane 30 does not include points where the angle between the side surface of the protruding structure 20 and the inner surface of the porous membrane 30 varies discontinuously.

[0051] In the following text, reference will be made to Figure 8 Describes a semiconductor device according to some example embodiments. Figure 8 This is a cross-sectional view used to illustrate a semiconductor device according to some example embodiments. For ease of illustration, the description will focus on the above references. Figures 1 to 7 The differences described.

[0052] Reference Figure 8 The semiconductor device may include a porous film 30a on the side surface of the protruding structure 20. The inner surface of the porous film 30a may contact a portion of the outer surface of the dielectric layer 50 and the outer surface of the air gap 40. Therefore, the porous film 30a may not be located on the upper surface of the protruding structure 20. The porous film 30a may be arranged to cover a portion of the side surface of the protruding structure 20.

[0053] An air gap 40 may be formed between a portion of the side surface of the protruding structure 20 and the inner surface of the porous membrane 30. Therefore, the air gap 40 may be defined by the outer surface of the dielectric layer 50, the inner surface of the porous membrane 30, and the upper surface of the substrate 10.

[0054] In the following text, reference will be made to Figure 9 Describes a semiconductor device according to some example embodiments. Figure 9 This is a cross-sectional view used to illustrate a semiconductor device according to some example embodiments. For ease of illustration, the description will focus on the above references. Figures 1 to 8 The differences described.

[0055] Reference Figure 9 The semiconductor device may include a protruding structure 20a on a substrate 10, which forms an integral structure with the substrate 10. For example, each of the protruding structure 20a and the substrate 10 may be part of a single integral substrate. Thus, the protruding structure 20a may be defined as a protruding portion of the integral substrate. The substrate 10 may be defined as the remaining portion of the integral substrate other than the protruding structure 20a.

[0056] In the following text, reference will be made to Figure 10 Describes a semiconductor device according to some example embodiments. Figure 10 This is a cross-sectional view used to illustrate a semiconductor device according to some example embodiments. For ease of illustration, the description will focus on the above references. Figures 1 to 9 The differences described.

[0057] Reference Figure 10The semiconductor device may include a first protruding structure 20a1 and a second protruding structure 20a2 on a substrate 10. The first protruding structure 20a1 and the second protruding structure 20a2 may be integrally formed with the substrate 10. The first protruding structure 20a1 and the second protruding structure 20a2 may form a trench structure together with the substrate 10. The first protruding structure 20a1 and the second protruding structure 20a2 may be two sidewalls of the trench structure, and the upper surface of the substrate 10 and the side surfaces of the first protruding structure 20a1 and the second protruding structure 20a2 may define the trench structure.

[0058] A porous membrane 30 may be located on the upper and side surfaces of each of the first protruding structures 20a1 and 20a2. The porous membrane 30 may be located on the upper surface of the substrate 10. A dielectric layer 50 may be located on the side surface of each of the first protruding structures 20a1 and 20a2. An air gap 40 may be disposed between the porous membrane 30 and a portion of the side surface of each of the first and second protruding structures 20a1 and 20a2. Therefore, an air gap 40 may be formed on each of the sidewalls of the trench structure.

[0059] In the following text, reference will be made to Figure 11 Describes a semiconductor device according to some example embodiments. Figure 11 This is a cross-sectional view used to illustrate a semiconductor device according to some example embodiments. For ease of illustration, the description will focus on the above references. Figures 1 to 10 The differences described.

[0060] Reference Figure 11 The semiconductor device may include a protruding structure 20b on the substrate 10. The protruding structure 20b may include an interlayer dielectric film 20b1, a conductive layer 20b2, and a capping layer 20b3.

[0061] An interlayer dielectric film 20b1 may be located on the substrate 10. Although the interlayer dielectric film 20b1 is shown as... Figure 11 The substrate 10 is a plane parallel to the substrate 10, but the interlayer dielectric film 20b1 may be formed on the substrate 10 and may include, for example, a U-shape surrounding a portion of the conductive layer 20b2.

[0062] For example, the interlayer dielectric film 20b1 may include one or more of a low-k dielectric material, an oxide film, a nitride film, or an oxynitride film. For example, the low-k dielectric material may include flowable oxide (FOX), tonnensilazen (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate-phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETOS), fluorosilicate glass (FSG), carbon-doped silica (CDO), degelatin, aerogel, amorphous fluorinated carbon, organosilicon glass (OSG), parylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer materials, or combinations thereof.

[0063] The conductive layer 20b2 may be located on the interlayer dielectric film 20b1. Therefore, the conductive layer 20b2 may be disposed between the interlayer dielectric film 20b1 and the capping layer 20b3. The conductive layer 20b2 may include a conductive material. The conductive layer 20b2 may include at least one metal or may include a conductive semiconductor material.

[0064] The capping layer 20b3 may be located on the conductive layer 20b2. The capping layer 20b3 may be an insulating layer formed on the upper surface of the conductive layer 20b2. The capping layer 20b3 may include, for example, a silicon nitride film.

[0065] exist Figure 11 In the semiconductor device shown according to the example embodiment, a dielectric layer 50 may be located on each of the sidewalls of the protruding structure 20b. The inner surface of the dielectric layer 50 may be located on the side surfaces of the interlayer dielectric film 20b1, the conductive layer 20b2, and the capping layer 20b3. An air gap 40 may be located on each of the side surfaces of the protruding structure 20b.

[0066] The first height H1 from the substrate 10 to the air gap 40 can be greater than the second height H2 from the substrate 10 to the conductive layer 20b2. The first height H1 can refer to the height from the upper surface of the substrate 10 to the point where the air gap 40, the dielectric layer 50, and the porous film 30 meet. The second height H2 can refer to the height from the upper surface of the substrate 10 to the upper surface of the conductive layer 20b2. In this way, the air gap 40 can be arranged at a higher level than the conductive layer 20b2 arranged within the protruding structure 20.

[0067] In the following text, reference will be made to Figure 12 Describes a semiconductor device according to some example embodiments. Figure 12 This is a cross-sectional view used to illustrate a semiconductor device according to some example embodiments. For ease of illustration, the description will focus on the above references. Figures 1 to 11 The differences described.

[0068] Reference Figure 12 The semiconductor device may include a dielectric layer 50b on the upper surface of the substrate 10. The dielectric layer 50b on the upper surface of the substrate 10 may extend along the upper surface of the substrate 10.

[0069] exist Figure 12 In the semiconductor device shown according to the example embodiment, an air gap 40 may be defined by the outer surface of dielectric layer 50a, the outer surface of dielectric layer 50b, and the inner surface of porous film 30. The inner surface of air gap 40 may contact a portion of the outer surface of dielectric layer 50a, and the lower surface of air gap 40 may contact a portion of the outer surface of dielectric layer 50b. The outer surface of air gap 40 may contact a portion of the inner surface of porous film 30.

[0070] In the following text, reference will be made to Figure 13 Describes a semiconductor device according to some example embodiments. Figure 13 This is a cross-sectional view used to illustrate a semiconductor device according to some example embodiments. For ease of illustration, the description will focus on the above references. Figures 1 to 12 The differences described.

[0071] Reference Figure 13 The semiconductor device may include an outer insulating layer 60 surrounding a portion of the porous film 30. For example, such as Figure 13 As shown, the outer insulating layer 60 may surround a portion of the porous membrane 30 on the side surface of the protruding structure 20 and the porous membrane 30 disposed along the upper surface of the substrate. In another embodiment, the outer insulating layer 60 may be arranged to surround a portion of the porous membrane 30, which includes the porous membrane 30 on the upper surface of the protruding structure 20.

[0072] The outer insulating layer 60 may include one or more of a silicon oxide film, a silicon nitride (SiN) film, a silicon carbonitride (SiCN) film, a silicon oxycarbonitride (SiOCN) film, a silicon oxycarbide (SiOC) film, or a silicon oxynitride film. The material forming the outer insulating layer 60 cannot pass through the multiple pores in the porous membrane 30.

[0073] In the following text, reference will be made to Figures 14 to 24 A method for manufacturing a semiconductor device according to some example embodiments is described. Figure 14 This is a flowchart illustrating a method for manufacturing a semiconductor device according to some example embodiments. Figure 15 It is used to illustrate the operation in detail. Figure 14 The flowchart of S120. Figure 16 It is used to show in detail Figure 14 The sectional view of operation S110. Figure 17 It is used to show in detail Figure 15 The sectional view of operation S122. Figure 18 yes Figure 17 A magnified view of region R2. Figure 19 It is used to show in detail Figure 15 Sectional views of steps S124 and S126. Figure 20 It is used to show through Figure 14 A cross-sectional view of the polymer brush film formed by operation S120. Figure 21 yes Figure 19 A magnified view of region R3. Figure 22 It is used to show in detail Figure 14 The sectional view of operation S130. Figure 23 It is used to show in detail Figure 14 The sectional view of operation S140. Figure 24 It is used to show through Figure 14 A cross-sectional view of the air gap formed by the method of manufacturing a semiconductor device.

[0074] Reference Figure 14 A method for manufacturing a semiconductor device according to some example embodiments may include preparing a substrate, a protruding structure, and a dielectric layer (operation S110).

[0075] For example, refer to Figure 16 In operation S110, a substrate 10, a protruding structure 20, and a dielectric layer 50 may be provided. The protruding structure 20 may be configured as a sidewall of a trench formed in an integral substrate. In another example, the protruding structure 20 may be configured as a conductive structure formed on the substrate 10.

[0076] The dielectric layer 50 may be formed along the side surface of the protruding structure 20. Although the dielectric layer 50 is shown not along... Figure 16 The substrate is formed on the upper surface of the substrate 10, but a dielectric layer 50 may be formed along the upper surface of the substrate 10.

[0077] Return to reference Figure 14 A method of manufacturing a semiconductor device according to some example embodiments may include forming a polymer brush film on the outer surface of a dielectric layer (operation S120).

[0078] For example, refer to Figure 15 The step of forming a polymer brush film on the outer surface of the dielectric layer (operation S120) may include providing a polymer solution (operation S122).

[0079] For example, refer to Figure 16 and Figure 17 A polymer solution 170 can be provided to fill the space defined by the side surfaces of the protruding structure 20 and the upper surface of the substrate 10. Figure 17In the example shown, the polymer solution 170 used in the polymer coating process is shown to include polymer 172 and a solvent. In another embodiment, for example, the polymer solution 170 may be a molten solution containing only polymer 172.

[0080] For example, polymer 172 included in polymer solution 170 may include polystyrene (PS) or polymethyl methacrylate (PMMA).

[0081] Polymer 172 contained in polymer solution 170 can be used as a reference for forming Figure 20 The material of the polymer brush film 70 is described in detail. Therefore, in order to make the polymer brush film 70 have a uniform thickness, a polymer 172 with a uniform molecular weight can be used.

[0082] The polymers used in polymer coating processes can have a uniform molecular weight distribution. This distribution can be defined by the polydispersity index (PDI). PDI can be a value obtained by dividing the weight average molecular weight (Mw) by the number average molecular weight (Mn) (Mw / Mn).

[0083] The number average molecular weight (Mn) can be obtained by dividing the total molecular weight of the polymer by the number of polymers (e.g., in moles). The weight average molecular weight (Mw) can be obtained by dividing the sum of the squares of the molecular weights of the corresponding polymers by the total molecular weight.

[0084] The polydispersity index (PDI) can be used as a standard to represent the breadth of molecular weight distribution. For example, as the PDI approaches one, the polymer has a more uniform molecular weight.

[0085] In a method of manufacturing a semiconductor device according to some example embodiments, the polydispersity index (PDI) of polymer 172 contained in polymer solution 170 may be from 1 to 1.5.

[0086] Reference Figure 18 In operation S122, polymer 172 can be provided on the outer surface of dielectric layer 50 by providing a polymer solution. For example, dielectric layer 50 may include hydroxyl and / or epoxy groups, such as... Figure 18 The example shown. For example, polymer 172 may include hydroxyl groups, such as... Figure 18 The example shown.

[0087] Return to reference Figure 15 Step S120, which forms a polymer brush film on the outer surface of the dielectric layer, may include performing polymer coating (operation S124).

[0088] For example, refer to Figure 19 Polymer coating can be performed on the outer surface of the dielectric layer 50. For example, when... Figure 17When a heat treatment process is performed while polymer 172 is provided on the outer surface of dielectric layer 50, as shown, hydroxyl or epoxy groups on the outer surface of dielectric layer 50 can form covalent bonds with the hydroxyl groups of polymer 172. The polymer 172 coated on the outer surface of dielectric layer 50 can be formed as a monolayer. The layer formed by polymer 172 coated on the outer surface of dielectric layer 50 can be transformed into a polymer brush film 70, which will be referred to... Figure 20 Describe it.

[0089] Return to reference Figure 15 The step of forming a polymer brush film on the outer surface of the dielectric layer (operation S120) may include removing the polymer solution (operation S126).

[0090] For example, refer to Figure 19 Excess polymer solution 170 not used for polymer coating may remain on the upper surface of substrate 10 and the outer surface of dielectric layer 50. In operation S126 to remove polymer solution 170, the polymer solution 170 containing polymer 172 not involved in the reaction may be cleaned with water, organic solvents, etc.

[0091] Figure 20 It shows the way Figure 14 The polymer brush film 70 is formed by the operation S120 of forming a polymer brush film on the outer surface of the dielectric layer 50. This can be achieved by... Figure 17 The height of the polymer solution 170 provided in the steps shown determines the height of the polymer brush film 70. In some example embodiments, the height of the polymer brush film 70 can be adjusted by a dry etching process or a wet etching process.

[0092] In a method of manufacturing a semiconductor device according to some example embodiments, when the dielectric layer 50 is located on the upper surface of the substrate 10, polymer coating may also be performed on the outer surface of the dielectric layer 50 on the upper surface of the substrate 10. Therefore, a polymer brush film can be formed along the upper surface of the substrate 10. The polymer brush film formed along the upper surface of the substrate 10 can be removed by a dry etching process or a wet etching process. For example, by performing a dry etching process or a wet etching process, the height of the polymer brush film 70 can be adjusted and the polymer brush film formed along the upper surface of the substrate 10 can be removed.

[0093] Figure 21 It shows in detail the Figure 20 A polymer brush film 70 is formed in region R3. The polymer brush film 70 may include polymer elements 72 that have covalent bonds with the outer walls of the dielectric layer 50. The polymer elements 72 are generated by the shape deformation of the polymer 172 through a heat treatment process performed in operation S124. The polymer elements 72, like the polymer 172, may include a plurality of carbon atoms. Therefore, the polymer brush film 70 may include a carbon layer.

[0094] Return to reference Figure 14 A method for manufacturing a semiconductor device according to some example embodiments may include forming a porous film covering a polymer brush film (operation S130).

[0095] For example, refer to Figure 22 A porous membrane 30 can be formed along the upper surface of the protruding structure 20, the outer surface of the dielectric layer 50, the outer surface of the polymer brush film 70, and the upper surface of the substrate 10. For example, the porous membrane 30 can be formed by a deposition process.

[0096] For example, the porous film 30 may be silicon nitride or silicon oxide deposited by a low-temperature ALD process. The porous film 30 may be silicon nitride or silicon oxide deposited by an ALD process performed, for example, at a temperature above room temperature and below 400°C. The porous film 30 deposited by a low-temperature ALD process may not be dense. Therefore, the porous film 30 may include multiple pores.

[0097] Return to reference Figure 14 A method of manufacturing a semiconductor device according to some example embodiments may include removing a polymer brush film (operation S140).

[0098] For example, refer to Figure 23 The polymer brush membrane 70 can be removed via an ashing process. For example, in the ashing process, oxygen (O2) can be transferred to the polymer brush membrane 70 through multiple pores of the porous membrane 30. The polymer brush membrane 70 can be oxidized by oxygen to produce byproducts, such as gases, like carbon dioxide (CO2) and water vapor (H2O). These byproducts generated in the ashing process can be removed through the pores of the porous membrane 30. Therefore, the carbon dioxide and water produced by the ashing process can be discharged through the porous membrane 30.

[0099] When the polymer brush membrane 70 is removed from the interior 40c of the porous membrane 30 via an ashing process, the interior 40c of the porous membrane 30 can be filled with air. For example, after the polymer brush membrane 70 is removed, gas can occupy the space inside the interior 40c of the porous membrane 30. For example, the interior 40c of the porous membrane 30 can be filled with nitrogen (N2), oxygen (O2), or carbon dioxide (CO2) through the pores of the porous membrane 30. The porous membrane 30 can be stretched or shaped by air to have... Figure 24 The smooth shape shown.

[0100] Figure 24 It shows the way Figure 14The air gap is formed by the method of manufacturing a semiconductor device shown. When the interior of the porous film 30 is filled with air, the porous film 30 may contact a portion of the outer surface of the dielectric layer 50 and the outer surface of the air gap 40. A portion of the porous film 30 may be located on the upper surface of the upper substrate 10. The porous film 30 may have a smooth shape. The shape of the air gap 40 may be defined by the outer surface of the dielectric layer 50, the upper surface of the substrate 10, and the inner surface of the porous film 30. Therefore, the outer surface of the air gap 40 may include smooth curves and straight lines along the inner surface of the porous film 30.

[0101] In summary, to reduce capacitance between wiring layers, the use of air gaps has been considered. For example, a portion of the insulating layer formed on each of the two sidewalls of a metal wiring layer can be etched, and then an insulating film can be deposited again to form an air gap. However, if a dry etching process is used, the capping film of the metal wiring layer, which has low etch resistance, may deform or be removed. On the other hand, if a wet etching process is used, the etching solution can penetrate into thin portions of the metal film, causing the metal wiring to collapse. Therefore, there is a need for semiconductor devices that have air gaps formed without deformation or collapse of the wiring layers.

[0102] As described above, the embodiments may provide a semiconductor device with improved electrical characteristics and a method for forming the same.

[0103] This document has disclosed exemplary embodiments. While specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as should be apparent to one of ordinary skill in the art, unless otherwise stated, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, along with the filing of this application. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A semiconductor device, comprising: Bottom substrate; The protruding structure on the bottom substrate; The porous membranes on the side and top surfaces of the protruding structure; Air gap between at least a portion of the side surface of the protruding structure and the porous membrane; as well as The dielectric layer between the side surface of the protruding structure and the inner surface of the air gap. The angle formed by the plane parallel to the side surface of the protruding structure and the inner surface of the porous membrane changes continuously along the inner surface of the porous membrane, and the concave and convex portions are defined along the inner surface of the porous membrane with the side surface of the protruding structure as a reference. Wherein, a portion of the porous membrane is in contact with a portion of the dielectric layer, the remaining portion of the porous membrane is in contact with a portion of the air gap, and the interface between the porous membrane and the dielectric layer is smoothly connected to the interface between the porous membrane and the air gap.

2. The semiconductor device according to claim 1, wherein, The angle formed by the plane parallel to the side surface of the protruding structure and the inner surface of the porous membrane is 90° or less.

3. The semiconductor device according to claim 1, wherein, The porous membrane is also located on the upper surface of the bottom substrate.

4. The semiconductor device according to claim 1, wherein, The bottom substrate and the protruding structure are implemented as a single structure.

5. The semiconductor device according to claim 1, wherein, The bottom substrate and the protruding structure comprise different materials.

6. The semiconductor device according to claim 5, wherein, The protruding structure includes a conductive layer.

7. The semiconductor device according to claim 6, wherein, The first height from the bottom substrate to the air gap is greater than the second height from the bottom substrate to the conductive layer.

8. The semiconductor device according to claim 1, wherein, The air gap surrounds a portion of the upper surface of the bottom substrate and is defined by the outer surface of the dielectric layer, the upper surface of the bottom substrate, and the inner surface of the porous membrane.

9. The semiconductor device according to claim 1, wherein: The dielectric layer is also disposed between the air gap and the bottom substrate, and The air gap is defined by the outer surface of the dielectric layer and the inner surface of the porous membrane.

10. The semiconductor device according to claim 1, wherein, The dielectric layer is silicon oxide or silicon nitride.

11. A semiconductor device, comprising: Bottom substrate; The protruding structure on the bottom substrate; A porous membrane extending along the side surface of the protruding structure; The air gap between the side surface of the protruding structure and the inner surface of the porous membrane; as well as A dielectric layer exists between the side surface of the protruding structure and the inner surface of the air gap, wherein: The upper surface of the bottom substrate includes a first point spaced apart from the side surface of the protruding structure by a first distance, and a second point spaced apart from the side surface of the protruding structure by a second distance greater than the first distance. The height of the air gap at the first point is greater than the height of the air gap at the second point. With the side surface of the protruding structure as a reference, the inner surface of the porous membrane includes concave and convex portions, and A portion of the porous membrane is in contact with a portion of the dielectric layer, the remainder of the porous membrane is in contact with a portion of the air gap, and the interface between the porous membrane and the dielectric layer is smoothly connected to the interface between the porous membrane and the air gap.

12. The semiconductor device according to claim 11, wherein: The air gap is defined at least partially by the inner surface of the porous membrane, and The angle formed between a plane parallel to the side surface of the protruding structure and the inner surface of the porous membrane changes continuously along the inner surface of the porous membrane.

13. The semiconductor device according to claim 11, wherein, The porous membrane is permeable to oxygen, carbon dioxide and water, and prevents silicon oxide and silicon nitride from passing through it.

14. The semiconductor device according to claim 11, wherein, The porous membrane comprises silicon oxide or silicon nitride deposited by an atomic layer deposition process at a temperature above room temperature and below 400°C.

15. The semiconductor device of claim 11, further comprising: An outer insulating layer that surrounds a portion of the porous membrane.

16. A semiconductor device, comprising: Bottom substrate; The protruding structure on the bottom substrate; A porous membrane extending along the side surface of the protruding structure; An air gap exists between the side surface of the protruding structure and the porous membrane, the air gap including a first portion having a width that decreases progressively with distance from the upper surface of the bottom substrate; as well as The dielectric layer between the side surface of the protruding structure and the inner surface of the air gap. The angle between the plane formed parallel to the side surface of the protruding structure and the outer surface of the first portion of the air gap varies continuously along the outer surface of the first portion of the air gap, and a concave portion and a convex portion are defined along the outer surface of the first portion of the air gap with the side surface of the protruding structure as a reference. Wherein, a portion of the porous membrane is in contact with a portion of the dielectric layer, the remaining portion of the porous membrane is in contact with a portion of the air gap, and the interface between the porous membrane and the dielectric layer is smoothly connected to the interface between the porous membrane and the air gap.

17. The semiconductor device according to claim 16, wherein, The air gap includes a second portion having a constant width as it extends away from the upper surface of the bottom substrate.

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