Semiconductor device and method of manufacturing the same

Abstract

The present application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate; a first epitaxial layer located on the substrate; a second epitaxial layer located on the first epitaxial layer; a high-voltage device located in the first epitaxial layer and the second epitaxial layer; a low-voltage device located in the second epitaxial layer; and a first isolation region located in the first epitaxial layer and the second epitaxial layer, the first isolation region being used to isolate the high-voltage device and the low-voltage device. By fabricating the low-voltage device in the second epitaxial layer in the present application, the size of the low-voltage device is significantly reduced, thereby significantly reducing the overall area of the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The manufacturing cost of an integrated circuit chip is usually determined by the chip area and the number of lithography layers for tape-out. The smaller the chip area and the fewer the lithography layers, the lower the cost and the lower the selling price. Different ways can be adopted to reduce the chip manufacturing cost, such as reducing the area and the number of lithography layers simultaneously, or significantly reducing the area and limitedly increasing the number of lithography layers, or significantly reducing the number of lithography layers and limitedly increasing the area.

[0003] In the prior art, for the way of reducing the chip area, it can only be achieved by adjusting the process and reducing the design rules. For low-voltage digital circuits, this method is very effective. However, for high-voltage analog circuits, especially for high-voltage bipolar analog circuits, this method has already encountered a bottleneck, because in the bipolar process, only sufficient process dimensions can achieve sufficient high voltage, and the design rules cannot be infinitely reduced. Therefore, in the case where the standard design rules cannot be reduced, only the devices in the chip can be distinguished between high voltage and low voltage, using the standard design rules for high-voltage devices and the reduced design rules for low-voltage devices. In the existing process, only when the design rules are greater than the critical value, the device breakdown voltage can be kept stable and the product parameters can be kept consistent. If the design rules are less than the critical value, it means a very large voltage fluctuation, and the breakdown voltage variation between the products manufactured in the same batch will be very large. Taking the 60V (40V - 100V) bipolar process as an example, in order to obtain a device that only needs to operate at 5V, the design rules will be reduced on the basis of the 60V device, so as to obtain a device with a typical value of 20 to 30V, which can ensure that the lowest voltage reaches above 5V when the voltage fluctuates, meeting the application of 5V. The idea of this method is to manufacture low-voltage devices with smaller design rules in the same high-voltage epitaxial layer as high-voltage devices, and only about 5% to 15% of the chip area can be reduced, and the degree of chip area reduction is relatively small. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor device and a manufacturing method thereof for the above problems existing in the prior art. By manufacturing low-voltage devices in the second epitaxial layer, the size of the low-voltage devices is significantly reduced, thereby significantly reducing the overall area of the chip.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, comprising: a substrate; a first epitaxial layer located on the substrate; a second epitaxial layer located on the first epitaxial layer; a high-voltage device located in the first epitaxial layer and the second epitaxial layer; a low-voltage device located in the second epitaxial layer; and a first isolation region located in the first epitaxial layer and the second epitaxial layer, the first isolation region being configured to isolate the high-voltage device and the low-voltage device.

[0006] Preferably, the low-voltage device comprises: a well region located in the second epitaxial layer, wherein the doping concentration of the well region is greater than that of the second epitaxial layer.

[0007] Preferably, the low-voltage device further comprises: a second base region located in the well region; and a second emitter region located in the second base region.

[0008] Preferably, the low-voltage device further comprises: a second buried layer located between the first epitaxial layer and the second epitaxial layer; and a second contact region located in the well region and connected to the second buried layer.

[0009] Preferably, the first isolation region comprises: an upper isolation region in which the low-voltage device is located; and a lower isolation region located below the upper isolation region and connected to the upper isolation region and the substrate respectively.

[0010] Preferably, it further comprises a second isolation region located in the upper isolation region and surrounding the low-voltage device.

[0011] Preferably, the high-voltage device comprises: a first base region located in the first epitaxial layer and the second epitaxial layer; and a first emitter region located in the first base region.

[0012] Preferably, the high-voltage device further comprises: a first buried layer located between the first epitaxial layer and the substrate; and a first contact region located in the first epitaxial layer and the second epitaxial layer and connected to the first buried layer.

[0013] Preferably, the first contact region comprises: a shallow contact region located in the second epitaxial layer; and a deep contact region located in the first epitaxial layer and the second epitaxial layer and connected to the first buried layer and the shallow contact region respectively.

[0014] Preferably, it further comprises: an isolation layer located on the second epitaxial layer and having a plurality of contact holes; and a plurality of leads located on the isolation layer and connected to the shallow contact region, the first base region, the first emitter region, the second contact region, the second base region, and the second emitter region respectively through the contact holes.

[0015] Preferably, the isolation layer includes: a first oxide layer located on the second epitaxial layer; a planarization layer located on the first oxide layer; a second oxide layer located on the planarization layer; and a third oxide layer located on the second oxide layer.

[0016] Preferably, each of the leads includes: a first metal layer located on the second oxide layer, with one end extending laterally along the surface of the second oxide layer and the other end sequentially passing through the planarization layer and the first oxide layer; and a second metal layer located on the third oxide layer, with one end extending laterally along the surface of the third oxide layer and the other end extending into the third oxide layer to contact the first metal layer.

[0017] Preferably, a passivation layer is further included, located on the isolation layer and covering the plurality of leads, wherein the passivation layer has a plurality of openings for exposing at least a part of the leads.

[0018] Preferably, the substrate, the first isolation region, the first base region, and the second base region are of a first doping type, and the first epitaxial layer, the second epitaxial layer, the well region, the first emitter region, the second emitter region, the first buried layer, the second buried layer, the first contact region, and the second contact region are of a second doping type.

[0019] Preferably, the first doping type is selected from one of P-type doping or N-type doping, and the second doping type is selected from the other of P-type doping or N-type doping.

[0020] Preferably, the thickness of the first epitaxial layer is greater than the thickness of the second epitaxial layer.

[0021] Preferably, the resistivity of the first epitaxial layer is the same as that of the second epitaxial layer.

[0022] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, including: forming a first epitaxial layer on a substrate; forming a second epitaxial layer on the first epitaxial layer; forming high-voltage devices in the first epitaxial layer and the second epitaxial layer; forming low-voltage devices in the second epitaxial layer; and forming a first isolation region in the first epitaxial layer and the second epitaxial layer, where the first isolation region is used to isolate the high-voltage devices and the low-voltage devices.

[0023] Preferably, the step of forming the low-voltage devices includes: forming a well region in the second epitaxial layer; increasing the doping concentration of the well region so that the doping concentration of the well region is greater than that of the second epitaxial layer; and diffusing the well region into the first epitaxial layer.

[0024] Preferably, the step of forming the first isolation region includes: forming an upper isolation region in the first epitaxial layer, wherein, in the step of forming the second epitaxial layer, the upper isolation region diffuses in the first epitaxial layer and the second epitaxial layer respectively.

[0025] Preferably, the step of forming the low-voltage device further includes: forming a second buried layer in the upper isolation region, wherein, in the step of forming the second epitaxial layer, the second buried layer diffuses into the second epitaxial layer and the first epitaxial layer respectively, and the diffusion of the second buried layer and the upper isolation region is carried out synchronously in the annealing process of the well region.

[0026] Preferably, the step of forming the high-voltage device includes: forming a first buried layer between the substrate and the first epitaxial layer; and forming a deep contact region in the first epitaxial layer and the second epitaxial layer, the deep contact region being connected to the first buried layer, wherein the diffusion of the well region, the second buried layer and the upper isolation region is carried out synchronously in the annealing process of the deep contact region, and the well region and the second buried layer are connected in the annealing process of the deep contact region.

[0027] Preferably, the step of forming the low-voltage device further includes: forming a second base region in the well region; and forming a second emitter region in the second base region.

[0028] Preferably, the step of forming the low-voltage device further includes: forming a second contact region in the well region, the second contact region being connected to the second buried layer.

[0029] Preferably, the step of forming the first isolation region further includes: forming a lower isolation region in the substrate, wherein the diffusion of the lower isolation region is carried out in the annealing processes of forming the first epitaxial layer, forming the second buried layer, forming the well region and forming the deep contact region respectively, and the upper isolation layer and the lower isolation layer are connected in the annealing process of the deep contact region.

[0030] Preferably, it further includes forming a second isolation region in the upper isolation region, the second isolation region surrounding the low-voltage device.

[0031] Preferably, the step of forming the high-voltage device further includes: forming a first base region in the first epitaxial layer and the second epitaxial layer; and forming a first emitter region in the first base region; forming a shallow contact region in the second epitaxial layer; and the deep contact region is connected to the shallow contact region to form a first contact region.

[0032] Preferably, the second isolation region is formed simultaneously with the first base region.

[0033] Preferably, the second contact region, the first emitter region, and the shallow contact region are formed simultaneously.

[0034] Preferably, it further includes: forming an isolation layer on the second epitaxial layer, the isolation layer having a plurality of contact holes; and forming a plurality of leads on the isolation layer, the plurality of leads being respectively connected to the shallow contact region, the first base region, the first emitter region, the second contact region, the second base region, and the second emitter region through the contact holes.

[0035] Preferably, the step of forming the isolation layer includes: forming a first oxide layer on the second epitaxial layer; forming a planarization layer on the first oxide layer; forming a second oxide layer on the planarization layer; and forming a third oxide layer on the second oxide layer.

[0036] Preferably, the step of forming each lead includes: forming a first metal layer on the second oxide layer, one end extending laterally along the surface of the second oxide layer, and the other end sequentially passing through the planarization layer and the first oxide layer; and forming a second metal layer on the third oxide layer, one end extending laterally along the surface of the third oxide layer, and the other end extending into the third oxide layer to contact the first metal layer.

[0037] Preferably, it further includes forming a passivation layer on the isolation layer, the isolation layer covering the plurality of leads, wherein the passivation layer has a plurality of openings for exposing at least a part of the leads.

[0038] Preferably, the thickness of the first epitaxial layer is greater than the thickness of the second epitaxial layer.

[0039] Preferably, the resistivity of the first epitaxial layer is the same as that of the second epitaxial layer.

[0040] Preferably, the substrate, the first isolation region, the first base region, and the second base region are of a first doping type, and the first epitaxial layer, the second epitaxial layer, the well region, the first emitter region, the second emitter region, the first buried layer, the second buried layer, the first contact region, and the second contact region are of a second doping type.

[0041] Preferably, the first doping type is selected from one of P-type doping or N-type doping, and the second doping type is selected from the other of P-type doping or N-type doping.

[0042] A semiconductor device and a manufacturing method thereof according to an embodiment of the present invention form a first epitaxial layer and a second epitaxial layer on a substrate in sequence, fabricate high-voltage devices in the first epitaxial layer and the second epitaxial layer respectively, fabricate low-voltage devices in the second epitaxial layer, and isolate the low-voltage devices from the high-voltage devices by surrounding the low-voltage devices with a first isolation region. By using a reduced design rule for the low-voltage devices, the size of the low-voltage devices is significantly reduced, thereby significantly reducing the overall area of the chip and achieving the purpose of cost reduction. Compared with the prior art, the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention replace the structure in which the low-voltage devices and the high-voltage devices are fabricated in the same epitaxial layer in the prior art with a structure in which the low-voltage devices are fabricated in the second epitaxial layer. Through a high-voltage process, the low-voltage devices are fabricated in the low-voltage epitaxial layer, thereby significantly reducing the area of the low-voltage devices and further significantly reducing the area of the overall chip.

[0043] Furthermore, when forming the low-voltage devices, the second epitaxial layer is locally doped. By locally increasing the doping concentration in the well region of the second epitaxial layer, the planar lateral distance between the structures in the low-voltage devices is reduced, and at the same time, the lateral diffusion is reduced. In addition, since the second epitaxial layer is located above the first epitaxial layer, the doping depth is reduced, thereby significantly reducing the size of the low-voltage devices. In some preferred embodiments, by fabricating well regions with the same doping type in the second epitaxial layer, the concentration of part of the second epitaxial layer is increased, and by reducing the thickness of the second epitaxial layer, the lateral design rule used for the low-voltage devices is further reduced, thereby reducing the area of the chip.

[0044] In addition, since the first isolation region is divided into an upper isolation region and a lower isolation region, in the first epitaxial layer and the second epitaxial layer, the upper isolation region and the lower isolation region are diffused to be connected respectively. Since the larger the lateral diffusion range of the doping region, the smaller the effective distance between the doping region and other adjacent structures, thereby reducing the breakdown voltage performance of the device. Therefore, in this embodiment, secondary diffusion, that is, the upper isolation region and the lower isolation region are diffused to be connected respectively, is adopted to reduce the lateral diffusion length, which is beneficial to reducing the chip area and the manufacturing cost. Similarly, the well region and the buried layer are diffused to be connected respectively, reducing the lateral diffusion length.

[0045] The manufacturing method of the semiconductor device of the present invention can be used to manufacture an integrated circuit chip operating at 40 - 100V. In the existing manufacturing method, 13 photolithography layers are required. Among them, 70% of the chip area is for 1 - 5V devices (i.e., low - voltage devices). In the manufacturing method of the present invention, the area of the high - voltage devices of the chip has been reduced by using the method of reducing the design rules in the high - voltage epitaxial layer (the first epitaxial layer and the second epitaxial layer). On this basis, for the low - voltage devices of the chip, the design rules are reduced in the low - voltage epitaxy (the second epitaxial layer) to reduce the area. The overall chip area is reduced by 56%. At the same time, the number of photolithography layers increases to 17 layers, an increase of 31% compared to the original 13 layers, but the overall chip cost is reduced by 25%, and the effect is remarkable. The significant reduction in the chip area of the present invention makes the obvious cost reduction sufficient to offset the cost increase of adding photolithography layers, and the overall cost is significantly reduced. Description of the Drawings

[0046] By describing the embodiments of the present disclosure with reference to the following drawings, the above - mentioned and other objects, features, and advantages of the present disclosure will become clearer.

[0047] Figure 1 The structural schematic diagram of the semiconductor device according to the embodiment of the present disclosure is shown.

[0048] Figures 2 to 17 The cross - sectional views at various stages of the manufacturing method of the semiconductor device according to the embodiment of the present invention are shown. Detailed Embodiments

[0049] The present disclosure will be described in more detail below with reference to the drawings. In each drawing, the same elements are denoted by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well - known parts may not be shown.

[0050] Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques, and technologies of the device, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details.

[0051] The present invention can be presented in various forms, and some examples will be described below.

[0052] Figure 1 The structural schematic diagram of the semiconductor device according to the embodiment of the present disclosure is shown.

[0053] As Figure 1As shown, the semiconductor device of an embodiment of the present disclosure includes: a substrate 100, a first epitaxial layer 211, a second epitaxial layer 212, a first isolation region 310, a second isolation region 320, a high-voltage device 410, a low-voltage device 420, an isolation layer 510, a plurality of leads 520, and a passivation layer 530. The first isolation region 310 includes: a lower isolation region 311 and an upper isolation region 312. The high-voltage device 410 includes: a first buried layer 411, a first base region 412, a first emitter region 413, and a first contact region (including a deep contact region 414 and a shallow contact region 415). The low-voltage device 420 includes: a second buried layer 421, a well region 422, a second base region 423, a second emitter region 424, and a second contact region 425. The isolation layer 510 includes: a first oxide layer 511, a planarization layer 512, a second oxide layer 513, and a fourth oxide layer 514. Each lead 520 includes a first metal layer 521 and a second metal layer 522. Among them, the substrate 100, the first isolation region 310, the second isolation region 320, the first base region 412, and the second base region 423 are of a first doping type. The first epitaxial layer 211, the second epitaxial layer 212, the first buried layer 411, the first emitter region 413, the deep contact region 414, the shallow contact region 415, the second buried layer 421, the well region 422, the second emitter region 424, and the second contact region 425 are of a second doping type. In this embodiment, the first doping type is selected from P-type doping, and the second doping type is selected from N-type doping. However, the embodiments of the present invention are not limited thereto, and those skilled in the art can make other settings for the doping type according to needs. For example, the first doping type is selected from N-type doping, and the second doping type is selected from P-type doping.

[0054] In this embodiment, the first epitaxial layer 211 is located on the substrate 100. The second epitaxial layer 212 is located on the first epitaxial layer 211. The high-voltage device 410 is located in the first epitaxial layer 211 and the second epitaxial layer 212. The low-voltage device 420 is located in the second epitaxial layer 212. Among them, since the low-voltage device 420 is only provided in the second epitaxial layer 212, and the high-voltage device 410 is in both the first epitaxial layer 211 and the second epitaxial layer 212, and due to the voltage limitation of the low-voltage device 420, the realization of the high breakdown voltage of the entire device needs to rely on the first epitaxial layer 211 to bear, so the thickness of the first epitaxial layer 211 needs to be greater than the thickness of the second epitaxial layer 212. In this embodiment, the resistivity of the first epitaxial layer 211 and the second epitaxial layer 212 is the same.

[0055] The first isolation region 310 is located in the first epitaxial layer 211 and the second epitaxial layer 212. At least a part of the first isolation region 310 surrounds the low-voltage device 420 and is used to isolate the low-voltage device 410 from the high-voltage device 420. The second isolation region 320 is located in the upper isolation region 312 and surrounds the low-voltage device 420. The isolation layer 510 is located on the second epitaxial layer 212 and has a plurality of contact holes. A plurality of leads 520 are located on the isolation layer 510 and are respectively connected to the shallow contact region 415, the first base region 412, the first emitter region 413, the second contact region 425, the second base region 423, and the second emitter region 424 through the contact holes. The passivation layer 530 is located on the isolation layer 510 to cover the plurality of leads 520. The passivation layer 530 has a plurality of openings 531 for exposing at least a part of the leads. In the first isolation region 310, the upper isolation region 312 surrounds the low-voltage device 420. The lower isolation region 311 is located below the upper isolation region 312 and is respectively connected to the upper isolation region 312 and the substrate 100.

[0056] In the high-voltage device 410, the first buried layer 411 is located between the first epitaxial layer 211 and the substrate 100. The first base region 412 is located in the first epitaxial layer 211 and the second epitaxial layer 212. The first emitter region 413 is located in the first base region 412. The shallow contact region 415 is located in the second epitaxial layer 212. The deep contact region 414 is located in the first epitaxial layer 211 and the second epitaxial layer 212 and is respectively connected to the first buried layer 411 and the shallow contact region 415.

[0057] In the low-voltage device 420, the second buried layer 421 is located between the first epitaxial layer 211 and the second epitaxial layer 212. The well region 422 is located in the second epitaxial layer 212. The second base region 423 is located in the well region 422. The second emitter region 424 is located in the second base region 423. The second contact region 425 is located in the well region 422 and is connected to the second buried layer 421.

[0058] In order to form the second contact region 425 of the low-voltage device by using the shallow contact region 415 of the high-voltage device 410, and the junction depth of the shallow contact region 415 is less than half of the deep contact region 414. In order for the second contact region 425 to communicate with the second buried layer 421, when setting the parameters of the epitaxial layer, the thickness of the second epitaxial layer 212 needs to be less than that of the first epitaxial layer 211.

[0059] Also, since the well region 422 increases the concentration of the local second epitaxial layer 212, the electrical parameters can be stabilized and made consistent under a smaller lateral design rule (lateral pitch). There is no need to greatly expand the lateral design rule to meet the minimum requirements of the electrical parameters, thus reducing the area of the low-voltage device 420 and the entire chip.

[0060] The following will be combined with Figures 2 to 17 For Figure 1The manufacturing method of the semiconductor device will be described in detail.

[0061] This manufacturing method starts with a substrate 100, and a first buried layer 411 is formed on the substrate 100, as Figure 2 shown.

[0062] In this step, a first sacrificial layer 101 is formed on the substrate 100. An etching window 1011 of the first buried layer is formed on the first sacrificial layer 101 by using photolithography and etching processes. The substrate 100 is ion-doped through the etching window 1011, and then the first buried layer 411 is formed through annealing and oxidation processes. Among them, the substrate 100 is a P-type doped crystalline silicon layer, the doping type of the first buried layer 411 is N-type doping, and the doping impurities include one of arsenic element, phosphorus element, and antimony element. The material of the first sacrificial layer 101 includes silicon dioxide.

[0063] Furthermore, a lower isolation region 311 is formed in the substrate 100, as Figure 3 shown.

[0064] In this step, the first sacrificial layer 101 formed on the surface of the substrate 100 in the previous step is removed, and a second sacrificial layer 102 is formed on the surface of the substrate 100. A mask is formed on the second sacrificial layer 102 by using photolithography. The substrate 100 is ion-doped through the mask, and then the lower isolation region 311 is formed through an annealing process. Among them, the doping type of the lower isolation region 311 is P-type doping, and the doping impurities include boron element or boron-containing compounds. The material of the second sacrificial layer 102 includes silicon dioxide.

[0065] In some other embodiments, the first sacrificial layer 101 may not be removed. An etching window of the lower isolation region is formed on the first sacrificial layer 101 by using photolithography and etching processes. The substrate 100 is ion-doped through the etching window, and then the lower isolation region 311 is formed through annealing and oxidation processes.

[0066] Furthermore, a first epitaxial layer 211 is formed on the substrate 100, as Figure 4 shown.

[0067] In this step, the second sacrificial layer 102 formed on the surface of the substrate 100 in the previous step is removed. A first epitaxial layer 211 suitable for high-voltage devices is formed on the substrate 100 by using a deposition process. During this process, the first buried layer 411 and the lower isolation region 311 respectively diffuse upward into the first epitaxial layer 211. Among them, the resistivity of the first epitaxial layer 211 is relatively large, and the doping type is N-type doping.

[0068] Furthermore, an upper isolation region 312 is formed in the first epitaxial layer 211, as Figure 5 shown.

[0069] In this step, a third sacrificial layer 103 is formed on the first epitaxial layer 211. An etching window 1031 for the upper isolation region is formed on the third sacrificial layer 103 by using photolithography and etching processes. The first epitaxial layer 211 is ion-doped through the etching window 1031, and then the upper isolation region 312 is formed through annealing and oxidation processes. Among them, the doping type of the upper isolation region 312 is P-type doping, and the doping impurities include elemental boron or boron-containing compounds. The material of the third sacrificial layer 103 includes silicon dioxide.

[0070] Further, a second buried layer 421 is formed in the upper isolation region 312, as Figure 6 shown.

[0071] In this step, the third sacrificial layer 103 formed on the surface of the first epitaxial layer 211 in the previous step is removed, and a fourth sacrificial layer 104 is formed on the first epitaxial layer 211. An etching window 1041 for the second buried layer is formed on the fourth sacrificial layer 104 by using photolithography and etching processes. The first epitaxial layer 211 is ion-doped through the etching window 1041, and then the second buried layer 421 is formed through annealing and oxidation processes. Among them, the doping type of the second buried layer 421 is N-type doping, and the doping impurities include one of arsenic element, phosphorus element, and antimony element. The material of the fourth sacrificial layer 104 includes silicon dioxide.

[0072] Further, a second epitaxial layer 212 is formed on the first epitaxial layer 211, as Figure 7 shown.

[0073] In this step, the fourth sacrificial layer 104 formed on the surface of the first epitaxial layer 211 in the previous step is removed. The second epitaxial layer 212 is formed on the first epitaxial layer 211 by using a deposition process. During this process, the lower isolation region 311 and the upper isolation region 312 are partially diffused in the first epitaxial layer 211 and the second epitaxial layer 212 respectively, and the second buried layer 421 diffuses upward into the second epitaxial layer 212 and downward into the first epitaxial layer 211. Among them, the resistivity of the second epitaxial layer 212 is equal to that of the first epitaxial layer 212, and the doping type of the second epitaxial layer 212 is N-type doping.

[0074] In this embodiment, the thickness of the first epitaxial layer 211 is greater than that of the second epitaxial layer 212. This is because low-voltage devices will be formed in the second epitaxial layer 212 and high-voltage devices will be formed in the first epitaxial layer 211 and the second epitaxial layer 212 in the following steps. After reducing the size of the low-voltage devices, the breakdown voltage of the low-voltage devices is limited. The realization of high breakdown voltage of the entire device (including low-voltage devices and high-voltage devices) needs to rely on the first epitaxial layer 211 to bear. Therefore, when setting the parameters of the epitaxial layer, the thickness of the first epitaxial layer 211 needs to be greater than that of the second epitaxial layer 212.

[0075] Further, a well region 422 is formed in the second epitaxial layer 212, as Figure 8 shown.

[0076] In this step, a fifth sacrificial layer 105 is formed on the second epitaxial layer 212. A mask is formed on the fifth sacrificial layer 105 by using a photolithography process. The second epitaxial layer 212 is ion-doped through the mask, and then the well region 422 is formed through annealing and oxidation processes.

[0077] In this embodiment, it is necessary to additionally increase the doping concentration of the well region 422 so that the doping concentration of the well region 422 is greater than that of the second epitaxial layer 212. Among them, the doping type of the well region 422 is N-type doping, the doping impurities include phosphorus elements, and the material of the fifth sacrificial layer 105 includes silicon dioxide. During the annealing process, the lower isolation region 311 and the upper isolation region 312 are further diffused in the first epitaxial layer 211 and the second epitaxial layer 212 respectively.

[0078] In this embodiment, since the well region 422 increases the concentration of the local second epitaxial layer 212, the electrical parameters can be stabilized and made consistent under a smaller lateral design rule. There is no need to greatly expand the lateral design rule to meet the minimum requirements of the electrical parameters, thereby reducing the area of the low-voltage device 420 and the entire chip.

[0079] Further, a deep contact region 414 is formed in the first epitaxial layer 211 and the second epitaxial layer 212, as Figure 9 shown.

[0080] In this step, an etching window 1051 for the deep contact region is formed on the fifth sacrificial layer 105 by using photolithography and etching processes. The first epitaxial layer 211 and the second epitaxial layer 212 are ion-doped through the etching window 1051, and then the deep contact region 414 is formed through annealing and oxidation processes. Among them, the doping type of the deep contact region 414 is N-type doping. During the annealing process, the lower isolation region 311 and the upper isolation region 312 are completely diffused in the first epitaxial layer 211 and the second epitaxial layer 212 respectively until they are connected up and down. The upper isolation region 312 penetrates through the second epitaxial layer 212 and extends to the surface of the lower isolation region 311. The well region 422 diffuses in the second epitaxial layer 212 and is connected to the second buried layer 421.

[0081] Since the larger the lateral diffusion range of the doping region, the smaller the effective spacing between this doping region and other adjacent structures, which reduces the breakdown voltage performance of the device. Therefore, in this embodiment, secondary diffusion is used to reduce the lateral diffusion length, that is, to avoid too large a lateral diffusion range, which is beneficial to reducing the chip area. And because the chip area is small, the manufacturing cost is reduced.

[0082] In a specific embodiment, it can be simply considered that the lateral diffusion length is the same as the vertical diffusion depth. For example, if the diffusion penetrates 10 microns of epitaxial thickness from the surface downwards, then the lateral diffusion length is also 10 microns. If an epitaxial layer is split into two epitaxial layers with a thickness of 5 microns each, and the upper and lower isolation regions 321 and 311 diffuse upwards and downwards simultaneously from the interface of the two epitaxial layers, then the lateral diffusion length only needs to be 5 microns, so the lateral diffusion is 5 microns less than that of the single-layer 10-micron epitaxy mentioned above. Of course, according to the above settings, the thickness of the first epitaxial layer should be greater than that of the second epitaxial layer.

[0083] Further, a first base region 412 is formed in the first epitaxial layer 211 and the second epitaxial layer 212, and a second isolation region 320 is formed in the upper isolation region 312, as Figure 10 shown.

[0084] In this step, the fifth sacrificial layer 105 formed on the surface of the second epitaxial layer 212 is removed, and a first oxide layer 511 is formed on the surface of the second epitaxial layer 212. A mask is formed on the first oxide layer 511 by photolithography, and the second epitaxial layer 212 is ion-doped through the mask, and then the first base region 412 and the second isolation region 320 are formed through annealing and oxidation processes. Among them, the doping types of the first base region 412 and the second isolation region 320 are both P-type doping, and the doping impurities both include: elemental boron or boron-containing compounds, and the doping concentration of the second isolation region 320 is greater than that of the upper isolation region 312. During the annealing process, the lower isolation region 311 and the upper isolation region 312 are more thoroughly connected in the first epitaxial layer 211 and the second epitaxial layer 212.

[0085] Further, a first emitter region 413 is formed in the first base region 412, a shallow contact region 415 is formed in the second epitaxial layer 212, and a second contact region 425 is formed in the well region 422, as Figure 11 shown.

[0086] In this step, an etching window 505 for the shallow contact region, an etching window 506 for the second contact region, and an etching window 507 for the first emitter region 413 are formed on the first oxide layer 511 by photolithography and etching processes. The second epitaxial layer 212, the well region 422, and the first base region 412 are ion-doped through the etching windows 505, 506, and 507 respectively, and then the shallow contact region 415 connected to the deep contact region 424, the second contact region 425 connected to the second buried layer 421, and the first emitter region 413 are formed through annealing and oxidation processes. Among them, the doping types of the second contact region 425, the shallow contact region 415, and the first emitter region 413 are N-type doping, and the doping impurities include phosphorus element, and the material of the first oxide layer 511 includes silicon oxide.

[0087] Further, a second base region 423 is formed in the well region 422, as Figure 12 shown.

[0088] In this step, an etching window 508 for the second base region is formed on the first oxide layer 511 by using photolithography and etching processes. The well region 422 is ion-doped through the etching window 508, and then the second base region 423 is formed through annealing and oxidation processes. Among them, the doping type of the second base region 423 is P-type doping, and the doping impurities all include boron element or boron-containing compounds.

[0089] Further, a second emitter region 424 is formed in the second base region 423, as Figure 13 shown.

[0090] In this step, a mask is formed on the first oxide layer 511 by using photolithography. The second base region 423 is ion-doped through the mask, and then the second emitter region 424 is formed through annealing and oxidation processes. Among them, the doping type of the second emitter region 424 is N-type doping, and the doping impurities include arsenic element or phosphorus element. After the ion doping is completed, the photolithography mask is removed by using an ashing process.

[0091] Further, a planarization layer 512 and a second oxide layer 513 are sequentially formed on the first oxide layer 511, as Figure 14 shown.

[0092] In this step, the planarization layer 512 is formed on the first oxide layer 511 by using a reflow process. Since the surface of the first oxide layer 511 is uneven, the planarization layer 512 can improve the flatness of the device. Then, the second oxide layer 513 is formed on the planarization layer 512 by using a deposition process. Among them, the material of the planarization layer 512 includes borophosphosilicate glass (BPSG), and the material of the second oxide layer 513 includes silicon dioxide.

[0093] Further, a first metal layer 521 is formed on the second oxide layer 513, as Figure 15 shown.

[0094] In this step, a plurality of contact holes penetrating through the first oxide layer 511, the planarization layer 512, and the first oxide layer 511 are formed by using photolithography and etching processes. Metal is deposited on the second oxide layer 513, and a patterned first metal layer 521 is formed by using photolithography and etching processes. Part of the first metal layer 521 fills in the plurality of contact holes. The formed first metal layer 521 is located on the second oxide layer 513, with one end extending laterally along the surface of the second oxide layer 513; the other end sequentially passes through the planarization layer 512 and the first oxide layer 511 and is connected to the shallow contact region 415, the first base region 412, the first emitter region 413, the second contact region 425, the second base region 423, and the second emitter region 424 respectively.

[0095] Further, a third oxide layer 514 is formed on the second oxide layer 513 by covering the first metal layer 521, and a second metal layer 522 is formed on the third oxide layer 514, as Figure 16 shown.

[0096] In this step, the third oxide layer 514 is formed on the second oxide layer 513 by using a deposition process, and a plurality of contact holes are formed in the third oxide layer 514 by using photolithography and etching processes. Metal is deposited on the third oxide layer 514, and a patterned second metal layer 522 is formed by using photolithography and etching processes. Part of the second metal layer 522 fills in the plurality of contact holes. The formed second metal layer 522 is located on the third oxide layer 514, one end extends laterally along the surface of the third oxide layer 514; the other end extends into the third oxide layer 514 to contact the first metal layer 521, so as to further connect to the shallow contact region 415, the first base region 412, the first emitter region 413, the second contact region 425, the second base region 423, and the second emitter region 424, so as to realize the electrical lead-out of the low-voltage device and the high-voltage device.

[0097] Further, a passivation layer 530 is formed on the third oxide layer 514 by covering the second metal layer 522, as Figure 17 shown.

[0098] In this step, the passivation layer 530 is formed on the third oxide layer 514 by using a deposition process, and then a plurality of openings 531 for exposing at least part of the leads are formed on the passivation layer 530 by using photolithography and etching processes. The plurality of openings 531 are windows for connecting the chip to the outside through package leads, so as to form a semiconductor device as Figure 1 shown.

[0099] In some specific embodiments, the manufacturing method of the semiconductor device of the present invention can be used to manufacture an integrated circuit chip operating at 40 - 100V. In the existing manufacturing method, the number of photolithography layers required is 13. Among them, 70% of the chip area is for 1 - 5V devices (i.e., low-voltage devices). In the manufacturing method of the present invention, the high-voltage devices of the chip have reduced the area by using the method of reducing the design rule in the high-voltage epitaxial layer (the first epitaxial layer and the second epitaxial layer). On this basis, the design rule of the low-voltage devices of the chip is reduced in the low-voltage epitaxy (the second epitaxial layer) to reduce the area. The overall chip area is reduced by 56%, and at the same time, the number of photolithography layers is increased to 17 layers, an increase of 31% compared with the original 13 layers, but the overall chip cost is reduced by 25%, and the effect is remarkable. The significant reduction in the chip area of the present invention results in an obvious decrease in cost, which is sufficient to offset the increase in cost caused by the increased photolithography layers, and the overall cost is significantly reduced.

[0100] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.

[0101] As described above with reference to the embodiments of the present invention, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications based on the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate; A first epitaxial layer located on the substrate; A second epitaxial layer located on the first epitaxial layer; A high-voltage device located in the first epitaxial layer and the second epitaxial layer; A low-voltage device located in the second epitaxial layer; And A first isolation region located in the first epitaxial layer and the second epitaxial layer, the first isolation region being used to isolate the high-voltage device and the low-voltage device, wherein the low-voltage device includes a second buried layer, The first isolation region includes: an upper isolation region, the low-voltage device being located in the upper isolation region; and a lower isolation region, located below the upper isolation region and connected to the upper isolation region and the substrate respectively.

2. The semiconductor device according to claim 1, characterized in that, The low-voltage device further includes: A well region located in the second epitaxial layer, wherein the doping concentration of the well region is greater than that of the second epitaxial layer.

3. The semiconductor device according to claim 2, wherein, The low-voltage device further includes: A second base region located in the well region; and A second emitter region located in the second base region.

4. The semiconductor device according to claim 3, characterized in that, The low-voltage device further includes: a second contact region located in the well region and connected to the second buried layer, wherein the second buried layer is located between the first epitaxial layer and the second epitaxial layer.

5. The semiconductor device according to claim 4, characterized in that, It further includes a second isolation region located in the upper isolation region and surrounding the low-voltage device.

6. The semiconductor device according to claim 5, characterized in that, The high-voltage device includes: A first base region located in the first epitaxial layer and the second epitaxial layer; and A first emitter region located in the first base region.

7. The semiconductor device according to claim 6, characterized in that, The high-voltage device further includes: A first buried layer located between the first epitaxial layer and the substrate; and A first contact region located in the first epitaxial layer and the second epitaxial layer and connected to the first buried layer.

8. The semiconductor device according to claim 7, characterized in that, The first contact region includes: A shallow contact region located in the second epitaxial layer; and A deep contact region located in the first epitaxial layer and the second epitaxial layer and connected to the first buried layer and the shallow contact region respectively.

9. The semiconductor device according to claim 8, characterized in that, It further includes: An isolation layer located on the second epitaxial layer and having a plurality of contact holes; And A plurality of leads located on the isolation layer and connected to the shallow contact region, the first base region, the first emitter region, the second contact region, the second base region and the second emitter region respectively through the contact holes.

10. The semiconductor device according to claim 9, wherein, The isolation layer includes: A first oxide layer located on the second epitaxial layer; A planarization layer located on the first oxide layer; A second oxide layer located on the planarization layer; and A third oxide layer located on the second oxide layer.

11. The semiconductor device according to claim 10, wherein, Each of the leads includes: A first metal layer located on the second oxide layer, one end extending horizontally along the surface of the second oxide layer, and the other end passing through the planarization layer and the first oxide layer in sequence; and A second metal layer located on the third oxide layer, one end extending horizontally along the surface of the third oxide layer, and the other end extending into the third oxide layer to contact the first metal layer.

12. The semiconductor device according to claim 9, wherein, It further includes a passivation layer located on the isolation layer and covering the plurality of leads, wherein the passivation layer has a plurality of openings for exposing at least part of the leads.

13. The semiconductor device according to claim 8, wherein, The substrate, the first isolation region, the first base region and the second base region are of a first doping type, The first epitaxial layer, the second epitaxial layer, the well region, the first emitter region, the second emitter region, the first buried layer, the second buried layer, the first contact region, and the second contact region are of a second doping type.

14. The semiconductor device according to claim 13, wherein, The first doping type is selected from one of P-type doping or N-type doping, and the second doping type is selected from the other of P-type doping or N-type doping.

15. The semiconductor device according to any one of claims 1-14, wherein, The thickness of the first epitaxial layer is greater than the thickness of the second epitaxial layer.

16. The semiconductor device according to any one of claims 1-14, wherein, The resistivity of the first epitaxial layer is the same as that of the second epitaxial layer.

17. A method for manufacturing a semiconductor device, wherein, Comprising: Forming a first epitaxial layer on a substrate; Forming a second epitaxial layer on the first epitaxial layer; Forming high-voltage devices in the first epitaxial layer and the second epitaxial layer; Forming low-voltage devices in the second epitaxial layer; and Forming a first isolation region in the first epitaxial layer and the second epitaxial layer, the first isolation region being used to isolate the high-voltage devices and the low-voltage devices, wherein the first isolation region includes an upper isolation region and a lower isolation region formed step by step, the lower isolation region is located below the upper isolation region, and the upper isolation region and the lower isolation region are brought into contact through diffusion to form the first isolation region, and the lower isolation region is connected to the substrate, the low-voltage devices are located in the upper isolation region, and the steps of forming the low-voltage devices include: forming a second buried layer in the upper isolation region.

18. The manufacturing method according to claim 17, wherein, The steps of forming the low-voltage devices include: Forming a well region in the second epitaxial layer; Increasing the doping concentration of the well region so that the doping concentration of the well region is greater than that of the second epitaxial layer; and Diffusing the well region into the first epitaxial layer.

19. The manufacturing method according to claim 18, wherein, The steps of forming the first isolation region include: forming an upper isolation region in the first epitaxial layer, wherein, in the step of forming the second epitaxial layer, the upper isolation region diffuses in the first epitaxial layer and the second epitaxial layer respectively.

20. The manufacturing method according to claim 19, wherein, In the step of forming the second epitaxial layer, the second buried layer diffuses into the second epitaxial layer and the first epitaxial layer respectively, wherein the diffusion of the second buried layer and the upper isolation region is carried out synchronously in the annealing process of the well region.

21. The manufacturing method according to claim 20, wherein, The steps of forming the high-voltage devices include: Forming a first buried layer between the substrate and the first epitaxial layer; and Forming a deep contact region in the first epitaxial layer and the second epitaxial layer, the deep contact region being connected to the first buried layer, wherein the diffusion of the well region, the second buried layer, and the upper isolation region is carried out synchronously in the annealing process of the deep contact region, and the well region and the second buried layer are connected in the annealing process of the deep contact region.

22. The manufacturing method according to claim 21, wherein, The steps of forming the low-voltage devices further include: Forming a second base region in the well region; and Forming a second emitter region in the second base region.

23. The manufacturing method according to claim 22, wherein, The steps of forming the low-voltage devices further include: Forming a second contact region in the well region, the second contact region being connected to the second buried layer.

24. The manufacturing method according to claim 23, wherein, The steps of forming the first isolation region further include: forming a lower isolation region in the substrate, Among them, the lower isolation region diffusion is carried out respectively in the annealing process of forming the first epitaxial layer, forming the second buried layer, forming the well region, and forming the deep contact region, and the upper isolation layer and the lower isolation layer are connected in the annealing process of the deep contact region.

25. The manufacturing method according to claim 24, wherein, It further includes forming a second isolation region in the upper isolation region, and the second isolation region surrounds the low-voltage device.

26. The manufacturing method according to claim 25, wherein, The step of forming the high-voltage device further includes: forming a first base region in the first epitaxial layer and the second epitaxial layer; and forming a first emitter region in the first base region; forming a shallow contact region in the second epitaxial layer; and the deep contact region is connected to the shallow contact region to form a first contact region.

27. The manufacturing method according to claim 26, wherein, The second isolation region is formed simultaneously with the first base region.

28. The manufacturing method according to claim 26, wherein, The second contact region, the first emitter region, and the shallow contact region are formed simultaneously.

29. The manufacturing method according to claim 26, wherein, It further includes: forming an isolation layer on the second epitaxial layer, and the isolation layer has a plurality of contact holes; and forming a plurality of leads on the isolation layer, and the plurality of leads are respectively connected to the shallow contact region, the first base region, the first emitter region, the second contact region, the second base region, and the second emitter region through the contact holes.

30. The manufacturing method according to claim 29, wherein, The step of forming the isolation layer includes: forming a first oxide layer on the second epitaxial layer; forming a planarization layer on the first oxide layer; forming a second oxide layer on the planarization layer; and forming a third oxide layer on the second oxide layer.

31. The manufacturing method according to claim 30, wherein, The step of forming each lead includes: forming a first metal layer on the second oxide layer, one end extending laterally along the surface of the second oxide layer, and the other end sequentially passing through the planarization layer and the first oxide layer; and forming a second metal layer on the third oxide layer, one end extending laterally along the surface of the third oxide layer, and the other end extending into the third oxide layer to contact the first metal layer.

32. The manufacturing method according to claim 29, wherein, It further includes forming a passivation layer on the isolation layer, and the isolation layer covers the plurality of leads, wherein the passivation layer has a plurality of openings for exposing at least part of the leads.

33. The manufacturing method according to any one of claims 17 - 32, wherein, The thickness of the first epitaxial layer is greater than the thickness of the second epitaxial layer.

34. The manufacturing method according to any one of claims 17 - 32, wherein, The resistivity of the first epitaxial layer is the same as that of the second epitaxial layer.

35. The manufacturing method according to claim 29, wherein, The substrate, the first isolation region, the first base region, and the second base region are of the first doping type, The first epitaxial layer, the second epitaxial layer, the well region, the first emitter region, the second emitter region, the first buried layer, the second buried layer, the first contact region, and the second contact region are of the second doping type.

36. The manufacturing method according to claim 35, wherein, The first doping type is selected from one of P-type doping or N-type doping, and the second doping type is selected from the other of P-type doping or N-type doping.

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