A low residual voltage and low capacitance unidirectional ESD protection device and its manufacturing method

Abstract

The invention discloses a low residual voltage and low capacitance unidirectional ESD protection device, comprising an N-type single crystal, wherein three isolation dielectric layers are arranged on the top surface of the N-type single crystal, a front metal area is arranged between two adjacent isolation dielectric layers, a P-type diffusion area is arranged on one side of the top of the N-type single crystal, and a connected N-type contact area and a P-type contact area are arranged on the other side, an N-type adjustment area is arranged at the bottom of the P-type diffusion area, and a connected N-type contact area and a P-type contact area are arranged at the top. The invention can obtain a lower residual voltage parameter under the condition that the chip area and the chip processing procedure remain unchanged; the N-type adjustment area 105 is adjusted from the chip surface position to the bottom of the P-type diffusion area 102 by high-energy injection, so that the residual voltage parameter can be reduced by a certain proportion; compared with a conventional structure, under the condition that the chip area is constant, the residual voltage parameter of the invention can be reduced by 10-30%.

Description

Technical Field

[0001] The present invention relates to the field of electronic science and technology, and in particular to a low residual voltage and low capacitance unidirectional ESD protection device and a manufacturing method thereof. Background Art

[0002] High-speed signal lines, such as USB (Universal Serial Bus) and HDMI (High Definition Multimedia Interface), are often impacted by ESD. Low-capacitance ESD protection devices are needed. Generally, in order to ensure that signal transmission is not affected, the total capacitance of the ESD protection device needs to be less than 1pF. For USB3.0, USB3.1 and HDMI2.0 applications, the capacitance of the ESD protection device is required to be no higher than 0.5pF. Compared with the influence of capacitance parameters, the residual voltage (clamping voltage) of the ESD protection device directly determines the quality of the protection effect. With the continuous updating of the protected chip solutions, especially the emergence of USB and TYPE-C interface solutions, a residual voltage difference of 2V is equivalent to a difference of 1 grade, and a residual voltage difference of 5V is equivalent to a difference of 1 generation. Therefore, under the condition that the capacitance parameters meet customer needs, the residual voltage index becomes the determining factor of the performance of the ESD protection device. The lower the residual voltage, the wider the application scenarios of the ESD protection device and the greater the competitive advantage.

[0003] From the perspective of design structure, ESD protection devices mainly include diode structure, triode structure, thyristor structure, etc. The diode structure mainly uses the clamping protection function of the reverse breakdown voltage of the diode to discharge ESD. Its advantages are simple process and low cost. The disadvantage is that the reverse breakdown voltage of the diode gradually increases with the increase of the discharge current, which makes the discharge current value it bears low and the residual voltage parameter high. In addition, the breakdown of the diode is avalanche breakdown, and the concentration on both sides of the PN junction is high, so the capacitance value is large, usually above 100pF. The triode structure mainly uses the voltage BVCEO between the collector and emitter of the triode to discharge the ESD current. Its advantage is that the BVCEO value is low, and it can discharge a higher ESD current compared to the diode structure. Since BVCEO has the characteristics of light retracement, it has a relatively low residual voltage parameter. The disadvantage is that its capacitance value is still large, usually above 5pF. The thyristor structure mainly uses the low on-state voltage drop (usually around 1.0-1.5V) of the thyristor to discharge the ESD current. Its advantage is that due to the reduced on-state voltage, a higher ESD current can be discharged. The capacitance of the thyristor structure is also relatively low, which can be less than 1pF. Since the thyristor structure has the characteristics of deep retracement, it has a lower residual voltage parameter.

[0004] Taking the conventional low residual voltage and low capacitance unidirectional ESD protection device as an example, its structure is as followsFigure 3 As shown, it includes: N-type single crystal material 101, P-type diffusion region 102, N-type contact region 103, P-type contact region 104, N-type adjustment region 105, isolation dielectric layer 106, front metal region 107, and front metal region 108. This structure belongs to the thyristor structure, and its IV characteristic diagram is shown in Figure 2 As shown, when the front metal region 108 is applied with a high potential and the front metal region 107 is applied with a negative potential, the ESD protection device avalanche breakdown, showing the deep retrace characteristics of the thyristor. When the front metal region 108 is applied with a low potential and the front metal region 107 is applied with a high potential, the ESD protection device is forward-conducted, showing the typical characteristics of the PN junction forward conduction. In order to obtain a capacitance lower than 1pF, the resistivity of the N-type single crystal material 101 is usually relatively high (generally 10-50Ω.cm). In order to obtain low-voltage ESD protection, the high-concentration N-type adjustment region 105 and the P-type diffusion region 102 form an avalanche breakdown to obtain the low voltage required by the product (generally 5-24V). After the thyristor structure is turned on, the main flow paths of its current are: P-type contact region 104, N-type single crystal material 101, P-type diffusion region 102, and N-type contact region 103. The main factors affecting the residual voltage parameters are as follows Figure 3 The L size indicated by the N-type single crystal material 101 is relatively smaller, and the residual voltage is lower. At present, the residual voltage of thyristor structure ESD protection device products is generally around 8-10V. This is relatively high for high-speed data signal transmission. Summary of the invention

[0005] The object of the present invention is to provide a low residual voltage and low capacitance unidirectional ESD protection device and a manufacturing method thereof.

[0006] The technical solution adopted by the present invention is:

[0007] A low residual voltage and low capacitance unidirectional ESD protection device, characterized in that it includes an N-type single crystal, three isolation dielectric layers are arranged on the top surface of the N-type single crystal, a front metal area is arranged between two adjacent isolation dielectric layers, a P-type diffusion area is arranged on one side of the top of the N-type single crystal, and a connected N-type contact area and P-type contact area are arranged on the other side, the bottom of the P-type diffusion area is an N-type adjustment area, and a connected N-type contact area and P-type contact area are arranged on the top, and the N-type contact area and P-type contact area on the top of the P-type diffusion area and the N-type contact area and P-type contact area on the other side of the top of the N-type single crystal are respectively arranged below the two front metal areas on the top surface of the N-type single crystal.

[0008] A method for manufacturing a low residual voltage and low capacitance unidirectional ESD protection device, characterized in that it comprises the following steps:

[0009] Step 1: Prepare N-type single crystal material, the crystal orientation of the N-type single crystal material is <111> , the resistivity is 10-50Ω.cm;

[0010] Step 2: Grow a sacrificial oxide layer with a thickness of 680-1000Å, form an N-type adjustment area pattern on the front side by photolithography, and implant phosphorus on the front side with a dose of 5E15-1E16cm -2 , energy is 200-500KeV, phosphorus is driven, the temperature of phosphorus driving is 1150-1200℃, the time is 240-420min, and an N-type adjustment area is formed;

[0011] Step 3: Photolithography on the front side to form the P-type diffusion region pattern, and boron implantation on the front side with a dose of 5E13-1E14cm -2 , energy is 80-120KeV, boron is driven, temperature is 1050-1150℃, time is 60-240min, forming a P-type diffusion region;

[0012] Step 4: Photolithography on the front side to form the N-type contact area pattern, and phosphorus implantation on the front side with a dose of 1E15-5E15cm -2 , energy is 40-80KeV, phosphorus is driven, temperature is 950-1000℃, time is 30-90min, and N-type contact area is formed;

[0013] Step 5: Photolithography on the front side to form the P-type contact area pattern, and boron implantation on the front side with a dose of 1E15-5E15cm -2 , energy is 40-80KeV, boron is driven, temperature is 850-950℃, time is 30-90min, forming a P-type contact area;

[0014] Step 6: Deposit an isolation dielectric layer on the front side, which is tetraethoxysilane TEOS with a thickness of 5000-10000Å, and form a contact hole area by photolithography on the front side. After photolithography of the contact hole, deposit a layer of TI / TIN;

[0015] Step 7: Sputter or evaporate metal on the front side, the metal is aluminum or aluminum copper or aluminum silicon copper, the thickness is 2-4um, and the front side metal is photolithographically formed into a metal area, an alloy, the alloy temperature is 360-430℃, and the time is 25-45min.

[0016] The advantages of the present invention are as follows: a lower residual pressure parameter can be obtained under the condition that the chip area and chip processing procedures remain unchanged; the N-type adjustment area 105 is adjusted from the chip surface position to the bottom of the P-type diffusion area 102 by high-energy injection, so that the residual pressure parameter can be reduced by a certain proportion; compared with conventional structures, under the condition that the chip area is constant, the residual pressure parameter of the present invention can be reduced by 10-30%. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0018] Figure 1It is a cross-sectional structural diagram of the present invention;

[0019] Figure 2 It is a schematic diagram of IV characteristics of the present invention;

[0020] Figure 3 Schematic diagram of the cross-section structure of a conventional low residual voltage and low capacitance unidirectional ESD protection device.

[0021] Figure 4 It is a structural diagram of the N-type single crystal material of the present invention;

[0022] Figure 5 It is a schematic diagram of step 2 of the present invention;

[0023] Figure 6 Schematic diagram of step 3 of the present invention

[0024] Figure 7 Schematic diagram of step 4 of the present invention

[0025] Figure 8 is a schematic diagram of step 5 of the present invention;

[0026] Fig. 9 is a schematic diagram of step 6 of the present invention;

[0027] Fig.10 This is a schematic diagram of step 7 of the present invention.

[0028] Among them: 1. N-type single crystal; 2. P-type diffusion area; 3. N-type contact area; 4. P-type contact area; 5. N-type adjustment area; 6. Isolation dielectric layer; 7. Front metal area. DETAILED DESCRIPTION

[0029] Example 1

[0030] like Figure 1-10 As shown, a low residual voltage and low capacitance unidirectional ESD protection device includes an N-type single crystal 1, three isolation dielectric layers 6 are arranged on the top surface of the N-type single crystal 1, a front metal area 7 is arranged between two adjacent isolation dielectric layers 6, and a P-type diffusion area 2 is arranged on one side of the top of the N-type single crystal 1, and a connected N-type contact area 3 and P-type contact area 4 are arranged on the other side. The bottom of the P-type diffusion area 2 is an N-type adjustment area 5, and a connected N-type contact area 3 and P-type contact area 4 are arranged on the top. The N-type contact area 3 and P-type contact area 4 on the top of the P-type diffusion area 2 and the N-type contact area 3 and P-type contact area 4 on the other side of the top of the N-type single crystal 1 are respectively arranged under the two front metal areas 7 on the top surface of the N-type single crystal 1.

[0031] In this device, when a high potential is applied to the left front metal area and a negative potential is applied to the right front metal area, the ESD protection device avalanche breakdown presents the deep flyback characteristics of the thyristor; when a low potential is applied to the right front metal area and a high potential is applied to the left front metal area, the ESD protection device is forward-conducted, presenting the typical characteristics of a PN junction forward conduction.

[0032] The present invention adjusts the N-type adjustment area from the chip surface position to the bottom of the P-type diffusion area by high-energy injection, so the main factor affecting the residual voltage parameter, that is, the L size indicated by the N-type single crystal material can be reduced by a certain proportion. The smaller the L size, the smaller the on-resistance of the N-type single crystal material itself within the L size range, so the residual voltage parameter will also be reduced by the same proportion.

[0033] A method for manufacturing a low residual voltage and low capacitance unidirectional ESD protection device comprises the following steps:

[0034] Step 1: Prepare N-type single crystal material, the crystal orientation of the N-type single crystal material is <111> , the resistivity is 10Ω.cm;

[0035] Step 2: Grow a sacrificial oxide layer with a thickness of 680Å, form an N-type adjustment region pattern on the front side by photolithography, and implant phosphorus on the front side with a dose of 5E15cm -2 , energy is 200KeV, phosphorus is driven, the temperature of phosphorus driving is 1150℃, the time is 240min, and an N-type adjustment area is formed;

[0036] Step 3: Photolithography on the front side to form the P-type diffusion region pattern, and boron implantation on the front side with a dose of 5E13cm -2 , energy is 80KeV, boron is driven, temperature is 1050℃, time is 60min, and a P-type diffusion region is formed;

[0037] Step 4: Photolithography on the front side to form the N-type contact area pattern, and phosphorus implantation on the front side with a dose of 1E15cm -2 , energy of 40KeV, phosphorus push, temperature of 950℃, time of 30min, forming an N-type contact area;

[0038] Step 5: Photolithography on the front side to form the P-type contact area pattern, and boron implantation on the front side with a dose of 1E15cm -2 , energy of 40KeV, boron driving, temperature of 850℃, time of 30min, forming a P-type contact area;

[0039] Step 6: Deposit an isolation dielectric layer on the front side, which is tetraethoxysilane TEOS with a thickness of 5000Å. Photolithography is performed on the front side to form a contact hole area. After photolithography of the contact hole, a layer of TI / TIN is deposited, which can effectively reduce the failure rate of metal overheating while reducing the contact resistance.

[0040] Step 7: sputter or evaporate metal on the front side, the metal is aluminum or aluminum copper or aluminum silicon copper, the thickness is 2um, and the front side metal is photolithographically formed into a metal area, an alloy, the alloy temperature is 360°C, and the time is 25 minutes.

[0041] The present invention can obtain a lower residual pressure parameter under the condition that the chip area and chip processing procedures remain unchanged; the N-type adjustment area 105 is adjusted from the chip surface position to the bottom of the P-type diffusion area 102 by high-energy injection, so that the residual pressure parameter can be reduced by a certain proportion; compared with the conventional structure, under the condition that the chip area is constant, the residual pressure parameter of the present invention can be reduced by 10-30%.

[0042] Example 2

[0043] like Figure 1-10 As shown, a low residual voltage and low capacitance unidirectional ESD protection device includes an N-type single crystal 1, three isolation dielectric layers 6 are arranged on the top surface of the N-type single crystal 1, a front metal area 7 is arranged between two adjacent isolation dielectric layers 6, and a P-type diffusion area 2 is arranged on one side of the top in the N-type single crystal 1, and a connected N-type contact area 3 and P-type contact area 4 are arranged on the other side. The bottom of the P-type diffusion area 2 is an N-type adjustment area 5, and a connected N-type contact area 3 and P-type contact area 4 are arranged on the top. The N-type contact area 3 and P-type contact area 4 on the top of the P-type diffusion area 2 and the N-type contact area 3 and P-type contact area 4 on the other side of the top in the N-type single crystal 1 are respectively arranged under the two front metal areas 7 on the top surface of the N-type single crystal 1.

[0044] In this device, when a high potential is applied to the left front metal area and a negative potential is applied to the right front metal area, the ESD protection device avalanche breakdown presents the deep flyback characteristics of the thyristor; when a low potential is applied to the right front metal area and a high potential is applied to the left front metal area, the ESD protection device is forward-conducted, presenting the typical characteristics of a PN junction forward conduction.

[0045] The present invention adjusts the N-type adjustment area from the chip surface position to the bottom of the P-type diffusion area by high-energy injection, so the main factor affecting the residual voltage parameter, that is, the L size indicated by the N-type single crystal material can be reduced by a certain proportion. The smaller the L size, the smaller the on-resistance of the N-type single crystal material itself within the L size range, so the residual voltage parameter will also be reduced by the same proportion.

[0046] A method for manufacturing a low residual voltage and low capacitance unidirectional ESD protection device comprises the following steps:

[0047] Step 1: Prepare N-type single crystal material, the crystal orientation of the N-type single crystal material is <111> , the resistivity is 50Ω.cm;

[0048] Step 2: Grow a sacrificial oxide layer with a thickness of 1000Å, form an N-type adjustment region pattern on the front side by photolithography, and implant phosphorus on the front side with a dose of 1E16cm-2 , energy is 500KeV, phosphorus is driven, the temperature of phosphorus driving is 1200℃, the time is 420min, and an N-type adjustment area is formed;

[0049] Step 3: Photolithography on the front side to form the P-type diffusion region pattern, and boron implantation on the front side with a dose of 1E14cm -2 , energy is 120KeV, boron is driven, temperature is 1150℃, time is 240min, and a P-type diffusion region is formed;

[0050] Step 4: Photolithography on the front side to form the N-type contact area pattern, and phosphorus implantation on the front side with a dose of 5E15cm -2 , energy of 80KeV, phosphorus push, temperature of 1000℃, time of 90min, forming an N-type contact area;

[0051] Step 5: Photolithography on the front side to form the P-type contact area pattern, and boron implantation on the front side with a dose of 5E15cm -2 , energy of 80KeV, boron driving, temperature of 950℃, time of 90min, forming a P-type contact area;

[0052] Step 6: Deposit an isolation dielectric layer on the front side, which is tetraethoxysilane TEOS with a thickness of 10,000Å. Photolithography is performed on the front side to form a contact hole area. After photolithography of the contact hole, a layer of TI / TIN is deposited, which can effectively reduce the failure rate of metal overheating while reducing the contact resistance.

[0053] Step 7: sputter or evaporate metal on the front side, the metal is aluminum or aluminum copper or aluminum silicon copper, the thickness is 4um, and the front side metal is photolithographically formed into a metal area, an alloy, the alloy temperature is 430°C, and the time is 45 minutes.

[0054] The present invention can obtain a lower residual pressure parameter under the condition that the chip area and chip processing procedures remain unchanged; the N-type adjustment area 105 is adjusted from the chip surface position to the bottom of the P-type diffusion area 102 by high-energy injection, so that the residual pressure parameter can be reduced by a certain proportion; compared with the conventional structure, under the condition that the chip area is constant, the residual pressure parameter of the present invention can be reduced by 10-30%.

[0055] Example 3

[0056] like Figure 1-10As shown, a low residual voltage and low capacitance unidirectional ESD protection device includes an N-type single crystal 1, three isolation dielectric layers 6 are arranged on the top surface of the N-type single crystal 1, a front metal area 7 is arranged between two adjacent isolation dielectric layers 6, and a P-type diffusion area 2 is arranged on one side of the top in the N-type single crystal 1, and a connected N-type contact area 3 and P-type contact area 4 are arranged on the other side. The bottom of the P-type diffusion area 2 is an N-type adjustment area 5, and a connected N-type contact area 3 and P-type contact area 4 are arranged on the top. The N-type contact area 3 and P-type contact area 4 on the top of the P-type diffusion area 2 and the N-type contact area 3 and P-type contact area 4 on the other side of the top in the N-type single crystal 1 are respectively arranged under the two front metal areas 7 on the top surface of the N-type single crystal 1.

[0057] In this device, when a high potential is applied to the left front metal area and a negative potential is applied to the right front metal area, the ESD protection device avalanche breakdown presents the deep flyback characteristics of the thyristor; when a low potential is applied to the right front metal area and a high potential is applied to the left front metal area, the ESD protection device is forward-conducted, presenting the typical characteristics of a PN junction forward conduction.

[0058] The present invention adjusts the N-type adjustment area from the chip surface position to the bottom of the P-type diffusion area by high-energy injection, so the main factor affecting the residual voltage parameter, that is, the L size indicated by the N-type single crystal material can be reduced by a certain proportion. The smaller the L size, the smaller the on-resistance of the N-type single crystal material itself within the L size range, so the residual voltage parameter will also be reduced by the same proportion.

[0059] A method for manufacturing a low residual voltage and low capacitance unidirectional ESD protection device comprises the following steps:

[0060] Step 1: Prepare N-type single crystal material, the crystal orientation of the N-type single crystal material is <111> , the resistivity is 30Ω.cm;

[0061] Step 2: Grow a sacrificial oxide layer with a thickness of 840Å, form an N-type adjustment region pattern on the front side by photolithography, and implant phosphorus on the front side with a dose of 5E15cm -2 , energy is 350KeV, phosphorus is driven, the temperature of phosphorus driving is 1170℃, the time is 330min, and an N-type adjustment area is formed;

[0062] Step 3: Photolithography on the front side to form the P-type diffusion region pattern, and boron implantation on the front side with a dose of 5E13cm -2 , energy is 100KeV, boron is driven, temperature is 1100℃, time is 150min, and a P-type diffusion region is formed;

[0063] Step 4: Photolithography on the front side to form the N-type contact area pattern, and phosphorus implantation on the front side with a dose of 1E15cm -2 , energy of 60KeV, phosphorus push, temperature of 975℃, time of 60min, forming an N-type contact area;

[0064] Step 5: Photolithography on the front side to form the P-type contact area pattern, and boron implantation on the front side with a dose of 1E15cm -2 , energy of 60KeV, boron driving, temperature of 900℃, time of 60min, forming a P-type contact area;

[0065] Step 6: Deposit an isolation dielectric layer on the front side, which is tetraethoxysilane TEOS with a thickness of 7500Å. Photolithography is performed on the front side to form a contact hole area. After photolithography of the contact hole, a layer of TI / TIN is deposited, which can effectively reduce the failure rate of metal overheating while reducing the contact resistance.

[0066] Step 7: sputter or evaporate metal on the front side, the metal is aluminum or aluminum copper or aluminum silicon copper, the thickness is 3um, and the front metal is photolithography to form a metal area, alloy, the alloy temperature is 395℃, and the time is 35min.

[0067] The present invention can obtain a lower residual pressure parameter under the condition that the chip area and chip processing procedures remain unchanged; the N-type adjustment area 105 is adjusted from the chip surface position to the bottom of the P-type diffusion area 102 by high-energy injection, so that the residual pressure parameter can be reduced by a certain proportion; compared with the conventional structure, under the condition that the chip area is constant, the residual pressure parameter of the present invention can be reduced by 10-30%.

Claims

1. A method for manufacturing a low residual voltage and low capacitance unidirectional ESD protection device, characterized in that: The device comprises an N-type single crystal, three isolation dielectric layers are arranged on the top surface of the N-type single crystal, a front metal area is arranged between two adjacent isolation dielectric layers, a P-type diffusion area is arranged on one side of the top of the N-type single crystal, and a connected N-type contact area and a P-type contact area are arranged on the other side, the bottom of the P-type diffusion area is an N-type adjustment area, and a connected N-type contact area and a P-type contact area are arranged on the top, the N-type contact area and the P-type contact area on the top of the P-type diffusion area and the N-type contact area and the P-type contact area on the other side of the top of the N-type single crystal are respectively arranged below the two front metal areas on the top surface of the N-type single crystal, and the device manufacturing method comprises the following steps: Step 1: Prepare N-type single crystal material, the crystal orientation of the N-type single crystal material is <111> , resistivity is 10-50Ω .cm; Step 2: Grow a sacrificial oxide layer with a thickness of 680-1000Å, form an N-type adjustment area pattern by front lithography, and implant phosphorus on the front with a dose of 5E15-1E16cm-2, an energy of 200-500KeV, and phosphorus push-in at a temperature of 1150-1200℃ for 240-420min to form an N-type adjustment area; Step 3: Photolithography on the front side forms a P-type diffusion region pattern, and boron is implanted on the front side with a dose of 5E13-1E14cm-2, an energy of 80-120KeV, boron push-in, a temperature of 1050-1150℃, and a time of 60-240min to form a P-type diffusion region; Step 4: Photolithography on the front side forms an N-type contact area pattern, and phosphorus is implanted on the front side with a dose of 1E15-5E15cm-2, an energy of 40-80KeV, phosphorus advancement, a temperature of 950-1000℃, and a time of 30-90min to form an N-type contact area; Step 5: Photolithography on the front side forms a P-type contact area pattern, and boron is implanted on the front side with a dose of 1E15-5E15cm-2, an energy of 40-80KeV, boron push-in, a temperature of 850-950℃, and a time of 30-90min to form a P-type contact area; Step 6: Deposit an isolation dielectric layer on the front side, which is tetraethoxysilane TEOS with a thickness of 5000-10000Å, and form a contact hole area by photolithography on the front side. After photolithography of the contact hole, deposit a layer of TI / TIN; Step 7: Sputter or evaporate metal on the front side, the metal is aluminum or aluminum copper or aluminum silicon copper, the thickness is 2-4um, and the front side metal is photolithographically formed into a metal area, an alloy, the alloy temperature is 360-430℃, and the time is 25-45min.

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