Semiconductor device and power supply control method thereof

Abstract

Embodiments of the present disclosure relate to semiconductor devices and power control methods thereof. A semiconductor device includes a semiconductor chip, the semiconductor chip including: a first non-volatile memory including a first memory block and a second memory block; a CPU controlling the first non-volatile memory; a first switch electrically connected to the first memory block and controlling the supply of a first power supply voltage to the first memory block; a second switch electrically connected to the second memory block and controlling the supply of the first power supply voltage to the second memory block; and a second non-volatile memory electrically connected to each of the first switch and the second switch and storing flag information for controlling the first switch and the second switch, wherein the control of each of the first switch and the second switch is performed based on the flag information, the flag information indicating whether program data executed by the CPU is written in the first memory block and the second memory block.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2018-242324 filed on December 26, 2018, including its specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The invention relates to a semiconductor device and a power supply control method thereof. Background Art

[0004] There are semiconductor devices having a semiconductor chip including a built-in microcomputer (microcontroller, microprocessor), and the semiconductor devices are incorporated into automobiles, industrial equipment, home appliances, electronic equipment, and the like.

[0005] Recent microcomputers generally include a flash memory module including a flash memory, which is a nonvolatile memory, and a control circuit for controlling writing and erasing of the flash memory. The microcomputer operates and controls according to the contents of a program written in the flash memory.

[0006] Japanese Unexamined Patent Application Publication No. 2009-258925 (hereinafter referred to as Patent Document 1) discloses a memory management technology for a computer system. In addition, Japanese Unexamined Patent Application Publication No. 2008-47155 (hereinafter referred to as Patent Document 2) discloses a bulk erasable nonvolatile memory technology that can also be used to store data that is frequently rewritten. Summary of the invention

[0007] The semiconductor device has a semiconductor chip and a plurality of external terminals electrically connected to the semiconductor chip. The plurality of external terminals include a terminal to which a power supply voltage for operating the semiconductor device is supplied.

[0008] The power supply voltage supplied from the external power supply via the external terminal is supplied to the microcomputer incorporated in the semiconductor chip, and thereby supplied to the CPU, ROM and flash memory module in the microcomputer. As a result, the power supply voltage is also supplied to the flash memory incorporated in the flash memory module, so that the flash memory can operate.

[0009] As described above, the supply of power supply voltage to the flash memory module included in the microcomputer is usually the same as the power supply used to supply the power supply voltage to the entire semiconductor chip. Therefore, even if there is a control circuit built into the flash memory module, or there is an unused area in which program data of the flash memory is not stored, it is difficult to stop the supply of power supply voltage to the control circuit or the unused area.

[0010] As a result, the power supply voltage is continuously supplied to the control circuit built into the flash memory module and the unused area of ​​the flash memory, which causes the problem of unnecessary increase in current consumption. In addition, since the wiring in the semiconductor chip is standardized, the problem of increased leakage current cannot be ignored.

[0011] In recent years, final systems in which semiconductor devices are installed have become more complex, and semiconductor device manufacturers are very inclined to adopt product configurations in which the capacity of flash memory is increased to cope with the complex final systems. Therefore, when the capacity of program data to be written to the flash memory by the user is small, the unused area in the flash memory becomes larger, making the above-mentioned problem more obvious.

[0012] An object of the present invention is to reduce power consumption of a semiconductor device.

[0013] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0014] Patent Documents 1 and 2 describe a memory management technology and a bulk erase type nonvolatile memory technology, but neither describe nor raise the problem that consumption current or leakage current occurs when an unused area of ​​a flash memory mounted on a microcomputer exists.

[0015] According to one embodiment, a semiconductor device includes a semiconductor chip, which includes: a first nonvolatile memory having a first memory block and a second memory block; a CPU that controls the first nonvolatile memory; a first switch that is electrically connected to the first memory block and controls the supply of a first power supply voltage to the first memory block; a second switch that is electrically connected to the second memory block and controls the supply of the first power supply voltage to the second memory block; and a second nonvolatile memory that is electrically connected to each of the first switch and the second switch and stores flag information for controlling the first switch and the second switch, wherein control of each of the first switch and the second switch is performed based on the flag information, which indicates whether program data to be executed by the CPU is written in the first memory block and the second memory block.

[0016] In addition, according to one embodiment, a semiconductor device includes a semiconductor chip, the semiconductor chip including: a first nonvolatile memory having a first memory block and a second memory block on the A side, and a third memory block and a fourth memory block on the B side; a CPU electrically connected to the first memory block; a first switch electrically connected to the first memory block, and controlling the supply of a first power supply voltage to the first memory block; a second switch electrically connected to the second memory block, and controlling the supply of the first power supply voltage to the second memory block; a third switch electrically connected to the third memory block, and controlling the supply of the first power supply voltage to the third memory block; a fourth switch electrically connected to the fourth memory block, and controlling supply of a first power supply voltage to a fourth memory block; a second nonvolatile memory electrically connected to each of the first switch, the second switch, the third switch, and the fourth switch, and flag information for controlling the first switch, the second switch, the third switch, and the fourth switch is stored in the second nonvolatile memory; and a plurality of discrimination circuits, which discriminate between the A side and the B side and are electrically connected to each of the first switch, the second switch, the third switch, and the fourth switch, wherein the discrimination circuit discriminates whether program data to be executed by the CPU is written to the A side and the B side based on the flag information, and control of the first switch, the second switch, the third switch, and the fourth switch is performed based on the discrimination result of the discrimination circuit.

[0017] According to one embodiment, a power control method for a semiconductor device includes the following steps: (a) reading a boot program stored in a ROM by a CPU; (b) after step (a), reading flag information from a second non-volatile memory by the CPU, the flag information being used to control a first switch and a second switch, the first switch being electrically connected to a first memory block of the first non-volatile memory, and the second switch being electrically connected to a second memory block of the first non-volatile memory; and (c) after step (b), controlling the first switch and the second switch based on the flag information, whereby the CPU controls the supply of a first power supply voltage to the first memory block and the supply of the first power supply voltage to the second memory block, wherein the flag information is information indicating whether program data to be executed by the CPU has been written to the first memory block and the second memory block. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a plan view showing the configuration of a semiconductor device according to one embodiment.

[0019] Figure 2 is a side view showing the configuration of a semiconductor device according to one embodiment.

[0020] Figure 3 is a circuit block diagram of a plurality of circuits formed in a semiconductor chip according to one embodiment.

[0021] Figure 4 It is a circuit block diagram studied by the inventor.

[0022] Figure 5 is a first hard macro configuration diagram of a memory block of a flash memory according to one embodiment.

[0023] Figure 6 is a second hard macro configuration diagram of a memory block of a flash memory according to one embodiment.

[0024] Figure 7 is an operational timing diagram of a normal operating mode according to one embodiment.

[0025] Figure 8 is an operational timing diagram of a flash memory rewrite operation mode according to one embodiment.

[0026] Fig. 9 is an operation timing diagram of the control circuit and the CPU in the normal operation mode according to one embodiment.

[0027] Fig.10 is an operation timing chart of the control circuit and the CPU when flag information is erased in the flash memory rewrite operation mode according to one embodiment.

[0028] Fig.11 is an operation timing chart of the control circuit and the CPU when flag information is written in the flash memory rewrite operation mode according to one embodiment.

[0029] Fig.12 is a circuit diagram for preventing a read error of a memory block in which supply of a first power supply voltage is stopped according to an embodiment.

[0030] Fig.13 is a circuit block diagram of a plurality of circuits formed in a semiconductor chip when a first flash memory is in a dual bank mode according to an embodiment. Specific embodiments

[0031] Hereinafter, embodiments of the present invention are described in detail with reference to the accompanying drawings. Note that throughout the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated descriptions thereof are omitted.

[0032] <Overview of semiconductor device configuration>

[0033] Figure 1 is a plan view showing the configuration of the semiconductor device PKG according to the present embodiment. Figure 2 is a side view showing the configuration of the semiconductor device PKG related to the present embodiment. Figure 1 and Figure 2 The semiconductor device PKG shown in FIG. 1 is exemplified here by a QFP (Quad Flat Package).

[0034] exist Figure 1 In the present invention, CHP represents a semiconductor chip. The semiconductor chip CHP is manufactured by forming various circuit blocks on a semiconductor wafer (semiconductor substrate) using a wafer processing manufacturing technology and cutting the semiconductor wafer into chips.

[0035] The semiconductor chip CHP is mounted on the upper surface of the metal chip mounting part CHPM, and the lower surface of the semiconductor chip CHP and the upper surface of the chip mounting part CHPM are fixed to each other via an adhesive (not shown). Four suspension leads SUSLD are integrally formed and arranged at the corners of the chip mounting part CHPM.

[0036] like Figure 1 As shown in , a plurality of lead terminals LD are external terminals, which are arranged around the chip mounting portion CHPM so as to surround the semiconductor chip CHP. Each of the plurality of lead terminals LD is formed of the same metal as that of the chip mounting portion CHPM.

[0037] A plurality of bonding pads BP are arranged on the upper surface of the semiconductor chip CHP, which is a surface opposite to the lower surface of the semiconductor chip CHP. The bonding pads BP are electrically connected to a circuit block formed in the semiconductor chip CHP. In addition, the plurality of bonding pads BP are electrically connected to a plurality of lead terminals LD via metal wires WR.

[0038] The semiconductor chip CHP, the chip mounting portion CHPM, and each portion of the plurality of leads LD connected to the wires WR are sealed with a sealing body ML mainly composed of epoxy resin. The planar shape of the sealing body ML is as follows: Figure 1 The square shown in .

[0039] like Figure 1 and Figure 2 As shown in , parts of the plurality of leads LD protrude from the side surface of the sealing body ML, and the wire WR is not connected to the parts of the plurality of leads LD. In addition, the parts of the plurality of leads LD protruding from the side surface of the sealing body ML are formed into a gull-wing shape. When the semiconductor device PKG is mounted on a wiring substrate, the end parts of the plurality of leads LD formed into a gull-wing shape are welded and electrically connected to the terminals of the wiring substrate. The wiring substrate on which the semiconductor device PKG is mounted is eventually incorporated into automobiles, industrial equipment, household appliances, electronic equipment, etc.

[0040] <Overview of Circuit Configuration within Semiconductor Chip>

[0041] Figure 31 is a circuit diagram of a plurality of circuits formed in a semiconductor chip CHP related to the present embodiment. A microcomputer MCU (microcontroller, microprocessor) is built in the semiconductor chip CHP. The microcomputer MCU includes a CPU (central processing unit), a flash memory module FMJ, and a ROM (read-only memory). The CPU, the flash memory module FMJ, and the ROM are electrically connected to each other via wiring formed in the semiconductor chip CHP.

[0042] The flash memory module FMJ includes: a first flash memory FM1, which is a first non-volatile memory; a second flash memory FM2, which is a second non-volatile memory; a control circuit WECL, which controls the writing and erasing of program data to and from the first flash memory FM1; and a plurality of power control switches SW0, SW1, SW2 and SW3.

[0043] The first flash memory FM1 includes a plurality of memory blocks BL0, BL1, BL2, and BL3. In addition, each of the plurality of memory blocks BL0, BL1, BL2, and BL3 includes a plurality of decoder circuits DEC0, DEC1, DEC2, and DEC3, and memory cell arrays MSAL0, MSAL1, MSAL2, and MSAL3, and the memory cell arrays MSAL0, MSAL1, MSAL2, and MSAL3 are electrically connected to the outputs of the decoder circuits DEC0, DEC1, DEC2, and DEC3.

[0044] The CPU, ROM, control circuit WECL in flash module FMJ and multiple memory blocks BL0, BL1, BL2 and BL3 of first flash memory FM1 are electrically connected through CPU address bus and data bus ADB respectively. CPU address bus and data bus ADB are wiring formed in semiconductor chip CHP.

[0045] The CPU, ROM, control circuit WECL, and corresponding decoders DEC0, DEC1, DEC2, and DEC3 of the memory blocks BL0, BL1, BL2, and BL3 of the first flash memory FM1 are electrically connected to the bonding pad BP1 through wiring in the semiconductor chip CHP. The bonding pad BP1 is electrically connected to the lead terminal LD1 via the wire WR1. As a result, the first power supply voltage is supplied from the power supply PW provided outside the semiconductor device PKG via the lead terminal LD1 to the CPU, ROM, control circuit WECL, and corresponding decoder circuits of the memory blocks BL0, BL1, BL2, and BL3 of the first flash memory FM1.

[0046] In addition, each of the plurality of power control switches SW0, SW1, SW2, and SW3 is electrically connected to the input portion of the corresponding decoder circuits DEC0, DEC1, DEC2, and DEC3 of the memory blocks BL0, BL1, BL2, and BL3 of the first flash memory FM1. Therefore, the supply of the first power supply voltage to the decoder circuits DEC0, DEC1, DEC2, and DEC3 is controlled by closing / opening each of the plurality of power control switches SW0, SW1, SW2, and SW3.

[0047] The second flash memory FM2 in the flash memory module FMJ is electrically connected to the plurality of power control switches SW0, SW1, SW2, SW3 via wiring formed in the semiconductor chip CHP, and is electrically connected to the memory cell array MSAL of each of the memory blocks BL0, BL1, BL2, and BL3 of the first flash memory FM1. As a result, the closing / opening of each of the plurality of power control switches SW0, SW1, SW2, and SW3 is controlled according to the flag information written in the second flash memory FM2.

[0048] Each of the memory cell arrays MSAL of the memory blocks BL0, BL1, BL2, and BL3 of the first flash memory FM1 is electrically connected to the bonding pad BP2 through the wiring in the semiconductor chip CHP. The bonding pad BP2 is electrically connected to the lead terminal LD2 via the wire WR2. As a result, a second power supply voltage from the write / erase power supply PWWE provided outside the semiconductor device PKG for writing program data to the flash memory and for erasing program data from the flash memory is supplied to the memory cell arrays MSAL of the memory blocks BL0, BL1, BL2, and BL3 via the lead LD2.

[0049] In the above, so far, based on Figure 3 Several features are described. Among these features, a typical feature is that a plurality of power control switches SW0, SW1, SW2, and SW3 are controlled according to flag information stored in a second storage unit FM2, and the second storage unit FM2 is provided to enable on / off control of the supply of a first power supply voltage to each of the memory blocks BL0, BL1, BL2, and BL3 of the first flash memory FM1.

[0050] Figure 4 It is the inventor who discovered Figure 3 The circuit block diagram of the previously studied circuit block diagram. Figure 4 Describe the technical problem discovered by the inventor.

[0051] Figure 4 The circuit diagram does not include the above-mentioned second flash memory FM2 and multiple power control switches SW0, SW1, SW2 and SW3, which are controlled according to the flag information stored in the second flash memory FM2.

[0052] Figure 4 The program data use area PG of the first flash memory FM1 in the flash memory module FMJ shown in the figure indicates an area in which program data for operating the microcomputer MCU is stored, and the program data unused area NPG indicates an area in which program data is not stored, in other words, a so-called blank area. The supply of the first power supply voltage to the flash memory module FMJ incorporated in the microcomputer MCU is common to the power supply PW, and the power supply PW supplies the first power supply voltage to the entire semiconductor chip CHP. Therefore, even if the control circuit WECL that is not in operation or the program data unused area NPG exists in the first flash memory FM1, the supply of the first power supply voltage may not be stopped. That is, even after the user of the semiconductor device PKG writes program data in the first flash memory FM1, the program data unused area NPG exists in the first flash memory FM1, and the area is constantly supplied with energy.

[0053] As a result, since the first power supply voltage is continuously supplied to the control circuit WECL incorporated in the flash module FMJ and the program data unused area NPG in the first flash memory FM1, unnecessary consumption current increases. In addition, since the wiring in the semiconductor chip CHP is miniaturized, the problem of increased leakage current cannot be ignored.

[0054] In recent years, in particular, semiconductor device PKG is installed in the final system, and the final system has become complicated, and the manufacturer of semiconductor device PKG is very inclined to adopt a product configuration in which the flash memory FM1 has a large capacity to cope with the complicated final system. Therefore, when the capacity of program data written by the user is small, the program data unused area NPG of the first flash memory FM1 further increases, and the above-mentioned problems of consumption current and leakage current become more obvious. In order to solve the above-mentioned problems, the inventors have found that Figure 3 The circuit block diagram is shown in .

[0055] Reference below Figure 3 Here, among the memory blocks BL0, BL1, BL2, and BL3 of the first flash memory FM1, it is assumed that the memory blocks BL0 and BL1 are the program data used area PG, and the memory blocks BL2 and BL3 are the program data non-used area NPG.

[0056] At this time, the flag information "1" defining the memory blocks BL0 and BL1 of the first flash memory FM1 as the program data used area PG, and the flag information "0" defining the memory blocks BL2 and BL3 of the first flash memory FM1 as the program data unused area NPG are written in the second flash memory FM2.

[0057] Based on the flag information written in the second flash memory FM2, the CPU turns on the power control switches SW0 and SW1, which are electrically connected to the corresponding input portions of the memory blocks BL0 and BL1 of the first flash memory FM1, which are the program data use area PG. On the other hand, based on the flag information written in the second flash memory FM2, the CPU turns off the power control switches SW2 and SW3, which are electrically connected to the corresponding input portions of the memory blocks BL2 and BL3 of the first flash memory FM1, which are the program data non-use area NPG.

[0058] As a result, the first power supply voltage is not supplied to the memory blocks BL2 and BL3 which are the program data unused area NPG of the first flash memory FM1, so that Figure 4 Compared with the case of the circuit block diagram shown in , unnecessary consumption current can be reduced. In addition, if the wiring in the semiconductor chip CHP is miniaturized, the leakage current from the program data unused area NPG of the first flash memory FM1 can be reduced. And, as a result, the total power consumption of the semiconductor device PKG can be reduced.

[0059] Figure 5 0 is a first hard macro configuration diagram of the memory blocks BL0 and BL1 of the first flash memory FM1 according to this embodiment. Figure 5 As shown in , each of the memory blocks BL0 and BL1 includes decoder circuits DEC0 and DEC1, memory cell arrays MSAL0 and MSAL1, a plurality of sense amplifiers SA, a control circuit SACL, and an output driver OUTDR which is an output circuit.

[0060] Each of the multiple outputs of the decoder circuits DEC0 and DEC1 is electrically connected to the multiple word lines WL of the memory cell arrays MSAL0 and MSAL1 through the wiring in the semiconductor chip CHP. In addition, the output parts of the multiple data lines DL of the memory cell arrays MSAL0 and MSAL1 are electrically connected to the input parts of the multiple sense amplifiers SA through the wiring in the semiconductor chip CHP via the transistors pMOS.

[0061] The control circuit SACL is electrically connected to the gates of the plurality of transistors pMOS through wiring in the semiconductor chip CHP. The output parts of the plurality of sense amplifiers SA are electrically connected to the latch circuit Latch of the output driver OUTDR through wiring in the semiconductor chip CHP.

[0062] The CPU data bus CPU_DA_BUS is electrically connected to the output parts of the output drivers OUTDR of the memory blocks BL0 and BL1, respectively, and transmits the output program data to the CPU. The CPU address bus CPU_AD_BUS is electrically connected to the input part of the decoder circuit DEC of each memory block in the memory blocks BL0 and BL1, and the signal from the CPU is input to the input part of the decoder circuit DEC. The decoder circuit DEC receives the signal from the CPU and transmits the processed signal to the memory cell array MSAL. The CPU data bus CPU_DA_BUS and the CPU address bus CPU_AD_BUS are both wirings in the semiconductor chip CHP.

[0063] As described above, by configuring each memory block of the first flash memory FM1 to consist of Figure 5 By reading the sense amplifier SA of each memory cell array MSAL shown in , the program data stored in the following memory block can be read: the memory block is the program data use area PG. In addition, the supply of the first power supply voltage to the following memory block can be stopped by turning off the power control switch: the memory block is the program data unused area NPG. As a result, unnecessary consumption current flowing through the following memory block can be reduced: the memory block is the program data unused area NPG. As a result, the total power consumption of the semiconductor device PKG can be reduced.

[0064] Figure 6 is a second hard macro configuration diagram of the memory blocks BL0 and BL1 of the first flash memory FM1 according to the present embodiment. Figure 6 The hard macro configuration and Figure 5 The difference between the hard macro configurations is that the memory cell arrays MSAL of the corresponding memory blocks are combined, and the stored program data is read out through one sense amplifier SA. Specifically, the word line WL of the memory cell array MSAL0 of the memory block BL0 is electrically connected to the output part of the decoder circuit DEC0, the word line WL of the memory cell array MSAL1 of the memory block BL1 is electrically connected to the output part of the decoder circuit DEC1, and each of the data lines DL of the memory cell array MSAL0 and the data lines DL of the memory cell array MSAL1 is electrically connected to the input part of the plurality of sense amplifiers SA via the transistor pMOS.

[0065] In this configuration, Figure 5 Compared to the configuration of FIG. 1 , since the power control switch SW is not electrically connected to the multiple memory cell arrays MSAL, the supply of the first power supply voltage from the corresponding memory blocks BL0 to BLX of the multiple memory cell arrays MSAL cannot be stopped. However, in this configuration, since the power control switch is electrically connected to an arbitrary decoder circuit DEC, which is connected to each memory cell array in the multiple memory cell arrays MSAL and is electrically connected to an arbitrary peripheral control circuit not shown, the supply of the first power supply voltage to these circuits can be stopped. In this way, unnecessary consumption current flowing through the unused decoder circuit DEC and the peripheral control circuit can be reduced. As a result, the total power consumption of the semiconductor device PKG can be reduced.

[0066] <Power Supply Control Operation Mode of Semiconductor Device>

[0067] Next, the operation mode of the power supply control will be described. Figure 3 As shown in , the CPU is provided with a mode unit terminal MODE_SEL for selecting a power control operation mode and a reset terminal Reset for resetting the CPU.

[0068] There are two types of operation modes for performing power supply control in units of memory blocks: “normal operation mode” and “flash memory rewrite operation mode.” Specifically, these two operation modes are switched by the mode unit terminal MODE_SEL.

[0069] Figure 7 is an operation timing chart of the normal operation mode according to the present embodiment. Figure 8 : is an operation timing diagram of the flash memory rewrite operation mode according to the present embodiment. The normal operation mode is a mode in which the CPU executes the program data stored in the flash memory FM1. The flash memory rewrite operation mode is a mode in which erasing and writing of the program data stored in the flash memory FM1 via the CPU are performed in memory block units to be controlled by power supply. The details of each operation mode are described below.

[0070] (Description of normal operation mode)

[0071] Figure 3 The mode unit terminal MODE_SEL shown in is set to low, and a reset signal is input to the reset terminal Reset or the microcomputer MCU to release the reset of the microcomputer MCU and start the microcomputer MCU ( Figure 7 in S1).

[0072] The CPU reads the Figure 3 The bootloader in the ROM ( Figure 7 Ope1), and through Figure 3 The control circuit WECL reads the flag information set for each memory block of the second flash memory FM2 ( Figure 7 Ope2 in ). The memory blocks with flag information "1" are memory blocks BL0, BL1, and BL2, and the power control switches SW0, SW1, and SW2 connected to the memory blocks are turned on. Here, the memory block with flag "0" is memory block BL3, and the power control switch SW3 connected to the memory block BL3 is turned off ( Figure 7 Ope3 and Ope4 in .

[0073] Thereafter, the CPU jumps to the program stored in the first flash memory FM1, and the CPU starts operating ( Figure 7 Ope5 in ).

[0074] (Description of Flash Memory Rewrite Operation Mode)

[0075] Erasing of the memory block BL3 and writing of the memory block BL2 will be taken as an example.

[0076] First, the second power supply voltage is supplied from the flash memory write / erase power supply PWWE to the memory cell arrays MSAL of the plurality of memory blocks BL0 , BL1 , BL2 , and BL3 of the first flash memory FM1 , respectively.

[0077] Next, the mode unit terminal MODE_SEL becomes high, and a reset signal is input to the reset terminal Reset or the microcomputer MCU to cancel the reset of the microcomputer MCU, thereby starting the microcomputer MCU ( Figure 8 S2 in ).

[0078] The CPU reads the Figure 3 Flash rewrite procedure in ROM ( Figure 8 Ope6 in ).

[0079] The CPU erases the program data of the memory block BL3 to be erased in the first flash memory FM1 ( Figure 8 Thereafter, the CPU sets the flag information of the memory block BL3 of the second flash memory FM2 to "OFF(0)" ( Figure 8 Ope8 in ).

[0080] Then, the CPU sets the flag information of the memory block BL2 of the second flash memory FM2 to "ON (1)" ( Figure 8 Thereafter, the CPU writes the predetermined program data into the memory block BL2 of the first flash memory FM1 ( Figure 8 Ope10 in ).

[0081] As described above, the "normal operation mode" and the "flash memory rewrite operation mode" have been described as operation modes for performing power control in memory block units. The program for controlling the operation of the second flash memory FM2 and the power control switch of the corresponding memory block of the first flash memory FM1 as described above is pre-stored as a boot program of the ROM. Therefore, the user can easily use the semiconductor device PKG without the user being aware of the control.

[0082] (Description of Modification Example of Normal Operation Mode)

[0083] In addition, in the normal operation mode, the CPU controls the power control switch of each memory block connected to the first flash memory FM1 based on the flag information set for each memory block of the second flash memory FM2 by the boot program stored in the ROM, but the control circuit WECL can control the power control switch based on the flag information set for each memory block of the second flash memory FM2.

[0084] Fig. 9 is an operation timing chart of the control circuit WECL and the CPU in the normal operation mode according to the present embodiment. Figure 3 The mode unit terminal MODE_SEL shown in is set to low, and a reset signal is input to the reset terminal Reset or the microcomputer MCU to cancel the reset of the microcomputer MCU and start the microcomputer MCU ( Fig. 9 in S3).

[0085] The CPU reads the Figure 3 The bootloader in the ROM shown in ( Fig. 9 Ope15 in the control circuit WECL), and sends a power control command to the control circuit WECL ( Fig. 9 After receiving the power control command from the CPU, the control circuit WECL reads the flag information ( Fig. 9 Here, the memory blocks whose flag information is "1" are the memory blocks BL0, BL1, BL2, and BL3, and the power control switches SW0, SW1, SW2, and SW3 connected to the memory blocks are turned on. The memory blocks whose flag information is "0" are the memory blocks BL4, BL5, and BL6, and the power control switches SW4, SW5, and SW6 connected to the memory blocks are turned off ( Fig. 9While the control circuit WECL is executing these settings, the CPU waits for a response from the control circuit WECL ( Fig. 9 Ope17 in ).

[0086] When the setting of the control circuit WECL is completed, the control circuit WECL returns a completion response to the CPU ( Fig. 9 Ope14 in ).

[0087] After receiving the completion response from the control circuit WECL ( Fig. 9 Ope18 in the first flash memory FM1), the CPU jumps to the program stored in the first flash memory FM1 and starts the operation of the program ( Fig. 9 in Ope19).

[0088] (Description of Modification Example of Flash Memory Rewrite Operation Mode)

[0089] In addition, in the flash memory rewriting operation mode, the control circuit WECL can update the flag information set for each memory block of the second flash memory FM2 through the instruction of the CPU.

[0090] Fig.10 is an operation timing diagram of the control circuit and the CPU when flag information is erased in the flash memory rewrite operation mode according to the present embodiment.

[0091] First, the second power supply voltage is supplied from the flash memory write / erase power supply PWWE to the memory cell array MSAL of the plurality of memory blocks BL0 to BL6 of the first flash memory FM1.

[0092] Next, the mode unit terminal MODE_SEL becomes high, and a reset signal is input to the reset terminal Reset or the microcomputer MCU to cancel the reset of the microcomputer MCU and start the microcomputer MCU ( Fig.10 in S4).

[0093] The CPU reads the Figure 3 Flash rewriting procedure in ROM shown in ( Fig.10 In addition, the CPU issues an instruction to the control circuit WECL to erase the flag information of the memory block BL3 ( Fig.10 Ope24 in ).

[0094] After receiving a command to erase the flag information from the CPU, the control circuit WECL erases the program data of the memory block BL3 to be erased from the first flash memory FM1 ( Fig.10Then, the control circuit WECL sets the flag information of the memory block BL3 of the second flash memory FM2 to "OFF(0)" ( Fig.10 While the control circuit WECL is executing these settings, the CPU waits for a response from the control circuit WECL ( Fig.10 Ope25 in ).

[0095] When the setting of the control circuit WECL is completed, the control circuit WECL returns a completion response to the CPU ( Fig.10 Ope22 in ).

[0096] When the CPU receives a completion response from the control circuit WECL ( Fig.10 Ope26 in the process), the CPU ends a series of erase operations.

[0097] Fig.11 is an operation timing diagram of the control circuit WECL and the CPU when flag information is written in the flash memory rewrite operation mode according to the present embodiment.

[0098] First, the second power supply voltage is supplied from the flash memory write / erase power supply PWWE to the memory cell array MSAL of the plurality of memory blocks BL0 to BL6 of the first flash memory FM1.

[0099] Next, the mode unit terminal MODE_SEL becomes high, and a reset signal is input to the reset terminal Reset or the microcomputer MCU to cancel the reset of the microcomputer MCU, thereby starting the microcomputer MCU ( Fig.11 Step S5).

[0100] The CPU reads the Figure 3 Flash rewriting procedure in ROM shown in ( Fig.11 Then, the CPU issues a command to the control circuit WECL to write the flag information of the memory block BL3 ( Fig.11 Ope31 in ).

[0101] After receiving a command to write the flag information from the CPU, the control circuit WECL writes the predetermined program data into the memory block BL3 of the first flash memory FM1 ( Fig.11 Ope27 in the figure), wherein the flag information is to be written to the memory block BL3 of the first flash memory FM1. Then, the control circuit WECL sets the flag information of the memory block BL3 of the second flash memory FM2 to "ON(1)" ( Fig.11While the control circuit WECL is executing these settings, the CPU waits for a response from the control circuit WECL ( Fig.11 Ope32 in ).

[0102] When the setting of the control circuit WECL is completed, the control circuit WECL returns a completion response to the CPU ( Fig.11 Ope29 in ).

[0103] When the CPU receives the end response from the control circuit WECL ( Fig.11 Ope33 in the CPU ends a series of write operations.

[0104] The above describes a modification example of each of the normal operation mode and the flash memory rewrite operation mode. As a result, (1) since the CPU does not need to refer to or set the flag information set for each of the memory blocks of the second flash memory FM2, the program of the corresponding operation mode can be simplified. In addition, (2) since the CPU does not need to refer to or set the flag information set for each of the memory blocks of the second flash memory FM2, the CPU does not need to disclose the existence of the second flash memory FM2 to the user. In addition, (3) since the control circuit WECL controls the power control switch based on the flag information set for each memory block of the second flash memory FM2, the startup time when the system is started in the normal operation mode can be shortened compared to the case where the CPU performs the control of the power control switch based on the flag information set for each memory block of the second flash memory FM2. In addition, (4) since the control circuit WECL sets the second flash memory FM2, the time required to erase / write the first flash memory FM1 can be shortened compared to the case where the CPU performs the setting.

[0105] <First Modification Example of Circuit Configuration Inside Semiconductor Chip>

[0106] Fig.12 1 is a circuit diagram for preventing a read error of a memory block in which the supply of the first power supply voltage is stopped according to the present embodiment. So far, it has been described that the second flash memory FM2 is established, and it has been described that the first power supply voltage to be supplied to the first flash memory FM1 is closed / open controlled for each memory block based on the flag information set for each memory block stored in the second flash memory FM2.

[0107] In this case, the CPU may erroneously read a memory block to which the first power supply voltage is not supplied. Fig.12As shown in , a selector Selector may be provided at the output of the flash memory module FMJ, and a fixed value may be read out based on the flag information for each memory block stored in the second flash memory FM2. The fixed value is preferably a low level or an undefined instruction code at which no current flows. As a result, even when the memory block BL0 to which the first power supply voltage is not supplied is erroneously read out, the fixed value is read out, thereby preventing a malfunction of reading out the fixed value.

[0108] <Second Modification Example of Circuit Configuration Inside Semiconductor Chip>

[0109] In addition, the first flash memory FM1 may be, for example, a dual-bank mode having an A-side and a B-side. Fig.13 is a circuit block diagram of a plurality of circuits formed in the semiconductor chip CHP of the present embodiment when the first flash memory FM1 is in the dual bank mode.

[0110] In this case, if Fig.13 As shown in, by newly providing a 1-bit discrimination circuit for discriminating the A side and the B side in the second flash memory FM2, where the discrimination circuit is the flag information of the memory block BL7 and the AND circuit ANDC, the first power supply voltage can be closed / open controlled for each memory block.

[0111] More specifically, by providing such a discrimination circuit, the power control switch is turned off on the side where the program data of the first flash memory FM1 is not stored, and the power control switch is turned on on the side where the program data is stored. As a result, since the first power supply voltage is not supplied to the side of the first flash memory FM1 where the program data is not stored, unnecessary consumption current can be reduced compared to the case where the discrimination circuit is not provided. As a result, the total power consumption of the semiconductor device PKG can be reduced.

[0112] When the microcomputer MCU can determine whether the microcomputer MCU uses the A side or the B side of the dual bank mode, the setting content can be reflected in a determination bit newly provided in the second flash memory FM2, which in this case is the memory block BL7.

[0113] Although a microcomputer is mainly exemplified here, several features that have been described so far are not limited to microcomputers and can be applied to a semiconductor chip called a system LSI or SOC (System on Chip).

[0114] Although QFP is described here as an example of a package type, the package type is not limited thereto. For example, a BGA (ball grid array) package or an LGA (land grid array) package may be adopted, in which a semiconductor chip is mounted on an interposer substrate and is electrically connected to the interposer via metal wires or bumps. In this case, a plurality of ball electrodes and land electrodes provided on a surface opposite to the surface of the interposer substrate on which the semiconductor chip is mounted are used as external terminals.

[0115] Although a semiconductor package in which a semiconductor chip is sealed with a sealing member has been described as a semiconductor device, the semiconductor chip itself may be defined as a semiconductor device.

Claims

1. A semiconductor device, comprising: Semiconductor chips, including: A first non-volatile memory having a first memory block and a second memory block; A central processing unit CPU, controlling the first non-volatile memory; a first switch electrically connected to the first memory block and controlling supply of a first power supply voltage to the first memory block; a second switch electrically connected to the second memory block and controlling supply of the first power supply voltage to the second memory block; and a second nonvolatile memory electrically connected to each of the first switch and the second switch and storing flag information for controlling the first switch and the second switch, The control of each of the first switch and the second switch is performed based on the flag information indicating whether program data to be executed by the CPU is written in the first memory block and the second memory block.

2. The semiconductor device according to claim 1, When the program data is written into the first memory block and the second memory block is blank, the first switch and the second switch are controlled by the flag information, and the flag information is defined so that the first power supply voltage is supplied to the first memory block and the first power supply voltage is not supplied to the second memory block.

3. The semiconductor device according to claim 2, The flag information includes: first flag information, the first flag information defining that the first switch is to be turned on based on the program data being written into the first memory block; and second flag information defining that the second switch is to be turned off based on the second memory block being blank.

4. The semiconductor device according to claim 3, The first memory block comprises: a first decoder circuit to which a signal from the CPU is input; a first memory cell array electrically connected to an output portion of the first decoder circuit to write the program data; a first sense amplifier having an input portion, the input portion of the first sense amplifier being electrically connected to the first memory cell array via a first transistor; a first control circuit electrically connected to a gate of the first transistor and configured to control the gate of the first transistor; as well as a first output circuit electrically connected to an output portion of the first sense amplifier to transmit the program data output from the first memory cell array to a CPU, and The second memory block comprises: a second decoder circuit to which a signal from the CPU is input; a second memory cell array electrically connected to an output portion of the second decoder circuit for writing the program data; a second sense amplifier having an input portion, the input portion of the second sense amplifier being electrically connected to the second memory cell array via a second transistor; a second control circuit electrically connected to the gate of the second transistor and configured to control the gate of the second transistor; and A second output circuit is electrically connected to an output of the second sense amplifier to transmit the program data output from the second memory cell array to a CPU.

5. The semiconductor device according to claim 4, wherein a data line of the first memory cell array is electrically connected to the input portion of the first sense amplifier via the first transistor, wherein word lines of the first memory cell array are electrically connected to the output portion of the first decoder circuit, wherein a data line of the second memory cell array is electrically connected to the input portion of the second sense amplifier via the second transistor, and Wherein word lines of the second memory cell array are electrically connected to the output portion of the second decoder circuit.

6. The semiconductor device according to claim 5, wherein the first switch and the second switch are electrically connected to an external terminal, the first power supply voltage is supplied from an externally provided power supply to the external terminal, and The semiconductor chip is sealed by a sealing member.

7. The semiconductor device according to claim 3, The first memory block comprises: a first decoder circuit to which a signal from the CPU is input; as well as a first memory cell array electrically connected to an output portion of the first decoder circuit to write the program data, The second memory block comprises: a second decoder circuit to which a signal from the CPU is input; and a second memory cell array electrically connected to an output portion of the second decoder circuit to write the program data, It also includes: a sense amplifier having an input portion electrically connected to the second memory cell array via a transistor; a control circuit, configured to control a gate of the transistor; and an output circuit electrically connected to an output portion of the sense amplifier to transmit the program data output from the first memory cell array or the second memory cell array to a CPU, wherein the first switch is electrically connected to the first decoder circuit and is not electrically connected to the second decoder circuit, and Wherein the second switch is electrically connected to the second decoder circuit and is not electrically connected to the first decoder circuit.

8. The semiconductor device according to claim 7, wherein word lines of the first memory cell array are electrically connected to the output portion of the first decoder circuit, wherein a word line of the second memory cell array is electrically connected to the output portion of the second decoder circuit, and Each of the data lines of the first memory cell array and the data lines of the second memory cell array is electrically connected to the input portion of the sense amplifier via the transistor.

9. The semiconductor device according to claim 8, The first switch and the second switch are electrically connected to an external terminal, the first power supply voltage is supplied from an external power supply to the external terminal, and the semiconductor chip is sealed by a sealing member.

10. A semiconductor device comprising: Semiconductor chips, including: a first nonvolatile memory having a first memory block and a second memory block on a side A of the first nonvolatile memory, and a third memory block and a fourth memory block on a side B of the first nonvolatile memory; a central processing unit CPU electrically connected to the first non-volatile memory; a first switch electrically connected to the first memory block and controlling supply of a first power supply voltage to the first memory block; a second switch electrically connected to the second memory block and controlling supply of the first power supply voltage to the second memory block; a third switch electrically connected to the third memory block and controlling supply of the first power supply voltage to the third memory block; a fourth switch electrically connected to the fourth memory block and controlling supply of the first power supply voltage to the fourth memory block; a second nonvolatile memory electrically connected to each of the first switch, the second switch, the third switch, and the fourth switch, and in which flag information for controlling the first switch, the second switch, the third switch, and the fourth switch is stored; and a plurality of discrimination circuits that discriminate the A side or the B side and are electrically connected to each of the first switch, the second switch, the third switch, and the fourth switch, The discrimination circuit discriminates whether program data to be executed by the CPU is written to the A side and the B side based on the flag information, and the control of the first switch, the second switch, the third switch and the fourth switch is performed based on the discrimination result of the discrimination circuit.

11. The semiconductor device according to claim 10, The first switch, the second switch, the third switch and the fourth switch are controlled so that when the program data is written on the A side and the B side is blank, the first power supply voltage is supplied to the first memory block and the second memory block, and the first power supply voltage is not supplied to the third memory block and the fourth memory block.

12. A power control method for a semiconductor device, comprising the following steps: (a) The central processing unit CPU reads the boot program stored in the read-only memory ROM; (b) after step (a), reading flag information from the second nonvolatile memory by the CPU, the flag information being used to control a first switch and a second switch, the first switch being electrically connected to a first memory block of the first nonvolatile memory, and the second switch being electrically connected to a second memory block of the first nonvolatile memory; as well as (c) after step (b), the CPU controls the first switch and the second switch based on the flag information, thereby controlling the supply of the first power supply voltage to the first memory block and the supply of the first power supply voltage to the second memory block, The flag information is information indicating whether program data to be executed by the CPU has been written to the first memory block and the second memory block.

13. The power supply control method of a semiconductor device according to claim 12, The flag information includes first flag information, which defines that the first switch is turned on by the program data being written in the first memory block; and second flag information, which defines that the second switch is turned off by the second memory block being blank.

14. The power supply control method of a semiconductor device according to claim 13, The semiconductor device includes a semiconductor chip, and the semiconductor chip includes a CPU, a ROM, the first nonvolatile memory, and the second nonvolatile memory.

15. The power supply control method of a semiconductor device according to claim 12, Wherein after the step (c), the CPU retrieves the program data stored in the first nonvolatile memory to start the operation of the program data, and the power supply control method of the semiconductor device starts.

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