Digital signal processing waveform synthesis for fixed sampling rate signal sources

Abstract

A test and measurement instrument includes a digital-to-analog converter having an output sampling rate, which is configured to receive a digital sampled waveform and a reference clock and output an analog waveform at the sampling rate; a waveform synthesizer, which is configured to receive an input waveform having a baud rate and output a digital sampled waveform having a baud rate less than the sampling rate of the digital-to-analog converter; and a port, which is configured to output the analog waveform.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Provisional U.S. Patent Application No. 62 / 787,192, filed on December 31, 2018, the entire contents of which are hereby incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to systems and methods related to test and measurement systems, and in particular to synthesizing waveforms for fixed sampling rate signal sources. Background Art

[0004] Conventional signal sources that synthesize waveforms for data communications applications typically use sampling rates that are integer multiples of the desired baud rate of the generated waveform. These waveforms can include signaling techniques such as non-return to zero (NRZ), pulse amplitude modulation (PAM), quadrature amplitude modulation (QAM) for in-phase (I) and quadrature (Q) signal components across two synchronization channels, such as those used in coherent optical communications applications.

[0005] Using traditional waveform generation methods, the signal source can use simple replication of the waveform symbol values ​​with a constant integer interpolation factor to upsample from the waveform baud rate to the sampling rate used by the digital-to-analog converter (DAC). At a minimum, supporting arbitrary baud rate waveform generation using traditional synchronous waveform synthesis methods requires a reference clock and a DAC sampling rate that can vary in frequency over a full octave, i.e., across a 1:2 times frequency range, that is synchronized with the desired waveform baud rate by an integer ratio.

[0006] However, designing synchronized waveform generation with high-speed DACs and signal sources whose sampling frequencies can vary across a full octave can be challenging. Moreover, changing the DAC sampling frequency to support different waveform baud rates for test and measurement applications that require switching between several different baud rates can often require time-consuming recalibration, as many DAC impairments can be sensitive to sampling rate.

[0007] Embodiments of the present disclosure address these and other deficiencies of the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects, features and advantages of embodiments of the present disclosure will become apparent from the following description of embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 is a block diagram of a test and measurement instrument with a waveform synthesizer according to some embodiments of the present disclosure.

[0010] Figure 2is an example of a Farrow resampling filter according to some embodiments of the present disclosure.

[0011] Figure 3 is an example of a test and measurement instrument having another waveform synthesizer according to other embodiments of the present disclosure.

[0012] Figure 4 is a result graph of linear edge interpolation according to an embodiment of the present disclosure.

[0013] Figure 5 is a result graph of linear edge interpolation performed according to an embodiment of the present disclosure.

[0014] Figure 6 is a block diagram of a test and measurement instrument with a waveform synthesizer according to other embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] Embodiments of the present disclosure may address the challenges of conventional and traditional techniques by using digital signal processing (DSP) to synthesize waveforms using an asynchronous fixed rate DAC or a narrow adjustable rate DAC that is oversampled relative to a target waveform baud rate. As will be discussed in more detail below, embodiments of the present disclosure may support arbitrary waveform baud rates through fractional replication / interpolation techniques in the DSP to upsample a waveform at a desired baud rate to the sampling rate of the DAC.

[0016] Embodiments of the present disclosure utilizing a fixed rate DAC or a narrowly adjustable rate DAC and a signal source are superior to conventional integer replication approaches utilizing a DAC and a signal source that can vary its sampling rate over at least an octave because a high speed fixed rate DAC can be easier to design and optimize relative to a variable sampling rate DAC. This is true even for situations where the fixed rate DAC has a higher sampling rate than a comparable variable sampling rate DAC.

[0017] Additionally, embodiments of the present disclosure may allow a fixed rate DAC or narrowly adjustable rate DAC and sampled signal to be calibrated once, and then the waveform baud rate may be dynamically changed without recalibration. Some of the DSP waveform synthesis embodiments used to replicate and / or interpolate waveforms at fractional ratios may also be utilized to dynamically modulate symbol periods during waveform generation to introduce spread spectrum clocking, add jitter impairments, and / or other timing or phase related impairments to waveforms generated using a signal source for stress testing applications.

[0018] The embodiments disclosed herein may be implemented in real-time DSP hardware such as a field programmable gate array (FPGA) or application specific integrated circuit (ASIC) or by pre-calculation if the waveform replication / interpolation is done in advance and loaded into a waveform pattern memory in a signal source that is used to generate a real-time output waveform at the DAC sampling rate.

[0019] Figure 1 1 is a block diagram of a test and measurement instrument 100 having a waveform synthesizer according to some embodiments of the present disclosure. An input waveform 102, x[n], is a digital representation of the symbol value of the desired output waveform to be generated, which may be generated at the baud rate (F) of the waveform to be synthesized. s,symbol ) to sample it. The input waveform 102 may be received at a waveform synthesizer 104 that replicates the waveform by an integer factor N to upsample the input waveform to a higher sampling rate. Upsampling the input waveform 102 by a larger factor (such as by a factor of ten or more) will improve the time resolution when mapped to the output asynchronous sampling rate of the DAC 112 and may reduce artifacts introduced in the process, but will also increase hardware complexity if implemented using a real-time DSP. The input waveform 102 may have a baud rate that may be less than the sampling rate of the DAC 112 by a non-integer rational ratio.

[0020] Once the input waveform 102 has been replicated N times, a low pass filter 106, G(z), is applied to remove signal content above the Nyquist frequency of the DAC 112, as well as to perform any other desired shaping of the frequency and transient response characteristics of the output waveform, which may include pre-emphasis to compensate for the response of the DAC 112 and / or downstream channel signal paths.

[0021] After the low pass filter 106, the data is downsampled 108 by M to reduce the sampling rate to match the output sampling rate of the DAC 112. In some embodiments, M is a constant integer value. However, in other embodiments, M can be a fractional downsampling factor, which can be supported by dithering the downsampling factor M used for each DAC sampling cycle when synthesizing the output waveform. That is, the M factor can alternate between consecutive integer values ​​so that the average downsampling factor averaged over many DAC sampling cycles reaches the desired fractional downsampling factor.

[0022] Based on the above, the waveform baud rate is determined by equation (1):

[0023] (1)

[0024] The downsampled waveform y[m] is received at the DAC 112 and converted to an analog signal. The DAC 112 may also receive a reference clock 114 from another component of the test and measurement instrument 100. After the waveform is converted to an analog signal by the DAC 112, the analog waveform may be filtered by an analog low pass filter 116, H(f), which is used to remove signal content above the first Nyquist zone of the DAC 112. This may remove the zero order hold effect of a conventional DAC in the higher Nyquist zones, which causes a sin(πf) / (πf) replication of the waveform spectrum in the first Nyquist zone across the higher Nyquist zones, which may be undesirable for situations where the DAC sampling rate is not related to the input waveform baud rate by an integer upsampling factor, as it may create artifacts in the output waveform, such as when the baud rate is less than the sampling rate of the DAC 112 by a non-integer rational ratio. The filtered waveform is output to a port 118 in the test and measurement instrument 100. The device under test may be connected to port 118 via a cable (or optical fiber if an electrical-to-optical converter is used after the DAC 112 output) to receive the filtered analog waveform.

[0025] At which the DAC 112 sampling rate (F s,DAC ) is the waveform baud rate (F s,symbol ), since the zero-order hold response of DAC 112 is coherent with the waveform being synthesized and can enhance the desired sign transition in the output waveform, the analog low-pass filter 116 can be removed or bypassed and the output from DAC 112 can be sent directly to port 118.

[0026] In some embodiments, a waveform may be synthesized using a direct linear interpolation resampler or a Farrow resampling filter structure instead of the low pass filter 106 discussed above, instead of the waveform copier 104, low pass filter 106, and downsampler 108. In such an embodiment, Figure 1 The remaining components of the embodiment will remain the same.

[0027] Using a direct linear interpolation resampler, the DAC input samples y[m] may be calculated from the input waveform 102, x[n] using equations (2), (3), and (4) below.

[0028] (2)

[0029] (3)

[0030] (4)

[0031] in, That is, r is the ratio of the output sample rate to the waveform baud rate. However, assuming the use of a fairly sharp DSP low-pass filter 106 with a cutoff frequency close to the Nyquist frequency of the DAC 112, the direct linear interpolation resampling method is superior to other methods (such as those described above). Figure 1 A limitation of the discussed replication and decimation methods is the degradation in the edge rise / fall times of the synthesized waveform.

[0032] use Figure 2 The Farrow resampling filter 200 shown in FIG. 1 performs cubic interpolation, The value will change dynamically within each DAC 112 sampling cycle to adjust the waveform baud rate (F s,symbol ) and the DAC 112 output sampling rate (F s,DAC ) to achieve the desired fractional resampling rate.

[0033] If a real-time DSP is used to implement the embodiment, the Farrow resampling filter 200 may include high-order terms to avoid edge rise / fall time degradation similar to the direct linear interpolation resampling method, but at the expense of additional hardware complexity. However, the real-time DSP hardware complexity of the Farrow filter 200 may be less than Figure 1 The general DSP waveform replication and extraction method is shown.

[0034] The direct linear interpolation resampler and Farrow filter 200 can be advantageous because the resulting transitions between symbol periods and symbol values ​​can be dynamically modulated in phase to support the insertion of spread spectrum clocks, jitter impairments, and / or other timing or phase related impairments in the output waveform to support stress impairment generation for test and measurement applications.

[0035] Figure 3 Another embodiment of the present disclosure for waveform synthesis with edge interpolation is illustrated. Figure 3 The embodiment of the present invention combines direct integer replication of symbol values ​​with interpolation of a single DAC sample value at each symbol transition edge. This can be done to utilize the full resolution of the oversampled DAC 112 to improve the timing accuracy of the sub-sample edge crossings of the synthesized output waveform, thereby minimizing the creation of unintended jitter artifacts in the synthesized waveform.

[0036] Compared to the above-mentioned DSP waveform replication and extraction 100 or high-order Farrow filter 200, waveform synthesis using edge interpolation (an example of which is shown in Figure 3) has much lower hardware complexity for a real-time DSP implementation. There is also less degradation in rise / fall times compared to direct linear interpolation resampling or low-order Farrow filters because interpolation is limited to a single sample for each symbol edge transition.

[0037] exist Figure 3 In the illustrated embodiment 300, a waveform symbol clock generator 302 may receive a DAC reference clock 304 from a test and measurement instrument and a waveform symbol clock modulation signal 306. The waveform symbol clock generator 302 outputs a symbol transition event 308 and a symbol transition downsampled phase 310 to a waveform synthesis edge interpolator 312, which also receives the input signal 102, x[n]. The waveform synthesis edge interpolator 312 outputs a digital signal y[m] to be converted to an analog signal by the DAC 112. Figure 1 similar, Figure 3 Embodiments of the present invention also include an analog filter 116 to filter the analog signal before outputting it to port 118, and as such, these components will not be described further herein.

[0038] The waveform symbol clock generator 302 is clocked at a rate relative to the DAC output sampling rate ( F s,DAC ) of the asynchronous input waveform baud rate F s,Symbol The waveform symbol clock generator 302 can track when the transition of each symbol should occur in time based on equation (5) which determines the symbol period relative to the DAC output sampling:

[0039] (5)

[0040] The waveform symbol clock generator 302 may be implemented as a counter with fractional sample time resolution that can track the DAC 112 sample period in which a symbol transition 308 will occur, and a fractional downsampled component 310 that tracks where a symbol transition should occur between two adjacent DAC 112 samples (which are asynchronous to the waveform being synthesized). The fractional downsampled symbol transition times 310 are used as input to a waveform synthesis edge interpolator 312. The purpose of edge interpolation is to select DAC 112 input samples that, after taking into account the response of the DAC and the downstream analog signal path to the output port 118, will cause a symbol transition in the generated output waveform to occur at the desired downsampled time between consecutive DAC 112 output samples in the output waveform generated by the signal source.

[0041] The following equations (6)-(8) describe the calculation of the waveform symbol transition times by the waveform symbol clock generator 302, which are divided into a component 308 (k) of integer DAC sample transition events when synthesizing the output waveform at the DAC sample rate and a downsampled fractional transition phase component 310 (Φ) of consecutive symbol periods.

[0042] (6)

[0043] (7)

[0044] (8)

[0045] As calculated by equation (7) above, the waveform synthesis edge interpolator 312 may be active for output DAC samples with symbol period transitions. Otherwise, the current waveform symbol value x[n] will be copied until the next sample period transition occurs.

[0046] The waveform synthesis edge interpolator 312 uses the downsampled fractional symbol transition phase (Φ[n]) component 310 to calculate the appropriate interpolated DAC value to obtain the desired symbol transition time between consecutive DAC output samples.

[0047] The waveform synthesis edge interpolator 312 can operate in different ways to calculate the interpolated DAC sample values. For example, the following equation (9) for symbol transitions and equation (10) for other samples after the transition can be used to interpolate the DAC sample values ​​for each symbol period transition:

[0048] (9)

[0049] (10)

[0050] The waveform synthesis edge interpolator 312 using equations (9) and (10) can achieve the desired down-sampled decision threshold crossing time with a constant edge slope of the synthesized waveform between symbol values.

[0051] Figure 4 Graph 400 is illustrated. Graph 400 illustrates an ideal continuous-time waveform 402 with a lower bandwidth output channel (where the unit interval is 4.23 times the DAC sampling interval), an interpolated waveform 404 using equations (9) and (10), and an interpolated waveform 406 using equations (9) and (10).

[0052] Alternatively, rather than keeping the edge slope constant for each symbol transition, as described above, in some embodiments, the waveform synthesis edge interpolator 312 may vary the edge slope to achieve a desired downsampled decision threshold crossing time between symbol values. This is described in equations (11)-(15):

[0053] (11)

[0054] (12)

[0055] (13)

[0056] (14)

[0057] (15)

[0058] Figure 5 Graph 500 using equations (11)-(15) is illustrated. Graph 500 illustrates an ideal continuous-time waveform 502 with a lower bandwidth output channel (where the unit interval is 4.23 times the DAC sampling interval), an interpolated waveform 504 using equations (11)-(15), and an interpolated waveform 506 using equations (11)-(15).

[0059] The performance of each of the above-described embodiments depends on the bandwidth and frequency response of the DAC 112 and the source output signal path at port 118 , as well as the resolution and other performance characteristics of the DAC 112 .

[0060] Figure 6 Another embodiment of the present disclosure is illustrated, which may better optimize edge interpolation to account for the effects of non-ideal channel frequency response and / or bandwidth limitations, while still having an implementation that is efficient for real-time DSP hardware implementation.

[0061] Figure 6 The embodiment also includes a waveform symbol clock generator 302 that can receive a DAC reference clock 304 and a waveform symbol clock modulation signal 306 and output a symbol transition down-sampling phase 310 and a symbol transition event 308 .

[0062] The input signal 102 is received at both the waveform synthesis edge interpolation lookup table 602 and the waveform symbol copier 604. The output of each waveform synthesis edge interpolation lookup table 602 and the waveform symbol copier 604, as well as the symbol transition event 308, are sent to the multiplexer 606, which outputs the digital signal y[m], which is converted to an analog signal at the DAC 112 and filtered at the analog low pass filter 116 before being output to the port 118. The multiplexer 606 selects the output of the waveform synthesis edge interpolation lookup table 602 or the output of the waveform symbol copier 604 based on the received symbol transition event 308.

[0063] The waveform synthesis edge interpolation lookup table 602 can generate DAC sample values ​​that can be used to transition between consecutive symbol values ​​based on the current symbol value or input signal 102, x[n], the next symbol value x[n+1], and the symbol transition downsampling phase 310. The waveform synthesis edge interpolation lookup table 602 selects DAC sample values ​​that are used to transition between consecutive symbol values, taking into account the overall frequency response, bandwidth, and other characteristics of the signal path to port 118, at the output of port 118 for a given ɸ[n] , which DAC sample value achieves the closest desired downsampling decision threshold crossing phase between consecutive DAC samples.

[0064] The values ​​of the waveform synthesis edge interpolation lookup table 602 can be calibrated by characterizing the step response of each possible DAC 112 level in the interpolated edge value between symbol value transitions at port 118, and then measuring the downsampled edge decision threshold crossing phase for each DAC 112 level. This information can then be used to generate coefficients to save or store in the waveform synthesis edge interpolation lookup table 602 to select the interpolated output DAC sample value for each waveform edge that is closest to the desired decision threshold crossing phase at the signal source output. The DAC112 input samples can be replicated between symbol transitions, just as is done with the other edge interpolation methods discussed above.

[0065] Aspects of the present disclosure may operate on specially created hardware, firmware, digital signal processors, or on a specifically programmed computer including a processor that operates according to programming instructions. The term controller or processor as used herein is intended to include microprocessors, microcomputers, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and dedicated hardware controllers. One or more aspects of the present disclosure may be embodied in computer-usable data and computer-executable instructions executed by one or more computers (including monitoring modules) or other devices, such as in one or more program modules. Typically, program modules include routines, programs, objects, components, data structures, etc., which perform specific tasks or implement specific abstract data types when executed by a processor in a computer or other device. Computer executable instructions may be stored on computer-readable storage media such as hard disks, optical disks, removable storage media, solid-state memory, random access memory (RAM), etc. As will be appreciated by those skilled in the art, the functions of program modules may be combined or distributed as needed in various aspects. In addition, the functions may be embodied in firmware or hardware equivalents, such as integrated circuits, FPGAs, and the like, in whole or in part. Certain data structures may be used to more efficiently implement one or more aspects of the present disclosure, and such data structures are contemplated within the scope of the computer-executable instructions and computer-usable data described herein.

[0066] In some cases, the disclosed aspects may be implemented in the form of hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried or stored on one or more computer-readable storage media, which may be read and executed by one or more processors. Such instructions may be referred to as computer program products. As discussed herein, computer-readable media refers to any medium that can be accessed by a computing device. As an example and not limitation, computer-readable media may include computer storage media and communication media.

[0067] Computer storage media refers to any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital video disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any volatile or non-volatile, removable or non-removable media implemented in any technology. Computer storage media does not include the signal itself and the signal transmission in a temporary form.

[0068] Communication media refers to any medium that can be used for communication of computer-readable information. By way of example and not limitation, communication media may include coaxial cables, fiber optic cables, air, or any other medium suitable for communication of electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0069] Example

[0070] Illustrative examples of the technology disclosed herein are provided below. Embodiments of the technology may include any one or more of the examples described below and any combination thereof.

[0071] Example 1: A test and measurement instrument comprising a digital-to-analog converter having an output sampling rate, configured to receive a digital sampling waveform and a reference clock and output an analog waveform at the sampling rate; a waveform synthesizer configured to receive an input waveform having a baud rate that is less than the sampling rate of the digital-to-analog converter by a non-integer rational number ratio and provide the digital sampling waveform; and a port configured to output the analog waveform.

[0072] Example 2 is the test and measurement instrument of Example 1, wherein the waveform synthesizer operates in real time.

[0073] Example 3 is a test and measurement instrument of any one of Examples 1 or 2, wherein the waveform synthesizer includes: a waveform copier configured to upsample an input waveform by an integer factor N, where N is greater than 1; a low-pass filter configured to receive the upsampled input waveform and remove waveform content above the Nyquist frequency of the digital-to-analog converter; and a downsampler configured to downsample the filtered upsampled input waveform to match the output sampling rate.

[0074] Example 4 is the test and measurement instrument of any of Examples 1-3, further comprising an analog low-pass filter configured to receive the analog signal and remove signal content above a first Nyquist zone of the digital-to-analog converter.

[0075] Example 5 is a test and measurement instrument of any one of Examples 1-4, wherein the waveform synthesizer includes: a waveform symbol clock generator, which is configured to receive a reference clock and output symbol transition events and symbol transition downsampling phases; and an edge interpolator, which is configured to receive an input waveform, symbol transition events, and symbol transition downsampling, and output a digital sampling waveform with a baud rate less than the sampling rate of the digital-to-analog converter at a rational ratio of the baud rate and the digital-to-analog sampling rate.

[0076] Example 6 is the test and measurement instrument of Example 5, wherein the edge interpolator is configured to interpolate a digital sampled waveform having a baud rate less than a sampling rate by linear edge interpolation with a constant slope.

[0077] Example 7 is the test and measurement instrument of Example 5, wherein the edge interpolator is configured to interpolate a digital sampled waveform having a baud rate less than a sampling rate by linear edge interpolation with a variable slope.

[0078] Example 8 is the test and measurement instrument of Example 5, wherein the edge interpolator includes an edge interpolator lookup table configured to receive an input signal and a sign transition downsampled phase, and output an interpolated edge signal.

[0079] Example 9 is the test and measurement instrument of Example 5, wherein the waveform-symbol clock generator is further configured to receive a waveform-symbol clock modulation signal.

[0080] Example 10 is a method for synthesizing a waveform, comprising converting a digital sampling waveform into an analog waveform at an output sampling rate through a digital-to-analog converter having the output sampling rate; receiving an input waveform having a baud rate; synthesizing a digital sampling waveform having a baud rate less than the sampling rate through a waveform synthesizer; and outputting the analog waveform to a device under test.

[0081] Example 11 is the method of Example 10, wherein synthesizing the digitally sampled waveform comprises synthesizing the digitally sampled waveform in real time.

[0082] Example 12 is a method of any of Examples 10 or 11, wherein synthesizing the waveform includes upsampling the input waveform by an integer factor N, where N is greater than 1; filtering the upsampled waveform to remove waveform content above the Nyquist frequency of the digital-to-analog converter; and downsampling the filtered upsampled input waveform to match a fixed output sampling rate.

[0083] Example 13 is the method of any of Examples 10-12, further comprising filtering the analog signal to remove signal content above a first Nyquist zone of the digital-to-analog converter before outputting the analog waveform.

[0084] Example 14 is the method of Examples 10-13, wherein synthesizing the waveform includes: generating a symbol transition event and a symbol transition downsampling phase based on a reference clock used by a digital-to-analog converter; and generating a digital sampling waveform having a baud rate less than a sampling rate of the digital-to-analog converter based on an input waveform, a symbol transition event, and a symbol transition downsampling phase.

[0085] Example 15 is the method of Example 14, wherein generating the digital sampled waveform comprises interpolating the digital sampled waveform having a baud rate less than the sampling rate by linear edge interpolation with a constant slope.

[0086] Example 16 is the method of Example 14, wherein generating the digital sampled waveform comprises interpolating the digital sampled waveform having a baud rate less than the sampling rate by linear edge interpolation with a variable slope.

[0087] Example 17 is the method of Example 14, wherein generating the digital sample waveform includes: selecting an edge signal based on an edge interpolator lookup table, the edge interpolator lookup table being configured to receive an input signal and a sign transition downsampled phase, and output an interpolated edge signal.

[0088] Example 18 is the method of Example 14, wherein generating the symbol transition events and the symbol transition downsampling phase is further based on a waveform symbol clock modulation signal.

[0089] Example 19 is one or more computer-readable storage media, which include instructions that, when executed by one or more processors of a test and measurement instrument, cause the test and measurement instrument to convert a digital sampled waveform into an analog waveform at the sampling rate through a digital-to-analog converter having an output sampling rate; receive an input waveform having a baud rate; synthesize a digital sampled waveform having a baud rate less than the sampling rate in real time through a waveform synthesizer; and output the analog waveform to a device under test.

[0090] Example 20 is one or more computer-readable storage media of Example 19, further comprising instructions for synthesizing the waveform by: upsampling the input waveform by an integer factor N, where N is greater than 1; filtering the upsampled waveform to remove waveform content above the Nyquist frequency of the digital-to-analog converter; and downsampling the filtered upsampled input waveform by an integer factor to obtain a desired output baud rate.

[0091] The previously described versions of the disclosed subject matter have many advantages that have been described or will be apparent to those of ordinary skill in the art. Even so, not all versions of the disclosed apparatus, system or method require these advantages or features.

[0092] Additionally, this written description also refers to specific features. It is to be understood that the disclosure in this specification includes all possible combinations of those specific features. Where a specific feature is disclosed in the context of a particular aspect or example, the feature may also be used as much as possible in the context of other aspects and examples.

[0093] Furthermore, when the present application refers to a method having two or more defined steps or operations, the defined steps or operations may be performed in any order or simultaneously, unless the context excludes those possibilities.

[0094] Although specific examples of the present invention have been illustrated and described for purposes of illustration, it will be appreciated that various modifications may be made without departing from the spirit and scope of the present invention. Accordingly, the present invention should not be limited, except as by the appended claims.

Claims

1. A test and measurement instrument comprising: a digital-to-analog converter having an output sampling rate, configured to receive a digital sampled waveform and a reference clock and output an analog waveform at the sampling rate; a waveform synthesizer configured to receive an input waveform having a baud rate less than a sampling rate of the digital-to-analog converter by a non-integer rational ratio and to provide the digital sampled waveform; as well as port, which is configured to output the analog waveform, wherein the waveform synthesizer operates in real time, and The waveform synthesizer comprises: a waveform copier configured to upsample the input waveform by an integer factor N, where N is greater than 1; a low pass filter configured to receive the upsampled input waveform and remove waveform content above the Nyquist frequency of the digital-to-analog converter; A downsampler is configured to downsample the filtered upsampled input waveform to match the output sampling rate.

2. The test and measurement instrument of claim 1 , further comprising an analog low pass filter configured to receive the analog waveform and remove signal content above a first Nyquist zone of the digital-to-analog converter.

3. A test and measurement instrument comprising: a digital-to-analog converter having an output sampling rate, configured to receive a digital sampled waveform and a reference clock and output an analog waveform at the sampling rate; a waveform synthesizer configured to receive an input waveform having a baud rate less than a sampling rate of the digital-to-analog converter by a non-integer rational ratio and to provide the digital sampled waveform; as well as port, which is configured to output the analog waveform, The waveform synthesizer comprises: a waveform symbol clock generator configured to receive the reference clock and output a symbol transition event and a symbol transition downsampled phase; as well as An edge interpolator is configured to receive the input waveform, the sign transition event, and the sign transition downsampling phase, and output a digital sampling waveform with a baud rate less than the sampling rate of the digital-to-analog converter at a rational ratio of the baud rate to the sampling rate of the digital-to-analog converter. 4 . The test and measurement instrument of claim 3 , wherein the edge interpolator is configured to interpolate a digital sampled waveform having a baud rate less than the sampling rate by linear edge interpolation with a constant slope. 5 . The test and measurement instrument of claim 3 , wherein the edge interpolator is configured to interpolate the digital sampled waveform having a baud rate less than the sampling rate by linear edge interpolation with a variable slope.

6. The test and measurement instrument of claim 3, wherein the edge interpolator comprises: An edge interpolator lookup table is configured to receive the input waveform and the sign transition downsampled phase and output an interpolated edge signal. 7 . The test and measurement instrument of claim 3 , wherein the waveform-symbol clock generator is further configured to receive a waveform-symbol clock modulation signal.

8. A method for synthesizing a waveform, comprising: converting the digital sampled waveform into an analog waveform at the sampling rate via a digital-to-analog converter having an output sampling rate; receiving an input waveform having a baud rate; synthesizing a digital sampling waveform with a baud rate lower than the sampling rate by a waveform synthesizer; outputting the analog waveform to the device under test, wherein synthesizing the digital sampling waveform comprises synthesizing the digital sampling waveform in real time, and Wherein synthesizing the waveform comprises: Upsampling the input waveform by an integer factor N, where N is greater than 1; filtering the upsampled waveform to remove waveform content above a Nyquist frequency of the digital-to-analog converter; The filtered upsampled input waveform is downsampled to match the fixed output sample rate.

9. The method of claim 8, further comprising filtering the analog waveform to remove signal content above a first Nyquist zone of the digital-to-analog converter before outputting the analog waveform.

10. A method for synthesizing a waveform, comprising: converting the digital sampled waveform into an analog waveform at the sampling rate via a digital-to-analog converter having an output sampling rate; receiving an input waveform having a baud rate; synthesizing a digital sampling waveform with a baud rate lower than the sampling rate by a waveform synthesizer; outputting the analog waveform to the device under test, Wherein synthesizing the waveform comprises: generating a symbol transition event and a symbol transition down-sampling phase based on a reference clock used by the digital-to-analog converter; as well as A digital sampling waveform having a baud rate less than a sampling rate of the digital-to-analog converter is generated based on the input waveform, the symbol transition events, and the symbol transition downsampling phase.

11. The method of claim 10, wherein generating the digital sampling waveform comprises interpolating a digital sampling waveform having a baud rate less than the sampling rate by linear edge interpolation with a constant slope.

12. The method of claim 10, wherein generating the digital sampling waveform comprises interpolating a digital sampling waveform having a baud rate less than the sampling rate by linear edge interpolation with a variable slope.

13. The method of claim 10, wherein generating the digital sample waveform comprises: An edge signal is selected based on an edge interpolator lookup table configured to receive the input waveform and the sign transition downsampled phase and output an interpolated edge signal.

14. The method of claim 10, wherein generating the symbol transition events and the symbol transition down-sampling phase is further based on a waveform symbol clock modulation signal.

15. One or more computer-readable storage media comprising instructions that, when executed by one or more processors of a test and measurement instrument, cause the test and measurement instrument to: converting the digital sampled waveform into an analog waveform at the sampling rate via a digital-to-analog converter having an output sampling rate; receiving an input waveform having a baud rate; synthesizing a digital sampling waveform with a baud rate lower than the sampling rate in real time by a waveform synthesizer; as well as Outputting the simulated waveform to the device under test further includes instructions for synthesizing the waveform by: Upsampling the input waveform by an integer factor N, where N is greater than 1; filtering the upsampled waveform to remove waveform content above a Nyquist frequency of the digital-to-analog converter; as well as Downsample the filtered, upsampled input waveform by an integer factor to achieve the desired output baud rate.

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