System and method for reconfigurable hybrid analog-to-digital converter (ADC)

Abstract

The invention relates to a system and method for a reconfigurable hybrid analog-to-digital converter (ADC). A system may include a first analog-to-digital converter (ADC) of a first type electrically coupled to a plurality of ADCs of a second type through a plurality of switches. The plurality of switches may be configured to select a number of ADCs of the second type from among the plurality of ADCs of the second type based on a rate of analog-to-digital conversion to supply the analog-to-digital conversion at the rate. The plurality of switches may be configured to selectively bypass the first ADC according to a resolution of the analog-to-digital conversion. The plurality of switches may be configured to bypass the first ADC in response to the resolution of the conversion being below a threshold.

Description

Technical Field

[0001] The present disclosure relates generally to systems and methods for analog-to-digital converters (ADCs), and more particularly to reconfiguring a hybrid ADC including different types of ADCs for multiple communication systems. Background Art

[0002] Applications in data communications (e.g., Ethernet applications) may provide ADCs that support multiple communication standards (e.g., 10 Gigabit Ethernet, 5 Gigabit Ethernet, 2.5 Gigabit Ethernet, 1 Gigabit Ethernet, etc.). In some cases, a dedicated ADC may be used for each communication mode (or standard), but multiple dedicated ADCs occupy a large area, and each dedicated ADC has poor versatility in communication applications. Moreover, multiple dedicated ADCs increase the number of intellectual property blocks (IP blocks), thereby incurring additional costs. An IP block refers to a reusable logic unit, unit, or integrated circuit layout design that belongs to a party's intellectual property. On the other hand, an ADC with the highest resolution and highest speed can be used to support multiple communication modes (or standards). However, in this case, the use of such a high-performance ADC will result in low power efficiency in some of the multiple communication modes that do not require such high performance. Summary of the invention

[0003] In one aspect, the present disclosure provides a system comprising: a first analog-to-digital converter (ADC) of a first type, the first ADC being electrically coupled to a plurality of ADCs of a second type through a plurality of switches, wherein the plurality of switches are configured to: select a certain number of ADCs of the second type from among the plurality of ADCs of the second type based on a rate of analog-to-digital conversion to supply the analog-to-digital conversion at the rate; and selectively bypass the first ADC according to a resolution of the analog-to-digital conversion, wherein the plurality of switches are configured to bypass the first ADC in response to the resolution of the conversion being below a threshold.

[0004] In another aspect, the present disclosure provides a method comprising: selecting a certain number of ADCs of a second type from among the plurality of ADCs of a second type based on a rate of analog-to-digital conversion to supply the analog-to-digital conversion at the rate by a plurality of switches coupling a first analog-to-digital converter (ADC) of a first type to a plurality of ADCs of a second type; bypassing the first ADC through the plurality of switches in response to a resolution of the analog-to-digital conversion being lower than a threshold; and connecting the first ADC to the selected number of ADCs of the second type through the plurality of switches in response to the resolution of the analog-to-digital conversion being greater than or equal to the threshold.

[0005] In another aspect, the present disclosure provides a system comprising: a plurality of analog-to-digital converters (ADCs) of a first type, the plurality of ADCs being electrically coupled to a plurality of switches, each ADC of the first type being electrically coupled to a plurality of ADCs of a second type through a corresponding switch, wherein each switch being configured to: select a certain number of ADCs of the second type from among the plurality of ADCs based on a rate of analog-to-digital conversion to supply the analog-to-digital conversion at the rate; and selectively bypass the corresponding ADCs of the first type according to a resolution of the analog-to-digital conversion, wherein each switch being configured to bypass the corresponding ADCs of the first type in response to the resolution of the conversion being lower than a first threshold.

[0006] In another aspect, the present disclosure provides an analog-to-digital converter (ADC) comprising: a plurality of hybrid ADCs in corresponding channels, each hybrid ADC including one or more ADCs of a first type and a plurality of ADCs of a second type, wherein a power efficiency of the ADCs of the second type is greater than a power efficiency of the ADCs of the first type; a controller configured to: determine a first number indicating the number of ADCs of the second type and a second number indicating the number of channels; control (1) the second number of hybrid ADCs among the plurality of hybrid ADCs in the second number of channels and (2) the first number of ADCs of the second type among the plurality of ADCs of the second type in each of the second number of channels to perform a first analog-to-digital conversion; in response to determining that a speed of the first analog-to-digital conversion is less than a first speed, control the second number of hybrid ADCs in the second number of channels and a third number of ADCs of the second type in each of the second number of channels to perform a second analog-to-digital conversion, the third number being greater than the first number; and in response to determining that the speed of the second analog-to-digital conversion is less than the first speed, control the fourth number of hybrid ADCs in the fourth number of channels and the third number of ADCs of the second type in each of the fourth number of channels to perform a third analog-to-digital conversion, the fourth number being greater than the second number. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by referring to the detailed description in conjunction with the accompanying drawings, in which like reference symbols always identify corresponding elements. In the drawings, like reference numerals generally indicate identical, functionally similar and / or structurally similar elements.

[0008] Figure 1 is a schematic block diagram of a reconfigurable hybrid ADC including different types of ADCs according to an embodiment.

[0009] Figure 2is a schematic block diagram of an exemplary reconfigurable hybrid ADC including a pipeline ADC and a successive approximation register (SAR) ADC according to an embodiment.

[0010] Figure 3 is a schematic block diagram of reconfiguring a hybrid ADC including different types of ADCs using a plurality of multiplexers according to an embodiment.

[0011] Figure 4 is a schematic block diagram of a reconfigurable multi-channel ADC according to an embodiment.

[0012] Figure 5 is a flow chart showing a process of reconfiguring a hybrid ADC including different types of ADCs according to an embodiment.

[0013] The details of various embodiments of the method and system are set forth in the accompanying drawings and the description below. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. Various components may be omitted in the embodiments and examples of the present disclosure without excluding the use of additional components in the embodiments. In addition, although the drawings and descriptions of the embodiments in the present disclosure may depict components as being directly connected or in direct electrical contact, this does not exclude the use of additional intermediate components in the embodiments. For example, in the following description, a first feature is formed on or on a second feature, which may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not essentially specify the relationship between the various embodiments and / or configurations discussed.

[0015] Various embodiments disclosed herein relate to a system. The system includes a first analog / digital converter (ADC) of a first type, which is electrically coupled to a plurality of ADCs of a second type through a plurality of switches. In some embodiments, the first ADC of the first type can be used as a first-stage ADC of the first type, and the plurality of ADCs of the second type can be used as a second-stage ADC of the second type. In some embodiments, each of the plurality of switches can be one or more transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), power transistors, bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), etc.), analog switches, silicon controlled rectifiers (SCRs), gate turn-off thyristors (GTOs), or any electronic switch that can change the conductivity of a path in a circuit between two states (e.g., on and off, closed and open, connected and disconnected). The plurality of switches can be configured to select a certain number of ADCs of the second type from the plurality of ADCs of the second type based on a rate of analog / digital conversion (e.g., a target rate of analog / digital conversion). In some embodiments, the selection can be performed so that the system can supply analog / digital conversion at a target rate. In some embodiments, the configuration of a component "configured to do X, Y, Z" may encompass hardware configuration, software configuration, firmware configuration, and combinations thereof, as well as configurations achieved through interaction with other components. For example, a switch plus other components with which the switch interacts directly or indirectly may result in the switch being configured to do X, Y, Z. In some embodiments, the rate of analog-to-digital conversion may be the speed of the analog-to-digital conversion, the sampling rate of the analog-to-digital conversion, or the number of readings, samples, or conversions of an analog signal completed per second.

[0016] In some embodiments, the plurality of switches may be configured to selectively bypass the first ADC based on a resolution of the analog-to-digital conversion. The plurality of switches may be configured to bypass the first ADC in response to the resolution of the conversion being below a threshold. For example, if the target resolution of the analog-to-digital conversion is low (e.g., below a threshold), then the one or more ADCs of the second type may achieve the target resolution without using the first ADC of the first type. In this case, the first ADC of the first type may be turned off or deactivated or disconnected from the ADC of the second type, and the input analog signal may be provided directly to the one or more ADCs of the second type, thereby bypassing the first ADC of the first type.

[0017] In some embodiments, the first ADC of the first type may include a multiplying digital-to-analog converter (MDAC).The first type of ADC may be different from the second type of ADC.

[0018] In some embodiments, the plurality of ADCs of the second type may include time-interleaved successive approximation register (SAR) ADCs. In some embodiments, the selected number of ADCs of the second type increases as the rate of analog-to-digital conversion increases.

[0019] In some embodiments, the plurality of switches may include a plurality of multiplexers electrically coupled to the plurality of ADCs of the second type, respectively. Each multiplexer may be configured to selectively bypass the first ADC in response to a resolution of the conversion being below a threshold.

[0020] In some embodiments, in response to receiving an input signal, the first ADC may be configured to convert the input signal into a first digital signal (e.g., a coarse digital signal) and output an analog signal (e.g., an analog residual signal from the input signal minus the coarse digital signal). In response to receiving the analog signal, the second type of multiple ADCs may be configured to convert the analog signal into a second digital signal (e.g., a digital signal different from the first digital signal).

[0021] Various embodiments disclosed herein relate to a method. The method includes selecting a certain number of ADCs of a second type from among a plurality of ADCs of a second type based on a rate of analog-to-digital conversion (e.g., a target rate of analog-to-digital conversion) by coupling a first analog-to-digital converter (ADC) of a first type to a plurality of ADCs of a second type through a plurality of switches. In some embodiments, a first ADC of the first type may be used as a first-stage ADC of the first type, and a plurality of ADCs of the second type may be used as a second-stage ADC of the second type. In some embodiments, the selection may be performed so that the system can provide the target rate of analog-to-digital conversion. The method may include bypassing the first ADC through a plurality of switches in response to a resolution of the analog-to-digital conversion being below a threshold. The method may include connecting the first ADC to a selected number of ADCs of the second type through a plurality of switches in response to a resolution of the analog-to-digital conversion being greater than or equal to the threshold.

[0022] In some embodiments, the first ADC of the first type may include a multiplying digital-to-analog converter (MDAC).The first type of ADC may be different from the second type of ADC.

[0023] In some embodiments, the plurality of ADCs of the second type may include time-interleaved successive approximation register (SAR) ADCs. In some embodiments, the selected number of ADCs of the second type increases as the rate of analog-to-digital conversion increases.

[0024] In some embodiments, the plurality of switches may include a plurality of multiplexers electrically coupled to the plurality of ADCs of the second type, respectively. When bypassing the first ADC, in response to a resolution of the analog-to-digital conversion being below a threshold, each multiplexer may bypass the first ADC. When connecting the first ADC to a selected number of ADCs of the second type, in response to a resolution of the analog-to-digital conversion being greater than or equal to the threshold, the plurality of multiplexers may connect the first ADC to a selected number of ADCs of the second type.

[0025] In some embodiments, in response to receiving an input signal, the first ADC may convert the input signal into a first digital signal (e.g., a coarse digital signal) and output an analog signal (e.g., an analog residual signal from the input signal minus the coarse digital signal). In response to receiving the analog signal, the second type of multiple ADCs may convert the analog signal into a second digital signal (e.g., a digital signal different from the first digital signal).

[0026] Various embodiments disclosed herein relate to a system. The system includes a plurality of analog-to-digital converters (ADCs) of a first type electrically coupled to a plurality of switches, each ADC of the first type being electrically coupled to a plurality of ADCs of a second type through a corresponding switch. Each switch may be configured to select a certain number of ADCs of a second type from among the plurality of ADCs based on a rate of analog-to-digital conversion to provide analog-to-digital conversion at a rate. Each switch may be configured to selectively bypass a corresponding ADC of the first type based on a resolution of the analog-to-digital conversion. Each switch may be configured to bypass a corresponding ADC of the first type in response to a resolution of the conversion being below a first threshold.

[0027] In some embodiments, each ADC of the first type comprises a multiplying digital-to-analog converter (MDAC). In some embodiments, the plurality of ADCs of the second type may comprise a time-interleaved successive approximation register (SAR) ADC. In some embodiments, the selected number of ADCs of the second type may increase as the rate of analog-to-digital conversion increases.

[0028] In some embodiments, each switch may include a plurality of multiplexers electrically coupled to a plurality of ADCs of the second type, respectively. Each multiplexer may be configured to selectively bypass a corresponding ADC of the first type in response to a resolution of the conversion being below a threshold. In some embodiments, the system may include a plurality of ADCs of a third type electrically coupled to the plurality of ADCs of the first type, respectively, and a plurality of additional switches electrically coupled to the plurality of ADCs of the third type, respectively. Each additional switch may be configured to selectively bypass a corresponding ADC of the third type according to a resolution of the analog-to-digital conversion. Each additional switch may be configured to bypass a corresponding ADC of the third type in response to a resolution of the conversion being below a second threshold greater than the first threshold.

[0029] In some embodiments, the system may include a controller configured to determine a certain number of switches among a plurality of switches, the switches respectively connecting a selected number of ADCs of the second type. The controller may determine a first rate of analog / digital conversion because a certain number of switches of the selected number of ADCs of the second type are respectively connected. The controller may determine whether the first rate of analog / digital conversion is less than the rate of analog / digital conversion. In response to determining that the first rate of analog / digital conversion is less than the rate of analog / digital conversion, the controller may increase the selected number of ADCs of the second type to a second number of ADCs of the second type. The controller may determine a second rate of analog / digital conversion because a certain number of switches of the second number of ADCs of the second type are respectively connected. The controller may determine whether the second rate of analog / digital conversion is less than the rate of analog / digital conversion. In response to determining that the second rate of analog / digital conversion is less than the rate of analog / digital conversion, the controller may increase a certain number of switches to the second number of switches. The controller may control the second number of switches to respectively connect a second number of ADCs of the second type.

[0030] Various embodiments disclosed herein relate to an analog-to-digital converter (ADC). The ADC may include a plurality of hybrid ADCs in corresponding channels and a controller. Each of the plurality of hybrid ADCs may include one or more ADCs of a first type and a plurality of ADCs of a second type. The power efficiency of the second type of ADC may be greater than the power efficiency of the first type of ADC. The controller may be configured to determine a first number indicating the number of ADCs of the second type and a second number indicating the number of channels. The controller may be configured to control (1) a second number of hybrid ADCs among the plurality of hybrid ADCs in a second number of channels and (2) a first number of ADCs of the second type among the plurality of ADCs of the second type in each of the second number of channels to perform a first analog-to-digital conversion. In response to determining that a speed of the first analog-to-digital conversion is less than the first speed, the controller may be configured to control a second number of hybrid ADCs in the second number of channels and a third number of ADCs of the second type in each of the second number of channels to perform a second analog-to-digital conversion, the third number being greater than the first number. In response to determining that the speed of the second analog-to-digital conversion is less than the first speed, the controller may be configured to control a fourth number of hybrid ADCs in a fourth number of channels and a third number of ADCs of the second type in each of the fourth number of channels to perform a third analog-to-digital conversion, the fourth number being greater than the second number.

[0031] In one aspect, an application in data communication (e.g., an Ethernet application or receiver for a communication system) may provide an ADC capable of supporting multiple communication standards. In some cases, a dedicated ADC may be used for each communication mode (or standard), but multiple dedicated ADCs may occupy a large area, and each dedicated ADC may have poor versatility in communication applications. Moreover, multiple dedicated ADCs may increase the number of intellectual property blocks (IP blocks), thereby incurring additional costs. On the other hand, an ADC with the highest resolution and highest speed may be used to support multiple communication modes (or standards). However, in this case, the use of such a high-performance ADC may result in low power efficiency in some of the multiple communication modes that do not require such high performance.

[0032] To address this problem, according to certain aspects, embodiments in the present disclosure relate to a technique for achieving greater power efficiency in a multi-standard communication system via a reconfigurable architecture of a hybrid ADC that includes different types of ADCs. In some embodiments, the reconfigurable architecture may allow the hybrid ADC to have different configurations (e.g., different types of ADCs or different numbers of active ADCs) to support different communication modes or standards. In this way, the ADC with the highest resolution and highest conversion rate may not be used for all communication modes, thereby achieving greater power efficiency. Moreover, a single hybrid ADC may be used to support different communication modes or standards, thereby reducing the number of IP blocks, promoting IP block reuse, and simplifying analog / digital interfaces and software-hardware co-design. For example, using a single hybrid ADC may avoid multiple dedicated IP blocks for different communication modes.

[0033] In some embodiments, the reconfigurable ADC may include an ADC of a first type in a first stage, a plurality of ADCs of a second type in a second stage, a plurality of first switches electrically coupled between the ADC of the first type and the plurality of ADCs of the second type, a plurality of second switches electrically coupled to the plurality of ADCs of the second type, a circuit (e.g., an alignment and correction circuit) configured to perform alignment and correction, and / or a controller. The ADC of the first type may receive a first analog signal and convert the first analog signal into a first digital signal as a most significant bit (MSB). The first ADC may output a second analog signal to the plurality of first switches based on the first analog signal and the first digital signal. The plurality of first switches may select one or more ADCs of the second type and provide the second analog signal to the selected one or more ADCs of the second type. The selected one or more ADCs may convert the second analog signal into one or more digital signals as a least significant bit (LSB). The alignment and correction circuit may receive the first digital signal and the one or more digital signals (as LSB) as uncorrected output digital signals, perform alignment and / or correction of the uncorrected output digital signals, and output a corrected output digital signal. The controller may be any circuit, hardware or processor (e.g., a microprocessor) capable of controlling each of the first type of ADC and / or the second type of multiple ADCs to be turned on or off (or powered on or off) individually and / or individually. The controller may be any circuit, hardware or processor (e.g., a microprocessor) capable of controlling each of the plurality of first switches and / or each of the plurality of second switches to be turned on or off or connected (closed) or disconnected (disconnected). In some embodiments, the controller may control each of the first type of ADC and / or the second type of multiple ADCs to process only a portion (e.g., 8 bits) of the maximum bits (e.g., 11 bits) supported by the ADC. In some embodiments, the controller may receive an input signal indicating the desired (or target) resolution of the output of the hybrid ADC and / or an input signal indicating the desired (or target) speed (or conversion rate or sampling rate) of the hybrid ADC. The controller may generate one or more control signals based on the input signal to control at least one of the following: the first type of ADC; each of the second type of multiple ADCs; each of the plurality of first switches; or each of the plurality of second switches.

[0034] In some embodiments, the plurality of second switches may select one or more ADCs of the second type and provide the first analog signal to the selected one or more ADCs of the second type. The selected one or more ADCs may convert the first analog signal to one or more digital signals as the least significant bits. The alignment and correction circuit may receive the one or more digital signals as uncorrected output digital signals, perform alignment and / or correction of the uncorrected output digital signals, and output corrected output digital signals.

[0035] In some embodiments, the first type of ADC may be one or more flash ADCs, one or more pipeline ADCs (e.g., a pipeline ADC including a multiplying digital / analog converter (MDAC)), one or more SAR ADCs, or any circuit, hardware, microprocessor capable of converting an analog signal into a digital signal. Similarly, the second type of ADC may include one or more flash ADCs, one or more pipeline ADCs (e.g., a pipeline ADC including an MDAC), one or more SAR ADCs, or any circuit, hardware, microprocessor capable of converting an analog signal into a digital signal. The first type of ADC may be an ADC of a different type than the second type of ADC. The alignment and correction circuit may be any circuit or hardware or microprocessor capable of performing alignment and / or correction of the output signal of the ADC. For example, the alignment and correction circuit may perform timing alignment and bit alignment and correction. For timing alignment, digital bits from different stages may be aligned within the same clock cycle. For bit alignment and correction, the output (digital) signal of the ADC is right-aligned so that the LSB of the register and the LSB of the output signal are aligned, or the output signal can be left-aligned so that the MSB of the register and the MSB of the output signal are aligned. The alignment and correction circuit can perform correction of the output (digital) signal of the ADC to correct errors (e.g., quantization error, offset error, gain error, nonlinearity, etc.) of the output signal.

[0036] In some embodiments, the first type of ADC in the first stage may be a pipeline ADC including an MDAC (e.g., a ping-pong type MDAC) and a coarse ADC (e.g., an ADC configured to generate a coarse bit such as an MSB). The MDAC may include a DAC, a sample and hold (S / H) circuit, a subtractor circuit, and / or an amplifier with a gain (e.g., a gain K). The coarse ADC may be a flash ADC or any circuit or hardware capable of converting an analog signal to a digital signal. The DAC may be any circuit or hardware capable of converting a digital signal to an analog signal. In some embodiments, the ping-pong type MDAC may include an S / H circuit configured to perform double sampling (e.g., ping-pong sampling) such that sampling of one sampled input signal occurs during a holding phase of another sampled input signal. For example, assuming that the number of MSBs is three (e.g., 3-bit MSBs), the S / H circuit may sample and hold the first analog signal stable, while the coarse ADC quantizes the first analog signal into three bits. The 3-bit output signal may be provided to the alignment and correction circuit as the first digital signal (MSB). The 3-bit output signal may then be provided to a DAC that converts the 3-bit output signal to an analog output signal. The subtractor circuit may subtract the analog output signal from the first analog signal to generate a residual signal (e.g., an analog residual signal). The amplifier may amplify the residual signal by a factor "K" and provide the amplified residual signal (as a second analog signal) to a second stage (e.g., to a plurality of first switches).

[0037] In some embodiments, the plurality of ADCs of the second type in the second stage may be time-interleaved SAR ADCs. Based on different requirements for ADC resolution and / or speed (e.g., conversion rate or sampling rate), the ADCs of the first type in the first stage and each SAR ADC in the second stage may be selectively activated or used or turned on (via the plurality of first switches and / or the plurality of second switches). For example, the plurality of first switches may be individually and / or individually powered on or off to select one or more ADCs of the second type and provide the second analog signal to the selected one or more ADCs of the second type. In some embodiments, the plurality of second switches may be individually and / or individually turned on or off to select one or more ADCs of the second type and provide the first analog signal to the selected one or more ADCs of the second type. In this way, the hybrid ADC may be configured (or reconfigured) to different architectures (e.g., in terms of resolution and / or speed) to meet a variety of communication standards while achieving greater power efficiency.

[0038] For example, assume that the ADC of the first type in the first stage is a pipeline ADC including a ping-pong type MDAC configured to process 3-bit data (referred to as a "ping-pong type 2.5-bit MDAC" because the LSB in the 3-bit data is aligned with the MSB in the 11-bit data), and each of the ADCs of the second type in the second stage (for a corresponding lane) is a SAR ADC configured to process 11-bit data (referred to as a "lane of 11-bit SAR ADC"). The hybrid ADC may be configured (or reconfigured) as in the following example.

[0039] Example 1: For 10 Gigabit Ethernet mode, the hybrid ADC can be configured as an ADC to support 13-bit data resolution and 800 MHz speed by: (1) turning on the ping-pong type 2.5-bit MDAC; and (2) turning on the 11-bit SAR ADC of 2 channels.

[0040] Example 2: For 5 Gigabit Ethernet mode, the hybrid ADC can be configured as an ADC to support 11-bit data resolution and 800 MHz speed by: (1) turning off the ping-pong type 2.5-bit MDAC; and (2) turning on the 11-bit SAR ADC of 2 channels.

[0041] Example 3: For 2.5 Gigabit Ethernet mode, the hybrid ADC can be configured as an ADC to support 11-bit data resolution and 400 MHz speed by: (1) turning off the ping-pong type 2.5-bit MDAC; and (2) turning on 1 channel of the 11-bit SAR ADC.

[0042] Example 4: For 1 Gigabit Ethernet mode, the hybrid ADC can be configured as an ADC to support 8-bit data resolution and 125 MHz speed by: (1) turning off the ping-pong 2.5-bit MDAC; (2) turning on the 11-bit SAR ADC of 1 channel; and (3) (re)configuring the SAR ADC as an 8-bit SAR ADC by disabling 3 of the 11 bits (so that the SAR ADC can only use 8 bits and stop using the remaining 3 bits).

[0043] Examples 1 to 4 show that the hybrid ADC can be configured (or reconfigured) according to a desired resolution or target resolution and a desired speed or target speed. As shown in Example 2, in some embodiments, in response to receiving an input signal indicating a target resolution (e.g., 11 bits) below a threshold (e.g., an effective number of bits (ENOB) of 12 bits or 10 bits), the controller can generate a control signal to control the plurality of first switches to be turned off (or disconnected). In response to receiving an input signal indicating a target speed (e.g., 800 MHz), the controller can generate a control signal to select and turn on two switches from among the plurality of second switches, so that the 11-bit SAR ADC of the 2 channels can be turned on.

[0044] As shown in Example 3, in some embodiments, in response to receiving an input signal indicating a target resolution (e.g., 11 bits) below a threshold (e.g., ENOB of 12 bits or 10 bits), the controller may generate a control signal to control a plurality of first switches to be turned off (or disconnected). In response to receiving an input signal indicating a target speed (e.g., 400 MHz), the controller may generate a control signal to select and turn on one switch from among a plurality of second switches so that an 11-bit SAR ADC of 1 channel may be turned on or used. The controller may generate a control signal so that the greater the target speed, the more channels (or SAR ADCs) are turned on or used, or so that there is a linear relationship between the target speed and the number of channels.

[0045] As shown in Example 4, in some embodiments, in response to receiving an input signal indicating a target resolution (e.g., 8 bits) that is lower than a threshold value (e.g., ENOB of 12 bits or 10 bits), the controller may generate a control signal to control the plurality of first switches to be turned off (or disconnected). In response to receiving an input signal indicating a target speed (e.g., 125 MHz), the controller may generate a control signal to select and turn on one switch from among the plurality of second switches so that an 11-bit SAR ADC of 1 channel may be turned on or used. In response to determining that the target resolution (e.g., 8 bits) is less than the maximum resolution (e.g., 11 bits) supported by each of the plurality of ADCs of the second type (e.g., SAR ADC), the controller may generate one or more control signals to disable 3 of the 11 bits of the SAR ADC (so that the SAR ADC may use only 8 bits and stop using the remaining 3 bits).

[0046] SAR ADCs are typically power efficient, but can only provide moderate resolution (<=10-bit ENOB) without additional trimming due to device matching limitations. To support higher speeds (e.g., conversion rates or sampling rates), SAR ADCs can use more time-interleaved channels, which means more complex layout and digital correction. Meanwhile, pipeline ADCs (e.g., ADCs including ping-pong MDACs) can achieve high resolution (>10-bit ENOB) with high speed while having moderate power efficiency. Using a pipeline ADC can minimize time-interleaved channels to simplify layout and digital correction, thereby achieving higher speed. As shown in Examples 1 to 4, by powering on or off the ADC in the first stage (through multiple second switches) or each SAR ADC in the second stage (through multiple second switches), the hybrid ADC can be configured in different styles to meet different requirements for ADC resolution and speed, thereby achieving greater power efficiency. Such a hybrid ADC can also minimize time-interleaved channels or paths.

[0047] In some embodiments, the plurality of first switches and the plurality of second switches may include a plurality of T-switches or multiplexers to achieve good path-to-path isolation. In some embodiments, each multiplexer may have two inputs configured to receive a first analog signal and a second analog signal, respectively. Each multiplexer may selectively output a first analog signal or a second analog signal according to a selection signal. For example, in response to receiving a selection signal indicating a first value (e.g., "0"), one or more multiplexers (among a plurality of multiplexers) may be selected to provide the second analog signal to a corresponding one or more ADCs of the second type. On the other hand, in response to receiving a selection signal indicating a second value (e.g., "1"), one or more multiplexers (among a plurality of multiplexers) may be selected to provide the first analog signal to a corresponding one or more ADCs of the second type.

[0048] In some embodiments, the reconfigurable multi-channel ADC may include a plurality of hybrid ADCs in corresponding channels, circuits configured to perform alignment and correction (e.g., alignment and correction circuits), and / or controllers. Each hybrid ADC may include an ADC of a first type in a second stage, a plurality of ADCs of a second type in a third stage, and a plurality of switches electrically coupled between the ADC of the first type and the plurality of ADCs of the second type or electrically coupled to the plurality of ADCs of the second type, respectively. Each hybrid ADC may also include an ADC of a third type in a first stage and a third switch electrically coupled to the first type ADC.

[0049] Each hybrid ADC may receive a first analog signal and selectively provide the first analog signal (1) to a third type ADC in the first stage or (2) to a first type ADC in the second stage through a third switch. In response to receiving the first analog signal, the third type ADC in the first stage may convert the first analog signal into a first digital signal (e.g., a 2-bit digital signal), and output a second analog signal (residual signal) and the first digital signal to the first type ADC in the second stage based on the first analog signal and the first digital signal. In response to receiving the second analog signal and the first digital signal, the first type ADC in the second stage may convert the second analog signal into a second digital signal (e.g., a 3-bit digital signal), and combine the first digital signal with the second digital signal (e.g., excluding overlapping bits) to output an MSB output digital signal of the hybrid ADC (e.g., a 4-bit digital signal). The first type ADC in the second stage may output a third analog signal (residual signal) to one or more ADCs selected from a plurality of second type ADCs in the third stage based on the second analog signal and the second digital signal. The selected one or more ADCs may convert the third analog signal into one or more digital signals as the LSB output digital signal of the hybrid ADC.

[0050] In response to the ADC of the first type in the second stage receiving the first analog signal, the ADC of the first type in the second stage and the plurality of ADCs of the second type in the third stage may generate an MSB output digital signal and an LSB output digital signal of the hybrid ADC in a manner similar to the two-stage hybrid ADC described above. The alignment and correction circuit may receive the MSB output digital signal and the LSB output digital signal from each hybrid ADC as an uncorrected output digital signal, perform alignment and / or correction of the uncorrected output digital signal, and output a corrected output digital signal.

[0051] The controller may be any circuit, hardware or processor (e.g., a microprocessor) capable of controlling each of the third type of ADC (in the first stage), the first type of ADC (in the second stage), and the plurality of ADCs of the second type (in the third stage) to be individually and / or separately turned on or off (or powered on or off). The controller may be any circuit, hardware or processor (e.g., a microprocessor) capable of controlling each of the plurality of first switches, each of the plurality of second switches, and / or each third switch to be turned on or off or connected (closed) or disconnected (disconnected). In some embodiments, the controller may control the first type of ADC, each of the plurality of second types of ADCs, and / or the third type of ADC to use or process only a portion (e.g., 8 bits) of the maximum bits (e.g., 11 bits) supported by the ADC. In some embodiments, the controller may receive an input signal indicating a desired (or target) resolution of the output of the hybrid ADC and / or an input signal indicating a desired (or target) speed (or conversion rate or sampling rate) of the hybrid ADC. The controller may generate one or more control signals based on the input signal to control at least one of: a first type of ADC; each of a plurality of ADCs of a second type; a third type of ADC; each of a plurality of first switches; each of a plurality of second switches; or each third switch.

[0052] In some embodiments, the third type of ADC may be one or more flash ADCs, one or more pipeline ADCs (e.g., a pipeline ADC including a multiplying digital-to-analog converter (MDAC)), one or more SAR ADCs, or any circuit, hardware, microprocessor capable of converting an analog signal into a digital signal. The third type of ADC may be the same as the first type of ADC. The third type of ADC may be different from the second type of ADC.

[0053] In some embodiments, the reconfigurable multi-channel ADC may include ADCs in three stages (a first stage, a second stage, and a third stage). For example, a third type of ADC may be used as an ADC in the first stage, a first type of ADC may be used as an ADC in the second stage, and multiple ADCs of the second type may be used as ADCs in the third stage. If the ADCs in the first and second stages are pipeline ADCs including ping-pong type MDACs, and the ADC in the third stage is a SAR ADC, the reconfigurable multi-channel ADC may increase the speed of analog-to-digital conversion by increasing the number of channels. The reconfigurable multi-channel ADC may increase the resolution or accuracy of the analog-to-digital conversion by turning on one or more ADCs in the third stage. For higher speed (or higher sampling rate) applications, the reconfigurable multi-channel ADC may (1) increase the number of paths in the third stage, or (2) increase the number of channels. In some embodiments, the reconfigurable multi-channel ADC may first increase the number of SAR ADC paths in the third stage, determine whether the speed of the conversion meets the target speed, and increase the number of channels in response to determining that the speed of the conversion does not meet the target speed. The reconfigurable multi-channel ADC can first increase the number of lanes in the third stage, and then increase the number of channels to meet the target speed because the SAR ADC has great power efficiency and the ADCs in the first and second stages (e.g., pipeline ADCs) have less time interleaving between channels. For higher ADC resolution applications, the reconfigurable multi-channel ADC can configure the first stage to process higher bits (usually <= 4 bits) or add more stages (e.g., the second stage). At the same time, based on different requirements for ADC resolution and speed, each of the first, second, and third stages (e.g., SAR ADCs) can be powered on or off individually and / or individually. Therefore, the reconfigurable multi-channel ADC can be configured as different architectures to meet multi-standard communications with greater power efficiency.

[0054] The embodiments of the present disclosure have at least the following advantages and benefits. First, the embodiments of the present disclosure may provide useful techniques for reconfiguring a hybrid ADC to have different configurations (e.g., different types of ADCs or different numbers of active ADCs) to support different communication modes or standards with high power efficiency. In this way, the ADC with the highest resolution and the highest conversion rate may not be used for all communication modes, thereby achieving greater power efficiency. The reconfigurable hybrid ADC may achieve different ADC resolutions and different sampling rates while maintaining high power efficiency.

[0055] Second, embodiments of the present disclosure may provide useful techniques for a single hybrid ADC to support different communication modes or standards, thereby reducing the number of IP blocks, promoting IP block reuse, and simplifying analog-digital interfaces and hardware-software co-design. For example, using a single hybrid ADC may avoid many dedicated IP blocks for different communication modes.

[0056] Third, the embodiments of the present disclosure may provide useful techniques for implementing a multi-standard communication system or any product that may be more versatile in terms of communication standards or modes, reduce the number of IP blocks, promote IP block reuse, and / or simplify analog-digital interfaces and hardware-software co-design.

[0057] Figure 1 1 is a schematic block diagram of a reconfigurable hybrid ADC 1000 including different types of ADCs according to an embodiment. The reconfigurable ADC 1000 may include: an ADC 110-1 of a first type in a first stage 110; a plurality of ADCs 120-0, ..., 120-n of a second type in a second stage 120; a plurality of first switches (S0a, ..., Sna) 121-0, ..., 121-n electrically coupled between the ADC 110-1 of the first type and the plurality of ADCs 120-0, ..., 120-n of the second type; a plurality of second switches (S0b, ..., Snb) 122-0, ..., 122-n electrically coupled to the plurality of ADCs 120-0, ..., 120-n of the second type, respectively; a circuit configured to perform alignment and correction (e.g., alignment and correction circuit 150); and / or a controller 190.

[0058] refer to Figure 1, the first type of ADC 110-1 may receive the first analog signal 101 and convert the first analog signal 101 into a first digital signal 141 as the most significant bit (MSB). The first ADC 110-1 may output a second analog signal (e.g., a residual signal) 103 to the plurality of first switches 121-0, ..., 121-n based on the first analog signal 101 and the first digital signal 141. The plurality of first switches 121-0, ..., 121-n may select one or more ADCs of the second type (e.g., two ADCs 120-0 and ADC 120-1) and provide the second analog signal 103 to the selected one or more ADCs of the second type. The selected one or more ADCs 120-0, 120-1 may convert the second analog signal 103 into one or more digital signals (LSBs0 and LSBs1) 142-0, 142-1 (from LSBs0 (142-0), ..., LSBsn (142-n)) as the least significant bit (LSB). The alignment and correction circuit 150 may receive the first digital signal 141 and the one or more digital signals (as LSBs) 142-0, 142-1 as uncorrected output digital signals, perform alignment and / or correction of the uncorrected output digital signals, and output a corrected output digital signal (Dout) 160.

[0059] refer to Figure 1 , the plurality of second switches 122-0, ..., 122-n may select one or more ADCs of the second type (e.g., two ADCs 120-0 and ADC 120-1), and provide the first analog signal 101 to the selected one or more ADCs of the second type. The selected one or more ADCs 120-0, 120-1 may convert the first analog signal 101 into one or more digital signals (LSBs0 and LSBs1) 142-0, 142-1. The alignment and correction circuit 150 may receive the one or more digital signals 142-0, 142-1 as uncorrected output digital signals, perform alignment and / or correction of the uncorrected output digital signals, and output a corrected output digital signal 160.

[0060] refer to Figure 1The controller 190 may be any circuit, hardware or processor (e.g., a microprocessor) capable of controlling the first type ADC 110-1 and / or each of the plurality of ADCs 120-0, ..., 120-n of the second type to be individually and / or separately turned on or off (or powered on or off) and capable of controlling each of the plurality of first switches 121-0, ..., 121-n and / or each of the plurality of second switches 122-0, ..., 122-n to be turned on or off or connected (closed) or disconnected (disconnected). The controller 190 may control each of the first type ADC and / or the plurality of ADCs of the second type to use or process only a portion (e.g., 8 bits) of the maximum bits (e.g., 11 bits) supported by the ADC. The controller 190 may receive an input signal (Res-sig) 191 indicating a desired (or target) resolution of the output of the hybrid ADC 1000 and / or an input signal (Spe_sig) 192 indicating a desired (or target) speed (or conversion rate or sampling rate) of the hybrid ADC 1000. The controller 190 may generate one or more control signals 195 based on the input signals 191, 192 to control at least one of: the first type of ADC 110-1; each of the plurality of ADCs 120-0, ..., 120-n of the second type; each of the plurality of first switches 121-0, ..., 121-n; and / or each of the plurality of second switches 122-0, ..., 122-n.

[0061] refer to Figure 1 , the first type of ADC 110-1 may be one or more flash ADCs, one or more pipeline ADCs (e.g., a pipeline ADC including a multiplying digital-to-analog converter (MDAC)), one or more SAR ADCs, or any circuit, hardware, or microprocessor that can convert an analog signal into a digital signal. Similarly, the second type of ADC 120-0, ..., or 120-n may include one or more flash ADCs, one or more pipeline ADCs (e.g., a pipeline ADC including an MDAC), one or more SAR ADCs, or any circuit, hardware, or microprocessor that can convert an analog signal into a digital signal. The first type of ADC may be different from the second type of ADC.

[0062] refer to Figure 1The alignment and correction circuit 150 may be any circuit or hardware or microprocessor capable of performing alignment and / or correction of the output signal of the ADC. For example, the alignment and correction circuit may perform right alignment of the output (digital) signal of the ADC so that the LSB of a register (not shown) and the LSB of the output signal are aligned, or may perform left alignment of the output signal so that the MSB of the register and the MSB of the output signal are aligned. The alignment and correction circuit 150 may perform correction of the output (digital) signal of the ADC to correct errors (e.g., quantization error, offset error, gain error, nonlinearity, etc.) of the output signal.

[0063] Figure 2 2 is a schematic block diagram of an exemplary reconfigurable hybrid ADC 2000 including a pipeline ADC and a successive approximation register (SAR) ADC according to an embodiment. The reconfigurable hybrid ADC 2000 may have a configuration similar to that of the reconfigurable hybrid ADC 1000. For example, the reconfigurable ADC 2000 may include: an ADC 210-1 of the first type in the first stage 210; multiple ADCs 220-0, ..., 220-n of the second type in the second stage 120; multiple first switches (S0a, ..., Sna) 221-0, ..., 221-n (collectively referred to as first switches 221) electrically coupled between the first type ADC 210-1 and the multiple ADCs 220-0, ..., 220-n of the second type; multiple second switches (S0b, ..., Snb) 222-0, ..., 222-n (collectively referred to as second switches 222) electrically coupled to the multiple ADCs 220-0, ..., 220-n of the second type, respectively; a circuit configured to perform alignment and correction (for example, the alignment and correction circuit 250); and / or a controller 290.

[0064] refer to Figure 2, the first type of ADC 210-1 may receive the first analog signal 201 and convert the first analog signal 201 into a first digital signal 241 as the MSB. The first ADC 210-1 may output a second analog signal (e.g., a residual signal) 203 to a plurality of first switches 221-0, ..., 221-n based on the first analog signal 201 and the first digital signal 241. The plurality of first switches 221-0, ..., 221-n may select one or more ADCs of the second type (e.g., two ADCs 220-0 and ADC 220-1) and provide the second analog signal 203 to the selected one or more ADCs of the second type. The selected one or more ADCs 220-0, 220-1 may convert the second analog signal 203 into one or more digital signals (LSBs0 and LSBs1) 242-0, 242-1 (from LSBs0 (242-0), ..., LSBsn (242-n)) as the LSB. The alignment and correction circuit 250 may receive the first digital signal 241 and one or more digital signals (as LSBs) 242-0, 242-1 as uncorrected output digital signals, perform alignment and / or correction of the uncorrected output digital signals, and output a corrected output digital signal (Dout) 260. The plurality of second switches 222-0, ..., 222-n may select one or more ADCs of a second type (e.g., two ADCs 220-0 and ADC 220-1) and provide the first analog signal 201 to the selected one or more ADCs of the second type. The selected one or more ADCs 220-0, 220-1 may convert the first analog signal 201 into one or more digital signals (LSBs0 and LSBs1) 242-0, 242-1. The alignment and correction circuit 250 may receive one or more digital signals 242-0, 242-1 as uncorrected output digital signals, perform alignment and / or correction of the uncorrected output digital signals, and output a corrected output digital signal 260. The controller 190 may generate one or more control signals 295 based on the input signals 291, 292 to control at least one of: the first type of ADC 210-1; each of the plurality of ADCs 220-0, ..., 220-n of the second type; each of the plurality of first switches 221-0, ..., 221-n; and / or each of the plurality of second switches 222-0, ..., 222-n.

[0065] refer to Figure 2, the first type of ADC in the first stage 210 may be a pipeline ADC 210-1 including an MDAC (e.g., a ping-pong type MDAC 215) and a coarse ADC 212. The MDAC 215 may include a DAC 216, a sample and hold (S / H) circuit 217, a subtractor circuit 218, and / or an amplifier 219 with a gain (e.g., a gain K). The coarse ADC 212 may be a flash ADC or any circuit or hardware capable of converting an analog signal to a digital signal. The DAC 216 may be any circuit or hardware capable of converting a digital signal to an analog signal. In some embodiments, the ping-pong type MDAC 215 may include an S / H circuit 217 configured to perform double sampling (e.g., ping-pong sampling) such that sampling of one sampled input signal occurs during a holding phase of another sampled input signal. For example, assuming that the number of MSBs is three (e.g., 3-bit MSBs), the S / H circuit 217 can sample and stabilize the first analog signal 201, while the coarse ADC 212 quantizes the first analog signal 201 into three bits. The 3-bit output signal can be provided to the alignment and correction circuit 258 as the first digital signal 241 (MSB). The 3-bit output signal can then be provided to the DAC 216, which converts the 3-bit output signal into an analog output signal. The subtractor circuit 218 can subtract the analog output signal from the first analog signal 201 to generate a residual signal (e.g., an analog residual signal). The amplifier can amplify the residual signal by a factor "K" and provide the amplified residual signal (as the second analog signal 203) to the second stage 220 (e.g., to the plurality of first switches 221-0, ..., 221-n).

[0066] refer to Figure 2, the second type of multiple ADCs 220-0, ..., 220-n in the second stage 220 can be time-interleaved SAR ADCs. The first type of ADC in the first stage 210 and each SAR ADC in the second stage 220 can be selectively activated or used or turned on (via the plurality of first switches 221 and / or the plurality of second switches 222) based on different requirements of ADC resolution and / or speed (e.g., conversion rate or sampling rate). For example, the plurality of first switches 221 can be individually and / or individually powered on or off to select one or more ADCs of the second type (e.g., SAR ADCs 220-0, 220-1) and provide the second analog signal 203 to the selected one or more ADCs 220-0, 220-1 of the second type. In some embodiments, the plurality of second switches 222 may be individually and / or individually powered on or off to select one or more ADCs of the second type (e.g., SAR ADCs 220-0, 220-1) and provide the first analog signal 201 to the selected one or more ADCs 220-0, 220-1 of the second type. In this way, the hybrid ADC 2000 may be configured (or reconfigured) to different architectures (e.g., in terms of resolution and / or speed) to meet a variety of communication standards while achieving greater power efficiency.

[0067] For example, the first type of ADC in the first stage may be a pipeline ADC 210-1 including a ping-pong type MDAC 215 configured to process 3-bit data (referred to as a "ping-pong type 2.5-bit MDAC"), and each of the second type of ADCs in the second stage 220 (for a corresponding path) may be a SAR ADC configured to process 11-bit data (referred to as a "path of 11-bit SAR ADC"). With this configuration, the hybrid ADC 2000 may be configured (or reconfigured) as the following example.

[0068] Example 1: For 10 Gigabit Ethernet mode, the hybrid ADC 2000 can be configured to support an ADC with 13-bit data resolution and 800 MHz speed by: (1) turning on a ping-pong type 2.5-bit MDAC (e.g., turning on pipeline ADC 210-1); and (2) turning on a 2-channel 11-bit SAR ADC (e.g., SAR ADC 220-0, 220-1).

[0069] Example 2: For 5 Gigabit Ethernet mode, the hybrid ADC 2000 can be configured to support an ADC with 11-bit data resolution and 800 MHz speed by: (1) turning off the ping-pong type 2.5-bit MDAC (e.g., turning off the pipeline ADC 210-1); and (2) turning on the 11-bit SAR ADC with 2 channels (e.g., SAR ADC 220-0, 220-1).

[0070] Example 3: For 2.5 Gigabit Ethernet mode, the hybrid ADC 2000 can be configured to support an ADC with 11-bit data resolution and 400 MHz speed by: (1) turning off the ping-pong type 2.5-bit MDAC (e.g., turning off the pipeline ADC 210-1); and (2) turning on the 11-bit SAR ADC of one channel (e.g., SAR ADC 220-0).

[0071] Example 4: For 1 Gigabit Ethernet mode, the hybrid ADC 2000 can be configured to support an ADC with 8-bit data resolution and 125 MHz speed by: (1) turning off the ping-pong 2.5-bit MDAC (e.g., turning off the pipeline ADC 210-1); (2) turning on one channel of the 11-bit SAR ADC (e.g., SAR ADC 220-0); and (3) (re)configuring SAR ADC 220-0 as an 8-bit SAR ADC by disabling 3 of the 11 bits, so that SAR ADC 220-0 can use only 8 bits and stop using the remaining 3 bits.

[0072] Examples 1 to 4 show that the hybrid ADC 2000 can be configured (or reconfigured) according to a desired resolution or target resolution and a desired speed or target speed. As shown in Example 2, in response to receiving an input signal (e.g., signal 291) indicating a target resolution (e.g., 11 bits) below a threshold (e.g., 12 bits or 10 bits of ENOB), the controller 290 can generate a control signal 295 to control the plurality of first switches 221 to be turned off (or disconnected) so that the ADC 210-1 is not used. In response to receiving an input signal (e.g., signal 292) indicating a target speed (e.g., 800 MHz), the controller 290 can generate a control signal 295 to select and turn on two switches (e.g., 222-0, 222-1) from among the plurality of second switches 222 so that the 11-bit SAR ADCs (e.g., SAR ADCs 220-0, 220-1) of the two channels can be turned on.

[0073] As shown in Example 3, in response to receiving an input signal 291 indicating a target resolution (e.g., 11 bits) below a threshold (e.g., 12 bits or 10 bits of ENOB), the controller 290 may generate a control signal 295 to control the plurality of first switches 221 to be turned off (or disconnected) so that the ADC 210-1 is not used. In response to receiving an input signal 292 indicating a target speed (e.g., 400 MHz), the controller 290 may generate a control signal 295 to select and turn on one switch (e.g., 222-0) from among the plurality of second switches 222 so that a 11-bit SAR ADC (e.g., SAR ADC 220-0) of one channel may be turned on or used. The controller 290 may generate the control signal 295 so that the greater the target speed, the more channels (or SAR ADCs) are turned on or used, or so that there is a linear relationship between the target speed and the number of channels.

[0074] As shown in Example 4, in some embodiments, in response to receiving an input signal 291 indicating a target resolution (e.g., 8 bits) below a threshold (e.g., 12 bits or 10 bits of ENOB), the controller 290 may generate a control signal 295 to control the plurality of first switches to be turned off (or disconnected) so that the ADC 210-1 is not used. In response to receiving an input signal 292 indicating a target speed (e.g., 125 MHz), the controller 290 may generate a control signal 295 to select and turn on one switch (e.g., 220-0) from among the plurality of second switches 222 so that a 11-bit SAR ADC (e.g., SAR ADC 220-0) of one channel may be turned on or used. In response to determining that the target resolution (e.g., 8 bits) is less than the maximum resolution (e.g., 11 bits) supported by each of the plurality of ADCs of the second type (e.g., SAR ADC 220-0), the controller 290 may generate one or more control signals 295 to disable 3 of the 11 bits of the SAR ADC 220-0 so that the SAR ADC 220-0 may use only 8 bits and stop using the remaining 3 bits.

[0075] Figure 3is a schematic block diagram of reconfiguring a hybrid ADC 3000 including different types of ADCs using a plurality of multiplexers according to an embodiment. The reconfigurable hybrid ADC 3000 may have a configuration similar to that of the reconfigurable hybrid ADC 1000 or 2000, except for a plurality of first switches and a plurality of second switches. For example, the reconfigurable ADC 3000 may include: an ADC 310-1 of a first type in a first stage 310; a plurality of ADCs 320-0, ..., 320-n of a second type in a second stage 320; a plurality of T-switches or multiplexers 330-0, ..., 330-n (collectively referred to as a plurality of multiplexers 330) electrically coupled between the first type ADC 310-1 and the plurality of ADCs 320-0, ..., 320-n of a second type; a circuit configured to perform alignment and correction (e.g., alignment and correction circuit 350); and / or a controller 390.

[0076] refer to Figure 3 , the reconfigurable hybrid ADC 3000 may include a plurality of T-switches as multiplexers 330 to achieve good channel-to-channel isolation. Each multiplexer 330-0, ..., 330-n may have two inputs configured to receive the first analog signal 301 and the second analog signal 303, respectively. Each multiplexer 330-0, ..., 330-n may receive a selection signal 331-0, ..., 331-n. Each multiplexer may selectively output the first analog signal 301 or the second analog signal 303 according to the selection signal 331-0, ..., 331-n. For example, in response to receiving a selection signal indicating a first value (e.g., "0"), one or more multiplexers (e.g., multiplexers 330-0, 330-1 among the multiple multiplexers) may be selected to provide the second analog signal 303 to the corresponding one or more ADCs of the second type (e.g., ADC 320-0, 320-1). On the other hand, in response to receiving a selection signal indicating a second value (e.g., "1"), one or more multiplexers (e.g., multiplexers 330-0, 330-1 among the multiple multiplexers) may be selected to provide the first analog signal 301 to the corresponding one or more ADCs of the second type (e.g., ADC 320-0, 320-1).

[0077] refer to Figure 3, the first type of ADC 310-1 may receive the first analog signal 301 and convert the first analog signal 301 into a first digital signal 341 as the MSB. The first ADC 310-1 may output a second analog signal (e.g., a residual signal) 303 to a plurality of multiplexers 330 based on the first analog signal 301 and the first digital signal 341. The plurality of multiplexers 330 may select one or more ADCs of the second type (e.g., two ADCs 320-0 and ADC 320-1) according to a selection signal 331 indicating a first value (“0”), and provide the second analog signal 303 to the selected one or more ADCs of the second type. The selected one or more ADCs 320-0, 320-1 may convert the second analog signal 303 into one or more digital signals (LSBs0 and LSBs1) 342-0, 342-1 (from LSBs0 (342-0), ..., LSBsn (342-n)) as the LSB. The alignment and correction circuit 350 may receive the first digital signal 341 and one or more digital signals (as LSBs) 342-0, 342-1 as uncorrected output digital signals, perform alignment and / or correction of the uncorrected output digital signals, and output a corrected output digital signal (Dout) 360. The plurality of multiplexers 330 may select one or more ADCs of a second type (e.g., two ADCs 320-0 and ADC 320-1) according to a selection signal 331 indicating a second value ("1"), and provide the first analog signal 301 to the selected one or more ADCs of the second type. The selected one or more ADCs 320-0, 320-1 may convert the first analog signal 301 into one or more digital signals (LSBs0 and LSBs1) 342-0, 342-1. The alignment and correction circuit 350 may receive one or more digital signals 342-0, 342-1 as uncorrected output digital signals, perform alignment and / or correction of the uncorrected output digital signals, and output a corrected output digital signal 360. The controller 390 may generate one or more control signals 395 based on the input signals 391, 392 to control at least one of: the first type of ADC 310-1; each of the plurality of ADCs 320-0, ..., 320-n of the second type; or each of the plurality of multiplexers 330-0, ..., 330-n. For example, the one or more control signals 395 may include selection signals 331-0, ..., 331-n.

[0078] Figure 44 is a schematic block diagram of a reconfigurable multi-channel ADC 4000 according to an embodiment. The reconfigurable multi-channel ADC 4000 may include a plurality of hybrid ADCs 410-0, ..., 410-m in corresponding channels CH0, ..., CHm, a circuit configured to perform alignment and correction (e.g., alignment and correction circuit 450), and / or a controller 490. Each hybrid ADC may include: an ADC of a first type in a second stage 412-0, ..., 412-m (collectively referred to as the second stage 412); a plurality of ADCs of a second type (e.g., ADC0, ..., ADCn) in a third stage 413-0, ..., 413-m (collectively referred to as the third stage 413); and a plurality of switches (e.g., first switches S0a, ..., Sna and second switches S0b, ..., Snb) electrically coupled between the first type ADC and the plurality of ADCs of the second type or electrically coupled to the plurality of ADCs of the second type, respectively. Each hybrid ADC may further include a third type of ADC in the first stage 411-0, ..., 411-m (collectively referred to as the first stage 411) and a third switch 415-0, ..., 415-m electrically coupled to the first type of ADC. The third type of ADC may be one or more flash ADCs, one or more pipeline ADCs (e.g., a pipeline ADC including a multiplying digital-to-analog converter (MDAC)), one or more SAR ADCs, or any circuit, hardware, microprocessor capable of converting an analog signal into a digital signal. The third type of ADC may be the same as the first type of ADC. The third type of ADC may be different from the second type of ADC.

[0079] refer to Figure 4, each hybrid ADC 410-0, ..., 410-m can receive the first analog signal 401, and selectively provide the first analog signal 401 (1) to the third type ADC in the first stage 411-0, ..., 411-m, or (2) to the first type ADC in the second stage 412-0, ..., 412-m through the third switch 415-0, ..., 415-m. In response to receiving the first analog signal 401, the third type ADC in the first stage 411-0, ..., 411-m can convert the first analog signal 401 into a first digital signal (e.g., a 2-bit digital signal), and output a second analog signal (residual signal) and a first digital signal (e.g., a combined signal 416-0, ..., 416-m) to the first type ADC in the second stage 412-0, ..., 412-m based on the first analog signal 401 and the first digital signal. In response to receiving the second analog signal and the first digital signal (e.g., the combined signal 416-0, ..., 416-m), the first type of ADC in the second stage 412-0, ..., 412-m may convert the second analog signal into a second digital signal (e.g., a 3-bit digital signal), and combine the first digital signal with the second digital signal (e.g., excluding overlapping bits) to output the MSB output digital signal of the hybrid ADC (e.g., a 4-bit digital signal) 417-0, ..., 417-m. The first type of ADC in the second stage 412-0, ..., 412-m may output a third analog signal (residual signal) 418-0, ..., 418-m based on the second analog signal and the second digital signal to one or more ADCs selected from the plurality of second type ADCs in the third stage 413-0, ..., 413-m. The selected one or more ADCs may convert the third analog signals 418 - 0 , . . . , 418 - m into one or more digital signals 419 - 0 , . . . , 419 - m as LSB output digital signals of the hybrid ADCs 410 - 0 , . . . , 410 - m.

[0080] refer to Figure 4 In response to receiving the first analog signal 401 by the first type ADC in the second stage 412-0, ..., 412-m, the first type ADC in the second stage and the second type multiple ADCs in the third stage 413-0, ..., 413-m can be similar to Figure 1 , Figure 2 and Figure 3The two-stage hybrid ADC 1000, 2000, 3000 shown in the figure respectively generates the MSB output digital signals 417-0, ..., 417-m and the LSB output digital signals 419-0, ..., 419-m of the hybrid ADCs 410-0, ..., 410-m. The alignment and correction circuit 450 can receive the MSB output digital signals 417-0, ..., 417-m and the LSB output digital signals 419-0, ..., 419-m from each hybrid ADC as uncorrected output digital signals 440-0, ..., 440-m, perform alignment and / or correction of the uncorrected output digital signals 440-0, ..., 440-m, and output a corrected output digital signal 460.

[0081] refer to Figure 4 , the controller 490 can be any circuit, hardware or processor (for example, a microprocessor), which is capable of controlling the third type of ADC (in the first stage 411-0, ..., 411-m), the first type of ADC (in the second stage 412-0, ..., 412-m), and each of the multiple ADCs of the second type (in the third stage 413-0, ..., 413-m) to be turned on or off (or powered on or off) individually and / or individually, and is capable of controlling each of the multiple first switches (for example, switches S0a, ..., SNA), each of the multiple second switches (for example, switches S0b, ..., SNB) and / or each third switch 411-0, ..., 411-m to be turned on or off or connected (closed) or disconnected (disconnected). The controller 490 may control the first type of ADC, each of the plurality of ADCs of the second type, and / or the third type of ADC to use or process only a portion (e.g., 8 bits) of the maximum bits (e.g., 11 bits) supported by the ADC. In some embodiments, the controller 490 may receive an input signal 491 indicating a desired (or target) resolution of the output of the hybrid ADC, and / or an input signal 492 indicating a desired (or target) speed (or conversion rate or sampling rate) of the hybrid ADC. The controller 490 may generate one or more control signals 495 based on the input signal to control at least one of: the first type of ADC; each of the plurality of ADCs of the second type; the third type of ADC; each of the plurality of first switches; each of the plurality of second switches; or each third switch.

[0082] refer to Figure 4 The first and third types of ADCs are pipeline ADCs including ping-pong type MDACs (eg, including Figure 2 The pipeline ADC 210-1 of the ping-pong type MDAC 215 in FIG. 1 ) and the second type of ADC is a SAR ADC (eg, Figure 2SAR ADC 222-0, ..., 222-n), the reconfigurable multi-channel ADC 4000 can be configured by increasing the number of channels (e.g., increasing Figure 4 The reconfigurable multi-channel ADC 4000 can increase the resolution or accuracy of the analog-to-digital conversion by switching on one or more ADCs of the third type in the first stage 411 in one or more channels. For higher speed (or higher sampling rate) applications, the reconfigurable multi-channel ADC 4000 can (1) increase the number of channels in the third stage 413 (e.g., Figure 4 ), or (2) increase the number of channels (e.g., Figure 4 The reconfigurable multi-channel ADC 4000 may first increase the number of SAR ADC paths in the third stage 413 (eg, Figure 4 The reconfigurable multi-channel ADC 4000 may first increase the number of paths (e.g., number n) in the third stage 413, and then increase the number of channels (e.g., number m) if necessary, because the SAR ADC has great power efficiency and the ADCs in the first stage 411 and the second stage 412 (e.g., pipeline ADCs) have less time interleaving between channels. For higher ADC resolution applications, the reconfigurable multi-channel ADC 4000 may configure the first stage 411 to process higher bits (typically <= 4 bits) or add more stages (e.g., second stage 412). At the same time, each of the first stage 411, the second stage 412, and the third stage 413 (e.g., SAR ADC) may be powered on or off individually and / or separately based on different requirements for ADC resolution and speed. Therefore, the reconfigurable multi-channel ADC 4000 can be configured into different architectures to meet multi-standard communications with greater power efficiency.

[0083] refer to Figure 4, a system (e.g., a reconfigurable multi-channel ADC 4000) may include a first type of multiple analog / digital converters (ADCs) (e.g., ADCs in the second stage 412-0, ..., 412-m) electrically coupled to a plurality of switches (e.g., switches 420-0, ..., 420-m), each ADC of the first type (e.g., ADC 412-0) being electrically coupled to a second type of multiple ADCs (e.g., ADC0, ..., ADCn in the third stage 413-0) through a corresponding switch (e.g., switch 420-0). Each switch may be configured to select a certain number of ADCs of the second type from among the multiple ADCs (e.g., ADC0, ..., ADCn in the third stage 413-0) based on a rate of analog / digital conversion (e.g., a target rate or speed of the reconfigurable multi-channel ADC 4000) to supply analog / digital conversion at the rate. Each switch may be configured to selectively bypass a corresponding ADC of the first type (e.g., ADC in the second stage 412-0) according to a resolution of the analog / digital conversion (e.g., a target resolution of the analog / digital conversion). Each switch may be configured to bypass a corresponding ADC of the first type in response to a resolution of a conversion being below a first threshold (eg, the ADC in the second stage 412 - 0 may be bypassed when a target resolution is below a first threshold).

[0084] refer to Figure 4 , each ADC of the first type (e.g., ADC0, ADC1, ..., ADCn in the third stage 413-0) includes an MDAC (e.g., MDAC 215). In some embodiments, the plurality of ADCs of the second type (e.g., ADC0, ..., ADCn in the third stage 413-0) may include time-interleaved successive approximation register (SAR) ADCs. In some embodiments, the selected number of ADCs of the second type may increase as the rate of analog-to-digital conversion increases (e.g., the higher the target rate or speed becomes, the more number of ADCs of the second type that the corresponding switch or controller may select to meet the target rate or speed).

[0085] In some embodiments, each switch (e.g., switch 413-0) may include a plurality of multiplexers (e.g., multiplexers 330-0, ..., 330-n) electrically coupled to a plurality of ADCs of the second type (e.g., ADC0, ..., ADCn in the third stage 413-0), respectively. Each multiplexer may be configured to selectively bypass a corresponding ADC of the first type (e.g., ADC in the second stage 412-0) in response to a resolution of a conversion being below a threshold. In some embodiments, the system may include a plurality of ADCs of the third type (e.g., ADCs in the first stage 411-0, ..., 411-m) electrically coupled to a plurality of ADCs of the first type (e.g., ADCs in the second stage 412-0, ..., 412-m), respectively, and a plurality of additional switches (e.g., switches 415-0, ..., 415-m) electrically coupled to a plurality of ADCs of the third type (e.g., ADCs in the first stage 411-0, ..., 411-m), respectively. Each additional switch (e.g., switch 415-0) may be configured to selectively bypass a corresponding ADC of the third type (e.g., the ADC in the first stage 411-0) based on a resolution of the analog-to-digital conversion (e.g., a target resolution). Each additional switch (e.g., switch 415-0) may be configured to bypass a corresponding ADC of the third type (e.g., ADC 411-0 in the first stage) in response to a resolution of the conversion being below a second threshold that is greater than a first threshold (e.g., the resolution threshold of the ADC in the first stage is greater than the resolution threshold of the ADC in the second stage; in other words, if the ADC in the second stage is bypassed, then the ADC in the first stage is also bypassed).

[0086] In some embodiments, the system may include a controller (e.g., controller 490) configured to determine the number of switches (e.g., (1) the number of switches currently active or turned on, or (2) the number of active channels currently performing analog-to-digital conversion) among a plurality of switches (e.g., switches 420-0, 420-2, ..., 420-m) that respectively turn on a selected number of ADCs of the second type. The controller may determine a first rate of analog-to-digital conversion (e.g., a rate or speed actually achieved by turning on the selected number of ADCs of the second type in the active channels) due to turning on a certain number of switches of the selected number of ADCs of the second type respectively. The controller may determine whether the rate of the first analog-to-digital conversion is less than the rate of the analog-to-digital conversion (e.g., whether the current rate or speed of the reconfigurable ADC 4000 is less than the target rate or speed of the reconfigurable ADC 4000). In response to determining that the rate of the first analog-to-digital conversion is less than the rate of the analog-to-digital conversion, the controller may increase the selected number of ADCs of the second type to a second number of ADCs of the second type. For example, if the current rate or speed is less than the target rate or speed, the controller may turn on more ADCs of the second type so that the number of ADCs of the second type turned on in the third stage is the second number of ADCs of the second type. The controller may determine the second rate of analog-to-digital conversion (e.g., the rate or speed actually achieved by turning on the second number of ADCs of the second type in the active channel) due to a certain number of switches turning on the second number of ADCs of the second type, respectively. The controller may determine whether the rate of the second analog-to-digital conversion is less than the rate of the analog-to-digital conversion (e.g., whether the current rate or speed of the reconfigurable ADC 4000 is still less than the target rate or speed of the reconfigurable ADC 4000). In response to determining that the rate of the second analog-to-digital conversion is less than the rate of the analog-to-digital conversion, the controller may increase a certain number of switches to the second number of switches. The controller may control the second number of switches to turn on the second number of ADCs of the second type, respectively. For example, if the current rate or speed is still less than the target rate or speed, the controller may turn on more channels or switches so that the number of switches that turn on the second number of ADCs in the third stage (or the number of active channels) is the second number of switches.

[0087] In some embodiments, an ADC (e.g., a reconfigurable multi-channel ADC 4000) may include a plurality of hybrid ADCs (e.g., 410-0, ..., 410-m) in respective channels (e.g., Ch0, ..., CHm) and a controller (e.g., controller 490). Each of the plurality of hybrid ADCs (e.g., 410-0) may include one or more ADCs of a first type (e.g., an ADC in the first stage 411, an ADC in the second stage 412-0) and a plurality of ADCs of a second type (e.g., a SAR ADC in the third stage 413-0). The second type of ADC (e.g., SAR ADC 220-0) may have greater power efficiency than the first type of ADC (e.g., pipeline ADC 210-1 including MDAC 215). The controller may be configured to determine a first number indicating the number of ADCs of the second type (e.g., the number of SAR ADCs in the third stage 413-0) and a second number indicating the number of channels (e.g., the number of channels selected to perform analog-to-digital conversion). The controller may be configured to control (1) a second number of hybrid ADCs among the plurality of hybrid ADCs in the second number of channels and (2) a first number of ADCs of the second type among the plurality of ADCs of the second type in each of the second number of channels to perform a first analog-to-digital conversion. In response to determining that a speed of the first analog-to-digital conversion is less than the first speed (e.g., a target speed of the multi-channel ADC 4000 may be reconfigured), the controller may be configured to control a second number of hybrid ADCs in the second number of channels and a third number of ADCs of the second type in each of the second number of channels to perform a second analog-to-digital conversion, the third number being greater than the first number (e.g., the number of ADCs of the second type increases from the first number to the third number). In response to determining that a speed of the second analog-to-digital conversion is less than the first speed, the controller may be configured to control a fourth number of hybrid ADCs in the fourth number of channels and a third number of ADCs of the second type in each of the fourth number of channels to perform a third analog-to-digital conversion, the fourth number being greater than the second number (e.g., the number of channels increases from the second number to the fourth number). For example, to increase the speed of analog / digital conversion (e.g., conversion rate or sampling rate) in a reconfigurable multi-channel ADC, the controller may first increase the number of SAR ADCs in each channel to determine whether the speed of conversion meets the target speed because SAR ADCs have greater power efficiency (e.g., compared to a pipeline ADC including an MDAC). In response to determining that the speed of conversion does not meet the target speed (e.g., the speed of conversion is less than the target speed), the controller may increase the number of channels.

[0088] Figure 51 is a flow chart showing a process 5000 for reconfiguring a hybrid ADC including different types of ADCs according to one embodiment. In some embodiments, the process 5000 is performed by a reconfigurable hybrid ADC (e.g., ADC 1000, 2000, 3000, 4000). In other embodiments, the process 5000 is performed by other entities. In some embodiments, the process 5000 includes a Figure 5 More, fewer, or different steps may be shown in .

[0089] At step 502, a plurality of switches (e.g., first switches 221-0, ..., 221-n) coupling a first ADC of a first type (e.g., pipeline ADC 210-1) to a plurality of ADCs of a second type (e.g., SAR ADCs 220-0, ..., 220-n) may select a certain number of ADCs of a second type (e.g., two SAR ADCs 220-0, 220-1) from among the plurality of ADCs of a second type (e.g., SAR ADCs 220-0, ..., 220-n) to provide analog-to-digital conversion at the rate of analog-to-digital conversion (e.g., a target conversion rate of the ADC indicated by a signal 292 input to a controller 290) based on the rate of analog-to-digital conversion. In some embodiments, the first ADC of the first type may include an MDAC (e.g., MDAC 215). The ADC of the first type (e.g., pipeline ADC including a ping-pong type MDAC) may be different from the ADC of the second type (e.g., SAR ADC). The plurality of ADCs of the second type may include a time-interleaved SAR ADC. A certain number of ADCs of the second type may be selected such that the selected number of ADCs of the second type increases as the rate of analog-to-digital conversion (e.g., target conversion rate) increases. For example, a SAR ADC of two channels may select an 800 MHz target conversion rate, while a SAR ADC of one channel may select a 400 MHz or 125 MHz target conversion rate.

[0090] At step 504, in response to the resolution of the analog-to-digital conversion (e.g., the target resolution or accuracy of the ADC indicated by the signal 291 input to the controller 290) being lower than a threshold value (e.g., 12 bits or 10 bits ENOB), the plurality of switches (e.g., the second switches 222-0, ..., 222-n) may bypass the first ADC (e.g., the pipeline ADC 210-1). In some embodiments, the plurality of switches may include a plurality of multiplexers (e.g., multiplexers 330-0, ..., 330-n) electrically coupled to the plurality of ADCs of the second type (e.g., ADCs 320-0, ..., 320-n), respectively. When bypassing the first ADC, in response to the resolution of the analog-to-digital conversion being lower than the threshold value, each multiplexer may bypass the first ADC (e.g., by providing a selection signal 331 indicating the second value ("1") to each multiplexer).

[0091] At step 506, in response to the resolution of the analog-to-digital conversion being greater than or equal to a threshold value (e.g., 12 bits or 10 bits ENOB), a plurality of switches (e.g., first switches 221-0, ..., 221-n) may connect the first ADC (e.g., pipeline ADC 210-1) to a selected number of ADCs of a second type (e.g., two SAR ADCs 220-0, 220-1). When connecting the first ADC to the selected number of ADCs of the second type, in response to the resolution of the analog-to-digital conversion being greater than or equal to the threshold value, a plurality of multiplexers may connect the first ADC to the selected number of ADCs of the second type (e.g., by providing a selection signal 331 indicating a first value ("0") to each multiplexer). In some embodiments, in response to receiving an input signal (e.g., first analog signal 201), the first ADC (e.g., ADC 210-1) may convert the input signal into a first digital signal (e.g., first digital signal 241) and output an analog signal (e.g., second analog signal 203). In response to receiving the analog signal (eg, second analog signal 203 ), the second type of multiple ADCs (eg, SAR ADCs 220 - 0 , . . . , 220 - n ) may convert the analog signal into a second digital signal (eg, second digital signal 242 - 0 , . . . , 242 - n ).

[0092] The term "coupled" and its variations include two components being directly or indirectly connected to each other. The term "electrically coupled" and its variations include two components being directly or indirectly connected to each other through a conductive material (e.g., a metal, copper trace, or wire). Such connection (for both the terms "coupled" and "electrically coupled") can be stationary (e.g., permanent or fixed) or movable (e.g., removable or releasable). Such connection (for both the terms "coupled" and "electrically coupled") can be achieved by means of the two components being directly coupled to or coupled to each other, by means of the two components being coupled to each other using a separate intermediate component coupled to each other and any additional intermediate components coupled to each other, or by means of the two components being coupled to each other using an intermediate component that is integrally formed as a single entity with one of the two components. If "coupled" or variations thereof are modified by additional terms (e.g., directly coupled), the general definition of "coupled" provided above is modified by the plain language meaning of the additional terms (e.g., "directly coupled" means the joining of two components without any separate intermediate components), resulting in a narrower definition than the general definition of "coupled" provided above. Such coupling may be mechanical, electrical, or fluid.

[0093] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

[0094] It should be noted that certain paragraphs of the present disclosure may refer to terms such as "first" and "second" related to transmission spatial streams, sounding frames, responses, and subsets of devices in order to identify or distinguish one from another or between each other. These terms are not intended to relate entities (e.g., first device and second device) only in time or according to a sequence, although in some cases, these entities may include such a relationship. These terms also do not limit the number of possible entities that can operate in a system or environment. It should be understood that the system described above may provide multiple components of any or each of those components, and these components may be provided on a stand-alone machine or, in some embodiments, on multiple machines in a distributed system. In addition, the systems and methods described above may be provided as one or more computer-readable programs or executable instructions, which are embodied on or in one or more articles of manufacture, such as a floppy disk, hard disk, CD-ROM, flash memory card, PROM, RAM, ROM, or tape. The program may be implemented in any programming language such as LISP, PERL, C, C++, C#, or in any bytecode language such as JAVA. The software program or executable instructions may be stored as object code on or in one or more articles of manufacture. In some embodiments, the ADC is used as an integrated circuit in a transmitter for wireless communication. The ADC is disposed on an integrated circuit that includes a calibration engine. In some embodiments, the ADC and the calibration engine are disposed in a single chip or multi-chip integrated package.

[0095] Although the foregoing written description of the methods and systems enables those skilled in the art to make and use embodiments thereof, those skilled in the art will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiments, methods, and examples of the present article. Therefore, the methods and systems should not be limited to the embodiments, methods, and examples described above, but are limited to all embodiments and methods within the scope and spirit of the present disclosure.

Claims

1. A system comprising: a first analog-to-digital converter ADC of a first type, the first ADC being electrically coupled to a plurality of ADCs of a second type via a plurality of switches, wherein The plurality of switches are configured to: selecting a number of ADCs of the second type from among the plurality of ADCs of the second type based on a rate of analog-to-digital conversion to supply the analog-to-digital conversion at the rate; and selectively bypassing the first ADC based on a resolution of the analog-to-digital conversion, Wherein the plurality of switches are configured to bypass the first ADC in response to the resolution of the conversion being below a threshold. 2 . The system of claim 1 , wherein the first ADC of the first type comprises a multiplying digital-to-analog converter (MDAC). 3 . The system of claim 2 , wherein the MDAC is configured to perform double sampling or ping-pong sampling. 4 . The system of claim 1 , wherein the plurality of ADCs of the second type comprise time-interleaved successive approximation register (SAR) ADCs. 5 . The system of claim 1 , wherein the selected number of the second type of ADCs increases as the rate of the analog-to-digital conversion increases.

6. The system of claim 1, wherein The plurality of switches include a plurality of multiplexers electrically coupled to the plurality of ADCs of the second type, respectively, and Each multiplexer is configured to selectively bypass the first ADC in response to the resolution of the conversion being below the threshold.

7. The system of claim 1, wherein In response to receiving an input signal, the first ADC is configured to convert the input signal into a first digital signal and output an analog signal, and In response to receiving the analog signal, the plurality of ADCs of the second type are configured to convert the analog signal into a second digital signal.

8. A method comprising: selecting a number of ADCs of a second type from among the plurality of ADCs of a second type based on a rate of analog-to-digital conversion by a plurality of switches coupling a first analog-to-digital converter ADC of a first type to a plurality of ADCs of a second type to supply the analog-to-digital conversion at the rate; In response to a resolution of the analog-to-digital conversion being below a threshold, bypassing the first ADC via the plurality of switches; and In response to the resolution of the analog-to-digital conversion being greater than or equal to the threshold, connecting the first ADC to the selected number of ADCs of the second type through the plurality of switches. 9 . The method of claim 8 , wherein the first ADC of the first type comprises a multiplying digital-to-analog converter (MDAC).

10. The method of claim 9, wherein the MDAC is configured to perform double sampling or ping-pong sampling.

11. The method of claim 8, wherein the plurality of ADCs of the second type comprises time-interleaved successive approximation register (SAR) ADCs.

12. The method of claim 8, wherein the number of ADCs of the second type is selected such that the selected number of ADCs of the second type increases as the rate of the analog-to-digital conversion increases.

13. The method according to claim 8, wherein The plurality of switches include a plurality of multiplexers electrically coupled to the plurality of ADCs of the second type, respectively, Bypassing the first ADC includes: In response to the resolution of the analog-to-digital conversion being below the threshold, bypassing the first ADC through each multiplexer, and Connecting the first ADC to the selected number of ADCs of the second type comprises: In response to the resolution of the analog-to-digital conversion being greater than or equal to the threshold, connecting the first ADC to the selected number of ADCs of the second type through the plurality of multiplexers.

14. The method according to claim 8, further comprising: In response to receiving an input signal, converting the input signal into a first digital signal through the first ADC and outputting an analog signal; and In response to receiving the analog signal, the first analog signal is converted into a second digital signal by the plurality of ADCs of the second type.

15. A system comprising: a plurality of analog-to-digital converters ADC of a first type, the plurality of ADCs being electrically coupled to a plurality of switches, each ADC of the first type being electrically coupled to a plurality of ADCs of a second type via a corresponding switch, wherein Each switch is configured to: selecting a number of ADCs of the second type from among the plurality of ADCs based on a rate of analog-to-digital conversion to supply the analog-to-digital conversion at the rate; and selectively bypassing the corresponding ADC of the first type based on a resolution of the analog-to-digital conversion, Wherein each switch is configured to bypass the corresponding ADC of the first type in response to the resolution of the conversion being below a first threshold.

16. The system of claim 15, wherein Each ADC of the first type comprises a multiplying digital-to-analog converter MDAC, and The plurality of ADCs of the second type include time-interleaved successive approximation register (SAR) ADCs.

17. The system of claim 15, wherein the selected number of the second type of ADCs increases as the rate of the analog-to-digital conversion increases.

18. The system of claim 15, wherein Each switch includes a plurality of multiplexers electrically coupled to the plurality of ADCs of the second type, respectively, and Each multiplexer is configured to selectively bypass the corresponding ADC of the first type in response to the resolution of the conversion being below the threshold.

19. The system of claim 15, further comprising: a plurality of ADCs of a third type, the plurality of ADCs being electrically coupled to the plurality of ADCs of the first type, respectively; and a plurality of further switches electrically coupled to the plurality of ADCs of the third type, each further switch configured to selectively bypass the corresponding ADC of the third type according to the resolution of the analog-to-digital conversion, Wherein each additional switch is configured to bypass the corresponding ADC of the third type in response to the resolution of the conversion being below a second threshold that is greater than the first threshold.

20. An analog / digital converter ADC, comprising: a plurality of hybrid ADCs in respective channels, each hybrid ADC comprising one or more ADCs of a first type and a plurality of ADCs of a second type, wherein the power efficiency of the ADCs of the second type is greater than the power efficiency of the ADCs of the first type; A controller configured to: determining a first number indicative of a number of ADCs of the second type and a second number indicative of a number of channels; controlling (1) the second number of hybrid ADCs among the plurality of hybrid ADCs in the second number of channels and (2) the first number of ADCs of the second type among the plurality of ADCs of the second type in each of the second number of channels to perform a first analog-to-digital conversion; In response to determining that the speed of the first analog-to-digital conversion is less than a first speed, controlling the second number of hybrid ADCs in the second number of channels and a third number of ADCs of the second type in each of the second number of channels to perform a second analog-to-digital conversion, the third number being greater than the first number; and In response to determining that the speed of the second analog-to-digital conversion is less than the first speed, controlling the fourth number of hybrid ADCs in a fourth number of channels and the third number of ADCs of the second type in each of the fourth number of channels to perform a third analog-to-digital conversion, the fourth number being greater than the second number.

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