Reconfigurable transmit digital-to-analog converter (DAC) circuit

Abstract

A method and apparatus for sharing digital-to-analog (DAC) converters in a reconfigurable DAC circuit to support two or more transmit chains of a wireless transmitter configured for different radio access technologies (RATs) and / or different transmitter architectures. One exemplary DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit having at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit having at least two channels for a second set of one or more frequency bands, different from the first set of frequency bands.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS)

[0001] This application claims priority to U.S. patent application Ser. No. 18 / 068,941, filed Dec. 20, 2022, which is incorporated herein by reference.

[0002]

[0002] Certain aspects of the present disclosure relate generally to electronic circuits, and more specifically to reconfigurable digital-to-analog converter (DAC) circuits capable of supporting multiple radio access technologies (RATs), frequency bands, and / or transmitter architectures. [Background technology]

[0003] Wireless communication devices are widely deployed to provide various communication services such as telephony, video, data, messaging, broadcasts, etc. Such wireless communication devices may transmit and / or receive radio frequency (RF) signals via any of a variety of suitable radio access technologies (RATs), including, but not limited to, 5G New Radio (NR), Long Term Evolution (LTE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wideband CDMA (WCDMA), Global System for Mobility (GSM), Bluetooth, Bluetooth Low Energy (BLE), ZigBee, wireless local area network (WLAN) RATs (e.g., WiFi), Cellular Vehicle-to-Everything (C-V2X), etc.

[0004] A wireless communication network may include several base stations capable of supporting communication for several mobile stations. A mobile station (MS) may communicate with a base station (BS) via a downlink and an uplink. The downlink (or forward link) refers to the communication link from the base station to the mobile station, and the uplink (or reverse link) refers to the communication link from the mobile station to the base station. A base station may transmit data and control information to a mobile station on the downlink and / or receive data and control information from a mobile station on the uplink. A base station and / or a mobile station may include at least one transceiver, which may include, for example, multiple transmission paths designated for transmission using different RATs. Different RATs may use different sets of frequency bands for transmission, and in some cases, a single RAT (e.g., 5G NR) may use different sets of one or more frequency bands. Summary of the Invention

[0005]

[0005] The systems, methods, and devices of the present disclosure each have several aspects, none of which is solely responsible for its desirable attributes. Without limiting the scope of the present disclosure as expressed by the following claims, some features will now be briefly described. After considering this description, and particularly after reading the section entitled "Detailed Description of the Invention," one will understand how features of the present disclosure provide advantages, including reduced area and cost of digital-to-analog converter (DAC) circuitry (e.g., in a transmitter), by sharing hardware to support multiple radio access technologies (RATs), frequency bands, and / or transmitter architectures.

[0006] A specific aspect of the present disclosure provides a DAC circuit that generally includes: a first DAC and a first set of one or more switches coupled between an output of the first DAC and a first output of the DAC circuit; a second DAC and a second set of one or more switches coupled between the output of the second DAC and a second output of the DAC circuit; a third DAC and a third set of one or more switches coupled between the output of the third DAC and a third output of the DAC circuit; a fourth DAC and a fourth set of one or more switches coupled between the output of the fourth DAC and a fourth output of the DAC circuit; a fifth set of one or more switches coupled between the output of the first DAC and a fifth output of the DAC circuit; a sixth set of one or more switches coupled between the output of the second DAC and the fifth output of the DAC circuit; a seventh set of one or more switches coupled between the output of the third DAC and the sixth output of the DAC circuit; and an eighth set of one or more switches coupled between the output of the fourth DAC and the sixth output of the DAC circuit.

[0007] Certain aspects of the present disclosure provide a wireless device comprising the DAC circuit described herein, generally further including a first mixer configured to receive a first oscillating signal and a second mixer configured to receive a second oscillating signal, the second oscillating signal being phase shifted 90 degrees relative to the first oscillating signal.

[0008] A particular aspect of the present disclosure provides a DAC circuit that generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit having at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit having at least two channels for a second set of one or more frequency bands different from the first set of frequency bands.

[0009] Certain aspects of the present disclosure provide a method for wireless communication. The method generally includes configuring a DAC circuit in a first configuration configured to support at least four channels, converting a plurality of first digital signals to a plurality of first analog signals using the DAC circuit in the first configuration, configuring the DAC circuit in a second configuration configured to support at least one but less than four channels, and converting a plurality of second digital signals to one or more second analog signals using the DAC circuit in the second configuration.

[0010] To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of the various aspects may be employed, and the description is intended to include all such aspects and their equivalents. [Brief explanation of the drawings]

[0011]

[0011] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description thereof briefly summarized above can be had by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only certain exemplary embodiments of the present disclosure and therefore should not be considered as limiting the scope of the present disclosure, and that other equally effective embodiments may be recognized for the purposes of the description. [Figure 1]

[0012] FIG. 1 is a diagram of an example wireless communication network in which aspects of the present disclosure may be practiced. [Figure 2]

[0013] FIG. 1 is a block diagram conceptually illustrating an example base station (BS) and user equipment (UE) design in which aspects of the present disclosure may be practiced. [Figure 3]

[0014] 1 is a block diagram of an example radio frequency (RF) transceiver in which aspects of the present disclosure may be practiced. [Figure 4A]

[0015] FIG. 1 is a block diagram of a digital-to-analog converter (DAC) architecture that uses different DAC circuits for different sets of frequency bands. [Figure 4B]

[0016] FIG. 1 is a block diagram of an example reconfigurable DAC architecture that uses a single DAC circuit to support multiple different sets of frequency bands, in accordance with certain aspects of the present disclosure. [Figure 4C]

[0017] FIG. 1 is a block diagram of an example reconfigurable DAC architecture that uses a single DAC circuit to support different sets of frequency bands and different transmitter architectures, in accordance with certain aspects of the present disclosure. [Figure 5A]

[0018] FIG. 1 is a block diagram of a portion of an example wireless transmitter circuit having a reconfigurable DAC circuit supporting multiple different sets of frequency bands, in accordance with certain aspects of the present disclosure. [Figure 5B]

[0019] FIG. 1 is a block diagram of a portion of an example wireless transmitter circuit having a reconfigurable DAC circuit that supports different sets of frequency bands and different transmitter architectures, in accordance with certain aspects of the present disclosure. [Figure 6A]

[0020] FIG. 1 is a block diagram of a portion of an example transmitter front end configured to support sub-6 GHz frequency bands and coupled to a reconfigurable DAC circuit, in accordance with certain aspects of the present disclosure. [Figure 6B]

[0021] FIG. 1 is a block diagram of a portion of an example transmitter front end configured to support a millimeter wave (mmW) frequency band and coupled to a reconfigurable DAC circuit, in accordance with certain aspects of the present disclosure. [Figure 6C]

[0022] FIG. 1 is a block diagram of a portion of an example transmitter circuit having a reconfigurable DAC circuit supporting a dual-layer quadrature scheme in accordance with certain aspects of the present disclosure. [Figure 6D]

[0023] FIG. 1 is a block diagram of a portion of an example transmitter circuit having a reconfigurable DAC circuit supporting a dual-layer true intermediate-frequency (IF) scheme with interleaving, in accordance with certain aspects of the present disclosure. [Figure 6E]

[0024] FIG. 1 is a block diagram of a portion of an example transmitter circuit having a reconfigurable DAC circuit supporting a single-layer real IF scheme with interleaving, in accordance with certain aspects of the present disclosure. [Figure 6F]

[0025] FIG. 1 is a block diagram of a portion of an example transmitter circuit having a reconfigurable DAC circuit supporting a dual-layer real IF scheme without interleaving, in accordance with certain aspects of the present disclosure. [Figure 7]

[0026] FIG. 1 is a flow diagram of example operations for wireless communication in accordance with certain aspects of the present disclosure.

[0012]

[0027] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements common to the figures, and it is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION OF THE INVENTION

[0013]

[0028] Certain aspects of the present disclosure relate to techniques and apparatus for sharing DAC converters in a reconfigurable digital-to-analog (DAC) circuit to support two or more transmit (TX) chains of a radio frequency (RF) transceiver or transmitter. A reconfigurable DAC circuit, also referred to as a "converged DAC circuit," may be capable of supporting different radio access technologies (RATs) (using different sets of frequency bands) and / or different transmitter architectures. Using a single reconfigurable DAC circuit instead of multiple DAC circuits may reduce redundancy, save area and cost in integrated circuits (ICs), and reduce power consumption.

[0014]

[0029] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, the present disclosure may be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will understand that the scope of the present disclosure is intended to cover all aspects of the present disclosure disclosed herein, regardless of whether implemented independently or in combination with any other aspects of the present disclosure. For example, an apparatus can be implemented or a method can be practiced using any number of the aspects described herein. In addition, the scope of the present disclosure is intended to cover such apparatuses or methods that are practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the present disclosure described herein. It should be understood that any aspect of the present disclosure disclosed herein may be embodied by one or more elements of a claim.

[0015]

[0030] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0016]

[0031] As used herein, the term "connected to" in various tenses of the verb "connect" can mean that element A is directly connected to element B, or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the case of electrical components, the term "connected to" may also be used herein to mean the use of a wire, trace, or other conductive material to electrically connect element A and element B (and any components electrically connected between them).

[0017]

[0032] As used herein, a "transmit processor," "baseband processor," or "transmit front-end (TXFE) processor" generally refers to logic, such as phase control logic and delay control logic, for processing digital signals received from a modulator-demodulator (modem) before the digital signals are converted to analog signals by a DAC for upconversion, filtering, amplification, and transmission. A baseband processor may also be referred to as a "digital baseband transmit processor."

[0018] Exemplary Wireless System

[0033] 1 illustrates an example wireless communication network 100 in which aspects of the present disclosure may be practiced. For example, the wireless communication network 100 may be a New Radio (NR) system (e.g., a Fifth Generation (5G) NR network), an Evolved Universal Terrestrial Radio Access (E-UTRA) system (e.g., a Fourth Generation (4G) network), a Universal Mobile Telecommunications System (UMTS) (e.g., a Second Generation / Third Generation (2G / 3G) network), or a Code Division Multiple Access (CDMA) system (e.g., a 2G / 3G network), or may be configured for communication according to an IEEE standard, such as one or more of the 802.11 standards.

[0019]

[0034] 1, wireless communication network 100 may include several base stations (BSs) 110a-110z (each also referred to herein individually as a “BS 110” or collectively as “BSs 110”) and other network entities. A BS may also be referred to as an access point (AP), an evolved Node B (eNodeB or eNB), a next generation Node B (gNodeB or gNB), or some other terminology.

[0020]

[0035] The BSs 110 may provide communication coverage for a particular geographic area, sometimes referred to as a “cell,” which may be fixed or may move according to the location of a mobile BS. In some examples, the BSs 110 may be interconnected via various types of backhaul interfaces (e.g., direct physical connections, wireless connections, virtual networks, etc.) using any suitable transport network and / or to one or more other BSs or network nodes (not shown) in the wireless communication network 100. In the example shown in FIG. 1 , BSs 110a, 110b, and 110c may be macro BSs of macro cells 102a, 102b, and 102c, respectively. BS 110x may be a pico BS of pico cell 102x. BSs 110y and 110z may be femto BSs of femto cells 102y and 102z, respectively. A BS may support one or more cells.

[0021]

[0036] The BS 110 communicates with one or more user equipments (UEs) 120a-120y (each also referred to herein individually as a “UE 120” or collectively as “UE 120”) in the wireless communication network 100. The UEs may be fixed or mobile and may also be referred to as user terminals (UTs), mobile stations (MSs), access terminals, stations (STAs), clients, wireless devices, mobile devices, or some other terminology. A user terminal may be a wireless device such as a cellular phone, a smartphone, a personal digital assistant (PDA), a handheld device, a wearable device, a wireless modem, a laptop computer, a tablet, a personal computer, etc.

[0022]

[0037] The BS 110 is considered a transmitting entity on the downlink and a receiving entity on the uplink. The UE 120 is considered a transmitting entity on the uplink and a receiving entity on the downlink. As used herein, a "transmitting entity" is an independently operating apparatus or device capable of transmitting data over a frequency channel, and a "receiving entity" is an independently operating apparatus or device capable of receiving data over a frequency channel. In the following description, the subscript "dn" refers to the downlink and the subscript "up" refers to the uplink. N simultaneous transmissions on the uplink are allowed. up UEs may be selected to transmit simultaneously on the downlink. dn N UEs may be selected. up is N dn may or may not be equal to N up and N dn Θ may be a static value or may change at each scheduling interval. Beam-steering or some other spatial processing technique may be used at BS 110 and / or UE 120.

[0023]

[0038] The UEs 120 (e.g., 120x, 120y, etc.) may be dispersed throughout the wireless communication network 100, and each UE 120 may be fixed or mobile. The wireless communication network 100 may also include relay stations (e.g., relay station 110r), which may also be referred to as relays, that receive transmissions of data and / or other information from an upstream station (e.g., BS 110a or UE 120r), forward transmissions of data and / or other information to a downstream station (e.g., UE 120 or BS 110), or relay transmissions between UEs 120 to facilitate communication between the devices.

[0024]

[0039] The BS 110 may communicate with one or more UEs 120 at any given moment on the downlink and the uplink. The downlink (i.e., forward link) is the communication link from the BS 110 to the UEs 120, and the uplink (i.e., reverse link) is the communication link from the UEs 120 to the BS 110. A UE 120 may also communicate peer-to-peer with another UE 120.

[0025]

[0040] The wireless communication network 100 may use multiple transmit antennas and multiple receive antennas for data transmission on the downlink and uplink. The BS 110 may use N transmit antennas and multiple receive antennas to achieve transmit diversity for downlink transmissions and / or receive diversity for uplink transmissions. ap It can be equipped with N antennas. u A set of UEs 120 may receive downlink transmissions and transmit uplink transmissions. Each UE 120 may transmit user-specific data to and / or receive user-specific data from the BS 110. In general, each UE 120 may be equipped with one or multiple antennas. u The UEs 120 may have the same or different number of antennas.

[0026]

[0041] The wireless communication network 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. In a TDD system, the downlink and uplink share the same frequency band. In an FDD system, the downlink and uplink use different frequency bands. The wireless communication network 100 may also utilize a single carrier or multiple carriers for transmission. Each UE 120 may be equipped with a single antenna (e.g., to keep costs down) or multiple antennas (e.g., if the additional cost can be supported).

[0027]

[0042] A network controller 130 (sometimes referred to as a “system controller”) may communicate with the set of BSs 110 to provide coordination and control for these BSs 110 (e.g., via a backhaul). In certain cases (e.g., in a 5G NR system), the network controller 130 may include a centralized unit (CU) and / or a distributed unit (DU). In certain aspects, the network controller 130 may be in communication with a core network 132 (e.g., a 5G Core Network (5GC)), which provides various network functions such as access and mobility management, session management, user plane functions, policy control functions, authentication server functions, integrated data management, application functions, network exposure functions, network repository functions, and network slice selection functions.

[0028]

[0043] In certain aspects of the present disclosure, the BS 110 and / or the UE 120 may include transmitter circuitry having a reconfigurable digital-to-analog converter (DAC) circuit capable of supporting multiple radio access technologies (RATs), sets of frequency bands, and / or transmitter architectures and outputting analog signals to two or more transmit chains, as described in detail herein.

[0029]

[0044] FIG. 2 illustrates example components of a BS 110a and a UE 120a (eg, from the wireless communication network 100 of FIG. 1) in which aspects of the present disclosure may be implemented.

[0030]

[0045] On the downlink, at the BS 110a, the transmit processor 220 may receive data from the data source 212, control information from the controller / processor 240, and / or possibly other data (e.g., from the scheduler 244). Various types of data may be sent on different transport channels. For example, control information may be designated for a physical broadcast channel (PBCH), a physical control format indicator channel (PCFICH), a physical hybrid automatic repeat request (HARQ) indicator channel (PHICH), a physical downlink control channel (PDCCH), a group common PDCCH (GC PDCCH), etc. Data may be designated for a physical downlink shared channel (PDSCH), etc. A medium access control (MAC) control element (MAC-CE) is a MAC layer communication structure that may be used for control command exchange between wireless nodes. The MAC-CE may be carried in a shared channel, such as a PDSCH, a physical uplink shared channel (PUSCH), or a physical sidelink shared channel (PSSCH).

[0031]

[0046] The processor 220 may process (e.g., encode and symbol map) the data and control information to obtain data symbols and control symbols, respectively. The transmit processor 220 may also generate reference symbols for a primary synchronization signal (PSS), a secondary synchronization signal (SSS), a PBCH demodulation reference signal (DMRS), and a channel state information reference signal (CSI-RS), etc.

[0032]

[0047] A transmit (TX) multiple-input, multiple-output (MIMO) processor 230 may perform spatial processing (e.g., precoding) on ​​the data symbols, control symbols, and / or reference symbols, if applicable, and may provide output symbol streams to modulators (MODs) in transceivers 232a through 232t. Each modulator in transceivers 232a through 232t may process a respective output symbol stream (e.g., using orthogonal frequency division multiplexing (OFDM)) to obtain an output sample stream. Each of transceivers 232a through 232t may further process (e.g., convert to analog, amplify, filter, and upconvert) the output sample stream to obtain a downlink signal. The downlink signals from transceivers 232a through 232t may be transmitted via antennas 234a through 234t, respectively.

[0033]

[0048] At UE 120a, antennas 252a through 252r may receive downlink signals from BS 110a and may provide received signals to transceivers 254a through 254r, respectively. Transceivers 254a through 254r may condition (e.g., filter, amplify, downconvert, and digitize) the respective received signals to obtain input samples. Each demodulator (DEMOD) in transceivers 232a through 232t may further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. A MIMO detector 256 may obtain received symbols from all demodulators in transceivers 254a through 254r, perform MIMO detection on the received symbols if applicable, and provide detected symbols. A receive processor 258 may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for UE 120a to a data sink 260, and provide decoded control information to a controller / processor 280.

[0034]

[0049] On the uplink, at the UE 120a, a transmit processor 264 may receive and process data from a data source 262 (e.g., on a physical uplink shared channel (PUSCH)) and control information from a controller / processor 280 (e.g., on a physical uplink control channel (PUCCH)). The transmit processor 264 may also generate reference symbols for a reference signal (e.g., a sounding reference signal (SRS)). The symbols from the transmit processor 264 may be precoded by a TX MIMO processor 266, processed by modulators (MODs) in transceivers 254a through 254r (e.g., for single-carrier frequency division multiplexing (SC-FDM), etc.), and transmitted to the BS 110a. At BS 110a, the uplink signal from UE 120a may be received by antenna 234, processed by demodulators within transceivers 232a-232t, detected by a MIMO detector 236 if applicable, and further processed by a receive processor 238 to obtain decoded data and control information sent by UE 120a. Receive processor 238 may provide the decoded data to a data sink 239 and the decoded control information to a controller / processor 240.

[0035]

[0050] Memories 242 and 282 may store data and program codes for BS 110a and UE 120a, respectively. Memories 242 and 282 may also interface with controllers / processors 240 and 280, respectively. Scheduler 244 may schedule UEs for data transmission on the downlink and / or uplink.

[0036]

[0051] Antenna 252, processors 258, 264, 266, and / or controller / processor 280 of UE 120a and / or antenna 234, processors 220, 230, 238, and / or controller / processor 240 of BS 110a may be used to implement various techniques and methods described herein.

[0037]

[0052] In certain aspects of the present disclosure, transceiver 232 and / or transceiver 254 may include transmitter circuitry having reconfigurable digital-to-analog converter (DAC) circuitry capable of supporting different radio access technologies (RATs), different sets of one or more frequency bands, and / or different transmitter architectures and outputting analog signals to two or more transmit chains, as described in detail herein.

[0038] Exemplary RF Transceiver

[0053] 3 is a block diagram of an example radio frequency (RF) transceiver circuit 300 according to certain aspects of the present disclosure. The RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also referred to as a “transmit chain”) for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also referred to as a “receive chain”) for receiving signals via the antenna 306. When the TX path 302 and the RX path 304 share the antenna 306, these paths may be connected to the antenna via an interface 308, which may include any of a variety of suitable RF devices, such as a switch, a duplexer, a diplexer, a multiplexer, etc.

[0039]

[0054] The TX path 302, which receives in-phase (I) and / or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, mixer 314, DA 316, and PA 318 may be included within a radio frequency integrated circuit (RFIC). In certain aspects, the PA 318 may be external to the RFIC.

[0040]

[0055] The BBF 312 filters the baseband signal received from the DAC 310, and the mixer 314 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to translate the baseband signal of interest to a different frequency (e.g., upconvert from baseband to radio frequency). This frequency translation process generates sum and difference frequencies between the LO frequency and the frequency of the baseband signal. The sum and difference frequencies are called "beat frequencies." The beat frequencies are typically in the RF range; therefore, the signal output by the mixer 314 is typically an RF signal that can be amplified by the DA 316 and / or PA 318 before transmission by the antenna(s) 306. Although one mixer 314 is shown, several mixers may be used to upconvert the filtered baseband signal to one or more intermediate frequencies and then upconvert the intermediate frequency (IF) signal to a frequency for transmission.

[0041]

[0056] The RX path 304 may include a low noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, mixer 326, and BBF 328 may be included in one or more RFICs, which may or may not be the same as the RFIC(s) containing the TX path components. RF signals received via the antenna(s) 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signal with a receive local oscillator (LO) signal to convert (e.g., downconvert) the RF signal to a different baseband frequency. The baseband signal output by the mixer 326 may be filtered by the BBF 328 before being converted to digital I and / or Q signals by an analog-to-digital converter (ADC) 330 for digital signal processing.

[0042]

[0057] A particular transceiver may employ a frequency synthesizer having a variable frequency oscillator (e.g., a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a particular tuning range. Thus, the transmit LO may be generated by the TX frequency synthesizer 320. Thus, the transmit LO may be buffered or amplified by an amplifier 322 before being mixed with the baseband signal in the mixer 314. Similarly, the receive LO may be generated by the RX frequency synthesizer 332. Similarly, the receive LO may be buffered or amplified by an amplifier 334 before being mixed with the RF signal in the mixer 326. In a particular aspect, a single frequency synthesizer may be used for both the TX path 302 and the RX path 304. In certain aspects, the TX frequency synthesizer 320 and / or the RX frequency synthesizer 332 may include a frequency multiplier, such as a frequency doubler, driven by an oscillator (eg, a VCO) within the frequency synthesizer.

[0043]

[0058] A controller 336 (e.g., controller / processor 280 of FIG. 2) may direct operation of the RF transceiver circuit 300A, such as transmitting signals via the TX path 302 and / or receiving signals via the RX path 304. The controller 336 may be a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. A memory 338 (e.g., memory 282 of FIG. 2) may store data and / or program code for operating the RF transceiver circuit 300. The controller 336 and / or memory 338 may include control logic (e.g., complementary metal-oxide-semiconductor (CMOS) logic).

[0044] Exemplary Multiple Separate Transmit DAC Circuits

[0059] In a transmitter supporting different radio access technologies (RATs), each RAT may be supported by at least one transmit chain (e.g., TX path 302), which may comprise one complete set of dedicated circuit elements, such as a transmit processor, DAC 310, BBF 312, mixer 314, DA 316, and PA 318. Each transmit chain may include such a separate set of dedicated elements due, for example, to the different frequency, noise, power, and / or distortion specifications of each RAT. For example, a single wireless device supporting Cellular Vehicle-to-Everything (C-V2X), 5G sub-6 GHz (or Frequency Range 1 (FR1)), and 5G Millimeter Wave (or Frequency Range 2 (FR2)) communications may include TX chains, each including a respective set of dedicated circuit elements, such as those listed above.

[0045]

[0060] 4A is a block diagram of a digital-to-analog converter (DAC) architecture 400A that uses different DAC circuits 402, 404 for different sets of frequency bands (or different radio access technologies (RATs)). As shown in FIG. 4A, the DAC architecture 400A is configured to support two different sets of frequency bands: sub-6 GHz and mmW. Thus, the DAC architecture 400A may include two DAC circuits: a sub-6 GHz DAC circuit 402 and an mmW DAC circuit 404.

[0046]

[0061] In some cases, a harmonic rejection mixer (HRM) scheme may be used for some frequency bands (e.g., sub-6 GHz frequency bands, but may additionally or alternatively be used for mmW frequency bands). The HRM scheme may include generating four phase-shifted outputs at the transmitter. Thus, the sub-6 GHz outputs 406 from the DAC circuit 402 may include a sub-6 GHz in-phase channel (sub6_Ich), a sub-6 GHz quadrature-phase channel (sub6_Qch) that is phase-shifted 90° relative to the in-phase channel, a sub-6 GHz 45° phase-shifted channel (sub6_I45ch), and a sub-6 GHz 135° phase-shifted channel (sub6_Q45ch). Each of the sub-6 GHz outputs 406 may be an input to a corresponding transmit chain (e.g., TX path 302). In other aspects, the sub-6 GHz mode may use only two outputs (e.g., sub6_Ich and sub6_Qch) when the HRM scheme is not used.

[0047]

[0062] Two phase-shifted outputs may be generated by the transmitter in mmW mode. The mmW outputs 408 from the DAC circuit 404 may include a mmW in-phase channel (mmW_Ich) and a mmW quadrature channel (mmW_Qch). Each of the mmW outputs 408 may be an input to a corresponding transmit chain.

[0048]

[0063] Although a transceiver may include multiple TX chains, in certain aspects, a limited number of TX chains may be used simultaneously. Furthermore, simultaneous transmission of a certain RAT from a single device may be prevented. For example, a sub-6 GHz (or C-V2X) transmit chain and an mmW transmit chain may not be enabled at the same time. For example, when the sub-6 GHz DAC circuit 402 is in use, the mmW DAC circuit 404 may be idle (or vice versa). However, even when one DAC circuit is idle, this idle circuit may still consume power. Therefore, providing a separate DAC circuit for each individual TX chain is considered redundant, wastes chip area, consumes power unnecessarily, and is not cost-effective.

[0049] Exemplary Reconfigurable Transmit DAC Circuit

[0064] Certain aspects of the present disclosure provide a reconfigurable transmit DAC circuit (also referred to as a "convergent DAC circuit") that can support multiple (and / or different sets of one or more frequency bands) to reduce redundancy, save integrated circuit (IC) area and cost, and potentially reduce power consumption. The reconfigurable DAC circuit comprises a shared set of DACs with outputs coupled to multiple switches that can route the DAC outputs to different transmit chains supporting different RATs (and / or different frequency bands). Additionally or alternatively, in certain aspects, the reconfigurable DAC circuit is reconfigurable to support different transmitter architectures, such as zero intermediate frequency (IF), complex IF, and real IF architectures, as well as single-layer and dual-layer transmitter architectures, with or without interleaving, enabling more versatile transmitters. Such a reconfigurable DAC circuit can support a wide range of full-scale currents (I FS) It may support scalability, may be able to drive different baseband filters and / or different mixer interfaces, and may operate with different sampling rates and clock phase specifications.

[0050]

[0065] 4B is a block diagram of an example DAC architecture using a reconfigurable DAC circuit 410B (labeled "converged DAC circuit") according to certain aspects of the present disclosure. The reconfigurable DAC circuit 410B may support different RATs and / or different sets of frequency bands, such as sub-6 GHz and mmW frequency bands (in 5G or C-V2X). While sub-6 GHz frequency bands and mmW frequency bands are used throughout this disclosure, it should be understood that these terms may be interchangeable with Frequency Range 1 (FR1) and Frequency Range 2 (FR2) frequency bands, respectively, unless explicitly or implicitly specified otherwise (e.g., by context).

[0051]

[0066] To support a sub-6 GHz harmonic rejection mixer (HRM) architecture, reconfigurable DAC circuit 410B may include four DACs: DAC412, DAC414, DAC416, and DAC418 (sometimes referred to as "sub-DACs" or "DAC cores"). While four DACs are shown in FIG. 4B, the reader should understand that the reconfigurable DAC circuit is not so limited and may include any suitable number of DACs. In certain aspects, DAC 412 (labeled "I") is designated as an in-phase (I) DAC, indicating that DAC 412 is configured to support the I channel in an HRM architecture. Similarly, DAC 414 (labeled "Q") may be designated as a quadrature (Q) DAC, indicating that DAC 414 is configured to support the Q channel in an HRM architecture. Continuing, DAC416 (labeled "I45") may be designated as a 45° phase-shifted DAC (I45), indicating that DAC416 is configured to support an I45 channel in an HRM architecture, and DAC418 (labeled "Q45") may be designated as a 135° phase-shifted quadrature DAC (Q45), indicating that DAC418 is configured to support a Q45 channel in an HRM architecture.

[0052]

[0067] In certain aspects, DAC 412 may be located physically adjacent to DAC 414 (e.g., to increase residual sideband (RSB) rejection in certain DAC circuit configurations). Additionally or alternatively, DAC 416 may be located physically adjacent to DAC 418. In other aspects, DAC 412 may be located physically adjacent to DAC 416 and / or DAC 414 may be located physically adjacent to DAC 418.

[0053]

[0068] The reconfigurable DAC circuit 410B may have at least six outputs, including four sub-6 GHz outputs 406 and two mmW outputs 408, as shown in FIG. 4B . To support reconfiguration, the DAC circuit 410B may include one or more sets of switches coupled between each output of the DACs 412, 414, 416, and 418 and the output of the DAC circuit 410B. In other words, each output of the DACs 412, 414, 416, and 418 may be selectively coupled to different outputs of the DAC circuit 410B by multiple sets of switches. The sets of switches are used to route the outputs of the DACs 412, 414, 416, and 418 to one or more transmit chains supporting the RAT (or frequency band) currently selected for the transmitter including the reconfigurable DAC circuit 410B. Each switch may be implemented by a transistor, a transmit gate, or any other suitable component for performing the function of a switch. A controller (eg, controller 336 in FIG. 3) can control the state (open or closed) of the switches in reconfigurable DAC circuit 410B.

[0054]

[0069] 4B, a first set of switches S1 may be coupled between the output of DAC 412 and the sub6_Ich output of DAC circuit 410B, a second set of switches S2 may be coupled between the output of DAC 414 and the sub6_Qch output of DAC circuit 410B, a third set of switches S3 may be coupled between the output of DAC 416 and the sub6_I45ch output of DAC circuit 410B, and a fourth set of switches S4 may be coupled between the output of DAC 418 and the sub6_Q45ch output of DAC circuit 410B. Sets S1-S4 of switches may be closed to support sub-6 GHz mode (using a four-channel HRM scheme).

[0055]

[0070] To support DAC convergence and reconfigurability, DAC circuit 410B also includes a fifth set of switches S5 coupled between the output of DAC 412 and the mmW_Ich output of DAC circuit 410B. In certain aspects, DAC circuit 410B also includes a sixth set of switches S6 coupled between the output of DAC 414 and the mmW_Ich output of DAC circuit 410B. That is, the mmW_Ich output of DAC circuit 410B may be shorted or otherwise coupled to both the fifth and sixth sets of switches S5, S6, as shown in FIG. 4B . Furthermore, DAC circuit 410B may include a seventh set of switches S7 coupled between the output of DAC 416 and the mmW_Qch output of DAC circuit 410B. In certain aspects, DAC circuit 410B also includes an eighth set of switches S8 coupled between the output of DAC 418 and the mmW_Qch output of DAC circuit 410B. In other words, the mmW_Qch output of DAC circuit 410B may be shorted or otherwise coupled to both the seventh and eighth sets of switches S7, S8 as shown in FIG. 4B.

[0056]

[0071] In certain aspects, any two of the fifth through eighth sets of switches S5-S8 may be closed to support the mmW mode (having two channels). In other aspects, any two of the fifth through eighth sets of switches S5-S8 (e.g., the fifth and seventh sets S5, S7) may be closed during a first interval, and two different sets of the fifth through eighth sets of switches S5-S8 (e.g., the sixth and eighth sets S6, S8) may be alternately closed during a second interval following the first interval to support the mmW mode using interleaving (e.g., for a faster DAC circuit sampling rate).

[0057]

[0072] As described above, sets of switches can be used to route the outputs of DAC412, DAC414, DAC416, and DAC418 to selected transmit chains. For example, when DAC circuit 410B is configured to support sub-6 GHz mode (and associated frequency bands), first through fourth sets of switches S1 through S4 coupled between the outputs of DAC412, DAC414, DAC416, and DAC418 and sub-6 GHz output 406 are closed, and fifth through eighth sets of switches S5 through S8 coupled to mmW output 408 are open. This routes the outputs of DAC412, DAC414, DAC416, and DAC418 to the four outputs used by the sub-6 GHz mode (in the HRM scheme).

[0058]

[0073] Because the mmW mode may not be able to utilize the HRM scheme, the mmW mode may use only two outputs of DAC circuit 410B (one for in-phase and one for quadrature). However, because reconfigurable DAC circuit 410B includes four DACs in the example of FIG. 4B , signals from pairs of outputs of the four DACs, i.e., DAC412, DAC414, DAC416, and DAC418, may be interleaved. When DAC circuit 410 is configured to support the mmW mode (and associated frequency band), during the first interval, the first through fourth sets of switches S1-S4 may remain open to route the outputs of two of DAC412, DAC414, DAC416, and DAC418 to the mmW transmit chain, and one set of two switches coupled to each of the mmW outputs 408 may be closed while the other set of switches in the pair may be open. Then, during a second interval, a previously closed set of switches coupled to each of the mmW outputs 408 may be opened, and a previously opened set of switches coupled to each of the mmW outputs 408 may be closed. The first and second intervals may alternate, thereby interleaving the outputs of DAC412, DAC414, DAC416, and DAC418. For example, during the first interval, the set of switches S5 and S7 may be closed and the set of switches S6 and S8 may be open, thereby routing the output of DAC412 to the mmW_Ich output and the output of DAC416 to the mmW_Qch output. Then, during the second interval, the set of switches S5 and S7 may be opened and the set of switches S6 and S8 may be closed, thereby routing the output of DAC414 to the mmW_Ich output and the output of DAC418 to the mmW_Qch output. In this manner, the reconfigurable DAC circuit 410B can be configured as an interleaved DAC circuit having two channels, mmW_Ich and mmW_Qch.

[0059]

[0074] Alternatively, in certain aspects, reconfigurable DAC circuit 410B may not be configured to interleave in mmW mode, in which case, in mmW mode, set S1-S4 of switches may be open, two sets of sets S5-S8 of switches (e.g., set S5 and set S7) may be closed, and two other sets of sets S5-S8 of switches (e.g., set S6 and set S8) may be open.

[0060]

[0075] Although DAC412, DAC414, DAC416, and DAC418 are shown in FIG. 4B as having single-ended outputs coupled to the single-ended output of DAC circuit 410B, each DAC may have a differential output selectively coupled to the differential output of the DAC circuit by a switch (e.g., as shown in FIG. 5A).

[0061]

[0076] 5A is a block diagram of a portion of an example wireless transmitter circuit 500A according to certain aspects of the present disclosure. The wireless transmitter circuit 500A may include a mmW finite impulse response (FIR) filter 502, a sub-6 GHz FIR filter 504, a multiplexer (MUX) 506, processing circuitry 508, and a reconfigurable DAC circuit 509 configured to support multiple different sets of frequency bands. The reconfigurable DAC circuit 509 may include a DAC 510, a DAC 512, a DAC 514, a DAC 516, a clock distribution circuit 513 (labeled "Clk-Rx"), and a MUX 515. The DACs 510, DAC 512, DAC 514, and DAC 516, in certain aspects, provide scalable full-scale current (I FS ).

[0062]

[0077] At least a portion of the mmW FIR filter 502, the sub-6 GHz FIR filter 504, the MUX 506, and the processing circuitry 508 may be part of a processor, such as a baseband processor. The mmW FIR filter 502 may receive and filter n-bit digital in-phase and quadrature-phase mmW inputs (labeled “Din_mmW_I” and “Din_mmW_Q,” respectively), which may be received, for example, from a modem or another part of a processor. Similarly, the sub-6 GHz FIR filter 504 may receive and filter n-bit digital in-phase and quadrature-phase sub-6 GHz inputs (labeled “Din_mmW_I” and “Din_mmW_Q,” respectively), which may also be received, for example, from a modem or another part of a processor. The MUX 506 may be used to select between the output of the mmW FIR filter 502 and the output of the sub-6 GHz FIR filter 504 for routing to the processing circuitry 508. Processing circuitry 508 may include, for example, at least one of a decoder, a parallel-to-serial converter, and a level shifter. The n-bit digital outputs of processing circuitry 508 (labeled “Din_I,” “Din_Q,” “Din_I45,” and “Din_Q45”) may be routed to corresponding DACs in reconfigurable DAC circuit 509.

[0063]

[0078] 4B, and DACs 510, 512, 514, and 516 may be similar to DACs 412, 414, 416, and 418, respectively, except that reconfigurable DAC circuit 509 has differential outputs, DACs 510, 512, 514, and 516 have differential outputs, and each set of switches S1-S8 includes a pair of switches (indicated by the designations "a" and "b"). For example, the first set of switches S1 includes switches S1a and S1b coupled between the differential output of DAC 510 and the sub6 Ich differential output. Similarly, the second set of switches S2 includes switches S2a and S2b coupled between the differential output of DAC512 and the sub6_Qch differential output, the third set of switches S3 includes switches S3a and S3b coupled between the differential output of DAC514 and the sub6_I45ch differential output, and the fourth set of switches S4 includes switches S4a and S4b coupled between the differential output of DAC516 and the sub6_Q45ch differential output. To support the mmW frequency band in the reconfigurable DAC circuit, a fifth set of switches S5 includes switches S5a and S5b coupled between the differential output of DAC510 and the mmW_Ich differential output, a sixth and ninth set of switches S6 includes switches S6a and S6b coupled between the differential output of DAC512 and the mmW_Ich differential output, a seventh set of switches S7 includes switches S7a and S7b coupled between the differential output of DAC514 and the mmW_Qch differential output, and an eighth set of switches S8 includes switches S8a and S8b coupled between the differential output of DAC516 and the mmW_Qch differential output.

[0064]

[0079] MUX 515 may receive clock signals from multiple sources (e.g., multiple frequency synthesizers such as TX frequency synthesizer 320 in FIG. 3) and select one of the received clock signals for output to clock distribution circuit 513. This selection may be controlled by a control signal (e.g., from controller 336) received by a control input of MUX 515. In certain aspects, as shown in FIG. 5A, MUX 515 may be implemented as a single-pole, double-throw (SPDT) switch. In the example of FIG. 5A, MUX 515 may receive a clock signal corresponding to the sub-6 GHz frequency band (labeled “Pll_sub6”) and a clock signal corresponding to the mmW frequency band (labeled “Pll_mmW”).

[0065]

[0080] Clock distribution circuit 513 can output multiple clock lines for routing to different DACs in reconfigurable DAC circuit 509. In certain aspects, clock distribution circuit 513 may output a different clock line to each of the multiple DACs. For example, as shown in FIG. 5A , clock distribution circuit 513 can output four clock lines Clk1-Clk4, one for each of the four DACs in reconfigurable DAC circuit 509. In this case, clock line Clk1 may be coupled between a first output of clock distribution circuit 513 and a clock input of DAC 510, clock line Clk2 may be coupled between a second output of clock distribution circuit 513 and a clock input of DAC 512, clock line Clk3 may be coupled between a third output of clock distribution circuit 513 and a clock input of DAC 514, and clock line Clk4 may be coupled between a fourth output of clock distribution circuit 513 and a clock input of DAC 516. By routing a different clock line to each DAC of the multiple DACs, each clock line may be separately calibrated (e.g., by adjusting the delay of each output of the clock distribution circuit), and thus the sample timing of each DAC in the reconfigurable DAC circuit can be separately controlled despite different physical lengths in the clock lines (and therefore different delays due to the clock lines). In other aspects, at least some of the DACs may share at least one clock line from the clock distribution circuit 513, so that for four DACs there are fewer than four clock lines.

[0066]

[0081] The ninth set of switches in reconfigurable DAC circuit 509 of Figure 5A may be operated in the same manner as the corresponding set of switches S1-S8 in reconfigurable DAC circuit 410B of Figure 4B. For example, when sub-6 GHz mode is selected, a Pll_sub6 clock signal may be selected by MUX 515 and distributed from clock distribution circuit 513, switches S1a, S1b, S2a, S2b, S3a, S3b, and S4a and S4b may be closed, and the remaining switches S5a-S8b may be open, thus routing the differential outputs of DACs 510-514 to the respective differential sub-6 GHz outputs of DAC circuit 509. The operation of sets of switches S1-S8, with or without interleaving, when wireless transmitter circuit 500A is in mmW mode was described above with respect to Figure 4B and need not be repeated here.

[0067]

[0082] 6A is a block diagram of a portion of an example transmitter front-end 600A configured to support sub-6 GHz frequency bands and coupled to the output of a reconfigurable DAC circuit 509 selected to operate in a sub-6 GHz mode, in accordance with certain aspects of the present disclosure. It should be understood that because transmitter front-end 600A is operating in a sub-6 GHz mode, a set of switches S1-S4 in reconfigurable DAC circuit 509 are closed (although not explicitly shown) and a set of switches S5-S8 are open (although not shown) to route the outputs of DACs 510, 512, 514, and 516 to the transmit path for sub-6 GHz transmission.

[0068]

[0083] The transmitter front-end 600A includes four transmit paths for sub-6 GHz transmission using the HRM scheme. Each of the four sub-6 GHz differential outputs (Sub6_Ich, Sub6_Qch, Sub6_I45ch, and Sub6_Q45ch) of the DAC circuit 509 may be coupled to a different transmit path. Each of the four transmit paths includes a baseband filter (one of baseband filters 610, 612, 614, and 616) and a mixer (one of mixers 618, 620, 622, and 624). Each of the baseband filters 610, 612, 614, and 616 may be similar to the BBF 312, and each of the mixers 618, 620, 622, and 624 may be similar to the mixer 314. 6A , the differential output (and sub_Ich) of DAC 510 is coupled to the differential input of baseband filter (BBF) 610, whose differential output is coupled to the differential input of mixer 618. Mixer 618 can also receive an in-phase local oscillator signal (labeled “LO0”), which is why DAC 510 can be designated as an in-phase DAC (IDAC) in sub-6 GHz mode. The differential output (and sub_Qch) of DAC 512 is coupled to the differential input of BBF 614, whose differential output is coupled to the differential input of mixer 622. Mixer 618 can also receive a quadrature local oscillator signal that is phase-shifted 90° (labeled “LO90”) relative to the in-phase local oscillator signal, which is why DAC 512 can be designated as a quadrature DAC (QDAC) in sub-6 GHz mode. The differential output of DAC514 (and sub_I45ch) is coupled to the differential input of BBF612, whose differential output is coupled to the differential input of mixer 620. Mixer 620 can also receive a local oscillator signal that is phase shifted 45° relative to the in-phase local oscillator signal (labeled “LO45”), which is why DAC514 may be designated as an I45DAC. The differential output of DAC516 (and sub_Q45ch) is coupled to the differential input of BBF616, whose differential output is coupled to the differential input of mixer 624.Mixer 624 may also receive a local oscillator signal that is phase shifted by 135° relative to the in-phase local oscillator signal (and 45° relative to the quadrature-phase local oscillator signal) (labeled "LO135"), which is why DAC 516 may be designated as a Q45 DAC.

[0069]

[0084] The transmitter front end 600A also includes an amplifier 626, which may represent a driver amplifier and / or a power amplifier (e.g., DA 316 and / or PA 318 in FIG. 3). Differential outputs from each transmit path (e.g., the output of each mixer) may be combined and coupled to the input of the amplifier 626.

[0070]

[0085] 6B is a block diagram of a portion of an example transmitter front-end 600B configured to support the mmW frequency band and coupled to the output of a reconfigurable DAC circuit 509 selected to operate in mmW mode, according to certain aspects of the present disclosure. It should be understood that because transmitter front-end 600B is operating in mmW mode, a set of switches S1-S4 in reconfigurable DAC circuit 509 are opened (although not explicitly shown) and a set of switches S5-S8 are selectively closed (although not shown) to route the outputs of DACs 510, 512, 514, and 516 to the transmit path for mmW transmission, with or without interleaving (as described above).

[0071]

[0086] As shown in FIG. 6B , the transmitter front-end 600B includes two transmit paths for mmW transmission. Each of the mmW differential outputs (mmW_Ich and mmW_Qch) of the DAC circuit 509 may be coupled to a different transmit path. Each of the two transmit paths includes a mixer (one of mixers 630, 632). Each of the mixers 630, 632 may be similar to the mixer 314. Due to interleaving, the differential output of the DAC 510 or DAC 512 may be coupled to the mmW_Ich output of the reconfigurable DAC circuit 509. The mmW_Ich output may be coupled to a differential input of the mixer 630. The mixer 630 may also receive an in-phase local oscillator signal (labeled “LO0”), which is why this differential output of the DAC circuit 509 is designated as “mmW_Ich.” The differential output (based on interleaving) of DAC 514 or DAC 516 may be coupled to the mmW_Qch output of reconfigurable DAC circuit 509. The mmW_Qch output may be coupled to the differential input of mixer 632. Mixer 632 may also receive a quadrature local oscillator signal (labeled "LO90"), which is why this differential output of DAC circuit 509 is designated as "mmW_Qch."

[0072]

[0087] Each of the transmit chains may include an optional baseband filter (BBF) disposed between the mmW outputs of the DAC circuit 509 and the inputs of each mixer 630, 632. For example, the differential mmW_Ich outputs may be coupled to the differential inputs of the BBF 628, whose differential outputs may be coupled to the differential inputs of the mixer 630. Similarly, the differential mmW_Qch outputs may be coupled to the differential inputs of the BBF 629, whose differential outputs may be coupled to the differential inputs of the mixer 632. Each of the BBFs 628, 629 may be similar to the BBF 312 in FIG. 3.

[0073]

[0088] The transmitter front end 600B also includes an amplifier 634, which may represent a driver amplifier and / or a power amplifier (e.g., DA 316 and / or PA 318 in FIG. 3). Differential outputs from each transmit path (e.g., the output of each mixer) may be combined and coupled to the input of the amplifier 634.

[0074] Exemplary Reconfigurable Transmit DAC Circuit Supporting More Than Two RATs (or Frequency Bands) and / or Multiple Transmitter Architectures

[0089] It may be desirable to provide a DAC circuit that can be reconfigured to support more or different frequency bands (or RATs) than sub-6 GHz and mmW frequency bands. Additionally or alternatively, it may be desirable to provide a DAC circuit that can be reconfigured to support different transmitter architectures. For example, the transmitter architecture shown in FIG. 3 is a zero intermediate frequency (IF) architecture in which a digital baseband signal is converted by a DAC circuit to an analog baseband signal, and the analog baseband signal is upconverted to a radio frequency (RF) signal for transmission. Other transmitter architectures (e.g., complex IF and real IF architectures) may include generating a digital IF signal from the digital baseband signal, converting the digital IF signal to an analog IF signal, and upconverting the analog IF signal to an RF signal for transmission. Different transmitter architectures have different advantages, which may make a particular architecture more or less suitable for a given scenario. For example, a real IF architecture may be preferred in certain mmW bands due to advantageous frequencies that allow low crosstalk, reduce power, reduce cable loss, and provide enhanced RSB rejection. In some designs, a real IF architecture may be preferred at lower bandwidths (e.g., <600 MHz), while a quadrature approach (e.g., a zero IF architecture) or a complex IF architecture may be preferred at higher bandwidths (e.g., 1000 MHz).

[0075]

[0090] Certain aspects of the present disclosure provide reconfigurable DAC circuits capable of supporting multiple transmitter architectures and / or more than two RATs (or frequency bands). Sharing a common reconfigurable DAC circuit can reduce redundancy, save chip area, and reduce power consumption.

[0076]

[0091] 4C is a block diagram of an example reconfigurable DAC circuit 410C configured to support multiple RATs, multiple frequency bands, and / or different transmitter architectures in accordance with certain aspects of the present disclosure. The reconfigurable DAC circuit 410C may be similar to the reconfigurable DAC circuit 410B, but with additional outputs and corresponding sets of switches to support, for example, multiple transmitter architectures and / or three or more RATs (or sets of frequency bands). For example, the reconfigurable DAC circuit 410C may be configured to support sub-6 GHz frequency bands, mmW frequency bands, real IF architectures, and dual-layer quadrature systems (legacy mmW architectures). For systems that support intermediate frequency (IF) signals (e.g., real IF architectures or complex IF architectures), the DACs 412, 414, 416, and 418 must be capable of processing digital IF signals.

[0077]

[0092] To achieve this, reconfigurable DAC circuit 410C may include eight additional outputs and eight additional sets of switches. While a total of 16 DAC circuit outputs and 16 sets of switches are shown in the example of FIG. 4C , the reader should understand that any suitable number of DAC circuit outputs and associated sets of switches may be selected. To support a real IF architecture with DAC circuit 410C, a ninth set of switches S9 may be coupled between the output of DAC 412 and a real IF horizontally polarized output (labeled “H_Real_IF1”). A tenth set of switches S10 may be coupled between the output of DAC 414 and another real IF horizontally polarized output (H_Real_IF2) of DAC circuit 410C. In certain aspects, the real IF horizontally polarized outputs H_Real_IF1 and H_Real_IF2 may be shorted or otherwise combined together and considered a single output, H_Real_IF. An eleventh set of switches S11 may be coupled between the output of DAC 416 and a real IF vertically polarized output (V_Real_IF1). A twelfth set of switches S12 may be coupled between the output of DAC 418 and another real IF vertically polarized output (V_Real_IF2) of the DAC circuit. In certain aspects, the real IF vertically polarized outputs V_Real_IF1 and V_Real_IF2 may be shorted or otherwise combined together and considered a single output V_Real_IF. To support a dual-layer quadrature system using DAC circuit 410C, a thirteenth set of switches S13 may be coupled between the output of DAC 412 and the in-phase horizontally polarized output (I_H), a fourteenth set of switches S14 may be coupled between the output of DAC 414 and the quadrature horizontally polarized output (Q_H), a fifteenth set of switches S15 may be coupled between the output of DAC 416 and the in-phase vertically polarized output (I_V), and a set of switches including switch S16 may be coupled between the output of DAC 418 and the quadrature vertically polarized output (Q_V). The sets of switches S1-S16 may be used to route the outputs of DAC 412, DAC 414, DAC 416, and DAC 418 to selected transmit chains based on a desired RAT, set of frequency bands, or transmit architecture.

[0078]

[0093] When the dual-layer quadrature (legacy mmW) mode is selected, the sets of switches are controlled to couple DAC412, DAC414, DAC416, and DAC418 to an in-phase horizontal (I_H) polarization output, a quadrature horizontal (Q_H) polarization output, an in-phase vertical (I_V) polarization output, and a quadrature vertical (Q_V) polarization output. In reconfigurable DAC circuit 410C, the twelfth through sixteenth sets of switches S13-S16 are closed, and the ninth set of other switches S1-S12 is opened (see, for example, FIG. 6C ). This routes the output of DAC412 to the I_H output, the output of DAC414 to the Q_H output, the output of DAC416 to the I_V output, and the output of DAC418 to the Q_V output. In this configuration, DAC 412 is designated as an in-phase horizontally polarized (I_H) DAC, DAC 414 is designated as a quadrature horizontally polarized (Q_H) DAC, DAC 416 is designated as an in-phase vertically polarized (I_V) DAC, and DAC 418 is designated as a quadrature vertically polarized (Q_V) DAC.

[0079]

[0094] When a real IF architecture is selected, DAC circuit 410C can be configured to support different real IF modes, such as dual-layer real IF or single-layer real IF, with or without interleaving.

[0080]

[0095] When the dual-layer real IF mode with interleaving is selected, two associated pairs of switches (e.g., a horizontal pair and a vertical pair) of ninth through twelfth sets of switches S9-S12 may be closed, with each member of the pair alternately closed and the remaining sets of switches (sets S1-S8 and S13-S16) open. In this alternating manner, a designated horizontal pair of switches (sets S9 and S10) alternately couples the output of DAC 412 or the output of DAC 414 to the real IF horizontally polarized output (H_Real_IF), and a designated vertical pair of switches (sets S11 and S12) alternately couples the output of DAC 416 or the output of DAC 418 to the real IF vertically polarized output (V_Real_IF) to achieve interleaving.

[0081]

[0096] When the single-layer real IF mode with interleaving is selected, only real IF horizontally polarized signals (or only real IF vertically polarized signals) can be output by the reconfigurable DAC circuit 410C. Thus, two associated sets of switches (e.g., either horizontal switches or vertical switches) (e.g., sets S9 and S10) among the ninth through twelfth sets of switches S9-S12 can be alternately closed, the other two sets (e.g., sets S11 and S12) can be open (see, e.g., FIG. 6E), and the remaining ninth set of switches (sets S1-S8 and S13-S16) can be open in the DAC circuit 410C. In this alternating manner, the two sets of switches coupled to the real IF horizontally polarized outputs (or the real IF vertically polarized outputs) are interleaved. For example, the sets of switches S9 and S10 coupled to outputs H_Real_IF1 and H_Real_IF2, respectively (which may be shorted or otherwise coupled together to form a single H_Real_IF output) may be interleaved, while the sets of switches S11 and S12 are always open in this mode. Alternatively, the sets of switches S11 and S12 coupled to outputs V_Real_IF1 and V_Real_IF2, respectively, may be interleaved, while the sets of switches S9 and S10 are always open.

[0082]

[0097] When the dual-layer real IF mode without interleaving is selected, two sets of switches (e.g., sets S9 and S11) of the ninth through twelfth sets of switches S9-S12 may be closed, the other two sets (e.g., sets S10 and S12) may be open (see, e.g., FIG. 6F), and the remaining sets of switches (sets S1-S8 and S13-S16) are open in DAC circuit 410C, which routes the output of DAC 412 to the H_Real_IF1 output (or the output of DAC 414 to the H_Real_IF2 output) as the horizontal real IF output. It also routes the output of DAC 416 to the V_Real_IF1 output (or the output of DAC 418 to the V_Real_IF2 output) as the vertical real IF output.

[0083]

[0098] 5B is a block diagram of a portion of an example wireless transmitter circuit 500B according to certain aspects of the present disclosure. The wireless transmitter circuit 500B may include mmW processing circuitry 540, sub-6 GHz processing circuitry 542, real IF processing circuitry 544, legacy mmW processing circuitry 546 (for dual-layer quadrature), MUX 506, processing circuitry 508, and a reconfigurable DAC circuit 549 configured to support different RATs, different sets of frequency bands, and / or different transmitter architectures. The reconfigurable DAC circuit 549 may include a clock distribution circuit 513, a DAC 510, a DAC 512, a DAC 514, a DAC 516, and a MUX 555.

[0084]

[0099] The mmW processing circuitry 540, the sub-6 GHz processing circuitry 542, the real IF processing circuitry 544, and the legacy mmW processing circuitry 546 may each be configured to process a digital input, and the control bits of the MUX 506 may be used to select among the processed digital signals. The processed digital signals may be digital baseband signals (e.g., in the case of a zero-IF transmitter architecture) or digital intermediate frequency (IF) signals (e.g., in the case of a complex-IF or real-IF architecture). While these four specific processing circuits are shown in the example of FIG. 5B , the reader should understand that the transmitter circuit 500B may include any suitable number of processing circuits capable of processing digital signals of multiple RATs, different sets of frequency bands, and / or different transmitter architectures than the exemplary processing circuits shown.

[0085]

[0100] Reconfigurable DAC circuit 549 may be similar to reconfigurable DAC circuit 509 of FIG. 5A, but with additional sets of switches S9-S12 to support a real IF architecture. Sets of switches S1-S12 are similar to sets of switches S1-S12 in reconfigurable DAC circuit 410C of FIG. 4C, except that sets of switches S1-S12 each include a pair of switches (indicated by the designations "a" and "b"). To avoid cluttering the drawing, sets of switches S13-S16 from FIG. 4C have not been added as differential pairs of switches in FIG. 5B, but the reader will understand how these sets of switches S13-S16 may be added to reconfigurable DAC circuit 549. With regard to the additional switches shown in FIG. 5B, a ninth set of switches includes switches S9a and S9b, which may be coupled between the differential outputs of DAC 510 and the differential H_Real_IF1 output of DAC circuit 549. Similarly, the tenth set of switches includes switches S10a and S10b coupled between the differential output of DAC512 and the differential H_Real_IF2 output, the eleventh set of switches includes switches S11a and S11b coupled between the differential output of DAC514 and the differential V_Real_IF1 output, and the twelfth set of switches includes switches S12a and S12b coupled between the differential output of DAC516 and the differential V_Real_IF2 output.

[0086]

[0101] Additional or alternative differential pairs of switches (e.g., a set of switches S13a / b-S16a / b (not shown)) for coupling to the dual-layer quadrature (legacy mmW) outputs of the reconfigurable DAC circuit 410C can be included in the wireless transmitter circuit 500B, as indicated by the I_H, Q_H, I_V, and Q_V outputs shown in parentheses.

[0087]

[0102] MUX 555 (e.g., a 4:1 MUX) may receive clock signals from multiple sources (e.g., multiple frequency synthesizers such as TX frequency synthesizer 320 of FIG. 3) and select one of the received clock signals for output to clock distribution circuit 513. This selection may be controlled by a control signal (e.g., from controller 336) received by a control input of MUX 555. In the example of FIG. 5B, MUX 555 may receive a clock signal corresponding to a sub-6 GHz frequency band (labeled “Pll_sub6”), a clock signal corresponding to an mmW frequency band (labeled “Pll_mmW”), a clock signal corresponding to a real IF architecture (labeled “pll_real_IF”), and a clock signal corresponding to a dual-layer quadrature (legacy mmW) scheme (labeled “pll_legacy_mmW”).

[0088]

[0103] The set of switches in reconfigurable DAC circuit 549 of FIG. 5B may be operated in the same manner as the corresponding set of switches S1-S12 (or S1-S16) in reconfigurable DAC circuit 410C of FIG. 4C and need not be repeated here.

[0089]

[0104] 6C is a block diagram of a portion of an example transmitter circuit 600C having a reconfigurable DAC circuit 410C implementing a dual-layer quadrature scheme (legacy mmW scheme) in accordance with certain aspects of the present disclosure. The legacy mmW processing circuitry 640 receives an in-phase horizontally polarized baseband signal (I_H * ), quadrature horizontally polarized baseband signal (Q_H * ), in-phase vertically polarized baseband signal (I_V * ), and quadrature vertically polarized baseband signal (Q_V *) and generates corresponding signals that are routed to corresponding DACs of reconfigurable DAC circuit 410C. Thus, legacy mmW processing circuitry 640 of FIG. 6C may represent legacy mmW processing circuitry 546, MUX 506, and processing circuitry 508 of FIG. 5B. As described above, set of switches S13-S16 may be closed (and the other set of switches S1-S12 may be open), and each DAC outputs a signal that is routed to a corresponding transmit chain (not shown) of the legacy mmW (in dual-layer quadrature)

[0090]

[0105] 6D is a block diagram of a portion of an example transmitter circuit 600D having a reconfigurable DAC circuit 410C implementing a dual-layer real IF scheme with interleaving, according to certain aspects of the present disclosure. In this case, a real IF signal generator 645 receives the digital baseband signals described above and generates corresponding real IF output signals that are routed to corresponding DACs of the reconfigurable DAC circuit 410C. Thus, the real IF signal generator 645 of FIG. 6D may represent the real IF processing circuitry 544, MUX 506, and processing circuitry 508 of FIG. 5B. When using a dual-layer real IF with interleaving, the outputs of DACs 412, 414, 416, and 418 may be provided to a programmable analog MUX 650, which may include an interleaver 652 and an interleaver 654. The interleaver 652 may be configured to receive the outputs of DACs 412 and 414. Interleaver 652 may be implemented by a set of switches S9 and S10, alternating between two outputs in an interleaved manner and operated in the same manner as described above, such that the real IF horizontally polarized output (H_Real_IF) of reconfigurable DAC circuit 410C alternates between H_Real_IF1 from the output of DAC 412 and H_Real_IF2 from the output of DAC 414. Interleaver 654 may be configured to receive the outputs of DAC 416 and DAC 418. Interleaver 654 may be implemented by a set of switches S11 and S12, alternating between two outputs in an interleaved manner and operated in the same manner as described above, such that the real IF vertically polarized output (V_Real_IF) of reconfigurable DAC circuit 410C alternates between V_Real_IF1 from the output of DAC 416 and V_Real_IF2 from the output of DAC 418.

[0091]

[0106] 6E is a block diagram of a portion of an example transmitter circuit 600E having a reconfigurable DAC circuit 410C implementing a single-layer real IF scheme with interleaving, according to certain aspects of the present disclosure. In certain aspects, the single-layer real IF scheme with interleaving may include only outputting a real IF horizontally polarized output (H_Real_IF) from the programmable analog MUX 650. In the example shown in FIG. 6E, only horizontal baseband input may be received by the real IF signal generator 645, and / or only DACs 412 and 414 and interleaver 652 may be enabled (i.e., DACs 416 and 418 and interleaver 654 are disabled). Thus, only DACs 412 and 414 may receive the real IF signal and generate analog IF output signals H_Real_IF1 and H_Real_IF2, respectively. Interleaver 652 operates in the same manner as described above, with the output H_Real_IF alternating between H_Real_IF1 and H_Real_IF2. Alternatively, a single-layer real IF scheme may include generating only a vertically polarized output V_Real_IF to the corresponding transmit chain (e.g., DACs 412 and 414 and interleaver 652 are disabled, and DACs 416 and 418 and interleaver 654 are enabled).

[0092]

[0107] FIG. 6F is a block diagram of a portion of an example transmitter circuit 600F having a reconfigurable DAC circuit 410C implementing a dual-layer real IF scheme without interleaving, in accordance with certain aspects of the present disclosure. Because that portion of the transmitter circuit 600F uses dual-layer real IF, both H_Real_IF and V_Real_IF outputs are generated and routed to the corresponding transmit chains. However, because interleaving is not used in this example, the real IF signal generator 645 can generate only both in-phase real IF signals (and / or only DACs 412 and 416 are enabled, as shown) or only both quadrature-phase real IF signals (and / or only DACs 414 and 418 are enabled). For example, as shown in FIG. 6F, the real IF signal generator 645 can send a real IF in-phase horizontally polarized signal to DAC 412 and a real IF in-phase vertically polarized signal to DAC 416. The DAC's clock signals (e.g., Clk1 and Clk3 for DAC 412 and DAC 416, respectively) may be phase shifted by 90° in this case. Programmable analog MUX 650 may be selected (or switch sets S9 and S11 may be effectively closed) to route the outputs of DAC 412 and DAC 416 to the H_Real_IF and V_Real_IF outputs of reconfigurable DAC circuit 410C. Alternatively, real IF signal generator 645 may send a real IF quadrature horizontally polarized signal to DAC 414 and a real IF quadrature vertically polarized signal to DAC 418, and programmable analog MUX 650 may be selected (or switch sets S10 and S12 may be effectively closed) to route the outputs of DAC 414 and DAC 418 to the H_Real_IF and V_Real_IF outputs of reconfigurable DAC circuit 410C.

[0093] Exemplary Operations for Wireless Communication

[0108] 7 is a flow diagram of example operations 700 for wireless communication according to certain aspects of the present disclosure. Operations 700 may be performed, for example, by a transmitter circuit (e.g., transmitter circuit 500A or 500B of FIG. 5A or 5B, respectively) that utilizes a reconfigurable DAC circuit (e.g., reconfigurable DAC circuit 410B, 410C, 509, or 549 of FIG. 4B, 4C, 5A, or 5B, respectively), as described above.

[0094]

[0109] The operations 700 may begin by configuring a DAC circuit in a first configuration configured to support at least four channels at block 702. At block 704, the DAC circuit in the first configuration may convert a plurality of first digital signals to a plurality of first analog signals.

[0095]

[0110] At block 706, the DAC circuit may be configured in a second configuration configured to support at least one but less than four channels. At block 708, the DAC circuit in the second configuration may convert the plurality of second digital signals to one or more second analog signals.

[0096]

[0111] According to certain aspects, the plurality of first digital signals are in a first set of one or more frequency bands, and the plurality of second digital signals are in a second set of one or more frequency bands that are different from the first set of one or more frequency bands. For example, the first set of one or more frequency bands may be one or more sub-6 GHz frequency bands, and the second set of one or more frequency bands may be one or more millimeter wave (mmW) frequency bands. As another example, the first set of one or more frequency bands may be one or more Frequency Range 1 (FR1) frequency bands, and the second set of one or more frequency bands may be one or more Frequency Range 2 (FR2) frequency bands.

[0097]

[0112] According to a particular aspect, the DAC circuit includes a plurality of switches coupled to the outputs of at least four DACs. In this case, configuring the DAC circuit in the second configuration may include selectively closing a first set of the plurality of switches and selectively opening a second set of the plurality of switches different from the first set of switches. In a particular aspect, selectively closing may include selectively closing the first set of the plurality of switches for a first interval, and selectively opening may include selectively opening the second set of the plurality of switches for the first interval. In this case, configuring the DAC circuit in the second configuration may further include selectively closing a third set of the plurality of switches different from the first set of the plurality of switches for a second interval, and selectively opening a fourth set of the plurality of switches different from the second set of the plurality of switches for the second interval.

[0098]

[0113] According to a particular aspect, the plurality of second digital signals include intermediate frequency (IF) digital signals, in which case the DAC circuit may include at least four DACs capable of operating as IF DACs, and at least one channel may be at least one real IF channel.

[0099] Exemplary Embodiments

[0114] In addition to the various aspects described above, certain combinations of aspects are within the scope of the present disclosure, some of which are detailed below.

[0100]

[0115] Aspect 1: A digital-to-analog converter (DAC) circuit comprising: a first DAC and a first set of one or more switches coupled between an output of the first DAC and a first output of the DAC circuit; a second DAC and a second set of one or more switches coupled between the output of the second DAC and a second output of the DAC circuit; a third DAC and a third set of one or more switches coupled between the output of the third DAC and a third output of the DAC circuit; a fourth DAC and a fourth set of one or more switches coupled between the output of the fourth DAC and a fourth output of the DAC circuit; a fifth set of one or more switches coupled between the output of the first DAC and a fifth output of the DAC circuit; a sixth set of one or more switches coupled between the output of the second DAC and the fifth output of the DAC circuit; a seventh set of one or more switches coupled between the output of the third DAC and the sixth output of the DAC circuit; and an eighth set of one or more switches coupled between the output of the fourth DAC and the sixth output of the DAC circuit.

[0101]

[0116] Aspect 2: The DAC circuit of aspect 1, wherein the first DAC is configured as an in-phase (I) DAC and the second DAC is configured as a quadrature (Q) DAC.

[0102]

[0117] Aspect 3: The DAC circuit of aspect 1 or 2, wherein the first DAC is disposed adjacent to the second DAC.

[0103]

[0118] Aspect 4: The DAC circuit of any one of aspects 1 to 3, wherein the third DAC is configured as a 45° phase shift (I45) DAC and the fourth DAC is configured as a 135° phase shift quadrature (Q45) DAC.

[0104]

[0119] Aspect 5: The DAC circuit according to any one of aspects 1 to 4, wherein the third DAC is disposed adjacent to the fourth DAC.

[0105]

[0120] Aspect 6: The DAC circuit according to any one of aspects 1 to 5, wherein the first DAC is disposed adjacent to the second DAC.

[0106]

[0121] Aspect 7: A DAC circuit according to any one of aspects 1 to 6, comprising: a clock distribution circuit; a first clock line coupled between a first output of the clock distribution circuit and a clock input of a first DAC; a second clock line coupled between a second output of the clock distribution circuit and the clock input of the second DAC; a third clock line coupled between a third output of the clock distribution circuit and the clock input of the third DAC; and a fourth clock line coupled between a fourth output of the clock distribution circuit and the clock input of the fourth DAC, wherein the first, second, third, and fourth outputs of the clock distribution circuit are all different outputs.

[0107]

[0122] Aspect 8: The DAC circuit of aspect 7, further comprising: a multiplexer including an output coupled to the input of the clock distribution circuit, the multiplexer including a plurality of inputs configured to receive clock signals from different sources.

[0108]

[0123] Aspect 9: A DAC circuit as described in any of aspects 1 to 8, wherein the DAC circuit is configured to use the first, second, third, and fourth outputs in a first set of one or more frequency bands, and the DAC circuit is configured to use the fifth and sixth outputs in a second set of one or more frequency bands different from the first set of one or more frequency bands.

[0109]

[0124] Aspect 10: The DAC circuit of aspect 9, wherein the first set of one or more frequency bands includes one or more sub-6 GHz frequency bands, and the second set of one or more frequency bands includes one or more millimeter wave (mmW) frequency bands.

[0110]

[0125] Aspect 11: The DAC circuit of aspect 9, wherein the first set of one or more frequency bands includes one or more frequency range 1 (FR1) frequency bands, and the second set of one or more frequency bands includes one or more frequency range 2 (FR2) frequency bands.

[0111]

[0126] Aspect 12: A DAC circuit as described in aspect 1 or any of aspects 5 to 11, wherein the first DAC is configured as an in-phase (I) DAC, the second DAC is configured as a 45° phase shift (I45) DAC, the third DAC is configured as a quadrature (Q) DAC, and the fourth DAC is configured as a 135° phase shift quadrature (Q45) DAC.

[0112]

[0127] Aspect 13: A DAC circuit as described in aspect 1 or any of aspects 5 to 11, wherein the first DAC is configured as an in-phase horizontally polarized (I_H) DAC, the second DAC is configured as a quadrature (Q) horizontally polarized (Q_H) DAC, the third DAC is configured as an in-phase vertically polarized (I_V) DAC, and the fourth DAC is configured as a quadrature (Q) vertically polarized (Q_V) DAC.

[0113]

[0128] Aspect 14: The DAC circuit of any one of aspects 1 to 13, further comprising at least one of a ninth set of one or more switches coupled between the output of the first DAC and a seventh output of the DAC circuit, a tenth set of one or more switches coupled between the output of the second DAC and the seventh output of the DAC circuit, or an eleventh set of one or more switches coupled between the output of the third DAC and an eighth output of the DAC circuit.

[0114]

[0129] Example 15: The DAC circuit of example 14, further comprising a twelfth set of one or more switches coupled between the output of the fourth DAC and an eighth output of the DAC circuit.

[0115]

[0130] Example 16: The DAC circuit of example 14 or 15, wherein the seventh output of the DAC circuit is a real intermediate frequency (real IF) output.

[0116]

[0131] Aspect 17: A wireless device comprising the DAC circuit of any of aspects 1 to 16, further comprising a first mixer configured to receive a first oscillating signal and a second mixer configured to receive a second oscillating signal, wherein the second oscillating signal is configured to be phase shifted by 90 degrees relative to the first oscillating signal.

[0117]

[0132] Aspect 18: The wireless device of aspect 17, wherein a fifth output of the DAC circuit is coupled to an input of the first mixer and a sixth output of the DAC circuit is coupled to an input of the second mixer.

[0118]

[0133] Aspect 19: A third mixer configured to receive a third oscillating signal; 19. The wireless device of aspect 17 or 18, further comprising: a fourth mixer configured to receive a fourth oscillating signal, wherein the third oscillating signal is configured to be phase shifted 45 degrees relative to the first oscillating signal and the fourth oscillating signal is configured to be phase shifted 135 degrees relative to the first oscillating signal; a first output of the DAC circuit is coupled to the input of the first mixer, a second output of the DAC circuit is coupled to the input of the second mixer, a third output of the DAC circuit is coupled to the input of the third mixer, and a fourth output of the DAC circuit is coupled to the input of the fourth mixer.

[0119]

[0134] Aspect 20: A digital-to-analog converter (DAC) circuit comprising: at least four DACs; and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit having at least four channels for a first set of one or more frequency bands, and as an interleaved DAC circuit having at least two channels for a second set of one or more frequency bands different from the first set of one or more frequency bands.

[0120]

[0135] Aspect 21: The DAC circuit of aspect 20, wherein the first set of one or more frequency bands includes one or more sub-6 GHz frequency bands, and the second set of one or more frequency bands includes one or more millimeter wave (mmW) frequency bands.

[0121]

[0136] Aspect 22: A DAC circuit as described in aspect 20, wherein the first set of one or more frequency bands includes one or more frequency range 1 (FR1) frequency bands, and the second set of one or more frequency bands includes one or more frequency range 2 (FR2) frequency bands.

[0122]

[0137] Aspect 23: The DAC circuit of aspect 20, wherein the DAC circuit is capable of operating as an intermediate frequency (IF) DAC circuit, and wherein a plurality of switches are coupled to the outputs of the at least four DACs such that the DAC circuit is reconfigurable with at least one real IF channel.

[0123]

[0138] Aspect 24: A method of wireless communication comprising: configuring a digital-to-analog converter (DAC) circuit in a first configuration configured to support at least four channels; and converting a plurality of first digital signals to a plurality of first analog signals using the DAC circuit of the first configuration; configuring the DAC circuit in a second configuration configured to support at least one, but fewer than four, channels; and converting a plurality of second digital signals to one or more second analog signals using the DAC circuit of the second configuration.

[0124]

[0139] Aspect 25: The method described in aspect 24, wherein the plurality of first digital signals are within a first set of one or more frequency bands, and the plurality of second digital signals are within a second set of one or more frequency bands that are different from the first set of one or more frequency bands.

[0125]

[0140] Aspect 26: The method of aspect 25, wherein the first set of one or more frequency bands includes one or more sub-6 GHz frequency bands, and the second set of one or more frequency bands includes one or more millimeter wave (mmW) frequency bands.

[0126]

[0141] Aspect 27: The method of aspect 25, wherein the first set of one or more frequency bands includes one or more frequency range 1 (FR1) frequency bands, and the second set of one or more frequency bands includes one or more frequency range 2 (FR2) frequency bands.

[0127]

[0142] Embodiment 28: A method according to any of embodiments 24 to 27, wherein the DAC circuit comprises a plurality of switches coupled to the outputs of at least four DACs, and configuring the DAC circuit in the second configuration includes selectively closing a first set of the plurality of switches and selectively opening a second set of the plurality of switches, the second set being different from the first set of the plurality of switches.

[0128]

[0143] Aspect 29: The method of aspect 28, wherein the selectively closing comprises selectively closing a first set of the plurality of switches during a first interval, the selectively opening comprises selectively opening a second set of the plurality of switches during the first interval, and configuring the DAC circuit in the second configuration further comprises selectively closing a third set of the plurality of switches different from the first set of the plurality of switches during a second interval, and selectively opening a fourth set of the plurality of switches different from the second set of the plurality of switches during the second interval.

[0129]

[0144] Aspect 30: The method of aspect 24, wherein the plurality of second digital signals include intermediate frequency (IF) digital signals, the DAC circuit includes at least four DACs capable of operating as IF DACs, and the at least one channel includes at least one real IF channel.

[0130] Additional Considerations

[0145] The above description provides examples and is not intended to limit the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements described without departing from the scope of the present disclosure. Various examples may omit, substitute, or add various procedures or components as appropriate. For example, the methods described may be performed in an order different from that described, and various steps may be added, omitted, or combined. Also, features described with respect to some examples may be combined in some other examples. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects described herein. In addition, the scope of the present disclosure is intended to cover such apparatuses or methods that are practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure described herein. It should be understood that any aspect of the present disclosure disclosed herein may be embodied by one or more elements of a claim. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0131]

[0146] The various operations of the above-described methods may be implemented by any suitable means capable of performing the corresponding functions. These means may include various hardware and / or software components and / or modules, including, but not limited to, circuits, application-specific integrated circuits (ASICs), or processors. Generally, where operations are illustrated, these operations may have corresponding counterpart means-plus-function components. For example, the means for converting may include a digital-to-analog converter (DAC) circuit, such as reconfigurable DAC circuit 410B or 410C of FIG. 4B or 4C, respectively.

[0132]

[0147] As used herein, phrases referring to "at least one of" a list of items refer to any combination of those items, including single members. As an example, "at least one of a, b, or c" is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other order of a, b, and c).

[0133]

[0148] The methods disclosed herein include one or more steps or actions for achieving the described method. The method steps and / or actions may be interchangeable with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order of specific steps and / or actions and / or the use of those steps and / or actions may be modified without departing from the scope of the claims.

[0134]

[0149] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. 1. A digital-to-analog converter (DAC) circuit, comprising: a first DAC; and a first set of one or more switches coupled between the output of the first DAC and a first output of the DAC circuit; a second DAC; and a second set of one or more switches coupled between the output of the second DAC and a second output of the DAC circuit; a third DAC; and a third set of one or more switches coupled between the output of the third DAC and a third output of the DAC circuit; a fourth DAC; and a fourth set of one or more switches coupled between the output of the fourth DAC and a fourth output of the DAC circuit; a fifth set of one or more switches coupled between the output of the first DAC and a fifth output of the DAC circuit; a sixth set of one or more switches coupled between the output of the second DAC and the fifth output of the DAC circuit; a seventh set of one or more switches coupled between the output of the third DAC and a sixth output of the DAC circuit; an eighth set of one or more switches coupled between the output of the fourth DAC and the sixth output of the DAC circuit; 1. A digital-to-analog converter (DAC) circuit comprising:

2. 2. The DAC circuit of claim 1, wherein the first DAC is configured as an in-phase (I) DAC and the second DAC is configured as a quadrature (Q) DAC.

3. The DAC circuit of claim 2 , wherein the first DAC is located adjacent to the second DAC.

4. 3. The DAC circuit of claim 2, wherein the third DAC is configured as a 45° phase shift (I45) DAC and the fourth DAC is configured as a 135° phase shift quadrature (Q45) DAC.

5. The DAC circuit of claim 4 , wherein the third DAC is located adjacent to the fourth DAC.

6. The DAC circuit of claim 5 , wherein the first DAC is located adjacent to the second DAC.

7. a clock distribution circuit; a first clock line coupled between a first output of the clock distribution circuit and a clock input of the first DAC; a second clock line coupled between a second output of the clock distribution circuit and a clock input of the second DAC; a third clock line coupled between a third output of the clock distribution circuit and a clock input of the third DAC; a fourth clock line coupled between a fourth output of the clock distribution circuit and a clock input of the fourth DAC, wherein the first, second, third, and fourth outputs of the clock distribution circuit are all different outputs.

2. The DAC circuit of claim 1.

8. 8. The DAC circuit of claim 7, further comprising a multiplexer including an output coupled to an input of the clock distribution circuit, the multiplexer including a plurality of inputs configured to receive clock signals from different sources.

9. 2. The DAC circuit of claim 1, wherein the DAC circuit is configured to use the first, second, third, and fourth outputs in a first set of one or more frequency bands, and the DAC circuit is configured to use the fifth and sixth outputs in a second set of one or more frequency bands different from the first set of one or more frequency bands.

10. 10. The DAC circuit of claim 9, wherein the first set of one or more frequency bands includes one or more sub-6 GHz frequency bands, and the second set of one or more frequency bands includes one or more millimeter-wave (mmW) frequency bands.

11. 10. The DAC circuit of claim 9, wherein the first set of one or more frequency bands includes one or more frequency range 1 (FR1) frequency bands, and the second set of one or more frequency bands includes one or more frequency range 2 (FR2) frequency bands.

12. the first DAC is configured as an in-phase (I) DAC; the second DAC is configured as a 45° phase shift (I45) DAC; the third DAC is configured as a quadrature (Q) DAC; the fourth DAC is configured as a 135° phase-shifted quadrature (Q45) DAC; 2. The DAC circuit of claim 1.

13. the first DAC is configured as an in-phase horizontally polarized (I_H) DAC; the second DAC is configured as a quadrature (Q) horizontally polarized (Q_H) DAC; the third DAC is configured as an in-phase vertically polarized (I_V) DAC; the fourth DAC is configured as a quadrature (Q) vertical polarization (Q_V) DAC; 2. The DAC circuit of claim 1.

14. a ninth set of one or more switches coupled between the output of the first DAC and a seventh output of the DAC circuit; a tenth set of one or more switches coupled between the output of the second DAC and the seventh output of the DAC circuit; or an eleventh set of one or more switches coupled between the output of the third DAC and an eighth output of the DAC circuit; and at least one of 10. The DAC circuit of claim 1 further comprising:

15. 15. The DAC circuit of claim 14, further comprising a twelfth set of one or more switches coupled between the output of the fourth DAC and the eighth output of the DAC circuit.

16. 15. The DAC circuit of claim 14, wherein the seventh output of the DAC circuit is a true intermediate frequency (true IF) output.

17. 10. A wireless device comprising the DAC of claim 1, a first mixer configured to receive a first oscillating signal; a second mixer configured to receive a second oscillating signal, the second oscillating signal configured to be phase shifted 90 degrees relative to the first oscillating signal. Wireless devices.

18. 18. The wireless device of claim 17, wherein the fifth output of the DAC circuit is coupled to an input of the first mixer and the sixth output of the DAC circuit is coupled to an input of the second mixer.

19. a third mixer configured to receive a third oscillating signal; a fourth mixer configured to receive a fourth oscillating signal; the third oscillating signal is configured to be phase shifted by 45° relative to the first oscillating signal; the fourth oscillating signal is configured to be phase shifted by 135° relative to the first oscillating signal; the first output of the DAC circuit is coupled to an input of the first mixer; the second output of the DAC circuit is coupled to an input of the second mixer; the third output of the DAC circuit is coupled to an input of the third mixer; the fourth output of the DAC circuit is coupled to an input of the fourth mixer; 18. The wireless device of claim 17.

20. at least four DACs; a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit having at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit having at least two channels for a second set of one or more frequency bands different from the first set of one or more frequency bands; 1. A digital-to-analog converter (DAC) circuit comprising:

21. 21. The DAC circuit of claim 20, wherein the first set of one or more frequency bands includes one or more sub-6 GHz frequency bands, and the second set of one or more frequency bands includes one or more millimeter-wave (mmW) frequency bands.

22. 21. The DAC circuit of claim 20, wherein the first set of one or more frequency bands includes one or more frequency range 1 (FR1) frequency bands, and the second set of one or more frequency bands includes one or more frequency range 2 (FR2) frequency bands.

23. 21. The DAC circuit of claim 20, wherein the DAC circuit is capable of operating as an intermediate frequency (IF) DAC circuit, and wherein the plurality of switches are coupled to the outputs of the at least four DACs such that the DAC circuit is reconfigurable with at least one real IF channel.

24. configuring a digital-to-analog converter (DAC) circuit in a first configuration configured to support at least four channels; converting a plurality of first digital signals to a plurality of first analog signals using the DAC circuit in the first configuration; configuring the DAC circuit in a second configuration configured to support at least one but less than four channels; converting a plurality of second digital signals to one or more second analog signals using the DAC circuit in the second configuration; A method of wireless communication, comprising:

25. 25. The method of claim 24, wherein the plurality of first digital signals are in a first set of one or more frequency bands and the plurality of second digital signals are in a second set of one or more frequency bands that are different from the first set of one or more frequency bands.

26. 26. The method of claim 25, wherein the first set of one or more frequency bands comprises one or more sub-6 GHz frequency bands, and the second set of one or more frequency bands comprises one or more millimeter-wave (mmW) frequency bands.

27. 26. The method of claim 25, wherein the first set of one or more frequency bands comprises one or more Frequency Range 1 (FR1) frequency bands, and the second set of one or more frequency bands comprises one or more Frequency Range 2 (FR2) frequency bands.

28. the DAC circuit comprises a plurality of switches coupled to the outputs of at least four DACs, and configuring the DAC circuit in the second configuration; selectively closing a first set of the plurality of switches; selectively opening a second set of the plurality of switches different from the first set of the plurality of switches; 25. The method of claim 24, comprising:

29. the selectively closing includes selectively closing the first set of the plurality of switches for a first interval; the selectively opening includes selectively opening the second set of the plurality of switches during the first interval; configuring the DAC circuit in the second configuration; selectively closing a third set of the plurality of switches different from the first set of the plurality of switches during a second interval; selectively opening a fourth set of the plurality of switches different from the second set of the plurality of switches during the second interval; 30. The method of claim 28, further comprising:

30. 25. The method of claim 24, wherein the plurality of second digital signals comprise intermediate frequency (IF) digital signals, the DAC circuitry comprises at least four DACs capable of operating as IF DACs, and the at least one channel comprises at least one real IF channel.

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