Polyphase oscillator circuit

Abstract

Embodiments of the present invention relate to a multiphase oscillator circuit. In the described example, a ring oscillator (110) comprises a series of N stages in a first ring. Each stage includes a corresponding output (112, 114, 116), which is coupled to a corresponding input of the next stage in the first ring. N is a positive odd integer of at least three. A series of N level shifters (L1, L2, LN) in a second ring are respectively connected to the N stages. Each level shifter (L1, L2, LN) receives a corresponding clock output from the corresponding output (L1, L2, LN) of the stage to which it is connected and generates a corresponding boosted clock output (130) in response to the clock output. The boosted clock output (130) is coupled to control the impedance state of the next level shifter in the second ring.

Description

Technical Field

[0001] This invention relates generally to circuits, and more specifically to a multiphase oscillator circuit. Background Technology

[0002] Systems with low power duty cycles typically employ oscillators that reach the target output frequency within a short timeframe, where data transmission depends on rapid clock recovery. In serial communication of digital data, clock recovery is the process of extracting timing information from the serial data stream to allow the receiving circuitry to decode the transmitted symbols within the stream. Clock recovery from the data stream can be accelerated by modifying the transmitted data. If the serial communication channel does not transmit the clock signal along with the data stream, the clock must be regenerated at the receiver using the timing information from the data stream. Clock recovery is a common component of systems that communicate via wires, optical fibers, or radio. Summary of the Invention

[0003] In the described example, a ring oscillator comprises a series of N stages in a first ring. Each stage includes a corresponding output coupled to a corresponding input of the next stage in the first ring. N is a positive odd integer of at least three. A series of N level shifters in a second ring are respectively connected to the N stages. Each level shifter receives a corresponding clock output from a corresponding output of the stage to which it is connected and generates a corresponding boosted clock output in response to the clock output. The boosted clock output is coupled to control the impedance state of the next level shifter in the second ring.

[0004] In another described example, a circuit includes a ring oscillator comprising a series of stages. A first level shifter is coupled to receive the output of one of the stages. The first level shifter includes a first transistor, a second transistor, and a third transistor, each having a corresponding first gate, a second gate, and a third gate. The first transistor is coupled between a voltage reference and the second transistor. The second transistor is coupled between the first transistor and the third transistor. The third transistor is coupled between the second transistor and a voltage supply. At the first gate, the first level shifter is coupled to receive the output. At the node between the second transistor and the third transistor, the first level shifter is coupled to generate a boosted output in response to the received output. The second gate and the third gate are coupled to receive the boosted output from the second level shifter to control the impedance state of the first level shifter.

[0005] In yet another described example, a method includes generating corresponding clock signals from a series of N stages in a ring oscillator, where N is a positive odd integer of at least three. In response to the clock signals, the method includes generating corresponding boosted clock signals from a series of N level shifters connected in a ring. In response to the corresponding boosted clock signal of each level shifter, the method includes controlling the impedance state of the next level shifter in the ring. Attached Figure Description

[0006] Figure 1 This is an example block diagram of a circuit that generates a clock signal boosted by multiple level shifters using a multi-stage ring oscillator.

[0007] Figure 2 An example of a ring oscillator and a level shift circuit for boosting the voltage level of a clock signal generated by the ring oscillator is shown.

[0008] Figure 3 yes Figure 2 A timing diagram depicting signals in a circuit.

[0009] Figure 4 An example of a level shifter circuit is shown, which receives control signals from another level shifter circuit to control the switching and impedance states of the level shifter circuit.

[0010] Figure 5 An example implementation of a ring oscillator and a level shifter circuit that receives an enable signal to control the oscillator startup is shown.

[0011] Figure 6 yes Figure 5 The timing diagram of the ring oscillator and level shifter is depicted in the figure.

[0012] Figure 7 An example method for generating a level-shifted polyphase oscillator signal is shown.

[0013] Figure 8 An example clock filtering circuit is shown for filtering the clock signal of a ring oscillator circuit and achieving accuracy in the oscillator's start-up frequency. Detailed Implementation

[0014] The example embodiment relates to a multiphase oscillator circuit that provides a clock signal boosted by multiple level shifters. The circuit includes a ring oscillator, in one example comprising at least three stages. However, any odd number of stages (e.g., 5, 7, 9, etc.) greater than or equal to three can be used. Each ring oscillator stage includes an oscillator output that provides a corresponding clock signal coupled to the input of another stage of the ring oscillator. Tight and accurate frequency control of the ring oscillator stages can be maintained at a lower voltage level, wherein voltage level shifters are provided to boost the lower voltage level of the corresponding clock signal from the ring oscillator stage to a higher voltage level, which can then be used by downstream circuitry (such as a clock recovery serial data system). Furthermore, the generated and boosted clock signal described herein can be used in electronic fuses, load switches, power multiplexers, linear regulators, switching regulators, etc.

[0015] For example, each level shifter can be configured to boost the voltage level of a clock signal from the output of the corresponding oscillator of the corresponding stage, wherein the input voltage level supplying the corresponding oscillator stage (e.g., the ring oscillator power rail) is less than the voltage level supplying the level shifter (e.g., the level shifter power rail). Current control can be used to control the frequency of the ring oscillator stage. In some instances, system power consumption can be reduced because each level shifter stage (when boosting the corresponding clock signal) can place another level shifter stage in a high-impedance state to save power in the system.

[0016] By providing at least three clock phases via corresponding ring oscillator stages, oversampling three or more times can be performed at a given oscillator frequency. As another example, the oscillator described herein comprises a current-starved multi-stage ring oscillator with oscillator stages (e.g., inverters, NOR gates, or NAND gates) configured in a similar manner. The frequency of the clock signal can be set by a controllable bias current supplied to the corresponding stage. For example, using NOR or NAND gates allows for efficient disable / enable control of the ring oscillator, which can be the same signal used to disconnect the bias current. To achieve a fast startup time for the ring oscillator, the operating voltage of the oscillator's power supply can be maintained (e.g., via a backup power supply circuit) when the oscillator is disconnected via an associated switching circuit.

[0017] In this specification, the term "circuit" may include a collection of active and / or passive components that perform electronic circuit functions, such as analog circuits or control circuits. Alternatively or alternatively, for example, the term "circuit" may include an integrated circuit (IC) on which all or some of the circuit elements are fabricated on a common substrate (e.g., a semiconductor substrate, such as a die or chip).

[0018] Figure 1 An example of a circuit 100 for generating a clock signal boosted by multiple level shifters is shown, comprising a multi-stage ring oscillator 110. The ring oscillator 110 comprises at least three stages, shown as stage 1, stage 2, and so on up to N (odd) stages, where N is a positive odd integer. In this specification, the term "ring oscillator" refers to a collection of inverting elements (such as logic inverters, NAND gates, NOR gates, etc.) connected in series (e.g., in a chain-like loop) in a series of successive stages, where the output from one oscillator stage drives the next oscillator stage, and the output of the last stage is fed back to the first stage. As described herein, the ring oscillator 110 has an odd number of stages, at least three. Each stage includes an oscillator output coupled to provide corresponding clock signals 112, 114, and 116, which are coupled to another stage of the ring oscillator 110. Circuit 100 includes an output stage with at least three level shifters (one level shifter for each phase of the output), the level shifters being shown as level shifters L1 to LN.

[0019] In this specification, the term "level shifter" refers to a circuit that: receives a signal (e.g., a clock signal) generated according to a supply voltage (e.g., a voltage power rail or domain); and boosts the signal to a higher voltage level to achieve consistency with another supply voltage (e.g., another voltage power rail or domain). In this example, each level shifter L1 to LN is configured to: boost the voltage level of a corresponding clock signal (from the corresponding oscillator output of stages 1 to N) in clock signals 112-116; and output a corresponding boosted clock output signal in clock output signals 130. The corresponding boosted clock output signal 130 of each level shifter is coupled to control the switching state of a corresponding level shifter in the other level shifters (e.g., toggling the corresponding level shifter in the other level shifters between a high-impedance state and a normal operating state).

[0020] Each stage of the ring oscillator 110 is coupled to receive the input supply voltage VDD IN, and each level shifter is coupled to receive the output supply voltage VDD OUT. Since the input voltage VDD IN is less than the output voltage VDD OUT, level shifters L1 to LN are configured to boost the voltage levels of the corresponding clock signals 112-116 (which are compatible with VDD IN) to the boosted voltage level of the clock output signal 130 (which is compatible with VDD OUT).

[0021] In some instances, a controllable constant current source 140 generates an output current that is supplied to each of stages 1 through N. Clock signals 112-116 have frequencies that can be adjusted in response to the level of the output current. For example, by setting the current source 140 to generate a lower output current, the corresponding frequency of each clock signal in clock signals 112-116 is lower than the frequency at which setting the current source 140 to generate a higher output current would occur.

[0022] Ring oscillator stages 1 to N can be implemented using inverters, NAND gates, and / or NOR gates to generate clock signals 112-116. Control inputs (such as...) can be coupled to... Figure 5 The enable signal 534 enables or disables the ring oscillator 110 circuitry at at least one of the control levels 1 to N for a specific number of clock pulses. In another example, to achieve the desired start frequency of the ring oscillator 110, one or more pulses of the clock signals 112-116 can be filtered in the form of a start oscillator sequence (e.g., by attenuating or not generating one or more pre-clock pulses).

[0023] In some instances, a pre-bias circuit (e.g., a capacitor and diode network or a sample-and-hold network, such as...) can be used. Figure 5 A diode-capacitor network 560 is coupled to VDD IN to prepare for the startup of the ring oscillator 110. For example, when the ring oscillator is controlled to be off, a pre-bias circuit keeps VDD IN at or above a specific voltage threshold level.

[0024] Furthermore, as described herein, level shifters L1 to LN can be implemented as high-impedance (high-Z) level shifters, wherein the corresponding boosted clock output signal of each level shifter is coupled to control the switching state of a corresponding level shifter among the other level shifters (e.g., placing a corresponding level shifter among the other level shifters in a high-impedance state) thereby saving power in circuit 100. For example, at least one level shifter among level shifters L1 to LN operates in its high-Z state during each clock cycle. In one example, circuit 100 and / or other circuits shown and described below can be implemented on a substrate as an integrated circuit. In other examples, one or more portions of circuit 100 can be implemented discretely from a common substrate.

[0025] Figure 2 A circuit 200 for boosting the voltage level of a clock signal is shown. Figure 1 (An example of circuit 100), where the clock signal is generated by a ring oscillator 210 of circuit 200. As described above, the ring oscillator 210 has an odd number of stages, at least three. Figure 2 In this example, the ring oscillator 210 includes inverters I1, I2, and I3 for generating three ring oscillator output signals A1, A2, and A3, respectively. Inverters I1, I2, and I3 receive an input supply voltage from VDD IN. Signals A1, A2, and A3 drive level shifters L1, L2, and L3, respectively, which generate level-shifted output signals B1, B2, and B3, which in turn drive output drivers D1, D2, and D3, respectively. Level shifters L1, L2, and L3 receive an input supply voltage from VDD OUT, the voltage level of which is higher than the voltage level of VDD IN. In this example, output drivers D1, D2, and D3 are shown as inverting output drivers. In other examples, output drivers D1, D2, and D3 can be implemented as non-inverting output drivers. Output drivers D1, D2, and D3 generate three-phase clock outputs PHI1, PHI2, and PHI3, respectively. Circuit 200 includes a current source 220 configured to provide current to pre-bias the ring oscillator 210. Furthermore, circuit 200 uses at least three phases for oversampling and clock recovery of downstream circuitry. As shown, VDDIN is supplied to inverters I1, I2, and I3 of the ring oscillator 210; in some instances, the inverters may also be as follows: Figure 5 It switches periodically as shown. If VDD IN is disconnected, capacitor C1 maintains the input voltage VDD IN for a short time interval. Capacitor C1 also reduces the jitter of the generated clock signal.

[0026] Level shifters L1 to L3 feature high-impedance control to save power in the system, where the output from one level shifter controls the impedance state of the other. For example... Figure 2 As shown, level shifters L1 to L3 are connected in a chain loop, wherein: (a) the output signal B3 (230) from level shifter L3 is connected to control the impedance state of L1 and pulls the output signal B1 to the high-voltage power rail when the output signal B3 has a low voltage state; (b) the output signal B1 (234) from level shifter L1 is connected to control the impedance state of L2 and pulls the output signal B2 to the high-voltage power rail when the output signal B1 has a low voltage state; and (c) the output signal B2 (236) from level shifter L2 is connected to control the impedance state of L3 and pulls the output signal B3 to the high-voltage power rail when the output signal B2 has a low voltage state.

[0027] By using three or more phases of the ring oscillator 210 and a current-controlled frequency, various shortcomings of previous circuits can be overcome. For example, circuit 200 does not require clock frequency fine-tuning (e.g., by using a trimmer resistor during manufacturing) and clock recovery training sequence. Furthermore, because multiple clock phases are generated and these multiple clock phases are shifted through multiple level shifters (instead of a single level shifter in previous systems), a lower clock frequency (compared to the data frequency) can be used, which further saves power in circuit 200.

[0028] Figure 3 yes Figure 2 The timing diagram of the signals in circuit 200 is shown in diagram 300. Clock signals A1, A2, and A3 are generated and output by ring oscillator 210. The rising edge on A1 triggers the signal... Figure 2 The falling edge on B1, the output of the level shifter L1. The falling edge of B1 is triggered by... Figure 2 The rising edge of B2 is the output of the level shifter L2. During this period, in response to B2 being high while A3 is low, the signal from... Figure 2 The output B3 of the level shifter L3 remains in its high-impedance state, such as through Figure 3 As shown by the dashed line. The rising edge of A3 triggers the falling edge of B3, which in turn triggers the rising edge of B1, thereby placing B2 in a high-impedance state. The rising edge of A2 triggers the falling edge of B2, which in turn places B1 in a high-impedance state. This cycle then repeats over time during normal operation. Figure 3As shown, when any one of the output clock signals PHI1, PHI2, and PHI3 is high, the corresponding level shifter in the level shifter operates in its high-impedance state, as indicated by the dashed lines passing through each of B1, B2, and B3. Output PHI1 (as mentioned above) Figure 2 The output PHI1 is the inverted version of B1 (PHI1 = !B1). Output PHI2 is the inverted version of B2 (PHI2 = !B2), and output PHI3 is the inverted version of B3 (PHI3 = !B3). To provide the desired three-phase clock timing sequence (where one signal of the sequence is generated before the next subsequent signal of the sequence) to downstream circuitry (not shown), output PHI1 provides the first rising clock edge of the desired sequence. As shown, the next rising clock edge is provided by output PHI3, which provides the next rising edge of the desired sequence, and the next rising edge of the clock timing sequence is provided by output PHI2.

[0029] Figure 4 An example of a level shifter circuit 400 is shown, which is described above regarding... Figure 1 The level shifters L1 to LN and about Figure 2 The level shifters L1 to L3 are representative of one of them. For ease of explanation, in the following example, level shifter circuit 400 is described as level shifter L1, such that oscillator 110 ( Figure 1 ) or 210 ( Figure 2 Level 1 of ) Figure 1 ) or I1( Figure 2 Clock signals A1 are provided to input 410 respectively. Furthermore, in this example, input 420 is coupled to another level shifter (e.g., Figure 2 The level shifter circuit 400 receives signal B3 to control the switching and impedance states of level shifter L1. Level shifter circuit 400 includes a first transistor device M1 (n-channel field-effect transistor) connected between a voltage reference (VSS) and node 414. M1 includes an input 410 (the gate of M1), which is coupled to receive a clock signal A1, and M1 provides its output at node 414 in response to the clock signal A1. A second transistor device M2 (n-channel field-effect transistor) is connected between nodes 414 and 424. A third transistor device M3 (p-channel field-effect transistor) is connected between a voltage supply (VDD OUT) and node 424. M2 and M3 are coupled at node 424 to provide the output B1 of level shifter L1. Output 420 (the gates of M2 and M3) is coupled to level shifter L3 (… Figure 2 The output of B3 is ).

[0030] Return to reference Figure 2For level shifter L1: (a) a high voltage at A1 and B3 (i.e., close to VDDOUT) activates the pull-down state of B1 (e.g., pull-down to VSS); and (b) a low voltage at B3 (e.g., equal to or close to VSS) activates the pull-up state of B1 (e.g., pull-up to VDDOUT). Similarly, for level shifter L2 ( Figure 2 ): (a) A high voltage at A2 and B1 activates the pull-down state of B2; and (b) a low voltage at B1 activates the pull-up state of B2. Similarly, for level shifter L3 ( Figure 2 (a) B3 is activated in a pull-down state in response to a high voltage at both A3 and B2; and (b) B3 is activated in a pull-up state in response to a low voltage at B2.

[0031] Figure 5 Example circuit 500 is shown (e.g., corresponding to...). Figure 1 Circuit 500 (circuit 100). Circuit 500 includes a ring oscillator 510 and a level shifter circuit 520, the level shifter circuit including level shifters L1, L2, and L3, which receive their input voltage from VDD OUT. (This is related to the circuit described above.) Figure 2 Similarly, the outputs B1, B2, and B3 of level shifters L1, L2, and L3 can be fed to drivers D4, D5, and D6, respectively, to provide corresponding clock output signals PHI1, PHI2, and PHI3. Circuit 500 also includes a controller 524 (e.g., control circuitry) configured to operate an enable signal 534 and control the oscillator to start (e.g., upon power-up). In this example, the ring oscillator 510 is implemented using NOR gates. In other examples, the ring oscillator 510 is implemented using other inverting logic circuitry, such as an arrangement of inverters or NAND gates. When the first switch 530 closes in response to the enable signal 534 from controller 524, switch 530 controls power to the ring oscillator 510 by switching power from current source 540. In this example, the ring oscillator 510 operates in an "on" state in response to an assertion of the enable signal 534 (e.g., the enable signal goes low). When in the ON state, switch 530 closes to supply current from current source 540 to the stage of ring oscillator 510.

[0032] In the normal operating mode of the ring oscillator 510, the controller 524 provides an enable signal 534 to close switch 530 and the second switch 550. When closed, the current drawn through the closed switches 530 and 550 charges capacitors C13 and C14 in the diode capacitor network 560 to provide VDD IN to the ring oscillator 510. When switch 530 is closed, current source 540 supplies current to each of the ring oscillator 510 and the diode capacitor network 560, which also provides VDD IN. Current source 570 is a backup current source for providing backup current during extended periods when switches 530 and 550 are open (e.g., disconnected switches). The diode capacitor network 560 includes diodes 562 and 564 to clamp the voltage of VDD IN to the desired operating voltage. For example, when switches 530 and 550 are open for extended periods, current source 570 charges VDD IN to the voltage level set by diodes 562 and 564. Figure 5 The example shown uses two diodes, but in other examples, different numbers of diodes or other clamping circuit systems may be used.

[0033] As another example, the diode-capacitor network 560 supports two operating modes of the ring oscillator 510, referred to as Mode 1 and Mode 2. In some instances, circuit 500 may be configured to support both operating modes, and in other instances, the circuit may be configured to support only one of the operating modes. Mode 1 refers to the operation of the ring oscillator 510 where the duration of the closed periods of switches 530 and 550 is longer than the duration of their open periods, thus providing a longer ring oscillator on-time (e.g., where the switches are closed) with intermittent, brief off-time periods (e.g., where the switches are open). In instances where Mode 1 is determined to be the sole or primary operating mode of the ring oscillator 510, capacitor C14, diodes 562 and 564, and current source 570 may be omitted from circuit 500. Mode 2 refers to the operation of the ring oscillator 510 where switches 530 and 550 are open for a long period, followed by a shorter closed period. In Mode 2, current source 570 maintains VDD IN by charging capacitor C14. As described above, diodes 562 and 564 clamp VDD IN to a predetermined level and prevent the value of VDD IN from rising too high when charging C14 during the periods when switches 530 and 550 are off. In instances where mode 2 is determined to be the sole or primary operating mode, capacitor C13 and switch 550 can be omitted from circuit 500. Some applications can support both modes 1 and 2.

[0034] Figure 6 yes Figure 5 The timing diagram for circuit 500 is shown in Figure 600. Figure 6 As shown, in this example, the enable signal (via Figure 5 After the assertion of enable signal 534 goes low, signals A1 to A3 and B1 to B3 begin to transition. If the enable signal (via the assertion of enable signal 534) is synchronized with the rising edge of PHI3, the additional logic conditions for gating B2 using enable signal 534 are simplified. Therefore, during the synchronization condition, the pull-up condition for B1 is the inverted version of B3 (!B3), as described above. In the example, when the enable signal (enable signal 534) is not synchronized with the rising edge of PHI3, the pull-up condition for B1 is: (a) the inverted version of B3 (!B3); or (b) the inverted version of B2 (!B2& enable) after an "AND operation" with enable signal 534. The other pull-up and pull-down conditions for B2 and B3 are as described above. Figure 4 The conditions described are the same. In another instance, a specific number of clock pulse edges of PHI1, PHI2, and / or PHI3 may be filtered (e.g., removed), as shown at 620, 630, and / or 640, to ensure that the ring oscillator 510 operates at the desired frequency before a level-shifted clock is applied to downstream circuitry.

[0035] Figure 7 An example method 700 for generating a level-shifted multiphase oscillator signal is illustrated. For simplicity, the method is shown and described as being performed sequentially, but the method is not limited to the order shown, as parts of the method may occur in different orders and / or simultaneously. At 710, method 700 generates corresponding clock signals from a series of N stages in a ring oscillator (e.g., ring oscillators 110, 210, and 510), where N is a positive odd integer of at least three. At 720, in response to the clock signals, method 700 generates corresponding boosted clock signals from a series of N level shifters (e.g., level shifters L1, L2, L3) connected in a ring. At 730, in response to the corresponding boosted clock signal from each level shifter, method 700 controls the impedance state of the next level shifter in the ring. Although... Figure 7 Not shown, but method 700 can also supply current to the stages of the ring oscillator and adjust the output frequency of the ring oscillator of each stage according to the supplied current.

[0036] Figure 8 Demonstrated for the purpose of Figure 1 , 2Example filter circuit 800 is shown in Figure 5, which filters the clock signal of the ring oscillator circuit. Circuit 800 is configured to achieve accurate start-up frequency of the ring oscillator circuit. NAND gate G1, NOR gate G2, and NAND gate G3 receive unfiltered clock signals PHI1, PHI2, and PHI3 at node A of each gate and generate outputs to drivers D7, D8, and D9, respectively. In response to the outputs from gates G1, G2, and G3, drivers D7, D8, and D9 generate filtered output clock signals PHI1', PHI2', and PHI3', respectively. Gates G1, G2, and G3 have corresponding node B control inputs to control the filtering of the clock signals by enabling or disabling the outputs of G1, G2, and G3, respectively. Flip-flop 814 has: (a) an output "Pass 1" that controls the passage of unfiltered clock signals PHI1 and PHI3 connected to the corresponding node A inputs of G1 and G3; and (b) an output "Pass 2" connected to the control input node B of G2 and controlling the passage of the unfiltered clock signal PHI2. In this example, flip-flop 814 is timed by the unfiltered PHI3, and its corresponding D input is connected high to VDD OUT via pull-up RP1. Input 820 receives... Figure 5 The enable signal 534 and provides control reset for the flip-flop 814. As described above, PHI1, PHI2, and PHI3 are as follows: Figure 1 , Figure 2 and Figure 5 The circuit example generates an unfiltered phase, and PHI1', PHI2', and PHI3' are the corresponding filtered phases. Although in this example, circuit 800 filters a pulse, the circuit can be expanded by adding more D flip-flops in series with flip-flop 814. As shown, each of flip-flop 814, gates G1 to G3, and drivers D7 to D9 is powered via VDD OUT about the common connection VSS.

[0037] In this description, the term "based on" means at least partially based on. Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

Claims

1. A multiphase oscillator circuit, comprising: A ring oscillator comprising a series of rings in a first ring. N Each stage contains a corresponding output terminal, which is coupled to the corresponding input terminal of the next stage in the first ring. N It is a positive odd integer that is at least three; A series in the second ring N A level shifter, the N Each level shifter is connected to the N Each level is configured to shift from the level of the level shifter described above. N The corresponding output terminal of the stage to which each level shifter is connected receives a corresponding clock signal and generates a corresponding boosted clock signal in response to the clock signal. The boosted clock signal controls the impedance state of the next level shifter in the second loop. A controller having a control output coupled to at least one of the stages, the controller being configured to drive the control output to enable or disable the ring oscillator on multiple pulse edges of the boosted clock signal; and A filtering circuit is configured to filter one or more of the pulse edges to achieve a specific start-up frequency before the control output enables the ring oscillator.

2. The multiphase oscillator circuit according to claim 1, wherein: The stage is coupled to the input power supply voltage terminal. The level shifter is coupled to the output power supply voltage terminal, which has a higher voltage than the input power supply voltage terminal. The level shifter is configured to receive the corresponding clock signal at the level of the input supply voltage terminal and generate the corresponding boosted clock signal at the level of the output supply voltage terminal.

3. The multiphase oscillator circuit of claim 2, further comprising a current source coupled to the stage, the current source being configured to supply current to the stage.

4. The multiphase oscillator circuit of claim 3, wherein the oscillator output frequency of each stage is adjustable in response to the current supplied from the current source.

5. The multiphase oscillator circuit of claim 2, further comprising a capacitor and diode network coupled to the input supply voltage terminal, the capacitor and diode network being configured to control the start-up of the ring oscillator.

6. The multiphase oscillator circuit of claim 5, further comprising a backup current source coupled to the capacitor and diode network, wherein the capacitor and diode network is configured to receive current from the backup current source to maintain the input supply voltage at or above a threshold voltage level.

7. The multiphase oscillator circuit according to claim 1, wherein each stage comprises: The corresponding NOR gate has an output that serves as the output terminal of the corresponding stage.

8. The multiphase oscillator circuit of claim 1, wherein the boosted clock signal controls the impedance state of the next level shifter by coupling to the output of another level shifter to place the next level shifter in a high impedance state.

9. The multiphase oscillator circuit according to claim 1, wherein: One of the level shifters includes a first transistor, a second transistor, and a third transistor having corresponding first gate, second gate, and third gate; The first transistor is coupled between the voltage reference terminal and the second transistor; The second transistor is coupled between the first transistor and the third transistor; The third transistor is coupled between the second transistor and the input power supply voltage terminal; At the first gate, a specific level shifter is coupled to the corresponding output of the stage to which the specific level shifter is connected; The specific level shifter is configured to generate a corresponding boosted clock output at the connection between the second transistor and the third transistor; and The second gate and the third gate are configured to receive a corresponding boosted clock signal from the previous level shifter in the second ring; Furthermore, the impedance state of the specific level shifter is controlled in response to the boosted clock signal.

10. The multiphase oscillator circuit of claim 9, wherein the third transistor is configured to place the specific level shifter in a high-impedance state in response to a transition of the second gate and the third gate from a first state to a second state.

11. A multiphase oscillator circuit, comprising: A ring oscillator comprising a series of N stages in a first ring, each stage comprising a corresponding output coupled to a corresponding input of the next stage in the first ring, wherein N is a positive odd integer of at least three; A series in the second ring N A level shifter, the N Each level shifter is connected to the N Each level is configured to shift from the level of the level shifter described above. N The corresponding output terminal of the stage to which each level shifter is connected receives a corresponding clock signal and generates a corresponding boosted clock signal in response to the clock signal. The boosted clock signal controls the impedance state of the next level shifter in the second loop. A capacitor and diode network coupled to an input supply voltage terminal, the capacitor and diode network being configured to control the start-up of the ring oscillator; The stage is coupled to the input supply voltage terminal, the level shifter is coupled to the output supply voltage terminal, the output supply voltage terminal has a voltage greater than the input supply voltage terminal, and the level shifter is configured to receive the corresponding clock signal at the level of the input supply voltage terminal and generate the corresponding boosted clock signal at the level of the output supply voltage terminal.

12. The multiphase oscillator circuit of claim 11, further comprising a backup current source coupled to the capacitor and diode network, wherein the capacitor and diode network is configured to receive current from the backup current source to maintain the input supply voltage at or above a threshold voltage level.

13. The multiphase oscillator circuit of claim 11, further comprising a controller having a control output coupled to at least one of the stages, the controller being configured to drive the control output to enable or disable the ring oscillator to sustain multiple pulse edges of the boosted clock signal.

14. The multiphase oscillator circuit of claim 13, further comprising a filter circuit configured to filter one or more pulse edges of the pulse edges to achieve a specific start-up frequency before the control output enables the ring oscillator.

15. A multiphase oscillator circuit, comprising: A ring oscillator comprising a series of stages; as well as A first level shifter and a second level shifter, wherein the first level shifter includes a first transistor, a second transistor, and a third transistor having corresponding first gates, second gates, and third gates, wherein: The first transistor is coupled between the voltage reference terminal and the second transistor; The second transistor is coupled between the first transistor and the third transistor; The third transistor is coupled between the second transistor and the input power supply voltage terminal; At the first gate, the first level shifter is coupled to the stage output of one of the stages of the ring oscillator; The first level shifter is configured to generate a first boosted output at the connection between the second transistor and the third transistor in response to: the stage output; and a second boosted output from the second level shifter; The second gate and the third gate are coupled to the second boosted output and configured to control the impedance state of the first level shifter in response to the second boosted output; The stage is coupled to the input power supply voltage terminal; The first level shifter is coupled to the output power supply voltage terminal, which has a higher voltage than the input power supply voltage terminal; and The stage output has the level of the input supply voltage terminal, and the first boosted output has the level of the output supply voltage terminal; and The circuit further includes a capacitor and a diode network coupled to the input supply voltage terminal, the capacitor and diode network being configured to control the start-up of the ring oscillator.

16. The multiphase oscillator circuit of claim 15, further comprising a current source coupled to the stage, the current source being configured to supply current to the stage, wherein the oscillator output frequency of each stage is adjustable in response to the current supplied from the current source.

17. The multiphase oscillator circuit of claim 15, further comprising a backup current source coupled to the capacitor and diode network, wherein the capacitor and diode network is configured to receive current from the backup current source to maintain the input supply voltage at or above a threshold voltage level.

18. The multiphase oscillator circuit of claim 15, further comprising a controller having a control output coupled to at least one of the stages, the controller being configured to drive the control output to enable or disable the ring oscillator for multiple pulse edges of the boosted signal.

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