Electronic devices that form digital-to-analog converters and mixers
By using the acquisition stage and processing stage in a hybrid digital-to-analog converter to generate corresponding digital and analog signals, and using a 180° phase offset clock signal for frequency shift, the increased complexity and timing mismatch of local oscillators are solved. Problem, achieving hybrid DAC electronics with low complexity and low power consumption.
Patent Information
- Application Number
- CN201911380410.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2018-12-28
- Filing Date
- 2019-12-27
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2039-12-27
AI Technical Summary
The placement and displacement signal distribution of existing hybrid digital-to-analog converters (DACs) in local oscillators adds design complexity and silicon area consumption, and requires a low complexity and footprint due to performance issues due to timing mismatch. A small method to realize digital-to-analog conversion and frequency shift of digital input signals.
The acquisition stage is used to generate the first and second digital signals, and the first and second processing stages are respectively used to generate corresponding analog signals using the clock signal. The output stage generates analog output signals based on the clock signal, avoiding the use of local oscillators and additional processing circuits. Calibration timing mismatch, and frequency shift is performed using a 180° phase offset clock signal.
It realizes efficient digital-to-analog conversion and frequency shift of digital input signals without increasing complexity and silicon area, which reduces the data rate of digital input signals, reduces silicon area occupation and power consumption, and improves the equipment's performance.
Smart Images
Figure CN111384952B_ABST
Abstract
Description
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS
[0002] This application claims priority from French patent application No. 1874286, filed on December 28, 2018, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field
[0003] Embodiments relate to electronic devices, and more particularly to those electronic devices known as hybrid digital-to-analog converters (also known as hybrid DACs), which are capable of operating as both digital-to-analog converters and mixers. Background Art
[0004] A conventional digital-to-analog converter clocked at a sampling frequency fs is typically configured to convert a digital signal (whose value is encoded on a number of bits) into an analog signal whose analog value is proportional to the encoded digital value.
[0005] Hybrid digital-to-analog converters are known to those skilled in the art and are typically integrated into a digital-to-analog converter such as that described above with a mixer configured to combine an analog signal delivered by the converter and a mixed signal received by the digital-to-analog converter (the mixed signal typically being referred to as a transposition signal) to frequency shift the input signal in order to deliver a frequency-shifted output signal.
[0006] The shifted signal may for example have a frequency equal to the sampling frequency fs. In this case, a signal shifted around the sampling frequency may be obtained at the output of such a hybrid DAC electronics.
[0007] In addition, the response of this hybrid DAC electronics with respect to frequency f is type of function, and the response of the DAC in terms of frequency f is Type of function.
[0008] Therefore, for frequency displacement around the sampling frequency fs, such hybrid DAC electronics delivers a greater output power than is the case with a conventional digital-to-analog converter.
[0009] Additionally, the structure of such hybrid DAC electronics is typically more compact in terms of silicon area and consumes less power relative to conventional combinations of digital-to-analog converters and mixers.
[0010] More specifically, a conventional structure of such a hybrid DAC device includes processing circuitry configured to receive a digital input signal comprising N bits.
[0011] The processing circuitry comprises N processing units, each of the N processing units being configured to receive a digital input signal and a corresponding bit of a shift signal, and each of the N processing units being configured to generate a corresponding mixed analog signal.
[0012] The processing circuitry also includes output circuitry configured to combine all of the mixed analog signals to generate a mixed analog output signal.
[0013] The shift signal is typically generated by at least one local oscillator of the hybrid DAC electronics.
[0014] However, the placement of the local oscillator and the distribution of the shift signal within the hybrid DAC electronics not only increases the complexity of the design of the electronics, but also increases the silicon area and consumption of the electronics.
[0015] Furthermore, there is also a timing mismatch between the mixed analog signals generated by the N processing units. It should be noted that a timing mismatch of the order of picoseconds between mixed analog signals having frequencies of the order of gigahertz may already cause performance issues in the mixed DAC electronics and result in errors in the mixed analog output signal.
[0016] To address these timing mismatch issues, additional processing circuits are typically used in the hybrid DAC electronics to calibrate these timing mismatches, which further increases the complexity, silicon area, and consumption of the hybrid DAC electronics.
[0017] Therefore, there is a need to provide a technical approach with low complexity and small footprint in terms of silicon area so that digital-to-analog conversion and frequency shifting of a digital input signal can be performed in the same structure without compromising performance. Summary of the invention
[0018] According to one aspect, an electronic device is provided.
[0019] The electronic device includes: an acquisition stage, configured to receive a digital input signal and configured to generate a first digital signal and a second digital signal opposite to the first digital signal, respectively; a first processing stage and a second processing stage, configured to receive the first digital signal and the second digital signal, respectively, and configured to generate a first analog signal in time using a first clock signal and generate a second analog signal in time using a second clock signal, respectively, the second analog signal being opposite to the first clock signal within a tolerance range; and an output stage, configured to generate an analog output signal equal to the first analog signal or equal to the second analog signal according to the value of the first clock signal or the second clock signal.
[0020] Using such an acquisition stage, which makes it possible to generate the first digital signal and the second digital signal from a single digital input signal, the input data rate of the digital input signal can advantageously be reduced, for example by a factor of two.
[0021] In addition, the use of such a first processing stage and a second processing stage, which respectively receive the first digital signal and the second digital signal as input and are clocked by the first clock signal and the second clock signal respectively (which have a phase offset equal to 180° relative to the first clock signal within a tolerance range), advantageously allows frequency shifting to be performed in the digital domain rather than in the analog domain as proposed in conventional methods.
[0022] Here, the first clock signal and the second clock signal are used as shift signals. When the output stage is controlled according to the first clock signal or the second clock signal, the electronic device can generate an analog output signal from the first digital input signal and the second digital input signal using the first clock signal and the inversion of the first clock signal.
[0023] In other words, the apparatus does not use a local oscillator to provide a shifted signal, nor does it use additional processing circuitry in each of the first and second processing stages to calibrate for a potential timing mismatch between the first and second analog signals.
[0024] Regarding the phase offset between the first clock signal and the second clock signal, it should be noted that a person skilled in the art will know how to select a suitable tolerance depending on the intended application, for example. As a non-limiting indication, the tolerance may be, for example, about 5%.
[0025] According to one embodiment, the digital input signal and the first and second digital signals each include N bits, and the acquisition stage has N inverters configured to generate N bits of the second digital signal from the N bits of the digital input signal, respectively.
[0026] Reducing the input data rate of the digital input signal advantageously results in a reduction in the number of bits, a reduction in the silicon area occupied by the stage, and a reduction in the consumption of an acquisition stage configured to receive the digital input signal.
[0027] As a non-limiting example, the first processing stage and the second processing stage may each include a digital-to-analog converter.
[0028] According to a further embodiment, the digital-to-analog converters of the first processing stage and of the second processing stage are current-steering digital-to-analog converters.
[0029] According to yet another embodiment, the output stage comprises an analog multiplexer configured to generate an analog output signal equal to the first analog signal or equal to the second analog signal depending on a value of the first phase-shifted clock signal or the second phase-shifted clock signal.
[0030] As a non-limiting indication, the phase shift of the first phase-shifted clock signal may, for example, correspond at least to the duration of a transient state of the first analog signal or the second analog signal in a period of the first clock signal or the second clock signal.
[0031] The electronic device may, for example, be formed in an integrated manner.
[0032] According to another aspect, a communication system is proposed, the communication system comprising an electronic device such as defined above.
[0033] According to a further aspect, an electronic device such as a mobile phone is proposed, incorporating at least one communication system such as described above. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Other advantages and features will become apparent from an examination of the accompanying drawings and detailed description of a purely non-limiting embodiment, in which:
[0035] Figure 1 An electronic device in the form of a mobile phone of the “smartphone” type is schematically illustrated.
[0036] Figure 2 An electronic device comprising an acquisition stage, a first processing stage, a second processing stage and an output stage is schematically illustrated.
[0037] Figure 3 A timing diagram of an exemplary embodiment for the generation of an analog output signal is schematically illustrated.
[0038] Figure 4 An embodiment of a converter is schematically illustrated. DETAILED DESCRIPTION
[0039] Figure 1 An electronic device AE is illustrated, here for example a mobile phone of the “smartphone” type.
[0040] The mobile phone AE comprises a communication system 1 , for example according to a mobile phone network standard based on the Long Term Evolution (LTE) technology.
[0041] The communication system 1 includes an electronic device 2 formed in an integrated manner with non-discrete components and configured to operate as both a digital-to-analog converter and a frequency mixer.
[0042] Reference now Figure 2 , in order to explain an exemplary embodiment of the electronic device 2 in more detail, the electronic device 2 includes an acquisition stage 3, a first processing stage 4, a second processing stage 5 and an output stage 6.
[0043] The acquisition stage 3 is configured to receive a digital input signal SEN comprising N bits at its input 3in and comprises a first output 3out1 directly coupled to the input 3in and N inverters INV coupled between the input 3in and a second output 3out2.
[0044] The output stage 6 will then deliver a frequency-shifted analog output signal SSA over an output terminal BS, as will be seen in more detail below.
[0045] The acquisition stage 3 is configured to: deliver a first digital signal SN1 equal to the digital input signal SEN to a first output 3out1; and deliver a second digital signal SN2 to a second output 3out2, the second digital signal SN2 being opposite to the first digital signal SN1 or the digital input signal SEN (ie, logically inverted).
[0046] Advantageously, the acquisition stage 3 generates two digital signals SN1 , SN2 of two N bits from a digital input signal SEN of N bits.
[0047] Therefore, the data rate of the digital input signal is reduced relative to directly using an input signal having 2*N bits.
[0048] Furthermore, the use of the first and second digital signals SN1 and SN2 having logically inverted values in conjunction with the first and second processing stages and the output stage advantageously allows frequency shifting in digital mode.
[0049] The first processing stage 4 includes a first digital-to-analog converter CNA4, which includes: an input terminal 4in, which is configured to receive a first digital signal SN1; a clock terminal 4clk, which is configured to receive a first clock signal Sclk1 with a conversion (shift) frequency Fc; and an output terminal 4out coupled to the output stage 6.
[0050] The second processing stage 5 comprises a second digital-to-analog converter CNA5 , which comprises an input terminal 5in configured to receive the second digital signal SN2 , a clock terminal 5clk configured to receive the second clock signal Sclk2 , and an output terminal 5out coupled to the output stage 6 .
[0051] The converters CNA4 , CNA5 of the first processing stage 4 , 5 , may be identical, for example.
[0052] It should be noted that the first clock signal Sclk1 and the second clock signal Sclk2 can be square wave signals, for example, and the second clock signal Sclk2 is phase-shifted by 180° (i.e., logically inverted) relative to the first clock signal Sclk1 within a tolerance. The first clock signal Sclk1 and the second clock signal Sclk2 are also used as shift signals having a shift frequency Fc.
[0053] Therefore, the first digital-to-analog converter CNA4 is configured to convert the first digital signal SN1 into the first analog signal SA1 in time using the first clock signal Sclk1 .
[0054] In the same manner, the second digital-to-analog converter CNA5 is configured to convert the second digital signal SN2 (i.e., the inversion of the first digital signal SN1) into a second analog signal SA2 in time using the second clock signal Sclk2 (i.e., in time using the first clock signal Sclk1 phase-shifted by 180° within tolerance).
[0055] Therefore, the second analog signal SA2 generated at the output terminal 5out of the second digital-to-analog converter CNA5 is inverted and, within tolerance, phase-shifted by 180° with respect to the first analog signal SA1 generated at the output terminal 4out of the first digital-to-analog converter CNA4.
[0056] The output stage 6 comprises an analog multiplexer MUX comprising a first input E1 and a second input E2.
[0057] The first input E1 is configured to receive a first analog signal SA1 , and the second input E2 is configured to receive a second analog signal SA2 .
[0058] The multiplexer MUX further includes an output terminal BS and a selection terminal SEL configured to receive the first clock signal Sclk1 or the second clock signal Sclk2 as a selection signal.
[0059] To keep it simple, Figure 2 The diagram shows a case where the selection terminal SEL receives the first clock signal Sclk1 .
[0060] Therefore, the multiplexer MUX is configured to deliver the analog output signal SSA equal to the first analog signal SA1 or equal to the second analog signal SA2 to the output terminal BS according to the value of the first clock signal Sclk1 or the second clock signal Sclk2.
[0061] It should be noted that whenever the values of the first analog signal SA1 and the second analog signal SA2 change, there is generally a transient state before the values of the first analog signal SA1 and the second analog signal SA2 become stable.
[0062] To avoid potential errors caused during these transient states when changing the values of the first and second analog signals SA1 and SA2 , the multiplexer MUX is preferably configured to generate the internal clock signal SHI from the received first or second clock signal Sclk1 or Sclk2 .
[0063] The internal clock signal SHI is equal to the first clock signal Sclk1 phase-shifted by at least a duration corresponding to the transient state, ie, the duration of the setup time TS of the first analog signal SA1 or the second analog signal SA2 in one cycle of the first clock signal Sclk1.
[0064] Now refer to Figure 3 A timing diagram of an exemplary embodiment for the generation of analog output signal SSA is illustrated.
[0065] Figure 3 The upper part of illustrates: a first clock signal Sclk1 having a conversion (shift) frequency Fc; a first analog signal SA1 synchronized with each rising edge of the first clock signal Sclk1; and a second analog signal SA2 synchronized with each rising edge of the second clock signal Sclk2.
[0066] It can also be seen that the internal clock signal SHI is the first clock signal Sclk1 that has undergone a time shift, where the shift is greater than the setup time TS of the first analog signal SA1 or the second analog signal SA2 in one cycle of the first clock signal Sclk1.
[0067] As described above, the second analog signal SA2 (which exhibits a phase shift of 180° within tolerance) is equal to the first analog signal SA1 but inverted in phase.
[0068] The multiplexer MUX is configured to generate an analog output signal SSA which is equal to the first analog signal SA1 when the internal clock signal SHI is at a high state and equal to the second analog signal SA2 when the internal clock signal SHI is at a low level.
[0069] Therefore, in Figure 3 It can be seen from FIG. 5 that the analog output signal SSA generated by the output stage 6 is not affected by the setup time TS of the first analog signal SA1 and the second analog signal SA2 .
[0070] Thus, a low complexity hybrid DAC electronic device with a smaller footprint and low power consumption is obtained, which is capable of performing digital-to-analog conversion of a digital input signal and frequency shifting of the digital input signal without using one or more local oscillators or additional circuits to calibrate potential timing mismatches.
[0071] It should be noted that the converters CNA4, CNA5 used in the first processing stage 4, and in the second processing stage 5 may be any type of conventional digital-to-analog converters.
[0072] With this in mind, now refer to Figure 4 An exemplary embodiment of converter CNA4 or CNA5 (here, converter CNA4, for example) will be described.
[0073] The converter CNA4 is, for example, a current-steering digital-to-analog converter.
[0074] The converter CNA4 comprises a synchronization stage ES and a conversion stage EC.
[0075] The synchronization stage ES is configured to receive a first digital signal SN1 (here, for example, comprising 3 bits) and a first clock signal Sclk1 , and is configured to deliver three binary signals D1 to D3 synchronized with the first clock signal Sclk1 .
[0076] Signal D1 represents the least significant bit (LSB), and signal D3 represents the most significant bit (MSB).
[0077] The conversion stage EC here comprises three differential stages 7, 8, 9, each of which comprises a first respective n-type MOS transistor T7a, T8a, T9a and a second respective n-type MOS transistor T7b, T8b, T9b.
[0078] The sources of these first and second transistors T7a, T7b, T8a, T8b, T9a, T9b of each differential stage 7, 8, 9 are commonly coupled to the ground GND via bias transistors TP7, TP8, TP9 wired as current sources.
[0079] The gates of these bias transistors TP7 , TP8 , TP9 are configured to receive a bias voltage Vbias.
[0080] By selecting the bias transistors TP7 , TP8 , TP9 of appropriate size, the bias transistors TP7 , TP8 , TP9 operate as current sources with the weighted currents I, 2I, 4I.
[0081] The gates of the first and second transistors T7a, T7b, T8a, T8b, T9a, T9b of each differential stage 7, 8, 9 respectively form differential inputs of each differential stage 7, 8, 9 and are configured to receive 1-bit signals D1, D2, D3 respectively.
[0082] The drains of the first and second transistors T7a, T7b, T8a, T8b, T9a, T9b of each differential stage 7, 8, 9 are respectively coupled to the first resistor R1 via the positive output terminal OUT+ and to the second resistor R2 via the negative output terminal OUT-. The first resistor R1 and the second resistor R2 are commonly coupled to the power supply VDD.
[0083] The output terminals OUT+, OUT− form differential output terminals of the converter CNA4.
[0084] The differential stages 7 , 8 , 9 are configured to divert their weighted currents into the first resistor R1 or the second resistor R2 depending on the values of the signals D1 , D2 , D3 , respectively.
[0085] For example, if signals D1 and D3 are in a high state and signal D2 is in a low state, the output terminal OUT+ (or OUT-) receives a combination of weighted currents I, 4I generated by bias transistors TP7 and TP9, while the other output terminal OUT- (or OUT+) receives a weighted current 2I generated by bias transistor TP8.
[0086] The converter CNA4 is configured to deliver the first analog voltage signal SA1 to the differential outputs OUT+ and OUT− according to the generated combination of the weighted currents I, 2I, 4I and the combination of the first resistor R1 and the second resistor R2 .
[0087] Although the above disclosure has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description are to be considered illustrative or exemplary rather than restrictive; the disclosure herein is not limited to the described embodiments. Other variations of the disclosed embodiments may be understood and implemented by those skilled in the art by studying the drawings, the disclosure, and the appended claims.
Claims
1. A device comprising: an acquisition stage configured to: receive a digital input signal, and generate a first digital signal and a second digital signal, respectively, wherein the second digital signal is a logical inversion of the first digital signal; a first processing stage and a second processing stage, each configured to receive the first digital signal and the second digital signal, the first processing stage being configured to generate a first analog signal from the first digital signal in time using a first clock signal, and the second processing stage being configured to generate a second analog signal from the second digital signal in time using a second clock signal, wherein the second analog signal is in opposite phase to the first clock signal; as well as The output stage is configured to generate an analog output signal equal to a selected signal of the first analog signal or the second analog signal according to a value of the first clock signal or the second clock signal.
2. The device of claim 1 , wherein the digital input signal and the first digital signal and the second digital signal each include N bits, and the acquisition stage includes N logic inverter circuits, the N logic inverter circuits being configured to generate N bits of the second digital signal from the N bits of the digital input signal, respectively.
3. The apparatus of claim 1, wherein the first processing stage and the second processing stage each comprise a digital-to-analog converter.
4. The apparatus of claim 3, wherein each digital-to-analog converter in the first processing stage and the second processing stage is a current-steering digital-to-analog converter.
5. The apparatus of claim 1, wherein the first processing stage and the second processing stage are identical.
6. The device of claim 1 , wherein the output stage comprises an analog multiplexer configured to generate the analog output signal equal to the first analog signal in response to a first logic state of the first clock signal or the second clock signal, or to generate the analog output signal equal to the second analog signal in response to a second logic state of the first clock signal or the second clock signal.
7. The apparatus of claim 6, wherein the analog output signal has a phase shift corresponding to at least a duration of a transient state of the first analog signal or the second analog signal in a cycle of the first clock signal or the second clock signal.
8. The device according to claim 1, which is manufactured in an integrated manner.
9. The device of claim 1, wherein the device comprises a communication system, the communication system comprises an electronic device, the electronic device comprises the acquisition stage, the first processing stage, the second processing stage, and the output stage.
10. The device of claim 1, wherein the device comprises a mobile phone having a communication system, the communication system comprising an electronic device, the electronic device comprising the acquisition stage, the first processing stage, the second processing stage, and the output stage.
11. A device comprising: an acquisition stage configured to: receive a digital input signal and generate a first digital signal and a second digital signal, wherein the second digital signal is a complement of the first digital signal; A first digital-to-analog converter, configured to convert the first digital signal into a first analog signal in time using a first clock signal; a second digital-to-analog converter configured to convert the second digital signal into a second analog signal in time using a second clock signal; wherein the second clock signal is the complement of the first clock signal; as well as The output stage is configured as: generating an internal clock signal equivalent to one of: the first clock signal phase-shifted by a duration of a transient state of the first clock signal occurring during a period of the first clock signal, or the second clock signal phase-shifted by a duration of a transient state of the second clock signal occurring during a period of the second clock signal; generating an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level; and When the internal clock signal is at a second logic level opposite to the first logic level, the analog output signal equal to the second analog signal is generated.
12. The apparatus of claim 11, wherein the first digital-to-analog converter and the second digital-to-analog converter are each current-steering digital-to-analog converters.
13. The apparatus of claim 11 , wherein the digital input signal and the first and second digital signals each comprise N bits, and the acquisition stage comprises N inverter circuits configured to generate N bits of the second digital signal from the N bits of the digital input signal, respectively.
14. The apparatus of claim 11, wherein the output stage comprises an analog multiplexer.
15. A method comprising: generating a first digital signal and a second digital signal from a digital input signal, wherein the second digital signal is the complement of the first digital signal; Converting the first digital signal into a first analog signal in time using a first clock signal; converting the second digital signal into a second analog signal in time using a second clock signal, wherein the second clock signal is the complement of the first clock signal; generating an internal clock signal that is equal to one of: the first clock signal phase-shifted by a duration of a transient state of the first clock signal that occurs during a period of the first clock signal, or the second clock signal phase-shifted by a duration of a transient state of the second clock signal that occurs during a period of the second clock signal; The analog output signal is generated by: selecting the first analog signal as the analog output signal in response to a first logic state of the internal clock signal, and The second analog signal is selected as the analog output signal in response to a second logic state of the internal clock signal.
16. The method of claim 15, wherein the digital input signal and the first and second digital signals each comprise N bits.